WO2024009872A1 - Circuit d'attaque de charge - Google Patents

Circuit d'attaque de charge Download PDF

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Publication number
WO2024009872A1
WO2024009872A1 PCT/JP2023/024050 JP2023024050W WO2024009872A1 WO 2024009872 A1 WO2024009872 A1 WO 2024009872A1 JP 2023024050 W JP2023024050 W JP 2023024050W WO 2024009872 A1 WO2024009872 A1 WO 2024009872A1
Authority
WO
WIPO (PCT)
Prior art keywords
drive circuit
pmos transistor
load drive
load
nmos transistor
Prior art date
Application number
PCT/JP2023/024050
Other languages
English (en)
Japanese (ja)
Inventor
望 古謝
晃裕 小野
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Publication of WO2024009872A1 publication Critical patent/WO2024009872A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only

Definitions

  • the present disclosure relates to a load drive circuit that drives an externally attached load circuit.
  • An open drain circuit is used as a load drive circuit that drives a load externally attached to a semiconductor integrated circuit (external load).
  • the open drain circuit includes a MOS transistor. When the gate-source voltage of the MOS transistor is zero, the MOS transistor is off and the power supply path for the external load is cut off. When a drive voltage exceeding a threshold voltage is applied to the gate-source voltage of the MOS transistor, the MOS transistor is turned on and the power supply path for the external load is made conductive.
  • the load will malfunction.
  • the present disclosure has been made in such a situation, and one exemplary objective of a certain aspect thereof is to provide a load drive circuit that can suppress malfunction of a load.
  • a certain aspect of the present disclosure relates to a load drive circuit.
  • the load drive circuit includes a power supply terminal, a ground terminal, a first output terminal to which one end of the external load is to be connected, a second output terminal to which the other end of the external load is to be connected, a power supply terminal and the first output.
  • a PMOS transistor connected between the terminals, an NMOS transistor connected between the second output terminal and the ground terminal, and a controller that controls turning on and off of the PMOS transistor and the NMOS transistor according to a control signal. Be prepared.
  • FIG. 1 is a circuit diagram of a load drive circuit according to comparative technique 1.
  • FIG. 2 is a time chart illustrating the operation of the load drive circuit of FIG. 1 at startup.
  • FIG. 3 is a circuit diagram of a load drive circuit according to comparative technique 2.
  • FIG. 4 is a diagram illustrating an abnormal state of the load drive circuit of FIG. 3.
  • FIG. 5 is a circuit diagram of the load drive circuit according to the embodiment.
  • FIG. 6 is an equivalent circuit diagram of the load drive circuit in an abnormal state where the second output terminal is shorted to the ground line.
  • FIG. 7 is an equivalent circuit diagram of the load drive circuit in an abnormal state where the first output terminal is shorted to the power supply line.
  • FIG. 8 is a time chart illustrating the operation of the load drive circuit at startup.
  • FIG. 9 is a circuit diagram showing a configuration example of a controller of a load drive circuit.
  • FIG. 10 is a circuit diagram showing another configuration example of the controller of the load drive circuit.
  • the load driving circuit includes a power supply terminal, a ground terminal, a first output terminal to which one end of the external load is to be connected, a second output terminal to which the other end of the external load is to be connected, and a power supply terminal.
  • a PMOS transistor connected between the terminal and the first output terminal, an NMOS transistor connected between the second output terminal and the ground terminal, and turning on and off of the PMOS transistor and the NMOS transistor according to the control signal is controlled. and a controller.
  • the controller may first turn on the NMOS transistor and then turn on the PMOS transistor in response to assertion of the control signal.
  • the controller may turn on the NMOS transistor and the PMOS transistor simultaneously in response to assertion of the control signal.
  • the controller may include a first driver with a push-pull configuration that drives a PMOS transistor, and a second driver with a push-pull configuration that drives an NMOS transistor.
  • the controller may include a first driver that drives a PMOS transistor and a second driver that drives an NMOS transistor.
  • the external load may be a fuse.
  • the external load may be a resistor
  • the external load may be a light emitting device.
  • the external load may be a one-time programmable (OTP) memory cell.
  • OTP one-time programmable
  • a state in which member A is connected to member B refers to not only a case where member A and member B are physically directly connected, but also a state in which member A and member B are electrically connected. This also includes cases in which they are indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects achieved by their combination.
  • a state in which member C is connected (provided) between member A and member B refers to a state in which member A and member C or member B and member C are directly connected. In addition, it also includes cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.
  • FIG. 1 is a circuit diagram of a load drive circuit 10 according to comparative technique 1.
  • the load drive circuit 10 supplies the drive current IDRV to the external load 2 when the control signal EN is asserted (on level).
  • the load drive circuit 10 is an open drain circuit including a PMOS transistor MP1.
  • a power supply voltage V DD is supplied to a power supply terminal V DD of the load drive circuit 10 .
  • External load 2 is connected between output terminal OUT and ground.
  • the external load 2 is shown by a simple resistance symbol, but its type is not particularly limited, and examples thereof include a fuse, a light emitting element, an OTP memory cell, and the like.
  • the PMOS transistor MP1 is connected between the power supply terminal VDD and the output terminal OUT.
  • a resistor R1 is connected between the gate and source of the PMOS transistor MP1.
  • Capacitor C1 represents the gate capacitance of PMOS transistor MP1.
  • the driver 12 drives the PMOS transistor MP1 according to the control signal EN. Specifically, when the control signal EN is asserted (eg, high), the driver 12 applies a low voltage to the gate of the PMOS transistor MP1 to turn on the PMOS transistor MP1. When the control signal EN is negated (for example, low), the driver 12 applies a high voltage to the gate of the PMOS transistor MP1 to turn off the PMOS transistor MP1.
  • FIG. 2 is a time chart illustrating the operation of the load drive circuit 10 of FIG. 1 at startup.
  • Control signal EN is negated (low).
  • the source voltage VDD of the PMOS transistor MP1 also rises. Since the gate of the PMOS transistor MP1 is pulled up by the resistor R1, when the power supply voltage VCC rises, the gate voltage VG of the PMOS transistor MP1 also rises accordingly.
  • the PMOS transistor MP1 is bypassed and current flows to the external load 2.
  • FIG. 3 is a circuit diagram of the load drive circuit 20 according to Comparative Technique 2.
  • the load drive circuit 20 is an open drain circuit including an NMOS transistor MP1, and includes an NMOS transistor MN1 and a driver 22.
  • the source of the NMOS transistor MN1 is connected to the ground terminal GND, and the drain thereof is connected to the output terminal OUT.
  • External load 2 is connected between output terminal OUT and power supply line VCC .
  • the driver 22 drives the NMOS transistor MN1 according to the control signal EN. Specifically, when the control signal EN is asserted (eg, high), the driver 22 applies a high voltage to the gate of the NMOS transistor MN1 to turn on the NMOS transistor MN1. When the control signal EN is negated (for example, low), the driver 22 applies a low voltage to the gate of the NMOS transistor MN1 to turn off the NMOS transistor MN1.
  • FIG. 4 is a diagram illustrating an abnormal state of the load drive circuit 20 of FIG. 3. Specifically, an abnormality has occurred in which the output terminal OUT is shorted to the ground line. In this case, even if the NMOS transistor MN1 is off, the current ILEAK flows to the external load 2 via the short path P1. As a result, the external load 2 malfunctions.
  • FIG. 5 is a circuit diagram of the load drive circuit 100 according to the embodiment.
  • the load drive circuit 100 has a power supply terminal VDD, a first output terminal OUT1, a second output terminal OUT2, and a ground terminal GND.
  • Power supply terminal VDD is connected to a power supply line and supplied with power supply voltage VCC .
  • the ground terminal GND is grounded.
  • External load 2 is connected between first output terminal OUT1 and second output terminal OUT2.
  • the load drive circuit 100 includes a PMOS transistor MP1, an NMOS transistor MN1, and a controller 110.
  • the source of the PMOS transistor MP1 is connected to the power supply terminal VDD, and the drain of the PMOS transistor MP1 is connected to the first output terminal OUT1.
  • the gate of PMOS transistor MP1 is pulled up by resistor R1.
  • the drain of the NMOS transistor MN1 is connected to the second output terminal OUT2, and the source of the NMOS transistor MN1 is connected to the ground terminal GND.
  • the gate of NMOS transistor MN1 is pulled down by resistor R2.
  • Controller 110 controls turning on and off of PMOS transistor MP1 and NMOS transistor MN1 according to control signal EN. Specifically, when the control signal EN is asserted (eg, high), the controller 110 applies a low voltage (eg, 0V) to the gate of the PMOS transistor MP1, and applies a high voltage (eg, power supply voltage V) to the gate of the NMOS transistor MN1. DD ) is applied to turn on both the PMOS transistor MP1 and the NMOS transistor MN1.
  • the controller 110 applies a high voltage (V DD ) to the gate of the PMOS transistor MP1, a low voltage (0V) to the gate of the NMOS transistor MN1, and Both transistor MP1 and NMOS transistor MN1 are turned off.
  • the controller 110 includes a first driver DR1, a second driver DR2, and a logic circuit 112.
  • FIG. 6 is an equivalent circuit diagram of the load drive circuit 100 in an abnormal state where the second output terminal OUT2 is shorted to the ground line.
  • the control signal EN is negated, and both the PMOS transistor MP1 and the NMOS transistor MN1 are in an off state.
  • the NMOS transistor MN1 When the second output terminal OUT2 is connected to the ground line via the path P1, the NMOS transistor MN1 is bypassed, but at this time, the PMOS transistor MP1 remains off, so the external load 2 separated from the line. Therefore, according to the load drive circuit 100, it is possible to prevent the external load 2 from malfunctioning when the second output terminal OUT2 is grounded.
  • FIG. 7 is an equivalent circuit diagram of the load drive circuit 100 in an abnormal state where the first output terminal OUT1 is shorted to the power supply line.
  • the control signal EN is negated, and both the PMOS transistor MP1 and the NMOS transistor MN1 are in an off state.
  • the PMOS transistor MP1 When the first output terminal OUT1 is connected to the power supply line via the path P2, the PMOS transistor MP1 is bypassed, but at this time, the off state of the NMOS transistor MN1 is maintained, so the external load 2 is connected to the ground. separated from the line. Therefore, according to the load drive circuit 100, it is possible to prevent the external load 2 from malfunctioning when the first output terminal OUT1 is shorted to power.
  • FIG. 8 is a time chart illustrating the operation of the load drive circuit 100 at startup.
  • Control signal EN is negated (low).
  • the source voltage VDD of the PMOS transistor MP1 also rises. Since the gate of the PMOS transistor MP1 is pulled up by the resistor R1, when the power supply voltage VCC rises, the gate voltage VG of the PMOS transistor MP1 also rises accordingly.
  • NMOS transistor MN1 when the power supply voltage V CC rises, the gate of the NMOS transistor MN1 maintains 0V because it is not affected by fluctuations in the power supply voltage V CC . Therefore, NMOS transistor MN1 can maintain an off state. Thereby, leakage current ILEAK can be prevented from flowing into the external load 2, and malfunction of the external load 2 can be prevented.
  • FIG. 9 is a circuit diagram showing a configuration example (110A) of the controller 110 of the load drive circuit 100.
  • the first driver DR1 and the second driver DR2 of the controller 110A are CMOS inverters having a push-pull configuration.
  • the control signal EN is supplied to the first driver DR1 in its original logic, and the control signal ⁇ EN inverted by the inverter 114 is supplied to the second driver DR2.
  • the PMOS transistor of the first driver DR1 may be omitted.
  • the NMOS transistor of the second driver DR2 may be omitted.
  • FIG. 10 is a circuit diagram showing another configuration example (110B) of the controller 110 of the load drive circuit 100.
  • the first driver DR1 and second driver DR2 of the controller 110B are composed of current sources CS1 and CS2.
  • the control signal EN is supplied to the current sources CS1 and CS2 with its logic unchanged. In other words, the logic circuit 112 is just a wire.
  • the respective gate voltages of the PMOS transistor MP1 and the NMOS transistor MN1 begin to change simultaneously, and can be turned on substantially simultaneously.
  • the controller 110 may turn on the PMOS transistor MP1 and the NMOS transistor MN1 with a time difference. Specifically, in response to the assertion of the control signal EN, the controller 110 first increases the gate voltage V G1 of the NMOS transistor MN1 to turn it on, and then decreases the gate voltage V G2 of the PMOS transistor MP1. You can also turn it on.
  • a load drive circuit comprising:
  • the controller includes: a first driver with a push-pull configuration that drives the PMOS transistor; a second driver with a push-pull configuration that drives the NMOS transistor;
  • the load drive circuit according to any one of items 1 to 3, comprising:
  • the controller includes: a first driver that drives the PMOS transistor; a second driver that drives the NMOS transistor;
  • the load drive circuit according to any one of items 1 to 3, comprising:
  • the present disclosure relates to a load drive circuit that drives an externally attached load circuit.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)

Abstract

Une extrémité d'une charge externe (2) est connectée à une première borne de sortie OUT1, et l'autre extrémité de la charge externe (2) est connectée à une seconde borne de sortie OUT2. Un transistor PMOS MP1 est connecté entre une borne d'alimentation VDD et la première borne de sortie OUT1, et un transistor NMOS MN1 est connecté entre une borne de masse GND et la seconde borne de sortie OUT2. Un dispositif de commande (110) effectue une commande MARCHE/ARRÊT du transistor PMOS MP1 et du transistor NMOS MN1 en fonction d'un signal de commande EN.
PCT/JP2023/024050 2022-07-04 2023-06-28 Circuit d'attaque de charge WO2024009872A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022108013 2022-07-04
JP2022-108013 2022-07-04

Publications (1)

Publication Number Publication Date
WO2024009872A1 true WO2024009872A1 (fr) 2024-01-11

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ID=89453509

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Application Number Title Priority Date Filing Date
PCT/JP2023/024050 WO2024009872A1 (fr) 2022-07-04 2023-06-28 Circuit d'attaque de charge

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WO (1) WO2024009872A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006333278A (ja) * 2005-05-30 2006-12-07 Denso Corp 車載電気負荷の駆動装置
JP2009278159A (ja) * 2008-05-12 2009-11-26 Denso Corp 負荷駆動装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006333278A (ja) * 2005-05-30 2006-12-07 Denso Corp 車載電気負荷の駆動装置
JP2009278159A (ja) * 2008-05-12 2009-11-26 Denso Corp 負荷駆動装置

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