WO2024009872A1 - Load drive circuit - Google Patents

Load drive circuit Download PDF

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Publication number
WO2024009872A1
WO2024009872A1 PCT/JP2023/024050 JP2023024050W WO2024009872A1 WO 2024009872 A1 WO2024009872 A1 WO 2024009872A1 JP 2023024050 W JP2023024050 W JP 2023024050W WO 2024009872 A1 WO2024009872 A1 WO 2024009872A1
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Prior art keywords
drive circuit
pmos transistor
load drive
load
nmos transistor
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PCT/JP2023/024050
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French (fr)
Japanese (ja)
Inventor
望 古謝
晃裕 小野
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ローム株式会社
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Publication of WO2024009872A1 publication Critical patent/WO2024009872A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only

Definitions

  • the present disclosure relates to a load drive circuit that drives an externally attached load circuit.
  • An open drain circuit is used as a load drive circuit that drives a load externally attached to a semiconductor integrated circuit (external load).
  • the open drain circuit includes a MOS transistor. When the gate-source voltage of the MOS transistor is zero, the MOS transistor is off and the power supply path for the external load is cut off. When a drive voltage exceeding a threshold voltage is applied to the gate-source voltage of the MOS transistor, the MOS transistor is turned on and the power supply path for the external load is made conductive.
  • the load will malfunction.
  • the present disclosure has been made in such a situation, and one exemplary objective of a certain aspect thereof is to provide a load drive circuit that can suppress malfunction of a load.
  • a certain aspect of the present disclosure relates to a load drive circuit.
  • the load drive circuit includes a power supply terminal, a ground terminal, a first output terminal to which one end of the external load is to be connected, a second output terminal to which the other end of the external load is to be connected, a power supply terminal and the first output.
  • a PMOS transistor connected between the terminals, an NMOS transistor connected between the second output terminal and the ground terminal, and a controller that controls turning on and off of the PMOS transistor and the NMOS transistor according to a control signal. Be prepared.
  • FIG. 1 is a circuit diagram of a load drive circuit according to comparative technique 1.
  • FIG. 2 is a time chart illustrating the operation of the load drive circuit of FIG. 1 at startup.
  • FIG. 3 is a circuit diagram of a load drive circuit according to comparative technique 2.
  • FIG. 4 is a diagram illustrating an abnormal state of the load drive circuit of FIG. 3.
  • FIG. 5 is a circuit diagram of the load drive circuit according to the embodiment.
  • FIG. 6 is an equivalent circuit diagram of the load drive circuit in an abnormal state where the second output terminal is shorted to the ground line.
  • FIG. 7 is an equivalent circuit diagram of the load drive circuit in an abnormal state where the first output terminal is shorted to the power supply line.
  • FIG. 8 is a time chart illustrating the operation of the load drive circuit at startup.
  • FIG. 9 is a circuit diagram showing a configuration example of a controller of a load drive circuit.
  • FIG. 10 is a circuit diagram showing another configuration example of the controller of the load drive circuit.
  • the load driving circuit includes a power supply terminal, a ground terminal, a first output terminal to which one end of the external load is to be connected, a second output terminal to which the other end of the external load is to be connected, and a power supply terminal.
  • a PMOS transistor connected between the terminal and the first output terminal, an NMOS transistor connected between the second output terminal and the ground terminal, and turning on and off of the PMOS transistor and the NMOS transistor according to the control signal is controlled. and a controller.
  • the controller may first turn on the NMOS transistor and then turn on the PMOS transistor in response to assertion of the control signal.
  • the controller may turn on the NMOS transistor and the PMOS transistor simultaneously in response to assertion of the control signal.
  • the controller may include a first driver with a push-pull configuration that drives a PMOS transistor, and a second driver with a push-pull configuration that drives an NMOS transistor.
  • the controller may include a first driver that drives a PMOS transistor and a second driver that drives an NMOS transistor.
  • the external load may be a fuse.
  • the external load may be a resistor
  • the external load may be a light emitting device.
  • the external load may be a one-time programmable (OTP) memory cell.
  • OTP one-time programmable
  • a state in which member A is connected to member B refers to not only a case where member A and member B are physically directly connected, but also a state in which member A and member B are electrically connected. This also includes cases in which they are indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects achieved by their combination.
  • a state in which member C is connected (provided) between member A and member B refers to a state in which member A and member C or member B and member C are directly connected. In addition, it also includes cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.
  • FIG. 1 is a circuit diagram of a load drive circuit 10 according to comparative technique 1.
  • the load drive circuit 10 supplies the drive current IDRV to the external load 2 when the control signal EN is asserted (on level).
  • the load drive circuit 10 is an open drain circuit including a PMOS transistor MP1.
  • a power supply voltage V DD is supplied to a power supply terminal V DD of the load drive circuit 10 .
  • External load 2 is connected between output terminal OUT and ground.
  • the external load 2 is shown by a simple resistance symbol, but its type is not particularly limited, and examples thereof include a fuse, a light emitting element, an OTP memory cell, and the like.
  • the PMOS transistor MP1 is connected between the power supply terminal VDD and the output terminal OUT.
  • a resistor R1 is connected between the gate and source of the PMOS transistor MP1.
  • Capacitor C1 represents the gate capacitance of PMOS transistor MP1.
  • the driver 12 drives the PMOS transistor MP1 according to the control signal EN. Specifically, when the control signal EN is asserted (eg, high), the driver 12 applies a low voltage to the gate of the PMOS transistor MP1 to turn on the PMOS transistor MP1. When the control signal EN is negated (for example, low), the driver 12 applies a high voltage to the gate of the PMOS transistor MP1 to turn off the PMOS transistor MP1.
  • FIG. 2 is a time chart illustrating the operation of the load drive circuit 10 of FIG. 1 at startup.
  • Control signal EN is negated (low).
  • the source voltage VDD of the PMOS transistor MP1 also rises. Since the gate of the PMOS transistor MP1 is pulled up by the resistor R1, when the power supply voltage VCC rises, the gate voltage VG of the PMOS transistor MP1 also rises accordingly.
  • the PMOS transistor MP1 is bypassed and current flows to the external load 2.
  • FIG. 3 is a circuit diagram of the load drive circuit 20 according to Comparative Technique 2.
  • the load drive circuit 20 is an open drain circuit including an NMOS transistor MP1, and includes an NMOS transistor MN1 and a driver 22.
  • the source of the NMOS transistor MN1 is connected to the ground terminal GND, and the drain thereof is connected to the output terminal OUT.
  • External load 2 is connected between output terminal OUT and power supply line VCC .
  • the driver 22 drives the NMOS transistor MN1 according to the control signal EN. Specifically, when the control signal EN is asserted (eg, high), the driver 22 applies a high voltage to the gate of the NMOS transistor MN1 to turn on the NMOS transistor MN1. When the control signal EN is negated (for example, low), the driver 22 applies a low voltage to the gate of the NMOS transistor MN1 to turn off the NMOS transistor MN1.
  • FIG. 4 is a diagram illustrating an abnormal state of the load drive circuit 20 of FIG. 3. Specifically, an abnormality has occurred in which the output terminal OUT is shorted to the ground line. In this case, even if the NMOS transistor MN1 is off, the current ILEAK flows to the external load 2 via the short path P1. As a result, the external load 2 malfunctions.
  • FIG. 5 is a circuit diagram of the load drive circuit 100 according to the embodiment.
  • the load drive circuit 100 has a power supply terminal VDD, a first output terminal OUT1, a second output terminal OUT2, and a ground terminal GND.
  • Power supply terminal VDD is connected to a power supply line and supplied with power supply voltage VCC .
  • the ground terminal GND is grounded.
  • External load 2 is connected between first output terminal OUT1 and second output terminal OUT2.
  • the load drive circuit 100 includes a PMOS transistor MP1, an NMOS transistor MN1, and a controller 110.
  • the source of the PMOS transistor MP1 is connected to the power supply terminal VDD, and the drain of the PMOS transistor MP1 is connected to the first output terminal OUT1.
  • the gate of PMOS transistor MP1 is pulled up by resistor R1.
  • the drain of the NMOS transistor MN1 is connected to the second output terminal OUT2, and the source of the NMOS transistor MN1 is connected to the ground terminal GND.
  • the gate of NMOS transistor MN1 is pulled down by resistor R2.
  • Controller 110 controls turning on and off of PMOS transistor MP1 and NMOS transistor MN1 according to control signal EN. Specifically, when the control signal EN is asserted (eg, high), the controller 110 applies a low voltage (eg, 0V) to the gate of the PMOS transistor MP1, and applies a high voltage (eg, power supply voltage V) to the gate of the NMOS transistor MN1. DD ) is applied to turn on both the PMOS transistor MP1 and the NMOS transistor MN1.
  • the controller 110 applies a high voltage (V DD ) to the gate of the PMOS transistor MP1, a low voltage (0V) to the gate of the NMOS transistor MN1, and Both transistor MP1 and NMOS transistor MN1 are turned off.
  • the controller 110 includes a first driver DR1, a second driver DR2, and a logic circuit 112.
  • FIG. 6 is an equivalent circuit diagram of the load drive circuit 100 in an abnormal state where the second output terminal OUT2 is shorted to the ground line.
  • the control signal EN is negated, and both the PMOS transistor MP1 and the NMOS transistor MN1 are in an off state.
  • the NMOS transistor MN1 When the second output terminal OUT2 is connected to the ground line via the path P1, the NMOS transistor MN1 is bypassed, but at this time, the PMOS transistor MP1 remains off, so the external load 2 separated from the line. Therefore, according to the load drive circuit 100, it is possible to prevent the external load 2 from malfunctioning when the second output terminal OUT2 is grounded.
  • FIG. 7 is an equivalent circuit diagram of the load drive circuit 100 in an abnormal state where the first output terminal OUT1 is shorted to the power supply line.
  • the control signal EN is negated, and both the PMOS transistor MP1 and the NMOS transistor MN1 are in an off state.
  • the PMOS transistor MP1 When the first output terminal OUT1 is connected to the power supply line via the path P2, the PMOS transistor MP1 is bypassed, but at this time, the off state of the NMOS transistor MN1 is maintained, so the external load 2 is connected to the ground. separated from the line. Therefore, according to the load drive circuit 100, it is possible to prevent the external load 2 from malfunctioning when the first output terminal OUT1 is shorted to power.
  • FIG. 8 is a time chart illustrating the operation of the load drive circuit 100 at startup.
  • Control signal EN is negated (low).
  • the source voltage VDD of the PMOS transistor MP1 also rises. Since the gate of the PMOS transistor MP1 is pulled up by the resistor R1, when the power supply voltage VCC rises, the gate voltage VG of the PMOS transistor MP1 also rises accordingly.
  • NMOS transistor MN1 when the power supply voltage V CC rises, the gate of the NMOS transistor MN1 maintains 0V because it is not affected by fluctuations in the power supply voltage V CC . Therefore, NMOS transistor MN1 can maintain an off state. Thereby, leakage current ILEAK can be prevented from flowing into the external load 2, and malfunction of the external load 2 can be prevented.
  • FIG. 9 is a circuit diagram showing a configuration example (110A) of the controller 110 of the load drive circuit 100.
  • the first driver DR1 and the second driver DR2 of the controller 110A are CMOS inverters having a push-pull configuration.
  • the control signal EN is supplied to the first driver DR1 in its original logic, and the control signal ⁇ EN inverted by the inverter 114 is supplied to the second driver DR2.
  • the PMOS transistor of the first driver DR1 may be omitted.
  • the NMOS transistor of the second driver DR2 may be omitted.
  • FIG. 10 is a circuit diagram showing another configuration example (110B) of the controller 110 of the load drive circuit 100.
  • the first driver DR1 and second driver DR2 of the controller 110B are composed of current sources CS1 and CS2.
  • the control signal EN is supplied to the current sources CS1 and CS2 with its logic unchanged. In other words, the logic circuit 112 is just a wire.
  • the respective gate voltages of the PMOS transistor MP1 and the NMOS transistor MN1 begin to change simultaneously, and can be turned on substantially simultaneously.
  • the controller 110 may turn on the PMOS transistor MP1 and the NMOS transistor MN1 with a time difference. Specifically, in response to the assertion of the control signal EN, the controller 110 first increases the gate voltage V G1 of the NMOS transistor MN1 to turn it on, and then decreases the gate voltage V G2 of the PMOS transistor MP1. You can also turn it on.
  • a load drive circuit comprising:
  • the controller includes: a first driver with a push-pull configuration that drives the PMOS transistor; a second driver with a push-pull configuration that drives the NMOS transistor;
  • the load drive circuit according to any one of items 1 to 3, comprising:
  • the controller includes: a first driver that drives the PMOS transistor; a second driver that drives the NMOS transistor;
  • the load drive circuit according to any one of items 1 to 3, comprising:
  • the present disclosure relates to a load drive circuit that drives an externally attached load circuit.

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Abstract

One end of an external load 2 is connected to a first output terminal OUT1, and the other end of the external load 2 is connected to a second output terminal OUT2. A PMOS transistor MP1 is connected between a power terminal VDD and the first output terminal OUT1, and an NMOS transistor MN1 is connected between a ground terminal GND and the second output terminal OUT2. A controller 110 performs ON/OFF control of the PMOS transistor MP1 and the NMOS transistor MN1 according to a control signal EN.

Description

負荷駆動回路load drive circuit
　本開示は、外付けされる負荷回路を駆動する負荷駆動回路に関する。 The present disclosure relates to a load drive circuit that drives an externally attached load circuit.
　半導体集積回路に外付けされる負荷（外部負荷）を駆動する負荷駆動回路として、オープンドレイン回路が利用される。オープンドレイン回路は、ＭＯＳトランジスタを含む。ＭＯＳトランジスタのゲートソース間電圧がゼロであるとき、ＭＯＳトランジスタはオフであり、外部負荷の給電経路が遮断される。ＭＯＳトランジスタのゲートソース間電圧にしきい値電圧を超える駆動電圧が印加されると、ＭＯＳトランジスタはオンとなり、外部負荷の給電経路が導通する。 An open drain circuit is used as a load drive circuit that drives a load externally attached to a semiconductor integrated circuit (external load). The open drain circuit includes a MOS transistor. When the gate-source voltage of the MOS transistor is zero, the MOS transistor is off and the power supply path for the external load is cut off. When a drive voltage exceeding a threshold voltage is applied to the gate-source voltage of the MOS transistor, the MOS transistor is turned on and the power supply path for the external load is made conductive.
特許７０８２９０２号公報Patent No. 7082902
　このような負荷駆動回路において、電源電圧の急峻な変動によって、ＭＯＳトランジスタのゲートソース間にしきい値電圧を超える電圧が発生すると、負荷が誤動作する。 In such a load drive circuit, if a voltage exceeding a threshold voltage is generated between the gate and source of the MOS transistor due to a sudden change in the power supply voltage, the load will malfunction.
　あるいは、ＭＯＳトランジスタのドレイン端子が、電源ラインあるいは接地ラインに対してショート（地絡）すると、負荷が誤動作する。 Alternatively, if the drain terminal of the MOS transistor is short-circuited (ground fault) to the power supply line or the ground line, the load will malfunction.
　本開示は係る状況においてなされたものであり、そのある態様の例示的な目的のひとつは、負荷の誤動作を抑制可能な負荷駆動回路の提供にある。 The present disclosure has been made in such a situation, and one exemplary objective of a certain aspect thereof is to provide a load drive circuit that can suppress malfunction of a load.
　本開示のある態様は、負荷駆動回路に関する。負荷駆動回路は、電源端子と、接地端子と、外部負荷の一端が接続されるべき第１出力端子と、外部負荷の他端が接続されるべき第２出力端子と、電源端子と第１出力端子の間に接続されたＰＭＯＳトランジスタと、第２出力端子と接地端子の間に接続されたＮＭＯＳトランジスタと、制御信号に応じて、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタのオン、オフを制御するコントローラと、を備える。 A certain aspect of the present disclosure relates to a load drive circuit. The load drive circuit includes a power supply terminal, a ground terminal, a first output terminal to which one end of the external load is to be connected, a second output terminal to which the other end of the external load is to be connected, a power supply terminal and the first output. A PMOS transistor connected between the terminals, an NMOS transistor connected between the second output terminal and the ground terminal, and a controller that controls turning on and off of the PMOS transistor and the NMOS transistor according to a control signal. Be prepared.
　なお、以上の構成要素を任意に組み合わせたもの、構成要素や表現を、方法、装置、システムなどの間で相互に置換したものもまた、本発明あるいは本開示の態様として有効である。さらに、この項目（課題を解決するための手段）の記載は、本発明の欠くべからざるすべての特徴を説明するものではなく、したがって、記載されるこれらの特徴のサブコンビネーションも、本発明たり得る。 Note that arbitrary combinations of the above components, and mutual substitution of components and expressions among methods, devices, systems, etc., are also effective as aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not describe all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. .
　本開示のある態様によれば、負荷の誤動作を抑制できる。 According to an aspect of the present disclosure, malfunction of the load can be suppressed.
図１は、比較技術１に係る負荷駆動回路の回路図である。FIG. 1 is a circuit diagram of a load drive circuit according to comparative technique 1. 図２は、図１の負荷駆動回路の起動時の動作を説明するタイムチャートである。FIG. 2 is a time chart illustrating the operation of the load drive circuit of FIG. 1 at startup. 図３は、比較技術２に係る負荷駆動回路の回路図である。FIG. 3 is a circuit diagram of a load drive circuit according to comparative technique 2. 図４は、図３の負荷駆動回路の異常状態を説明する図である。FIG. 4 is a diagram illustrating an abnormal state of the load drive circuit of FIG. 3. 図５は、実施形態に係る負荷駆動回路の回路図である。FIG. 5 is a circuit diagram of the load drive circuit according to the embodiment. 図６は、第２出力端子が接地ラインとショートした異常状態における負荷駆動回路の等価回路図である。FIG. 6 is an equivalent circuit diagram of the load drive circuit in an abnormal state where the second output terminal is shorted to the ground line. 図７は、第１出力端子が電源ラインとショートした異常状態における負荷駆動回路の等価回路図である。FIG. 7 is an equivalent circuit diagram of the load drive circuit in an abnormal state where the first output terminal is shorted to the power supply line. 図８は、負荷駆動回路の起動時の動作を説明するタイムチャートである。FIG. 8 is a time chart illustrating the operation of the load drive circuit at startup. 図９は、負荷駆動回路のコントローラの構成例を示す回路図である。FIG. 9 is a circuit diagram showing a configuration example of a controller of a load drive circuit. 図１０は、負荷駆動回路のコントローラの別の構成例を示す回路図である。FIG. 10 is a circuit diagram showing another configuration example of the controller of the load drive circuit.
（実施形態の概要）
　本開示のいくつかの例示的な実施形態の概要を説明する。この概要は、後述する詳細な説明の前置きとして、実施形態の基本的な理解を目的として、１つまたは複数の実施形態のいくつかの概念を簡略化して説明するものであり、発明あるいは開示の広さを限定するものではない。この概要は、考えられるすべての実施形態の包括的な概要ではなく、すべての実施形態の重要な要素を特定することも、一部またはすべての態様の範囲を線引きすることも意図していない。便宜上、「一実施形態」は、本明細書に開示するひとつの実施形態（実施例や変形例）または複数の実施形態（実施例や変形例）を指すものとして用いる場合がある。 (Summary of embodiment)
1 provides an overview of some exemplary embodiments of the present disclosure. This Summary is intended to provide a simplified description of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments and as a prelude to the more detailed description that is presented later. It does not limit the size. This summary is not a comprehensive overview of all possible embodiments and does not intend to identify key elements of all embodiments or to delineate the scope of any or all aspects. For convenience, "one embodiment" may be used to refer to one embodiment (example or modification) or multiple embodiments (examples or modifications) disclosed in this specification.
　一実施形態に係る負荷駆動回路は、電源端子と、接地端子と、外部負荷の一端が接続されるべき第１出力端子と、外部負荷の他端が接続されるべき第２出力端子と、電源端子と第１出力端子の間に接続されたＰＭＯＳトランジスタと、第２出力端子と接地端子の間に接続されたＮＭＯＳトランジスタと、制御信号に応じて、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタのオン、オフを制御するコントローラと、を備える。 The load driving circuit according to one embodiment includes a power supply terminal, a ground terminal, a first output terminal to which one end of the external load is to be connected, a second output terminal to which the other end of the external load is to be connected, and a power supply terminal. A PMOS transistor connected between the terminal and the first output terminal, an NMOS transistor connected between the second output terminal and the ground terminal, and turning on and off of the PMOS transistor and the NMOS transistor according to the control signal is controlled. and a controller.
　この構成によると、制御信号がオフレベルであるときに、第１出力端子が電源ラインとショート（天絡）し、ＰＭＯＳトランジスタがバイパスされたとしても、ＮＭＯＳトランジスタによって電流が遮断されるため、外部負荷が誤動作するのを防止できる。また制御信号がオフレベルであるときに、第２出力端子が接地ラインとショート（地絡）し、ＮＭＯＳトランジスタがバイパスされたとしても、ＰＭＯＳトランジスタによって電流が遮断されるため、外部負荷が誤動作するのを防止できる。またシステムの起動時に、電源ラインの電圧が上昇する際に、ＰＭＯＳトランジスタのゲート電圧の上昇が遅れて、ＰＭＯＳトランジスタが一時的にオン状態となったとしても、ＮＭＯＳトランジスタによって電流が遮断されるため、外部負荷が誤動作するのを防止できる。 According to this configuration, even if the first output terminal is short-circuited to the power supply line and the PMOS transistor is bypassed when the control signal is at the off level, the current is cut off by the NMOS transistor, so the external It can prevent the load from malfunctioning. Furthermore, even if the second output terminal is shorted to the ground line (ground fault) and the NMOS transistor is bypassed when the control signal is at the off level, the current is cut off by the PMOS transistor, causing the external load to malfunction. can be prevented. Furthermore, when the voltage on the power supply line increases at system startup, even if the gate voltage of the PMOS transistor is delayed and the PMOS transistor is temporarily turned on, the current is cut off by the NMOS transistor. , it is possible to prevent external loads from malfunctioning.
　一実施形態において、コントローラは、制御信号のアサートに応答して、ＮＭＯＳトランジスタを先行してオンし、続いてＰＭＯＳトランジスタをオンしてもよい。 In one embodiment, the controller may first turn on the NMOS transistor and then turn on the PMOS transistor in response to assertion of the control signal.
　一実施形態において、コントローラは、制御信号のアサートに応答して、ＮＭＯＳトランジスタとＰＭＯＳトランジスタを同時にオンしてもよい。 In one embodiment, the controller may turn on the NMOS transistor and the PMOS transistor simultaneously in response to assertion of the control signal.
　一実施形態において、コントローラは、ＰＭＯＳトランジスタを駆動するプッシュプル構成の第１ドライバと、ＮＭＯＳトランジスタを駆動するプッシュプル構成の第２ドライバと、を含んでもよい。 In one embodiment, the controller may include a first driver with a push-pull configuration that drives a PMOS transistor, and a second driver with a push-pull configuration that drives an NMOS transistor.
　一実施形態において、コントローラは、ＰＭＯＳトランジスタを駆動する第１ドライバと、ＮＭＯＳトランジスタを駆動する第２ドライバと、を含んでもよい。 In one embodiment, the controller may include a first driver that drives a PMOS transistor and a second driver that drives an NMOS transistor.
　一実施形態において、外部負荷はヒューズであってもよい。 In one embodiment, the external load may be a fuse.
　一実施形態において、外部負荷は抵抗であってもよい。 In one embodiment, the external load may be a resistor.
　一実施形態において、外部負荷は発光素子であってもよい。 In one embodiment, the external load may be a light emitting device.
　一実施形態において、外部負荷はＯＴＰ（One-Time Programmable）メモリのセルであってもよい。 In one embodiment, the external load may be a one-time programmable (OTP) memory cell.
（実施形態）
　以下、好適な実施形態について、図面を参照しながら説明する。各図面に示される同一または同等の構成要素、部材、処理には、同一の符号を付するものとし、適宜重複した説明は省略する。また、実施形態は、開示および発明を限定するものではなく例示であって、実施形態に記述されるすべての特徴やその組み合わせは、必ずしも開示および発明の本質的なものであるとは限らない。 (Embodiment)
Hereinafter, preferred embodiments will be described with reference to the drawings. Identical or equivalent components, members, and processes shown in each drawing are designated by the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are illustrative rather than limiting the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.
　本明細書において、「部材Ａが、部材Ｂと接続された状態」とは、部材Ａと部材Ｂが物理的に直接的に接続される場合のほか、部材Ａと部材Ｂが、それらの電気的な接続状態に実質的な影響を及ぼさない、あるいはそれらの結合により奏される機能や効果を損なわせない、その他の部材を介して間接的に接続される場合も含む。 In this specification, "a state in which member A is connected to member B" refers to not only a case where member A and member B are physically directly connected, but also a state in which member A and member B are electrically connected. This also includes cases in which they are indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects achieved by their combination.
　同様に、「部材Ｃが、部材Ａと部材Ｂの間に接続された（設けられた）状態」とは、部材Ａと部材Ｃ、あるいは部材Ｂと部材Ｃが直接的に接続される場合のほか、それらの電気的な接続状態に実質的な影響を及ぼさない、あるいはそれらの結合により奏される機能や効果を損なわせない、その他の部材を介して間接的に接続される場合も含む。 Similarly, "a state in which member C is connected (provided) between member A and member B" refers to a state in which member A and member C or member B and member C are directly connected. In addition, it also includes cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.
　実施形態に係る負荷駆動回路を説明する前に、本発明者が検討した比較技術に係る負荷駆動回路について説明する。 Before explaining the load drive circuit according to the embodiment, a load drive circuit according to a comparative technique studied by the present inventor will be explained.
（比較技術１）
　図１は、比較技術１に係る負荷駆動回路１０の回路図である。負荷駆動回路１０は、制御信号ＥＮがアサート（オンレベル）であるとき、外部負荷２に駆動電流ＩＤＲＶを供給する。負荷駆動回路１０は、ＰＭＯＳトランジスタＭＰ１を含むオープンドレイン回路である。負荷駆動回路１０の電源端子ＶＤＤには電源電圧ＶＤＤが供給される。外部負荷２は、出力端子ＯＵＴと接地の間に接続される。図１では、外部負荷２を、簡単な抵抗のシンボルで示しているが、その種類は特に限定されず、ヒューズ、発光素子、ＯＴＰメモリのセルなどが例示される。 (Comparative technology 1)
FIG. 1 is a circuit diagram of a load drive circuit 10 according to comparative technique 1. The load drive circuit 10 supplies the drive current IDRV to the external load 2 when the control signal EN is asserted (on level). The load drive circuit 10 is an open drain circuit including a PMOS transistor MP1. A power supply voltage V DD is supplied to a power supply terminal V DD of the load drive circuit 10 . External load 2 is connected between output terminal OUT and ground. In FIG. 1, the external load 2 is shown by a simple resistance symbol, but its type is not particularly limited, and examples thereof include a fuse, a light emitting element, an OTP memory cell, and the like.
　ＰＭＯＳトランジスタＭＰ１は、電源端子ＶＤＤと出力端子ＯＵＴの間に接続される。ＰＭＯＳトランジスタＭＰ１のゲートソース間には、抵抗Ｒ１が接続される。キャパシタＣ１は、ＰＭＯＳトランジスタＭＰ１のゲート容量を表す。 The PMOS transistor MP1 is connected between the power supply terminal VDD and the output terminal OUT. A resistor R1 is connected between the gate and source of the PMOS transistor MP1. Capacitor C1 represents the gate capacitance of PMOS transistor MP1.
　ドライバ１２は、制御信号ＥＮに応じて、ＰＭＯＳトランジスタＭＰ１を駆動する。具体的には、ドライバ１２は、制御信号ＥＮがアサート（たとえばハイ）のとき、ＰＭＯＳトランジスタＭＰ１のゲートに、ロー電圧を印加し、ＰＭＯＳトランジスタＭＰ１をオンする。ドライバ１２は、制御信号ＥＮがネゲート（たとえばロー）のとき、ＰＭＯＳトランジスタＭＰ１のゲートに、ハイ電圧を印加し、ＰＭＯＳトランジスタＭＰ１をオフする。 The driver 12 drives the PMOS transistor MP1 according to the control signal EN. Specifically, when the control signal EN is asserted (eg, high), the driver 12 applies a low voltage to the gate of the PMOS transistor MP1 to turn on the PMOS transistor MP1. When the control signal EN is negated (for example, low), the driver 12 applies a high voltage to the gate of the PMOS transistor MP1 to turn off the PMOS transistor MP1.
　図１の負荷駆動回路１０において生ずる問題を説明する。 A problem that occurs in the load drive circuit 10 of FIG. 1 will be explained.
　図２は、図１の負荷駆動回路１０の起動時の動作を説明するタイムチャートである。制御信号ＥＮは、ネゲート（ロー）である。時刻ｔ１に、電源電圧ＶＣＣが上昇すると、ＰＭＯＳトランジスタＭＰ１のソース電圧ＶＤＤも上昇する。ＰＭＯＳトランジスタＭＰ１のゲートは、抵抗Ｒ１によってプルアップされているため、電源電圧ＶＣＣが上昇すると、それに追従して、ＰＭＯＳトランジスタＭＰ１のゲート電圧ＶＧも上昇する。 FIG. 2 is a time chart illustrating the operation of the load drive circuit 10 of FIG. 1 at startup. Control signal EN is negated (low). At time t1 , when the power supply voltage VCC rises, the source voltage VDD of the PMOS transistor MP1 also rises. Since the gate of the PMOS transistor MP1 is pulled up by the resistor R1, when the power supply voltage VCC rises, the gate voltage VG of the PMOS transistor MP1 also rises accordingly.
　電源電圧ＶＣＣの上昇が急峻である場合、ＰＭＯＳトランジスタＭＰ１のゲート容量の影響によってゲート電圧ＶＧの上昇は、ソース電圧ＶＤＤの上昇に対して遅れる。その結果、ＰＭＯＳトランジスタＭＰ１のゲートソース間電圧ＶＧＳが、起動直後、大きくなる。ゲートソース間電圧ＶＧＳが、ＭＯＳＦＥＴのしきい値電圧ＶＴＨを超える期間ｔ２～ｔ３、制御信号ＥＮがネゲートであるにもかかわらず、ＰＭＯＳトランジスタＭＰ１が導通し、リーク電流ＩＬＥＡＫが流れてしまう。その結果、外部負荷２が誤動作する。 When the power supply voltage V CC rises steeply, the rise of the gate voltage V G lags behind the rise of the source voltage V DD due to the influence of the gate capacitance of the PMOS transistor MP1. As a result, the gate-source voltage VGS of the PMOS transistor MP1 increases immediately after startup. During the period t 2 to t 3 in which the gate-source voltage V GS exceeds the threshold voltage V TH of the MOSFET, the PMOS transistor MP1 conducts even though the control signal EN is negated, and the leakage current I LEAK flows. I end up. As a result, the external load 2 malfunctions.
　また、電源電圧ＶＣＣが立ち上がった後、出力端子ＯＵＴが、電源ラインに対してショートすると、ＰＭＯＳトランジスタＭＰ１がバイパスされて、外部負荷２に電流が流れてしまう。 Furthermore, if the output terminal OUT is short-circuited to the power supply line after the power supply voltage VCC rises, the PMOS transistor MP1 is bypassed and current flows to the external load 2.
（比較技術２）
　図３は、比較技術２に係る負荷駆動回路２０の回路図である。負荷駆動回路２０は、ＮＭＯＳトランジスタＭＰ１を含むオープンドレイン回路であり、ＮＭＯＳトランジスタＭＮ１およびドライバ２２を備える。ＮＭＯＳトランジスタＭＮ１のソースは、接地端子ＧＮＤと接続され、そのドレインは、出力端子ＯＵＴと接続される。外部負荷２は、出力端子ＯＵＴと電源ラインＶＣＣの間に接続される。 (Comparative technology 2)
FIG. 3 is a circuit diagram of the load drive circuit 20 according to Comparative Technique 2. The load drive circuit 20 is an open drain circuit including an NMOS transistor MP1, and includes an NMOS transistor MN1 and a driver 22. The source of the NMOS transistor MN1 is connected to the ground terminal GND, and the drain thereof is connected to the output terminal OUT. External load 2 is connected between output terminal OUT and power supply line VCC .
　ドライバ２２は、制御信号ＥＮに応じて、ＮＭＯＳトランジスタＭＮ１を駆動する。具体的には、ドライバ２２は、制御信号ＥＮがアサート（たとえばハイ）のとき、ＮＭＯＳトランジスタＭＮ１のゲートに、ハイ電圧を印加し、ＮＭＯＳトランジスタＭＮ１をオンする。ドライバ２２は、制御信号ＥＮがネゲート（たとえばロー）のとき、ＮＭＯＳトランジスタＭＮ１のゲートに、ロー電圧を印加し、ＮＭＯＳトランジスタＭＮ１をオフする。 The driver 22 drives the NMOS transistor MN1 according to the control signal EN. Specifically, when the control signal EN is asserted (eg, high), the driver 22 applies a high voltage to the gate of the NMOS transistor MN1 to turn on the NMOS transistor MN1. When the control signal EN is negated (for example, low), the driver 22 applies a low voltage to the gate of the NMOS transistor MN1 to turn off the NMOS transistor MN1.
　図３の負荷駆動回路２０において生ずる問題を説明する。 A problem that occurs in the load drive circuit 20 of FIG. 3 will be explained.
　図４は、図３の負荷駆動回路２０の異常状態を説明する図である。具体的には、出力端子ＯＵＴが接地ラインとショートする異常が生じている。この場合、ＮＭＯＳトランジスタＭＮ１がオフしていても、ショート経路Ｐ１を介して、外部負荷２に電流ＩＬＥＡＫが流れてしまう。その結果、外部負荷２が誤動作する。 FIG. 4 is a diagram illustrating an abnormal state of the load drive circuit 20 of FIG. 3. Specifically, an abnormality has occurred in which the output terminal OUT is shorted to the ground line. In this case, even if the NMOS transistor MN1 is off, the current ILEAK flows to the external load 2 via the short path P1. As a result, the external load 2 malfunctions.
　続いて、実施形態に係る負荷駆動回路１００について説明する。 Next, the load drive circuit 100 according to the embodiment will be explained.
　図５は、実施形態に係る負荷駆動回路１００の回路図である。負荷駆動回路１００は、電源端子ＶＤＤ、第１出力端子ＯＵＴ１、第２出力端子ＯＵＴ２、接地端子ＧＮＤを有する。電源端子ＶＤＤは、電源ラインと接続され、電源電圧ＶＣＣが供給される。接地端子ＧＮＤは、接地される。外部負荷２は、第１出力端子ＯＵＴ１と第２出力端子ＯＵＴ２の間に接続される。 FIG. 5 is a circuit diagram of the load drive circuit 100 according to the embodiment. The load drive circuit 100 has a power supply terminal VDD, a first output terminal OUT1, a second output terminal OUT2, and a ground terminal GND. Power supply terminal VDD is connected to a power supply line and supplied with power supply voltage VCC . The ground terminal GND is grounded. External load 2 is connected between first output terminal OUT1 and second output terminal OUT2.
　負荷駆動回路１００は、ＰＭＯＳトランジスタＭＰ１、ＮＭＯＳトランジスタＭＮ１およびコントローラ１１０を備える。ＰＭＯＳトランジスタＭＰ１のソースは、電源端子ＶＤＤと接続され、ＰＭＯＳトランジスタＭＰ１のドレインは、第１出力端子ＯＵＴ１と接続される。ＰＭＯＳトランジスタＭＰ１のゲートは、抵抗Ｒ１によってプルアップされている。 The load drive circuit 100 includes a PMOS transistor MP1, an NMOS transistor MN1, and a controller 110. The source of the PMOS transistor MP1 is connected to the power supply terminal VDD, and the drain of the PMOS transistor MP1 is connected to the first output terminal OUT1. The gate of PMOS transistor MP1 is pulled up by resistor R1.
　ＮＭＯＳトランジスタＭＮ１のドレインは、第２出力端子ＯＵＴ２と接続され、ＮＭＯＳトランジスタＭＮ１のソースは、接地端子ＧＮＤと接続される。ＮＭＯＳトランジスタＭＮ１のゲートは、抵抗Ｒ２によってプルダウンされている。 The drain of the NMOS transistor MN1 is connected to the second output terminal OUT2, and the source of the NMOS transistor MN1 is connected to the ground terminal GND. The gate of NMOS transistor MN1 is pulled down by resistor R2.
　コントローラ１１０は、制御信号ＥＮに応じて、ＰＭＯＳトランジスタＭＰ１およびＮＭＯＳトランジスタＭＮ１のオン、オフを制御する。具体的には、制御信号ＥＮがアサート（たとえばハイ）のとき、コントローラ１１０は、ＰＭＯＳトランジスタＭＰ１のゲートにロー電圧（たとえば０Ｖ）を印加し、ＮＭＯＳトランジスタＭＮ１のゲートにハイ電圧（たとえば電源電圧ＶＤＤ）を印加し、ＰＭＯＳトランジスタＭＰ１、ＮＭＯＳトランジスタＭＮ１を両方、オン状態とする。 Controller 110 controls turning on and off of PMOS transistor MP1 and NMOS transistor MN1 according to control signal EN. Specifically, when the control signal EN is asserted (eg, high), the controller 110 applies a low voltage (eg, 0V) to the gate of the PMOS transistor MP1, and applies a high voltage (eg, power supply voltage V) to the gate of the NMOS transistor MN1. DD ) is applied to turn on both the PMOS transistor MP1 and the NMOS transistor MN1.
　反対に制御信号ＥＮがネゲート（たとえばロー）のとき、コントローラ１１０は、ＰＭＯＳトランジスタＭＰ１のゲートにハイ電圧（ＶＤＤ）を印加し、ＮＭＯＳトランジスタＭＮ１のゲートにロー電圧（０Ｖ）を印加し、ＰＭＯＳトランジスタＭＰ１、ＮＭＯＳトランジスタＭＮ１を両方、オフ状態とする。 Conversely, when the control signal EN is negated (for example, low), the controller 110 applies a high voltage (V DD ) to the gate of the PMOS transistor MP1, a low voltage (0V) to the gate of the NMOS transistor MN1, and Both transistor MP1 and NMOS transistor MN1 are turned off.
　たとえばコントローラ１１０は、第１ドライバＤＲ１、第２ドライバＤＲ２、ロジック回路１１２を備える。 For example, the controller 110 includes a first driver DR1, a second driver DR2, and a logic circuit 112.
　以上が負荷駆動回路１００の構成である。続いてその動作を説明する。 The above is the configuration of the load drive circuit 100. Next, its operation will be explained.
　図６は、第２出力端子ＯＵＴ２が接地ラインとショートした異常状態における負荷駆動回路１００の等価回路図である。制御信号ＥＮはネゲートであり、ＰＭＯＳトランジスタＭＰ１、ＮＭＯＳトランジスタＭＮ１は両方オフ状態である。 FIG. 6 is an equivalent circuit diagram of the load drive circuit 100 in an abnormal state where the second output terminal OUT2 is shorted to the ground line. The control signal EN is negated, and both the PMOS transistor MP1 and the NMOS transistor MN1 are in an off state.
　第２出力端子ＯＵＴ２が、経路Ｐ１を介して接地ラインと接続されると、ＮＭＯＳトランジスタＭＮ１がバイパスされるが、このとき、ＰＭＯＳトランジスタＭＰ１のオフ状態は維持されるため、外部負荷２は、電源ラインと切り離される。したがって負荷駆動回路１００によれば、第２出力端子ＯＵＴ２が地絡した場合に、外部負荷２が誤動作するのを防止できる。 When the second output terminal OUT2 is connected to the ground line via the path P1, the NMOS transistor MN1 is bypassed, but at this time, the PMOS transistor MP1 remains off, so the external load 2 separated from the line. Therefore, according to the load drive circuit 100, it is possible to prevent the external load 2 from malfunctioning when the second output terminal OUT2 is grounded.
　図７は、第１出力端子ＯＵＴ１が電源ラインとショートした異常状態における負荷駆動回路１００の等価回路図である。制御信号ＥＮはネゲートであり、ＰＭＯＳトランジスタＭＰ１、ＮＭＯＳトランジスタＭＮ１は両方オフ状態である。 FIG. 7 is an equivalent circuit diagram of the load drive circuit 100 in an abnormal state where the first output terminal OUT1 is shorted to the power supply line. The control signal EN is negated, and both the PMOS transistor MP1 and the NMOS transistor MN1 are in an off state.
　第１出力端子ＯＵＴ１が、経路Ｐ２を介して電源ラインと接続されると、ＰＭＯＳトランジスタＭＰ１がバイパスされるが、このとき、ＮＭＯＳトランジスタＭＮ１のオフ状態は維持されるため、外部負荷２は、接地ラインと切り離される。したがって負荷駆動回路１００によれば、第１出力端子ＯＵＴ１が天絡した場合に、外部負荷２が誤動作するのを防止できる。 When the first output terminal OUT1 is connected to the power supply line via the path P2, the PMOS transistor MP1 is bypassed, but at this time, the off state of the NMOS transistor MN1 is maintained, so the external load 2 is connected to the ground. separated from the line. Therefore, according to the load drive circuit 100, it is possible to prevent the external load 2 from malfunctioning when the first output terminal OUT1 is shorted to power.
　図８は、負荷駆動回路１００の起動時の動作を説明するタイムチャートである。制御信号ＥＮは、ネゲート（ロー）である。時刻ｔ１に、電源電圧ＶＣＣが上昇すると、ＰＭＯＳトランジスタＭＰ１のソース電圧ＶＤＤも上昇する。ＰＭＯＳトランジスタＭＰ１のゲートは、抵抗Ｒ１によってプルアップされているため、電源電圧ＶＣＣが上昇すると、それに追従して、ＰＭＯＳトランジスタＭＰ１のゲート電圧ＶＧも上昇する。 FIG. 8 is a time chart illustrating the operation of the load drive circuit 100 at startup. Control signal EN is negated (low). At time t1 , when the power supply voltage VCC rises, the source voltage VDD of the PMOS transistor MP1 also rises. Since the gate of the PMOS transistor MP1 is pulled up by the resistor R1, when the power supply voltage VCC rises, the gate voltage VG of the PMOS transistor MP1 also rises accordingly.
　電源電圧ＶＣＣの上昇が急峻である場合、ＰＭＯＳトランジスタＭＰ１のゲート容量の影響によってゲート電圧ＶＧの上昇は、ソース電圧ＶＤＤの上昇に対して遅れる。その結果、ＰＭＯＳトランジスタＭＰ１のゲートソース間電圧ＶＧＳが、起動直後、大きくなる。ゲートソース間電圧ＶＧＳが、ＭＯＳＦＥＴのしきい値電圧ＶＴＨを超える期間ｔ２～ｔ３、制御信号ＥＮがネゲートであるにもかかわらず、ＰＭＯＳトランジスタＭＰ１が導通する。 When the power supply voltage V CC rises steeply, the rise of the gate voltage V G lags behind the rise of the source voltage V DD due to the influence of the gate capacitance of the PMOS transistor MP1. As a result, the gate-source voltage VGS of the PMOS transistor MP1 increases immediately after startup. During the period t 2 to t 3 during which the gate-source voltage V GS exceeds the threshold voltage V TH of the MOSFET, the PMOS transistor MP1 becomes conductive even though the control signal EN is negated.
　一方、電源電圧ＶＣＣが上昇する際に、ＮＭＯＳトランジスタＭＮ１のゲートは、電源電圧ＶＣＣの変動の影響を受けないため、０Ｖを維持する。したがってＮＭＯＳトランジスタＭＮ１はオフ状態を維持することができる。これにより、外部負荷２にリーク電流ＩＬＥＡＫが流れるのを防止でき、外部負荷２の誤動作を防止できる。 On the other hand, when the power supply voltage V CC rises, the gate of the NMOS transistor MN1 maintains 0V because it is not affected by fluctuations in the power supply voltage V CC . Therefore, NMOS transistor MN1 can maintain an off state. Thereby, leakage current ILEAK can be prevented from flowing into the external load 2, and malfunction of the external load 2 can be prevented.
　続いて、コントローラ１１０の具体的な構成あるいは制御について説明する。 Next, the specific configuration or control of the controller 110 will be explained.
　図９は、負荷駆動回路１００のコントローラ１１０の構成例（１１０Ａ）を示す回路図である。コントローラ１１０Ａの第１ドライバＤＲ１、第２ドライバＤＲ２は、プッシュプル構成を有するＣＭＯＳインバータである。制御信号ＥＮは、そのままの論理で、第１ドライバＤＲ１に供給され、インバータ１１４によって反転された制御信号＼ＥＮは、第２ドライバＤＲ２に供給される。 FIG. 9 is a circuit diagram showing a configuration example (110A) of the controller 110 of the load drive circuit 100. The first driver DR1 and the second driver DR2 of the controller 110A are CMOS inverters having a push-pull configuration. The control signal EN is supplied to the first driver DR1 in its original logic, and the control signal \EN inverted by the inverter 114 is supplied to the second driver DR2.
　なお、第１ドライバＤＲ１のＰＭＯＳトランジスタは省略してもよい。同様に、第２ドライバＤＲ２のＮＭＯＳトランジスタを省略してもよい。 Note that the PMOS transistor of the first driver DR1 may be omitted. Similarly, the NMOS transistor of the second driver DR2 may be omitted.
　図１０は、負荷駆動回路１００のコントローラ１１０の別の構成例（１１０Ｂ）を示す回路図である。コントローラ１１０Ｂの第１ドライバＤＲ１、第２ドライバＤＲ２は、電流源ＣＳ１，ＣＳ２で構成される。制御信号ＥＮは、そのままの論理で、電流源ＣＳ１，ＣＳ２に供給される。つまり、ロジック回路１１２は単なる配線である。 FIG. 10 is a circuit diagram showing another configuration example (110B) of the controller 110 of the load drive circuit 100. The first driver DR1 and second driver DR2 of the controller 110B are composed of current sources CS1 and CS2. The control signal EN is supplied to the current sources CS1 and CS2 with its logic unchanged. In other words, the logic circuit 112 is just a wire.
　図９および図１０のコントローラ１１０Ａ，１１０Ｂによれば、制御信号ＥＮがアサートされると、ＰＭＯＳトランジスタＭＰ１とＮＭＯＳトランジスタＭＮ１それぞれのゲート電圧が、同時に変化し始め、実質的に同時にターンオンさせることができる。 According to the controllers 110A and 110B of FIGS. 9 and 10, when the control signal EN is asserted, the respective gate voltages of the PMOS transistor MP1 and the NMOS transistor MN1 begin to change simultaneously, and can be turned on substantially simultaneously. .
　コントローラ１１０は、ＰＭＯＳトランジスタＭＰ１とＮＭＯＳトランジスタＭＮ１を、時間差を付けてターンオンしてもよい。具体的には、コントローラ１１０は、制御信号ＥＮのアサートに応答して、ＮＭＯＳトランジスタＭＮ１のゲート電圧ＶＧ１を先行して上昇させてオンし、続いてＰＭＯＳトランジスタＭＰ１のゲート電圧ＶＧ２を低下させて、オンしてもよい。 The controller 110 may turn on the PMOS transistor MP1 and the NMOS transistor MN1 with a time difference. Specifically, in response to the assertion of the control signal EN, the controller 110 first increases the gate voltage V G1 of the NMOS transistor MN1 to turn it on, and then decreases the gate voltage V G2 of the PMOS transistor MP1. You can also turn it on.
（付記）
　本明細書に開示される技術は、一側面において以下のように把握される。 (Additional note)
One aspect of the technology disclosed in this specification can be understood as follows.
（項目１）
　電源端子と、
　接地端子と、
　外部負荷の一端が接続されるべき第１出力端子と、
　前記外部負荷の他端が接続されるべき第２出力端子と、
　前記電源端子と前記第１出力端子の間に接続されたＰＭＯＳトランジスタと、
　前記第２出力端子と前記接地端子の間に接続されたＮＭＯＳトランジスタと、
　制御信号に応じて、前記ＰＭＯＳトランジスタおよび前記ＮＭＯＳトランジスタのオン、オフを制御するコントローラと、
　を備える負荷駆動回路。 (Item 1)
power terminal and
a ground terminal;
a first output terminal to which one end of an external load is connected;
a second output terminal to which the other end of the external load is connected;
a PMOS transistor connected between the power supply terminal and the first output terminal;
an NMOS transistor connected between the second output terminal and the ground terminal;
a controller that controls turning on and off of the PMOS transistor and the NMOS transistor according to a control signal;
A load drive circuit comprising:
（項目２）
　前記コントローラは、前記制御信号のアサートに応答して、前記ＮＭＯＳトランジスタを先行してオンし、続いて前記ＰＭＯＳトランジスタをオンする、項目１に記載の負荷駆動回路。 (Item 2)
The load drive circuit according to item 1, wherein the controller first turns on the NMOS transistor and then turns on the PMOS transistor in response to assertion of the control signal.
（項目３）
　前記コントローラは、前記制御信号のアサートに応答して、前記ＮＭＯＳトランジスタと前記ＰＭＯＳトランジスタを同時にオンする、項目１に記載の負荷駆動回路。 (Item 3)
The load drive circuit according to item 1, wherein the controller turns on the NMOS transistor and the PMOS transistor simultaneously in response to assertion of the control signal.
（項目４）
　前記コントローラは、
　前記ＰＭＯＳトランジスタを駆動するプッシュプル構成の第１ドライバと、
　前記ＮＭＯＳトランジスタを駆動するプッシュプル構成の第２ドライバと、
　を含む、項目１から３のいずれかに記載の負荷駆動回路。 (Item 4)
The controller includes:
a first driver with a push-pull configuration that drives the PMOS transistor;
a second driver with a push-pull configuration that drives the NMOS transistor;
The load drive circuit according to any one of items 1 to 3, comprising:
（項目５）
　前記コントローラは、
　前記ＰＭＯＳトランジスタを駆動する第１ドライバと、
　前記ＮＭＯＳトランジスタを駆動する第２ドライバと、
　を含む、項目１から３のいずれかに記載の負荷駆動回路。 (Item 5)
The controller includes:
a first driver that drives the PMOS transistor;
a second driver that drives the NMOS transistor;
The load drive circuit according to any one of items 1 to 3, comprising:
（項目６）
　前記外部負荷はヒューズである、項目１から５のいずれかに記載の負荷駆動回路。 (Item 6)
6. The load drive circuit according to any one of items 1 to 5, wherein the external load is a fuse.
（項目７）
　前記外部負荷は抵抗である、項目１から５のいずれかに記載の負荷駆動回路。 (Item 7)
6. The load drive circuit according to any one of items 1 to 5, wherein the external load is a resistor.
（項目８）
　前記外部負荷は発光素子である、項目１から５のいずれかに記載の負荷駆動回路。 (Item 8)
6. The load drive circuit according to any one of items 1 to 5, wherein the external load is a light emitting element.
　本開示に係る実施形態について、具体的な用語を用いて説明したが、この説明は、理解を助けるための例示に過ぎず、本開示あるいは請求の範囲を限定するものではない。本発明の範囲は、請求の範囲によって規定されるものであり、したがって、ここでは説明しない実施形態、実施例、変形例も、本発明の範囲に含まれる。 Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to aid understanding, and does not limit the scope of the present disclosure or claims. The scope of the present invention is defined by the claims, and therefore embodiments, examples, and modifications not described here are also included within the scope of the present invention.
　本開示は、外付けされる負荷回路を駆動する負荷駆動回路に関する。 The present disclosure relates to a load drive circuit that drives an externally attached load circuit.
　１００　負荷駆動回路
　ＭＰ１　ＰＭＯＳトランジスタ
　ＭＮ１　ＮＭＯＳトランジスタ
　２　外部負荷
　ＶＤＤ　電源端子
　ＯＵＴ１　第１出力端子
　ＯＵＴ２　第２出力端子,
　ＧＮＤ　接地端子
　１１０　コントローラ
　ＤＲ１　第１ドライバ
　ＤＲ２　第２ドライバ
　１１２　ロジック回路 100 Load drive circuit MP1 PMOS transistor MN1 NMOS transistor 2 External load VDD Power supply terminal OUT1 First output terminal OUT2 Second output terminal,
GND Grounding terminal 110 Controller DR1 1st driver DR2 2nd driver 112 Logic circuit

Claims (8)

  1. 　電源端子と、
    　接地端子と、
    　外部負荷の一端が接続されるべき第１出力端子と、
    　前記外部負荷の他端が接続されるべき第２出力端子と、
    　前記電源端子と前記第１出力端子の間に接続されたＰＭＯＳトランジスタと、
    　前記第２出力端子と前記接地端子の間に接続されたＮＭＯＳトランジスタと、
    　制御信号に応じて、前記ＰＭＯＳトランジスタおよび前記ＮＭＯＳトランジスタのオン、オフを制御するコントローラと、
    　を備える、負荷駆動回路。     power terminal and
    a ground terminal;
    a first output terminal to which one end of an external load is connected;
    a second output terminal to which the other end of the external load is connected;
    a PMOS transistor connected between the power supply terminal and the first output terminal;
    an NMOS transistor connected between the second output terminal and the ground terminal;
    a controller that controls turning on and off of the PMOS transistor and the NMOS transistor according to a control signal;
    A load drive circuit comprising:
  2. 　前記コントローラは、前記制御信号のアサートに応答して、前記ＮＭＯＳトランジスタを先行してオンし、続いて前記ＰＭＯＳトランジスタをオンする、請求項１に記載の負荷駆動回路。 The load drive circuit according to claim 1, wherein the controller turns on the NMOS transistor first and then turns on the PMOS transistor in response to assertion of the control signal.
  3. 　前記コントローラは、前記制御信号のアサートに応答して、前記ＮＭＯＳトランジスタと前記ＰＭＯＳトランジスタを同時にオンする、請求項１に記載の負荷駆動回路。 The load drive circuit according to claim 1, wherein the controller turns on the NMOS transistor and the PMOS transistor simultaneously in response to assertion of the control signal.
  4. 　前記コントローラは、
    　前記ＰＭＯＳトランジスタを駆動するプッシュプル構成の第１ドライバと、
    　前記ＮＭＯＳトランジスタを駆動するプッシュプル構成の第２ドライバと、
    　を含む、請求項１から３のいずれかに記載の負荷駆動回路。     The controller includes:
    a first driver with a push-pull configuration that drives the PMOS transistor;
    a second driver with a push-pull configuration that drives the NMOS transistor;
    The load drive circuit according to any one of claims 1 to 3, comprising:
  5. 　前記コントローラは、
    　前記ＰＭＯＳトランジスタを駆動する第１ドライバと、
    　前記ＮＭＯＳトランジスタを駆動する第２ドライバと、
    　を含む、請求項１から３のいずれかに記載の負荷駆動回路。     The controller includes:
    a first driver that drives the PMOS transistor;
    a second driver that drives the NMOS transistor;
    The load drive circuit according to any one of claims 1 to 3, comprising:
  6. 　前記外部負荷はヒューズである、請求項１から３のいずれかに記載の負荷駆動回路。 The load drive circuit according to claim 1, wherein the external load is a fuse.
  7. 　前記外部負荷は抵抗である、請求項１から３のいずれかに記載の負荷駆動回路。 The load drive circuit according to any one of claims 1 to 3, wherein the external load is a resistor.
  8. 　前記外部負荷は発光素子である、請求項１から３のいずれかに記載の負荷駆動回路。 The load drive circuit according to any one of claims 1 to 3, wherein the external load is a light emitting element.
PCT/JP2023/024050 2022-07-04 2023-06-28 Load drive circuit WO2024009872A1 (en)

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JP2022-108013 2022-07-04

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006333278A (en) * 2005-05-30 2006-12-07 Denso Corp Driving device of on-vehicle electric load
JP2009278159A (en) * 2008-05-12 2009-11-26 Denso Corp Load driver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006333278A (en) * 2005-05-30 2006-12-07 Denso Corp Driving device of on-vehicle electric load
JP2009278159A (en) * 2008-05-12 2009-11-26 Denso Corp Load driver

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