WO2024009734A1 - リニア電源装置、および電源システム - Google Patents

リニア電源装置、および電源システム Download PDF

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Publication number
WO2024009734A1
WO2024009734A1 PCT/JP2023/022450 JP2023022450W WO2024009734A1 WO 2024009734 A1 WO2024009734 A1 WO 2024009734A1 JP 2023022450 W JP2023022450 W JP 2023022450W WO 2024009734 A1 WO2024009734 A1 WO 2024009734A1
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Prior art keywords
current
power supply
linear power
mirror
output
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PCT/JP2023/022450
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English (en)
French (fr)
Japanese (ja)
Inventor
勇武 岩橋
浩樹 猪上
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024531995A priority Critical patent/JPWO2024009734A1/ja
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

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  • the present disclosure relates to a linear power supply device and a power supply system.
  • linear power supplies linear regulators
  • linear regulators linear regulators
  • Some linear power supply devices use two linear power supply devices and commonly connect the output terminals of the respective linear power supply devices to a common load (for example, Patent Document 1). That is, such linear power supplies are connected in parallel to a common load.
  • the purpose of such a linear power supply is to disperse heat by distributing the load current into the output current output from the output terminals, or to increase the load current based on the output current output from each output terminal. The purpose is to do something.
  • an object of the present disclosure is to provide a linear power supply device that can effectively perform parallel operation in parallel connection applications, regardless of variations in the linear power supply devices.
  • a linear power supply device includes: A first main electrode configured to be connectable to an input voltage application terminal, and connectable to the first feedback resistor in a first feedback resistor, a second feedback resistor, and a third feedback resistor connected in series.
  • an output transistor having a second main electrode; a first error amplifier configured to receive a reference voltage and a feedback voltage generated at a first node to which the second feedback resistor and the third feedback resistor are connected, and to be able to drive a control end of the output transistor; , an output terminal connected to the second main electrode; a first mirror transistor configured to be able to generate a first mirror current of the current flowing through the output transistor; a second mirror transistor configured to be able to generate a second mirror current of the current flowing through the output transistor; a source terminal configured to be able to output the first mirror current to the outside; a sink terminal configured to be able to input a third mirror current and separate from the source terminal; The third mirror current and the second mirror current are compared, and based on the comparison result, the current is extracted from a second node to which the first feedback resistor and the second feedback resistor are connected, or to the second node.
  • the comparison unit is configured to inject a current.
  • linear power supply device in parallel connection applications, it is possible to effectively perform parallel operation regardless of variations in the linear power supply devices.
  • FIG. 1 is a diagram showing the configuration of a power supply system according to a comparative example.
  • FIG. 2 is a diagram showing the configuration of a linear power supply device according to an embodiment of the present disclosure.
  • FIG. 3 is a diagram showing the configuration of a power supply system according to an embodiment of the present disclosure.
  • FIG. 4 is a diagram showing the flow of current in the power supply system according to the embodiment of the present disclosure.
  • FIG. 5 is a diagram showing an example of waveforms of output current and output voltage.
  • FIG. 6 is a diagram showing the configuration of a power supply system according to a modification.
  • FIG. 7 is a diagram showing the configuration of a linear power supply device according to a modification.
  • FIG. 1 is a diagram showing the configuration of a power supply system 50 according to a comparative example.
  • the power supply system 50 includes a linear power supply device 10A, a linear power supply device 10B, and resistors Ra and Rb.
  • Power supply system 50 supplies load current Iout to load RL using two linear power supplies 10A and 10B.
  • the linear power supplies 10A and 10B are linear regulators that step down the input voltage Vin to generate desired output voltages VoA and VoB, respectively.
  • the linear power supply device 10A and the linear power supply device 10B are ICs (Integrated Circuits) with the same configuration, and corresponding components are designated with “A” or "B” for the same reference numerals. It is illustrated. Below, the configuration of the linear power supply device 10A will be representatively explained.
  • the linear power supply device 10A is an IC that includes an output transistor M10A, resistors R11A and 12A, and an error amplifier AP10A, and integrates these into one chip.
  • the source of the output transistor M10A configured as a PMOS transistor (P-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) is connected to the input terminal of the input voltage Vin.
  • the drain of the output transistor M10A and the first end of the resistor R11A are commonly connected to an output terminal ToA for outputting the output voltage VoA.
  • a second end of resistor R11A is connected to a first end of resistor R12A.
  • a second end of the resistor R12A is connected to a ground terminal.
  • the inverting input terminal (-) of the error amplifier AP10A is connected to the application terminal of the reference voltage VrefA.
  • the output terminal of the error amplifier AP10A is connected to the gate of the output transistor M
  • the on-resistance value of the output transistor M10B is continuously controlled so that the output voltage VoB matches its target value.
  • the output terminal ToA is connected to the first end of a resistor Ra provided outside the linear power supply devices 10A and 10B.
  • the output terminal ToB is connected to a first end of a resistor Rb provided outside the linear power supply devices 10A and 10B.
  • the second ends of each of the resistors Ra and Rb are commonly connected to the load RL. Therefore, linear power supplies 10A and 10B are connected in parallel to a common load RL.
  • the standard values (Typ values) of the output voltages VoA and VoB of the linear power supplies 10A and 10B are set to be the same, but due to variations in the linear power supplies, the output voltage may vary from the standard value. be. For example, it varies by ⁇ 2% with respect to the standard value of 5V. Such variations are caused by, for example, variations in the reference voltage, feedback voltage, or threshold voltage of the output transistor, as well as variations in the input offset voltage of the error amplifier.
  • the output voltage VoA when the output voltage VoA is higher than VoB, as the load current Iout gradually increases from 0 A, the output voltage VoA is dropped by the resistor Ra.
  • the output voltage Vo generated at the node to which the second ends of the resistors Ra and Rb are connected gradually decreases.
  • the output transistor M10B on the linear power supply device 10B side starts operating, and output of the output current IoutB from the output terminal ToB starts. That is, a parallel operation is started in which the load current Iout is supplied by both the output currents IoutA and IoutB.
  • the resistors Ra and Rb may be set to such resistance values that the voltage drop across the resistors is greater than or equal to the voltage difference between the maximum and minimum values due to variations in the output voltage.
  • this comparative example has problems in that loss and heat generation occur due to the resistors Ra and Rb, and that the output currents IoutA and IoutB are not equal. Further, when the load current Iout changes, the output voltage Vo changes due to the voltage drop caused by the resistors Ra and Rb, causing a problem in the function as a regulator.
  • FIG. 2 is a diagram showing the configuration of the linear power supply device 1 according to the embodiment of the present disclosure.
  • the linear power supply device 1 is a linear regulator that steps down the input voltage Vin to generate a desired output voltage Vo.
  • the linear power supply device 1 includes an output transistor M1, mirror transistors M2, M3, NMOS transistors (N-channel MOSFETs) NM1, NM2, feedback resistors R1, R2, R3, and an error amplifier AP1. , and a voltage protection element MP, which are integrated into one chip. Furthermore, the linear power supply device 1 has external terminals such as an output terminal To, a source terminal Tsr, and a sink terminal Tsk in order to establish an electrical connection with the outside.
  • the source of the output transistor M1 configured as a PMOS transistor is connected to the application terminal of the input voltage Vin.
  • a drain of output transistor M1 is connected to a first end of feedback resistor R1.
  • a second end of feedback resistor R1 is connected to a first end of feedback resistor R2.
  • a second end of feedback resistor R2 is connected to a first end of feedback resistor R3.
  • a second end of the feedback resistor R3 is connected to a ground terminal.
  • the inverting input terminal (-) of the error amplifier AP1 is connected to the application terminal of the reference voltage Vref.
  • the output terminal of the error amplifier AP1 is connected to the gate of the output transistor M1.
  • the source of the mirror transistor M2 configured as a PMOS transistor is connected to the application terminal of the input voltage Vin.
  • the drain of mirror transistor M2 is connected to the drain of voltage protection element MP configured as an NMOS transistor.
  • the source of the voltage protection element MP is connected to the source terminal Tsr.
  • a predetermined bias voltage Vbs is applied to the gate of the breakdown voltage protection element MP.
  • the gate of mirror transistor M2 is connected to the output terminal of error amplifier AP1.
  • a mirror current Im2 of the current flowing through the output transistor M1 flows through the mirror transistor M2.
  • the mirror current Im2 is, for example, several hundredths or several thousandths of the current flowing through the output transistor M1.
  • the mirror current Im2 flows through the voltage protection element MP and is output to the outside via the source terminal Tsr.
  • the current mirror circuit CM has an NMOS transistor NM1 on the input side and an NMOS transistor NM2 on the output side.
  • the drain and gate of NMOS transistor NM1 are short-circuited.
  • the drain of the NMOS transistor NM1 is connected to the sink terminal Tsk.
  • the gate of NMOS transistor NM1 and the gate of NMOS transistor NM2 are connected.
  • the source of the NMOS transistor NM1 and the source of the NMOS transistor NM2 are commonly connected to a ground terminal.
  • the source of the mirror transistor M3 configured as a PMOS transistor is connected to the application terminal of the input voltage Vin.
  • the drain of mirror transistor M3 is connected to the drain of NMOS transistor NM2.
  • the gate of mirror transistor M3 is connected to the output terminal of error amplifier AP1.
  • a mirror current Im3 of the current flowing through the output transistor M1 flows through the mirror transistor M3.
  • the mirror current Im3 is, for example, several hundredths or several thousandths of the current flowing through the output transistor M1.
  • Mirror current Im3 flows into node N1 to which mirror transistor M3 and NMOS transistor NM2 are connected.
  • the current Icm mirrored and output by the current mirror circuit CM and the mirror current Im3 are compared at the node N1.
  • the current Icm is larger than the mirror current Im3, the current is drawn from the node N2 to which the feedback resistor R1 and the feedback resistor R2 are connected to the node N1 side.
  • current Icm is smaller than mirror current Im3, current is injected into node N2.
  • Feedback voltage Vfb is adjusted according to current extraction/injection to node N2, and output voltage Vo is controlled.
  • FIG. 3 is a diagram showing the configuration of a power supply system 5 configured using the linear power supply device 1 according to the embodiment of the present disclosure.
  • the power supply system 5 includes a linear power supply device 1A and a linear power supply device 1B.
  • the power supply system 5 supplies a load current Iout to the load RL using two linear power supplies 1A and 1B.
  • the linear power supply device 1A and the linear power supply device 1B are the linear power supply device 1 (power supply IC) having the same configuration as explained in FIG. 2, and in FIG. Or "B" is added and illustrated.
  • the output terminal ToA of the linear power supply device 1A and the output terminal ToB of the linear power supply device 1B are commonly connected to the load RL. That is, linear power supply devices 1A and 1B are connected in parallel to a common load RL.
  • the source terminal TsrA of the linear power supply device 1A and the sink terminal TskB of the linear power supply device 1B are connected for transmission and reception of mirror current. Note that the source terminal TsrA and the sink terminal TskB are connected via a resistor R10. Resistor R10 receives the voltage difference between the source of voltage protection element MPA and the drain of NMOS transistor NM1B, and limits the current.
  • the breakdown voltage protection element MPA allows the NMOS transistor NM1B to be configured with a low breakdown voltage element.
  • the source terminal TsrB of the linear power supply device 1B and the sink terminal TskA of the linear power supply device 1A are connected for transmission and reception of mirror current. Note that the source terminal TsrB and the sink terminal TskA are connected via a resistor R20. Resistor R20 receives the voltage difference between the source of voltage protection element MPB and the drain of NMOS transistor NM1A, and limits the current.
  • the breakdown voltage protection element MPB allows the NMOS transistor NM1A to be configured with a low breakdown voltage element.
  • FIG. 5 is a waveform diagram showing an example of the operation of the power supply system 5 at startup.
  • the output voltage VoA of the linear power supply 1A when used alone is higher than the output voltage VoB of the linear power supply 1B when used alone (see FIG. 5).
  • VoA, VoB the output voltage of the linear power supply 1A when used alone
  • the output current IoutB is not initially output from the output terminal ToB of the linear power supply 1B, but is output from the output terminal ToA of the linear power supply 1A.
  • the load current Iout is supplied only by the output current IoutA. Note that the sum of the output current IoutA and the output current IoutB is the load current Iout.
  • the mirror transistor M2A outputs the mirror current Im2A from the source terminal TsrA to the outside.
  • a mirror current Im2A flows from the outside into the NMOS transistor NM1B via the sink terminal TskB.
  • the mirror current Im2A flowing through the NMOS transistor NM1B on the input side is mirrored by the current mirror circuit CMB, and becomes the current IcmB flowing through the NMOS transistor NM2B on the output side.
  • the mirror current Im3B by the mirror transistor M3B does not flow, the differential current In2B is drawn from the node N2B to the node N1B side. Therefore, feedback voltage VfbB is adjusted and output voltage VoB increases.
  • the differential current In2A increases and the output voltage VoA decreases. Then, when the output voltage VoA reaches VoB, the output current IoutB starts to be output from the output terminal ToB of the linear power supply device 1B (timing t1 in FIG. 5). That is, parallel operation of the linear power supplies 1A and 1B is started.
  • FIG. 6 is a diagram illustrating another configuration example of the power supply system 5 according to the embodiment of the present disclosure.
  • two linear power supply devices 1 are connected in parallel to the load RL, but as shown in FIG. 6, three linear power supply devices 1 (1A, 1B, 1B, 1C) may be connected in parallel.
  • the source terminal TsrA of the linear power supply 1A is connected to the sink terminal TskB of the linear power supply 1B, and the source terminal TsrB of the linear power supply 1B is connected to the sink terminal TskC of the linear power supply 1C.
  • the source terminal TsrC of the linear power supply device 1C is connected to the sink terminal TskA of the linear power supply device 1A.
  • FIG. 7 is a diagram showing the configuration of a linear power supply device 1 according to a modification. The difference between the configuration shown in FIG. 7 and the configuration shown in FIG. 2 described above is that a circuit including an error amplifier AP2 is used instead of the current mirror circuit CM as a comparison section for comparing mirror currents.
  • a circuit including an error amplifier AP2 is used instead of the current mirror circuit CM as a comparison section for comparing mirror currents.
  • the linear power supply device 1 shown in FIG. 7 includes an error amplifier AP2 and sense resistors Rs1 and Rs2.
  • the sink terminal Tsk is connected to the first end of the sense resistor Rs1.
  • a second end of the sense resistor Rs1 is connected to a ground terminal.
  • the drain of mirror transistor M3A is connected to the first end of sense resistor Rs2.
  • a second end of the sense resistor Rs2 is connected to a ground terminal.
  • the inverting input terminal (-) of the error amplifier AP2 is connected to the first terminal of the sense resistor Rs1.
  • a non-inverting input terminal (+) of the error amplifier AP2 is connected to a first terminal of the sense resistor Rs2.
  • the output terminal of error amplifier AP2 is connected to node N2.
  • a mirror current Im2 flowing from the outside via the sink terminal Tsk is converted into a voltage Vs1 by the sense resistor Rs1.
  • mirror current Im3 flowing through mirror transistor M3 is converted into voltage Vs2 by sense resistor Rs2.
  • the error amplifier AP2 extracts and injects a current In2 into the node N2 based on the difference between the input voltages Vs1 and Vs2. According to this embodiment, the output current Iout can be controlled with higher accuracy.
  • the linear power supply device (1) includes: A first main electrode configured to be connectable to an application terminal of an input voltage (Vin), and a first feedback resistor (R1), a second feedback resistor (R2), and a third feedback resistor (R3) connected in series. an output transistor (M1) having a second main electrode configured to be connectable to the first feedback resistor; A feedback voltage (Vfb) generated at a first node to which the second feedback resistor and the third feedback resistor are connected and a reference voltage (Vref) are input and configured to be able to drive the control end of the output transistor.
  • a first error amplifier AP1, an output terminal (To) connected to the second main electrode; a first mirror transistor (M2) configured to be able to generate a first mirror current (Im2) of the current flowing through the output transistor; a second mirror transistor (M3) configured to be able to generate a second mirror current (Im3) of the current flowing through the output transistor; a source terminal (Tsr) configured to be able to output the first mirror current to the outside; a sink terminal (Tsk) configured to be able to input a third mirror current and separate from the source terminal;
  • the third mirror current and the second mirror current are compared, and based on the comparison result, the current is extracted from the second node (N2) to which the first feedback resistor and the second feedback resistor are connected, or the current is extracted from the second node (N2) where the first feedback resistor and the second feedback resistor are connected.
  • a comparator CM configured to inject current into the two nodes; (first configuration).
  • a configuration may be adopted in which a breakdown voltage protection element (MP) is connected between the first mirror transistor (M2) and the source terminal (Tsr) (second configuration).
  • MP breakdown voltage protection element
  • the breakdown voltage protection element may be configured with an NMOS transistor having a gate to which a bias voltage (Vbs) can be applied (third configuration).
  • the comparison section may include a current mirror circuit (CM) that mirrors and outputs the third mirror current (fourth configuration).
  • CM current mirror circuit
  • the comparison unit a first sense resistor (Rs1) that converts the third mirror current into a first voltage (Vs1); a second sense resistor (Rs2) that converts the second mirror current into a second voltage (Vs2);
  • a second error amplifier (AP2) may be configured to extract current from the second node or inject current into the second node based on the difference between the first voltage and the second voltage. 5 configuration).
  • a power supply system (5) includes a plurality of linear power supply devices (1) having any of the above configurations,
  • the output terminals (To) of each of the plurality of linear power supply devices can be commonly connected to a load (RL),
  • the source terminal (Tsr) and the sink terminal (Tsk) are sequentially connected between different linear power supply devices (sixth configuration).
  • the source terminal (Tsr) and the sink terminal (Tsk) may be connected via resistors (R10, R20) (seventh configuration).
  • the present disclosure can be used in power supply systems installed in various devices.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
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  • Automation & Control Theory (AREA)
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PCT/JP2023/022450 2022-07-06 2023-06-16 リニア電源装置、および電源システム Ceased WO2024009734A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04322129A (ja) * 1991-04-23 1992-11-12 Fujitsu Ltd 電源ユニット
JPH11122814A (ja) * 1997-10-07 1999-04-30 Fuji Electric Co Ltd 直流安定化電源の並列運転方式
JP2007143292A (ja) * 2005-11-18 2007-06-07 Cosel Co Ltd 並列運転電源システム
JP2016031719A (ja) * 2014-07-30 2016-03-07 新日本無線株式会社 シリーズレギュレータ
JP2020004214A (ja) * 2018-06-29 2020-01-09 ローム株式会社 リニアレギュレータ

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04322129A (ja) * 1991-04-23 1992-11-12 Fujitsu Ltd 電源ユニット
JPH11122814A (ja) * 1997-10-07 1999-04-30 Fuji Electric Co Ltd 直流安定化電源の並列運転方式
JP2007143292A (ja) * 2005-11-18 2007-06-07 Cosel Co Ltd 並列運転電源システム
JP2016031719A (ja) * 2014-07-30 2016-03-07 新日本無線株式会社 シリーズレギュレータ
JP2020004214A (ja) * 2018-06-29 2020-01-09 ローム株式会社 リニアレギュレータ

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