WO2024001703A1 - 存储装置 - Google Patents

存储装置 Download PDF

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Publication number
WO2024001703A1
WO2024001703A1 PCT/CN2023/098720 CN2023098720W WO2024001703A1 WO 2024001703 A1 WO2024001703 A1 WO 2024001703A1 CN 2023098720 W CN2023098720 W CN 2023098720W WO 2024001703 A1 WO2024001703 A1 WO 2024001703A1
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WO
WIPO (PCT)
Prior art keywords
memory
memory unit
interposer
branch
electrically connected
Prior art date
Application number
PCT/CN2023/098720
Other languages
English (en)
French (fr)
Inventor
梅萌
张颖
柳琳
李继峰
王剑
Original Assignee
北京有竹居网络技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 北京有竹居网络技术有限公司 filed Critical 北京有竹居网络技术有限公司
Publication of WO2024001703A1 publication Critical patent/WO2024001703A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]

Definitions

  • Example embodiments of the present disclosure relate generally to the field of computers, and in particular to a storage device.
  • Double Data Rate Synchronous Dynamic Random Access Memory can transmit data twice in one clock cycle, that is, in the rising and falling periods of the clock. one time data.
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • LPDDR SDRAM Low-power DDR SDRAM
  • LPDDR memory is a type of DDR SDRAM, known for its low power consumption and small size, and is specially used in mobile electronic products.
  • multiple small-capacity DDR SDRAM chips are often used to form a large-capacity storage device. For example, four 2GB chips are used to form an 8GB storage device. In this process, considering the actual wiring on the printed circuit board (PCB), multiple DDR SDRAM chips need to adopt a specific topology to meet timing requirements.
  • PCB printed circuit board
  • DDR memory In the case of using four chips to form a large-capacity storage device, for DDR memory, four separate chips can be used to form a four-grain single-channel DDR memory, while for LPDDR memory, four chips can be packaged together to form a single-grain four-channel DDR memory. Channel LPDDR memory. If a set of command and address lines (CA lines for short) are used, the conventional topologies that can be used by four chips include Fly-by topology, T+Fly-by topology and double T topology.
  • CA lines command and address lines
  • a storage device in a first aspect of the present disclosure, includes: a printed circuit board; an interposer arranged on the printed circuit board; a memory unit group arranged on the interposer layer; a control unit arranged on the printed circuit board and configured to control the memory unit group; and A transmission line is electrically connected between the control unit and the memory unit group and is configured to transmit commands or addresses.
  • the first transmission line includes a trunk electrically connected to the control unit, a first-level branch electrically connected to the trunk, and a first-level branch electrically connected to the trunk.
  • the second-level branch of the first-level branch is electrically connected to the memory unit group, wherein the main trunk and the first-level branch are arranged in the printed circuit board, and the second-level branch is arranged in the interposer layer.
  • Figure 1 shows a topological structure diagram of a storage device according to some embodiments of the present disclosure
  • FIGS. 2A and 2B show a schematic structural diagram of a transmission line according to some embodiments of the present disclosure
  • Figure 3 shows a schematic structural diagram of a storage device according to some embodiments of the present disclosure
  • Figure 4 shows a schematic diagram of a relative arrangement of memory cells and interposers in the memory device shown in Figure 3;
  • Figure 5 shows a schematic diagram of another relative arrangement of memory cells and interposers in the memory device shown in Figure 3;
  • Figure 6 shows a schematic structural diagram of a storage device according to some embodiments of the present disclosure. picture
  • Figure 7 shows a schematic diagram of a relative arrangement of memory cells and interposers in the memory device shown in Figure 6;
  • FIG. 8 shows a schematic diagram of another relative arrangement of memory cells and interposers in the memory device shown in FIG. 6 .
  • the conventional topologies that can be used by four chips include Fly-by topology, T+Fly-by topology and double-T topology. Double T topology is simpler than Fly-by topology and T+Fly-by topology in terms of overall timing control.
  • the PCB design of double T topology is more difficult to implement.
  • Figure 1 shows a topology diagram of a storage device according to some embodiments of the present disclosure.
  • the storage device 100 has a double-T topology, which includes a control unit 11 , a storage unit group 13 and a first transmission line 12 .
  • the first transmission line 12 is connected between the control unit 11 and the memory unit group 13 for transmitting commands or addresses.
  • the control unit 11 can control the memory unit group 13 via the first transmission line 12 , for example, to implement read and write operations on the memory units in the memory unit group 13 .
  • the memory unit group 13 includes a first memory unit unit 13-1, second storage unit 13-2, third storage unit 13-3 and fourth storage unit 13-4.
  • the first transmission line 12 includes a trunk 120 electrically connected to the control unit 11 , a first-level branch 121 electrically connected to the trunk 120 , and a second-level branch 122 electrically connected to the first-level branch 121 .
  • the first level branch 121 includes a first branch line 121-1 and a second branch line 121-2 electrically connected to the trunk 120.
  • the second level branch 122 includes a first sub-branch 122-1 and a second sub-branch 122-2 electrically connected to the first branch 121-1 and a third sub-branch 122-3 electrically connected to the second branch 121-2.
  • the fourth sub-branch 122-4 The first sub-branch line 122-1 is electrically connected to the first memory unit 13-1.
  • the second sub-branch line 122-2 is electrically connected to the second memory unit 13-2.
  • the third sub-branch line 122-3 is electrically connected to the third storage unit 13-3.
  • the fourth sub-branch line 122-4 is electrically connected to the fourth memory unit 13-4.
  • each of the first memory unit 13-1, the second memory unit 13-2, the third memory unit 13-3, and the fourth memory unit 13-4 is a DDR SDRAM.
  • the control unit 11 is a DDR controller.
  • DDR SDRAM and DDR controller will be used as examples to describe the principles of the present disclosure.
  • the DDR SDRAM and DDR controller are exemplary only and are not intended to limit the scope of the present disclosure.
  • each of the first storage unit 13-1, the second storage unit 13-2, the third storage unit 13-3, and the fourth storage unit 13-4 may be other types of storage units.
  • the control unit 11 may also be other types of control units.
  • the characteristic impedance of the first transmission line 12 is from the trunk 120 to the first-level branch 121 and from the first-level branch 121 to the second-level branch 122. All need to be doubled.
  • the impedance of the trunk 120 may be 30 ohms.
  • the first branch line 121-1 and the second branch line 121-2 in the first-level branch 121 The impedance should be 60 ohms, and the impedance of the first sub-branch 122-1, the second sub-branch 122-2, the third sub-branch 122-3 and the fourth sub-branch 122-4 in the second-level branch 122 should be 120 ohm.
  • the numbers, values, etc. that may be mentioned above and elsewhere in this disclosure are exemplary and are not intended to limit the scope of the disclosure in any way. Any other suitable numbers, values are possible.
  • transmission lines with characteristic impedances of 30 ohms and 60 ohms are relatively easy to implement, but transmission lines with high characteristic impedance of 120 ohms are difficult to implement.
  • the distance between the transmission line 25 and the reference planes 20 and 23 is directly increased, thus correspondingly increasing the distance between the transmission line 25 and the reference planes 20 and 23 The thickness of the dielectric layer between them. In this way, the characteristic impedance of the transmission line 25 can also be increased.
  • embodiments of the present disclosure provide a transmission line layout solution.
  • an interposer is inserted between the storage unit and the PCB.
  • the trunk and first-level branches of the transmission line are arranged in the PCB, while the second-level branches of the transmission line are arranged in the interposer.
  • the increase in the number of extra layers on the PCB can be avoided, and the wiring space of the PCB can be released, thereby overall reducing the cost of the storage device and improving the reliability of the storage device.
  • Exemplary embodiments of the storage device will be described below with reference to FIGS. 3 to 8 .
  • FIG. 3 shows a schematic structural diagram of a storage device according to some embodiments of the present disclosure
  • FIG. 4 shows a schematic diagram of a relative arrangement of storage units and interposers in the storage device shown in FIG. 3
  • FIG. 4 is the relative arrangement of the memory cells 13-1, 13-2, 13-3, and 13-4 and the interposer 15 when viewed along the direction indicated by arrow 40 in FIG. 3.
  • the storage device 300 shown in FIG. 3 can be regarded as one of the storage devices 100 shown in FIG. 1 Implementation.
  • the storage device 300 includes a PCB 10, an interposer layer 15, a storage unit group 13, a control unit 11 and a first transmission line 12.
  • the interposer 15 is disposed on the PCB 10 and is electrically connected to the PCB 10 through solder balls 18 .
  • the memory cell group 13 is arranged on the interposer 15 and is electrically connected to the interposer 15 through solder balls 19 . With such an arrangement, the interposer 15 is able to pass signals between the PCB 10 and the memory cell group 13.
  • the control unit 11 is arranged on the PCB 10 and is electrically connected to the PCB 10 through solder balls 17 to control the memory unit group 13 via the first transmission line 12.
  • the interposer 15 is a single interposer, and the first storage unit 13-1, the second storage unit 13-2, the third storage unit 13-3 and the fourth storage unit
  • the units 13 - 4 are arranged separately from each other on the interposer 15 .
  • the first memory unit 13 - 1 , the second memory unit 13 - 2 , the third memory unit 13 - 3 and the fourth memory unit 13 - 4 are individually packaged and individually arranged on the interposer layer 15 .
  • the first transmission line 12 is electrically connected between the control unit 11 and the memory unit group 13 .
  • FIG. 3 only the first branch line 121 - 1 in the first level branch 121 of the transmission line 12 and the first sub-branch line 122 - 1 and the second sub-branch line 122 - 1 in the second level branch 122 that are electrically connected to the first branch line 121 - 1 are shown.
  • the second branch line 121-2 in the first-level branch 121 of the transmission line 12 and the third sub-branch line 121 in the second-level branch 122 electrically connected to the second branch line 121-2 are not shown.
  • -3 and the fourth sub-branch 122-4 in order to clearly show the structural details in the storage device 300.
  • the second branch line 121-2 in the first-level branch 121 and the third sub-branch line 121-3 and the fourth sub-branch line 122-4 in the second-level branch 122 may be connected with the first branch line 121-2 in the first-level branch 121.
  • the branch line 121-1 and the first sub-branch line 122-1 and the second sub-branch line 122-2 in the second-level branch 122 are arranged in a similar manner.
  • the trunk 120 of the first transmission line 12 and the first branch 121 - 1 of the first level branches 121 are arranged in the PCB 10
  • the second level branches 122 of the first transmission line 12 are arranged in the PCB 10
  • the first sub-branch line 122-1 and the second sub-branch line 122-2 are arranged in the interposer 15.
  • the trunk 120 is electrically connected to a via hole 101 - 1 provided in the PCB 10
  • the via hole 101 - 1 is electrically connected to the control unit 11 via the solder ball 17 .
  • first level branch 121 One end of the first branch line 121-1 is electrically connected to the trunk 120, and the other end is electrically connected to the via hole 101-2 provided in the PCB 10.
  • the via hole 101-2 is electrically connected to the via hole 101-2 provided in the interposer 15 through the solder ball 18. of via 151-1.
  • One ends of the first sub-branch line 122-1 and the second sub-branch line 122-2 in the second-level branch 122 are electrically connected to the via hole 151-1 respectively.
  • the other end of the first sub-branch 122-1 is electrically connected to the via hole 151-2 provided in the interposer 15, and the via hole 151-2 is electrically connected to the memory unit 13-1 through the solder ball 19.
  • the other end of the second sub-branch line 122-2 is electrically connected to the via hole 151-3 provided in the interposer layer 15, and the via hole 151-3 is electrically connected to the memory unit 13-2 through the solder ball 19.
  • the second branch line 121-2 in the first-level branch 121 of the first transmission line 12 may be arranged in the PCB 10, and the third sub-branch line 122-3 and the second-level branch line 122 in the second-level branch 122 of the first transmission line 12.
  • Four sub-branch lines 122 - 4 may be arranged in the interposer 15 .
  • the second branch line 121-2 in the first-level branch 121 may be electrically connected to the third sub-branch line 122-3 and the fourth sub-branch line 122-4 in the second-level branch 122 through via holes and solder balls.
  • the third sub-branch line 122-3 and the fourth sub-branch line 122-4 in the second-level branch 122 may also be electrically connected to the memory cells 13-3 and 13-4 respectively through via holes and solder balls.
  • the specific arrangement of the second branch line 121-2 in the first-level branch 121 and the third sub-branch line 122-3 and the fourth sub-branch line 122-4 in the second-level branch 122 of the first transmission line 12 will not be discussed here. Repeat.
  • the trunk 120 of the first transmission line 12 and the first branch line 121-1 in the first level branch 121 may be formed in the same layer of the PCB 10. In other embodiments, the trunk 120 of the first transmission line 12 and the first branch line 121-1 in the first level branch 121 may be formed in different layers of the PCB 10 and connected through vias provided in the PCB 10.
  • the trunk 120 of the first transmission line 12 and the second branch line 121 - 2 in the first level branch 121 may be formed in the same layer of the PCB 10 .
  • the trunk 120 of the first transmission line 12 and the second branch line 121 - 2 in the first level branch 121 may be formed in different layers of the PCB 10 and connected through vias provided in the PCB 10 .
  • the first branch line 121-1 and the second branch line 121-2 in the first-level branch 121 may be formed in the same layer or different layers of the PCB 10, and embodiments of the present disclosure are not limited in this regard.
  • the second-level branch 122 of the first transmission line 12 in the interposer 15, the increase in the number of additional layers on the PCB 10 can be avoided, so that the PCB 10 can still adopt a conventional design and only use a smaller interposer 15 It is possible to provide a second stage branch 122 with a high characteristic impedance. In this way, on the one hand, a sharp increase in the cost of the storage device can be prevented, and on the other hand, the wiring space of the PCB can be released, thereby improving the reliability of the storage device.
  • the interposer 15 includes a packaging substrate in which the second level branch 122 is disposed. In other embodiments, the interposer 15 includes another printed circuit board in which the second level branch 122 is disposed. Compared with the manufacturing process of the printed circuit board, the manufacturing process of the packaging substrate can achieve a thinner line width, so when the second-level branch 122 is arranged in the packaging substrate, the crosstalk introduced on the second-level branch 122 can be optimized. , further improving the reliability of the storage device.
  • the storage device 300 further includes a second transmission line 16 .
  • the second transmission line 16 is electrically connected between the control unit 11 and the memory unit group 13 for transmitting data.
  • the second transmission line 16 is arranged in the PCB 10.
  • One end of the second transmission line 16 is electrically connected to the via hole 101-3 provided in the PCB 10, and the other end is electrically connected to the via hole 101-4 provided in the PCB 10.
  • the via hole 101 - 3 is electrically connected to the control unit 11 through the solder balls 17 .
  • Via 101 - 4 is electrically connected to via 151 - 4 provided in interposer 15 through solder balls 18 .
  • the via 151 - 4 is electrically connected to the memory cell 13 - 1 through the solder ball 19 .
  • the control unit 11 and other storage units in the storage unit group 13 can use data transmission lines for data transmission in a similar manner, which will not be described again.
  • the size of interposer 15 may be close to the size of memory cell group 13 . In some embodiments, the size of the interposer 15 may be larger than the size of the memory unit group 13 in order to set a test point thereon for testing signals of the memory device 300 . By introducing such test points, subsequent testing of high-speed signals of the storage device 300 can be facilitated.
  • FIG. 5 shows a schematic diagram of another relative arrangement of memory cells and interposers in the memory device shown in FIG. 3 .
  • Figure 5 is another view of the memory cells 13-1, 13-2, 13-3 and 13-4 and the interposer 15 when viewed along the direction indicated by arrow 40 in Figure 3 relatively arranged.
  • the interposer layer 15 includes a first interposer layer 15 - 1 and a second interposer layer 15 - 2 .
  • the first memory unit 13-1 and the second memory unit 13-2 are individually arranged on the first interposer layer 15-1.
  • the third memory unit 13-3 and the fourth memory unit 13-4 are individually arranged on the second interposer layer 15-2.
  • the first interposer layer 15-1 and the second interposer layer 15-2 are arranged on the same side of the PCB 10. In other embodiments, the first interposer layer 15-1 and the second interposer layer 15-2 may be disposed on different sides of the PCB 10. The embodiments of the present disclosure are not limited in this regard.
  • At least a portion of the memory cells 13 - 1 , 13 - 2 , 13 - 3 and 13 - 4 may be packaged into a single package and then placed on the interposer 15 . This arrangement will be described below with reference to FIGS. 6 to 8 .
  • Figure 6 shows a schematic structural diagram of a memory device according to some embodiments of the present disclosure.
  • Figure 7 shows a schematic diagram of a relative arrangement of memory units and interposers in the memory device shown in Figure 6.
  • Figure 8 shows A schematic diagram of another relative arrangement of the memory cells and the interposer in the memory device shown in FIG. 6 is shown.
  • the storage device 400 shown in FIG. 6 has a similar structure to the storage device 300 shown in FIG. 3 . The only difference is that at least part of the storage units 13-1, 13-2, 13-3 and 13-4 can be packaged into a single package. The parts that are the same between the two will not be repeated here, but the differences between the two will be described in detail.
  • the first memory unit 13-1, the second memory unit 13-2, the third memory unit 13-3 and the fourth memory unit 13-4 are packaged into a single Package 30.
  • Package 30 is electrically connected to interposer 15 through solder balls 19 .
  • the interposer 15 includes a first interposer 15 - 1 and a second interposer 15 - 2 .
  • the first memory unit 13-1 and the second memory unit 13-2 are packaged into a single package 30-1.
  • the third memory unit 13-3 and the fourth memory unit 13-4 are packaged into a single package 30-2.
  • Package 30 - 1 is electrically connected to first interposer 15 - 1 through solder balls 19 .
  • Package 30 - 2 is electrically connected to second interposer 15 - 2 through solder balls 19 .
  • the first interposer layer 15 - 1 and the second interposer layer 15 - 2 are disposed on the same side of the PCB 10 .
  • the first interposer layer 15-1 and the second interposer layer 15-2 may be disposed on different sides of the PCB 10 superior.
  • the embodiments of the present disclosure are not limited in this regard.
  • the second-level branch of the transmission line for transmitting commands or addresses in the interposer layer by arranging the second-level branch of the transmission line for transmitting commands or addresses in the interposer layer, the increase in the number of extra layers on the PCB can be avoided, thereby reducing the cost of the overall system.
  • the wiring space of the PCB can be released and the crosstalk part of the signal integrity can be optimized.

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Abstract

本公开的实施例涉及一种存储装置。该存储装置包括：印刷电路板；中介层，布置在印刷电路板上；存储单元组，布置在中介层上；控制单元，布置在印刷电路板上，并且被配置为控制存储单元组；以及第一传输线，电连接在控制单元与存储单元组之间，并且被配置为传输命令或地址，第一传输线包括电连接至控制单元的主干、电连接至主干的第一级分支、以及电连接至第一级分支的第二级分支，第二级分支电连接至存储单元组，其中主干和第一级分支布置在印刷电路板中，第二级分支布置在中介层中。

Description

存储装置
本申请要求2022年6月29日递交的申请号为202210764909.9、标题为“存储装置”的中国发明专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开的示例实施例总体涉及计算机领域，特别地涉及一种存储装置。
背景技术
双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，缩写为DDR SDRAM，也简称为DDR内存)能够在一个时钟周期内传输两次数据，即在时钟的上升期和下降期各传输一次数据。低功耗DDR SDRAM(缩写为LPDDR SDRAM，也简称为LPDDR内存)是DDR SDRAM的一种，以低功耗和小体积著称，专门用于移动式电子产品。
由于单片存储芯片的存储容量与价格之间的因素，经常使用多片小容量DDR SDRAM芯片组成大容量存储装置，例如使用四片2GB芯片的组成8GB的存储装置。在这个过程中，考虑到在印刷电路板(PCB)上实际布线的因素，多片DDR SDRAM芯片需要采用特定的拓扑结构来满足时序的要求。
在采用四片芯片组成大容量存储装置的情况下，对于DDR内存，可以采用四片单独的芯片形成四颗粒单通道DDR内存，而对于LPDDR内存，可以将四片芯片封装在一起形成单颗粒四通道LPDDR内存。如果采用一组命令和地址线(简称CA线)，四片芯片可以采用的常规拓扑结构包括Fly-by拓扑、T+Fly-by拓扑和双T拓扑。
发明内容
在本公开的第一方面，提供了一种存储装置。该存储装置包括：印刷电路板；中介层，布置在印刷电路板上；存储单元组，布置在中介层上；控制单元，布置在印刷电路板上，并且被配置为控制存储单元组；以及第一传输线，电连接在控制单元与存储单元组之间，并且被配置为传输命令或地址，第一传输线包括电连接至控制单元的主干、电连接至主干的第一级分支、以及电连接至第一级分支的第二级分支，第二级分支电连接至存储单元组，其中主干和第一级分支布置在印刷电路板中，第二级分支布置在中介层中。
应当理解，该内容部分中所描述的内容并非旨在限定本公开的实施例的关键特征或重要特征，也不用于限制本公开的范围。本公开的其它特征将通过以下的描述而变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标记表示相同或相似的元素，其中：
图1示出了根据本公开的一些实施例的存储装置的拓扑结构图；
图2A和图2B示出了根据本公开的一些实施例的传输线的结构示意图；
图3示出了根据本公开的一些实施例的存储装置的结构示意图；
图4示出了图3中所示的存储装置中的存储单元与中介层的一种相对布置的示意图；
图5示出了图3中所示的存储装置中的存储单元与中介层的另一种相对布置的示意图；
图6示出了根据本公开的一些实施例的存储装置的结构示意 图；
图7示出了图6中所示的存储装置中的存储单元与中介层的一种相对布置的示意图；以及
图8示出了图6中所示的存储装置中的存储单元与中介层的另一种相对布置的示意图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中示出了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反，提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“一些实施例”应当理解为“至少一些实施例”。下文还可能包括其他明确的和隐含的定义。
如上文中所述，对于四颗粒DDR内存或四通道LPDDR内存，四片芯片可以采用的常规拓扑结构包括Fly-by拓扑、T+Fly-by拓扑和双T拓扑。双T拓扑在整体的时序控制上比Fly-by拓扑以及T+Fly-by拓扑更简单，然而双T拓扑的PCB设计却比较难实现。
图1示出了根据本公开的一些实施例的存储装置的拓扑结构图。如图1所示，该存储装置100具有双T拓扑，其包括控制单元11、存储单元组13和第一传输线12。第一传输线12连接在控制单元11与存储单元组13之间，用于传输命令或地址。控制单元11可以经由第一传输线12来控制存储单元组13，例如实现对存储单元组13中的存储单元的读写操作。
在一些实施例中，如图1所示，存储单元组13包括第一存储单 元13-1、第二存储单元13-2、第三存储单元13-3和第四存储单元13-4。第一传输线12包括电连接至控制单元11的主干120、电连接至主干120的第一级分支121、以及电连接至第一级分支121的第二级分支122。第一级分支121包括电连接至主干120的第一支线121-1和第二支线121-2。第二级分支122包括电连接至第一支线121-1的第一子支线122-1和第二子支线122-2以及电连接至第二支线121-2的第三子支线122-3和第四子支线122-4。第一子支线122-1电连接至第一存储单元13-1。第二子支线122-2电连接至第二存储单元13-2。第三子支线122-3电连接至第三存储单元13-3。第四子支线122-4电连接至第四存储单元13-4。
在一些实施例中，第一存储单元13-1、第二存储单元13-2、第三存储单元13-3和第四存储单元13-4中的每个存储单元是DDR SDRAM。相应地，控制单元11是DDR控制器。在下文中，将以DDR SDRAM和DDR控制器作为示例来描述本公开的原理。然而，应当理解，DDR SDRAM和DDR控制器仅是示例性的，而无意限制本公开的范围。在其他实施例中，第一存储单元13-1、第二存储单元13-2、第三存储单元13-3和第四存储单元13-4中的每个存储单元可以是其他类型的存储单元，相应地，控制单元11也可以是其他类型的控制单元。
在第一传输线12中，考虑到信号的回波损耗(简称回损)，从主干120到第一级分支121以及从第一级分支121到第二级分支122，第一传输线12的特征阻抗都需要增加一倍。例如，在一个实施例中，结合PCB的制造工艺，主干120的阻抗可以为30欧姆，因此为了实现阻抗匹配，第一级分支121中的第一支线121-1和第二支线121-2的阻抗应为60欧姆，而第二级分支122中的第一子支线122-1、第二子支线122-2、第三子支线122-3和第四子支线122-4的阻抗应为120欧姆。应当注意，上述以及本公开其他地方可能提及的数字、数值等，都是示例性的，无意以任何方式限制本公开的范围。任何其他适当的数字、数值都是可能的。
对于PCB制造工艺而言，具有30欧姆和60欧姆的特征阻抗的传输线比较容易实现，然而具有120欧姆的高特征阻抗的传输线是很难实现的。
为了在PCB中实现具有高特征阻抗的传输线，目前主要有两种方案，如图2A和图2B所示。在图2A中所示的方案中，与传输线25相邻的层中的参考平面21和22的一部分被挖去，从而形成缺口211和221。利用这种布置，传输线25可以利用比参考平面21和22更远的参考平面20和23作为参考，增大了传输线25与参考平面之间的距离，因而相应地增大了传输线25与参考平面之间的介质层的厚度。以此方式，能够增大传输线25的特征阻抗。在图2B所示的方案中，与图2A所示的方案相比，直接增大了传输线25与参考平面20和23之间的距离，因而相应地增大了传输线25与参考平面20和23之间的介质层的厚度。以此方式，同样能够增大传输线25的特征阻抗。
虽然图2A和图2B所示的方案能够增大传输线25的特征阻抗，但是这些方案会极大地增加PCB的层数以及厚度，这会降低PCB的可靠性并且导致成本急剧提升。
为了解决在PCB中实现双T拓扑所产生的可靠性降低以及成本急剧提升的问题，本公开的实施例提供了一种传输线的布置方案。在该方案中，在存储单元与PCB之间插入了中介层，传输线的主干和第一级分支布置在PCB中，而传输线的第二级分支布置在中介层中。以此方式，能够避免PCB上额外层数的增加，并且释放PCB的布线空间，在整体上降低了存储装置的成本并提高了存储装置的可靠性。下面将结合图3至图8来描述存储装置的示例性实施例。
图3示出了根据本公开的一些实施例的存储装置的结构示意图，图4示出了图3中所示的存储装置中的存储单元与中介层的一种相对布置的示意图。图4是在沿着图3中的箭头40所示的方向查看时存储单元13-1、13-2、13-3和13-4与中介层15的相对布置。图3所示的存储装置300可以视为图1所示的存储装置100的一个 具体实现。
如图3所示，存储装置300包括PCB 10、中介层15、存储单元组13、控制单元11和第一传输线12。中介层15布置在PCB 10上，并且通过焊球18电连接至PCB 10。存储单元组13布置在中介层15上，并且通过焊球19电连接至中介层15。利用这样的布置，中介层15能够在PCB 10与存储单元组13之间传递信号。控制单元11布置在PCB 10上，并且通过焊球17电连接至PCB 10，用以经由第一传输线12来控制存储单元组13。
在一些实施例中，如图3和图4所示，中介层15为单个中介层，第一存储单元13-1、第二存储单元13-2、第三存储单元13-3和第四存储单元13-4彼此单独布置在中介层15上。换言之，第一存储单元13-1、第二存储单元13-2、第三存储单元13-3和第四存储单元13-4被单独封装，并且单独布置在中介层15上。
结合图1和图3，第一传输线12电连接在控制单元11与存储单元组13之间。在图3中仅示出传输线12的第一级分支121中的第一支线121-1以及第二级分支122中的与第一支线121-1电连接的第一子支线122-1和第二子支线122-2，而未示出传输线12的第一级分支121中的第二支线121-2以及第二级分支122中的与第二支线121-2电连接的第三子支线121-3和第四子支线122-4，以便于清楚地显示出存储装置300中的结构细节。应当理解，第一级分支121中的第二支线121-2以及第二级分支122中的第三子支线121-3和第四子支线122-4可以与第一级分支121中的第一支线121-1以及第二级分支122中的第一子支线122-1和第二子支线122-2以类似的方式进行布置。
在一些实施例中，如图3所示，第一传输线12的主干120和第一级分支121中的第一支线121-1布置在PCB 10中，第一传输线12的第二级分支122中的第一子支线122-1和第二子支线122-2布置在中介层15中。主干120电连接至设置在PCB 10中的过孔101-1，过孔101-1经由焊球17电连接至控制单元11。第一级分支121中 的第一支线121-1的一端电连接至主干120，另一端电连接至设置在PCB 10中的过孔101-2，过孔101-2通过焊球18电连接至设置在中介层15中的过孔151-1。第二级分支122中的第一子支线122-1和第二子支线122-2的一端分别电连接至过孔151-1。第一子支线122-1的另一端电连接至设置在中介层15中的过孔151-2，过孔151-2通过焊球19电连接至存储单元13-1。第二子支线122-2的另一端电连接至设置在中介层15中的过孔151-3，过孔151-3通过焊球19电连接至存储单元13-2。
类似地，第一传输线12的第一级分支121中的第二支线121-2可以布置在PCB 10中，而第一传输线12的第二级分支122中的第三子支线122-3和第四子支线122-4可以布置在中介层15中。此外，第一级分支121中的第二支线121-2可以通过过孔和焊球电连接至第二级分支122中的第三子支线122-3和第四子支线122-4。第二级分支122中的第三子支线122-3和第四子支线122-4也可以通过过孔和焊球分别电连接至存储单元13-3和13-4。对于第一传输线12的第一级分支121中的第二支线121-2和第二级分支122中的第三子支线122-3和第四子支线122-4具体布置，在此将不再赘述。
在一些实施例中，第一传输线12的主干120与第一级分支121中的第一支线121-1可以形成在PCB 10的同一层中。在另一些实施例中，第一传输线12的主干120与第一级分支121中的第一支线121-1可以形成在PCB 10的不同层中，并且通过设置在PCB 10中的过孔连接。
类似地，在一些实施例中，第一传输线12的主干120与第一级分支121中的第二支线121-2可以形成在PCB 10的同一层中。在另一些实施例中，第一传输线12的主干120与第一级分支121中的第二支线121-2可以形成在PCB 10的不同层中，并且通过设置在PCB 10中的过孔连接。此外，第一级分支121中的第一支线121-1和第二支线121-2可以形成在PCB 10的同一层或不同层中，本公开的实施例在此方面不做限制。
通过将第一传输线12的第二级分支122布置在中介层15中，能够避免PCB 10上的额外层数的增加，使得PCB 10仍然能够采用常规设计，而仅采用尺寸较小的中介层15就能够提供具有高特征阻抗的第二级分支122。以此方式，一方面能够防止存储装置的成本的急剧增加，另一方面能够释放PCB的布线空间，从而提高存储装置的可靠性。
在一些实施例中，中介层15包括封装基板，第二级分支122布置在封装基板中。在另一些实施例中，中介层15包括另一印刷电路板，第二级分支122布置在该另一印刷电路板中。与印刷电路板的制造工艺相比，封装基板的制造工艺能够实现更细的线宽，因而当将第二级分支122布置在封装基板中时，能够优化在第二级分支122上引入的串扰，进一步提高存储装置的可靠性。
在一些实施例中，如图3所示，存储装置300还包括第二传输线16。第二传输线16电连接在控制单元11与存储单元组13之间，以用于传输数据。第二传输线16布置在PCB 10中。第二传输线16的一端电连接至设置在PCB 10中的过孔101-3，另一端电连接至设置在PCB 10中的过孔101-4。过孔101-3通过焊球17电连接至控制单元11。过孔101-4通过焊球18电连接至设置在中介层15中的过孔151-4。过孔151-4通过焊球19电连接至存储单元13-1。控制单元11与存储单元组13中的其他存储单元可以通过类似的方式利用数据传输线进行数据传输，在此将不再赘述。
在一些实施例中，中介层15的尺寸可以接近于存储单元组13的尺寸。在一些实施例中，中介层15的尺寸可以大于存储单元组13的尺寸，以便于在其上设置用于对的存储装置300的信号进行测试的测试点。通过引入这样的测试点，可以方便后续对存储装置300的高速信号的测试。
图5示出了图3中所示的存储装置中的存储单元与中介层的另一种相对布置的示意图。图5是在沿着图3中的箭头40所示的方向查看时存储单元13-1、13-2、13-3和13-4与中介层15的另一种 相对布置。如图3和图5所示，中介层15包括第一中介层15-1和第二中介层15-2。第一存储单元13-1和第二存储单元13-2被单独布置在第一中介层15-1上。第三存储单元13-3和第四存储单元13-4被单独布置在第二中介层15-2上。
在一些实施例中，如图3和图5所示，第一中介层15-1和第二中介层15-2被布置在PCB 10的同一面上。在另一些实施例中，第一中介层15-1和第二中介层15-2可以被布置在PCB 10的不同面上。本公开的实施例在此方面不做限制。
在一些实施例中，存储单元13-1、13-2、13-3和13-4中的至少一部分可以被封装成单个封装体，继而被放置在中介层15上。下面将结合图6至图8对这种布置进行描述。
图6示出了根据本公开的一些实施例的存储装置的结构示意图，图7示出了图6中所示的存储装置中的存储单元与中介层的一种相对布置的示意图，图8示出了图6中所示的存储装置中的存储单元与中介层的另一种相对布置的示意图。图6所示的存储装置400与图3所示的存储装置300的结构类似，区别仅在于存储单元13-1、13-2、13-3和13-4中的至少一部分可以被封装成单个封装体。对于二者相同的部分，在此将不再赘述，而详细描述二者之间的区别。
在一些实施例中，如图6和图7所示，第一存储单元13-1、第二存储单元13-2、第三存储单元13-3和第四存储单元13-4被封装成单个封装体30。封装体30通过焊球19电连接至中介层15。
在一些实施例中，如图6和图8所示，中介层15包括第一中介层15-1和第二中介层15-2。第一存储单元13-1与第二存储单元13-2被封装成单个封装体30-1。第三存储单元13-3与第四存储单元13-4被封装成单个封装体30-2。封装体30-1通过焊球19电连接至第一中介层15-1。封装体30-2通过焊球19电连接至第二中介层15-2。
在一些实施例中，如图6和图8所示，第一中介层15-1和第二中介层15-2被布置在PCB 10的同一面上。在另一些实施例中，第一中介层15-1和第二中介层15-2可以被布置在PCB 10的不同面 上。本公开的实施例在此方面不做限制。
在根据本公开的实施例中，通过将用于传输命令或地址的传输线的第二级分支设置在中介层中，能够避免PCB上额外层数的增加，在整体系统上降低了成本。此外，通过将第二级分支设置在中介层中，能够释放PCB的布线空间，优化信号完整性上的串扰部分。
虽然在上文中针对双T拓扑描述了本公开的原理，但是应当理解本公开的在PCB与存储单元之间设置中介层的构思也可应用于其他拓扑，本公开的范围在此方面不做限制。
以上已经描述了本公开的各实现，上述说明是示例性的，并非穷尽性的，并且也不限于所公开的各实现。在不偏离所说明的各实现的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实现的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其他普通技术人员能理解本文公开的各个实现方式。

Claims (15)

  1. 一种存储装置，包括：
    印刷电路板(10)；
    中介层(15)，布置在所述印刷电路板(10)上；
    存储单元组(13)，布置在所述中介层(15)上；
    控制单元(11)，布置在所述印刷电路板(10)上，并且被配置为控制所述存储单元组(13)；以及
    第一传输线(12)，电连接在所述控制单元(11)与所述存储单元组(13)之间，并且被配置为传输命令或地址，所述第一传输线(12)包括电连接至所述控制单元(11)的主干(120)、电连接至所述主干(120)的第一级分支(121)、以及电连接至所述第一级分支(121)的第二级分支(122)，所述第二级分支(122)电连接至所述存储单元组(13)，其中所述主干(120)和所述第一级分支(121)布置在所述印刷电路板(10)中，所述第二级分支(122)布置在所述中介层(15)中。
  2. 根据权利要求1所述的存储装置，其中所述中介层(15)包括封装基板，所述第二级分支(122)布置在所述封装基板中。
  3. 根据权利要求1所述的存储装置，其中所述中介层(15)包括另一印刷电路板，所述第二级分支(122)布置在所述另一印刷电路板中。
  4. 根据权利要求1所述的存储装置，其中所述存储单元组(13)包括第一存储单元(13-1)、第二存储单元(13-2)、第三存储单元(13-3)和第四存储单元(13-4)，所述第一级分支(121)包括第一支线(121-1)和第二支线(121-2)，所述第二级分支(122)包括电连接至所述第一支线(121-1)的第一子支线(122-1)和第二子支线(122-2)以及电连接至所述第二支线(121-2)的第三子支线(122-3)和第四子支线(122-4)，所述第一子支线(122-1)电连接至所述第一存储单元(13-1)，所述第二子支线(122-2)电 连接至所述第二存储单元(13-2)，所述第三子支线(122-3)电连接至所述第三存储单元(13-3)，所述第四子支线(122-4)电连接至所述第四存储单元(13-4)。
  5. 根据权利要求4所述的存储装置，其中所述中介层(15)为单个中介层。
  6. 根据权利要求5所述的存储装置，其中所述第一存储单元(13-1)、所述第二存储单元(13-2)、所述第三存储单元(13-3)和所述第四存储单元(13-4)彼此单独布置在所述中介层(15)上。
  7. 根据权利要求5所述的存储装置，其中所述第一存储单元(13-1)与所述第二存储单元(13-2)被封装成单个封装体，和/或所述第三存储单元(13-3)与所述第四存储单元(13-4)被封装成单个封装体。
  8. 根据权利要求5所述的存储装置，其中所述第一存储单元(13-1)、所述第二存储单元(13-2)、所述第三存储单元(13-3)和所述第四存储单元(13-4)被封装成单个封装体。
  9. 根据权利要求4所述的存储装置，其中所述中介层(15)包括第一中介层(15-1)和第二中介层(15-2)，所述第一存储单元(13-1)和所述第二存储单元(13-2)布置在所述第一中介层(15-1)上，所述第三存储单元(13-3)和所述第四存储单元(13-4)布置在所述第二中介层(15-2)上。
  10. 根据权利要求9所述的存储装置，其中所述第一中介层(15-1)和所述第二中介层(15-2)被布置在所述印刷电路板(10)的同一面或不同面上。
  11. 根据权利要求9所述的存储装置，所述第一存储单元(13-1)和所述第二存储单元(13-2)单独布置在所述第一中介层(15-1)上，和/或所述第三存储单元(13-3)和所述第四存储单元(13-4)单独布置在所述第二中介层(15-2)上。
  12. 根据权利要求9所述的存储装置，其中所述第一存储单元(13-1)与所述第二存储单元(13-2)被封装成单个封装体，和/或 所述第三存储单元(13-3)与所述第四存储单元(13-4)被封装成单个封装体。
  13. 根据权利要求1所述的存储装置，其中所述中介层(15)包括用于对所述的存储装置的信号进行测试的测试点。
  14. 根据权利要求1所述的存储装置，还包括：
    第二传输线(16)，电连接在所述控制单元(11)与所述存储单元组(13)之间，并且被配置为传输数据，所述第二传输线(16)布置在所述印刷电路板(10)中，并且经由设置在所述中介层(15)中的过孔(151-4)电连接至所述存储单元组(13)。
  15. 根据权利要求1所述的存储装置，其中所述存储单元组(13)包括多个双倍速率同步动态随机存储器(DDR SDRAM)。
PCT/CN2023/098720 2022-06-29 2023-06-06 存储装置 WO2024001703A1 (zh)

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US7990727B1 (en) * 2006-04-03 2011-08-02 Aprolase Development Co., Llc Ball grid array stack
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CN112673524A (zh) * 2019-08-06 2021-04-16 三星电子株式会社 天线以及包括该天线的电子装置
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CN110556132A (zh) * 2018-05-30 2019-12-10 三星电子株式会社 印刷电路板、包括印刷电路板的存储器系统和存储装置
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