WO2024001276A1 - Preparation method for si-based gan-hemt device - Google Patents

Preparation method for si-based gan-hemt device Download PDF

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WO2024001276A1
WO2024001276A1 PCT/CN2023/079854 CN2023079854W WO2024001276A1 WO 2024001276 A1 WO2024001276 A1 WO 2024001276A1 CN 2023079854 W CN2023079854 W CN 2023079854W WO 2024001276 A1 WO2024001276 A1 WO 2024001276A1
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shaped groove
type
photoresist
preparing
area
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Chinese (zh)
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代书雨
周理明
徐峰
王毅
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扬州扬杰电子科技股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors

Definitions

  • the invention relates to the field of semiconductor technology, and in particular to a method for preparing a Si-based GaN-HEMT device.
  • GaN has a large band gap. , critical breakdown field strength and high electron mobility, it has strong application potential in power device markets such as fast charging, data centers, OBCs, and solar inverters.
  • GaN HEMT devices the main application form of GaN in power devices. Since Khan et al. produced the first AlGaN/GaN high electron mobility transistor (HEMT) in 1993, the horizontal structure of GaN HEMT devices is superior to Si devices. Its electrical performance and lower energy consumption have attracted widespread attention.
  • Nitronex launched the first commercial depletion mode RF GaN HEMT device grown on a Si substrate.
  • EPC launched the first enhancement mode Si-based GaN HEMT devices.
  • GaN HEMT devices have better performance than traditional Si devices, there are still some problems that restrict the application of GaN HEMT devices.
  • the current mainstream P GaN enhancement-mode devices require etching of the P GaN layer above AlGaN, and the interface states generated by etching The problem will seriously affect the performance of the device at high frequencies and cause serious current collapse effects.
  • Other disadvantages such as F ion implantation enhanced GaN HEMT and cascode hybrid enhancement GaN HEMT also have disadvantages such as difficult to control process conditions.
  • the present invention provides a method for preparing a Si-based GaN-HEMT device that effectively reduces the interface state problem caused by etching P GaN and improves the heat dissipation performance of the device.
  • the technical solution of the present invention is: a preparation method of Si-based GaN-HEMT devices, which includes the following steps:
  • the epitaxial wafer includes a buffer layer, a GaN intrinsic layer and an AlGaN barrier layer sequentially formed on the Si substrate.
  • the U-shaped groove preparation method in step S100 includes:
  • the epitaxial wafer is cleaned, coated with photoresist, photolithography and development processes in sequence, and then ICP dry etching is used to etch a U-shaped groove with a designed depth on the epitaxial wafer, and the photoresist is finally washed away.
  • the preparation method of P-type Si and N-type Si in step S200 includes:
  • step S240 clean the photoresist in step S210 and then perform the glue coating, photolithography and development processes in sequence to protect the P-type Si and N-type Si that need to be retained in the area outside the U-shaped groove and in the U-shaped groove; then use ICP dry etching removes excess P-type Si and N-type Si in the U-shaped groove and then cleans the photoresist.
  • the preparation method of SiO 2 thin film in step S300 includes:
  • S310 protect the area outside the U-shaped groove and the prepared P-type Si and N-type Si areas in the U-shaped groove with photoresist through glue coating, photolithography and development;
  • step S320 use the CVD process to deposit SiO 2 with a designed thickness in the remaining area in the U-shaped groove. Clean the photoresist in step S310 and then re-coat, photolithography and develop. The remaining P-type Si, N-type Si and SiO 2 films are protected, and then ICP dry etching is used to remove excess SiO 2 in the U-shaped groove and then the photoresist is cleaned.
  • step S400 includes:
  • the preparation method of the gate electrode in step S500 includes:
  • S510 protect the area where the gate electrode is located with photoresist through glue coating, photolithography and development processes;
  • the preparation method of the drain electrode in step S600 includes:
  • S610 protect the area where the drain electrode is located with photoresist through glue coating, photolithography and development processes;
  • step S630 clean the photoresist in step S610 and then re-perform the glue coating, photolithography and development processes to protect the area where the drain electrode is located with photoresist;
  • the preparation method of the source electrode in step S700 includes:
  • the gate structure proposed by the present invention is a U-shaped groove composite gate structure.
  • the composite gate structure is located in the U-shaped groove and forms a MOS-like structure with the n-type Si in the substrate.
  • This invention has the following advantages: placing the device source at the bottom, saving the source PAD area on the chip surface; avoiding the interface state caused by the current mainstream P-GaN enhancement device etching problems and high-frequency current collapse effects, thereby promoting the development and application of Si-based GaN HEMTs in the field of power electronics.
  • FIG. 1 is a process flow diagram of the present invention
  • FIG. 1 is a schematic diagram of step S100
  • FIG. 3 is a schematic diagram of step S200.
  • Figure 4 is a schematic diagram of step S300.
  • FIG. 5 is a schematic diagram of step S400.
  • Figure 6 is a schematic diagram of step S500.
  • Figure 7 is a schematic diagram of step S600.
  • Figure 8 is a schematic diagram of step S700.
  • Figure 9 is a graph showing the ratio test results of the actual current and saturation current of Sample 1, Sample 2 and the device in this case after the current collapse effect occurs at high frequency.
  • Figure 10 is the thermal resistance test result chart of sample 1, sample 2 and the device in this case from junction to case under 100% duty cycle condition;
  • 1 is the source electrode
  • 2 is the Si substrate
  • 3 is the buffer layer
  • 4 is the GaN intrinsic layer
  • 5 is the drain electrode
  • 6 is the AlGaN barrier layer
  • 7 is N-type Si
  • 8 is the gate electrode
  • 9 is Polycrystalline silicon
  • 10 is SiO 2 thin film
  • 11 is P-type Si.
  • the present invention is shown in Figures 1-10; a method for preparing Si-based GaN-HEMT devices, including the following steps:
  • the epitaxial wafer includes a buffer layer 3, a GaN intrinsic layer 4 and an AlGaN barrier layer 60 formed sequentially on the Si substrate 2.
  • the U-shaped groove preparation method in step S100 includes:
  • the epitaxial wafer is cleaned, coated with photoresist, photolithography and development processes in sequence, and then ICP dry etching is used to etch a U-shaped groove with a designed depth on the epitaxial wafer, and the photoresist is finally washed away.
  • the preparation method of P-type Si11 and N-type Si7 in step S200 includes:
  • step S240 clean the photoresist in step S210 and then perform the glue coating, photolithography and development processes in sequence to protect the P-type Si11 and N-type Si7 that need to be retained in the area outside the U-shaped groove and in the U-shaped groove; then use ICP dry etching removes the excess P-type Si11 and N-type Si7 in the U-shaped groove and then cleans the photoresist to prepare the P-type Si11 and N-type Si7 device morphology as shown in Figure 3.
  • the preparation method of SiO 2 thin film 10 in step S300 includes:
  • S310 protect the area outside the U-shaped groove and the prepared P-type Si11 and N-type Si7 areas with photoresist through glue coating, photolithography and development;
  • step S320 use the CVD process to deposit SiO 2 with a designed thickness in the remaining area in the U-shaped groove. Clean the photoresist in step S310 and then re-coat, photoetch and develop. The remaining P-type Si 11, N-type Si7 and SiO 2 films 10 are protected, and then ICP dry etching is used to remove excess SiO 2 in the U-shaped groove and then the photoresist is cleaned.
  • Figure 4 shows the preparation of SiO in the U-shaped groove. 2 Device morphology after film 10.
  • preparation method of polysilicon 9 in step S400 includes:
  • S410 protect the area outside the U-shaped groove and the prepared P-type Si 11 area, N-type Si 7 area and SiO 2 film 10 area with photoresist through glue coating, photolithography and development processes;
  • the preparation method of gate electrode 8 in step S500 includes:
  • the preparation method of drain electrode 5 in step S600 includes:
  • S610 protect the area where the drain electrode 5 is located with photoresist through glue coating, photolithography and development processes;
  • step S630 clean off the photoresist in step S610 and then perform the glue coating, photolithography and development processes again to protect the area where the drain electrode 5 is located with photoresist;
  • the preparation method of source electrode 1 in step S700 includes:
  • FIG. 8 shows the backside processing and preparation Device morphology behind source electrode 1.
  • the Si-based GaN-HEMT device includes a source electrode 1, a Si substrate 2, a buffer layer 3, a GaN intrinsic layer 4 and an AlGaN barrier layer 6 connected in sequence from bottom to top;
  • the drain electrode 5 is located at the end of the device. After passing through the AlGaN barrier layer 6 from top to bottom, it extends into the GaN intrinsic layer 4 to ensure a good connection with the two-dimensional electron gas;
  • SiO 2 film 10 is provided in the U-shaped groove
  • P-type Si 11 and N-type Si 7 are arranged in sequence from bottom to top between the SiO 2 film 10 and the inner wall of the U-shaped groove;
  • Polysilicon 9 is provided in the middle of the SiO 2 film 10;
  • a gate electrode 8 extending upward is provided on the top of the polysilicon 9 .
  • the gate electrode 8 is located above the polysilicon 9, and its lower surface is in contact with the upper surface of the polysilicon 9 to form an ohmic contact.
  • the gate electrode can be any material that can form an ohmic contact with the polysilicon.
  • the gate electrode 8 is a Ti/Al metal layer, ensuring good ohmic contact between the gate electrode 8 and the polysilicon 9 .
  • the U-shaped groove and the composite gate in the groove constitute the gate structure of the device.
  • the U-shaped groove is formed by etching to provide a vertical conductive channel for the device.
  • the U-shaped groove is deeply etched into the Si substrate layer of the epitaxial wafer and over-etched, and the composite gate structure is located in the groove gate.
  • the U-shaped groove needs to be etched into the Si substrate layer of the epitaxial wafer.
  • the bottom of the U-shaped groove can be located at any level of the Si substrate layer according to the actual process conditions and electrical parameters.
  • the width of the U-shaped groove is 100nm-5um, which can be determined according to the specific process. Conditions and machine accuracy determined.
  • the P-type Si 11 is connected to the inner wall of the U-shaped groove, the lower surface is flush with the bottom of the U-shaped groove, and the upper surface is lower than the upper surface of the GaN intrinsic layer 4.
  • the thickness of P-type Si11 in the horizontal direction from the inner wall of the U-shaped groove to the SiO 2 film 10 is 10nm-1um.
  • P-type Si 11 close to the surface of the SiO 2 film can form an inversion layer under forward-biased gate voltage conditions.
  • the thickness of the inversion layer can generally only reach 10nm.
  • the horizontal thickness of P-type Si11 is 10nm-1um.
  • N-type Si7 is in contact with the upper surface of P-type Si11, and the upper surface is flush with the AlGaN barrier layer 6.
  • N-type Si 7 is the same as that of P-type Si 11.
  • the horizontal thickness of P-type Si11 and N-type Si7 is 10nm-1um respectively, ensuring that P-type Si11 can form a saturated current channel under gate forward bias condition.
  • the sum of the vertical heights of P-type Si11 and N-type Si7 is U
  • the groove etching depth is that the upper surface of P-type Si11 is lower than the level of the two-dimensional electron gas of the GaN HEMT device, and the upper surface of N-type Si7 is flush with the upper surface of the AlGaN layer.
  • the lower surface of the SiO 2 film 10 is flush with the lower surface of the P-type Si 11, and the upper surface is flush with the AlGaN barrier layer 6.
  • the thickness is 5nm-100nm, ensuring that the gate leakage current is less than 1A/cm 2 .
  • Polycrystalline silicon 9 is filled inside the SiO 2 film 10, and the upper surface is flush with the AlGaN barrier layer 6.
  • the polysilicon 9 is located inside the groove surrounded by the SiO 2 film 10, that is, there are no gaps or obvious defects inside the polysilicon 9, ensuring good electrical conductivity.
  • the present invention proposes a new Si-based GaN HEMT new gate structure.
  • This gate structure avoids the P GaN etching step required for P GaN enhancement-mode devices, effectively reduces the interface state problems caused by etching P GaN, and etches
  • the interface state problems caused by corrosion will seriously affect the performance of the device at high frequencies and cause serious current collapse effects.
  • FIG 9 the vertical coordinates in the figure represent the actual current and saturation current after the current collapse effect occurs at high frequencies. percentage
  • the high-frequency current of P GaN enhancement-mode devices on the market is generally 50%-85% of that under static conditions.
  • the new Si-based GaN HEMT novel gate structure device proposed by the present invention (figure The device) has extremely low current collapse effect, and the current at high frequency can reach 95% of that under static conditions. Moreover, the gate adopts a vertical conductive structure, and the source is located under the chip and directly connected to the packaging frame, which enhances the heat dissipation capability of the device and solves the problem that most of the current mainstream GaN HEMT devices are horizontal structure devices. Under high power conditions It is easy to produce self-heating effects and the heat cannot be dissipated well. As shown in Figure 10, under the same power and the same packaging conditions (DFN5*6), the new Si-based GaN HEMT new gate structure device proposed by the present invention is connected to the package.
  • the typical value of the thermal resistance Rthjc on the surface is 0.5°C/W.
  • the thermal resistance Rthjc of P GaN enhancement-mode devices on the market is between 1.1-1.6.
  • the thermal resistance Rthjc of the new Si-based GaN HEMT new gate structure device proposed by the present invention The improvement is obvious.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A preparation method for a Si-based GaN-HEMT device, relating to the technical field of semiconductors. The method comprises the following steps: S100, preparing a U-shaped groove on an epitaxial wafer; S200, sequentially preparing P-type Si and N-type Si in the U-shaped groove from bottom to top; S300, preparing a SiO2 thin film in the U-shaped groove; S400, preparing polycrystalline silicon in the U-shaped groove; S500, preparing a gate electrode above the polycrystalline silicon; S600, etching a drain electrode region, and preparing a drain electrode; and S700, processing the back surface, and preparing a source electrode. Furthermore, in step S100, the epitaxial wafer comprises a buffer layer, a GaN intrinsic layer, and an AlGaN barrier layer which are sequentially formed on a Si substrate. According to the present invention, the area of a source PAD region on the surface of a chip is saved, and the interface state problem and the high-frequency current collapse effect caused by the etching of existing mainstream P-GaN enhanced devices are avoided, thereby promoting the development and application of Si-based GaN HEMTs in the field of power electronics.

Description

一种Si基GaN-HEMT器件的制备方法A method for preparing Si-based GaN-HEMT devices 技术领域Technical field
本发明涉及半导体技术领域，尤其涉及一种Si基GaN-HEMT器件的制备方法。The invention relates to the field of semiconductor technology, and in particular to a method for preparing a Si-based GaN-HEMT device.
背景技术Background technique
在电力电子器件技术领域，随着目前主流的Si器件越来越逼近其材料特性决定的性能极限，以GaN和SiC为代表的第三代半导体越来越被人们重视，GaN具有禁带宽度大、临界击穿场强和电子迁移率高等优点，在快充、数据中心、OBC、太阳能逆变器等功率器件市场具有强大的应用潜力。In the field of power electronic device technology, as the current mainstream Si devices are getting closer to the performance limits determined by their material characteristics, the third generation semiconductors represented by GaN and SiC are getting more and more attention. GaN has a large band gap. , critical breakdown field strength and high electron mobility, it has strong application potential in power device markets such as fast charging, data centers, OBCs, and solar inverters.
目前GaN在功率器件的主要应用形式是GaN HEMT器件，自1993年Khan等人制作出了第一个AlGaN/GaN高电子迁移率晶体管(HEMT)，水平结构的GaN HEMT器件以其优于Si器件的电学性能和更低的能耗受到人们的广泛关注，2005年Nitronex推出第一款生长在Si衬底上的商用耗尽型射频GaN HEMT器件，2009年EPC推出第一款增强型Si基GaN HEMT器件。At present, the main application form of GaN in power devices is GaN HEMT devices. Since Khan et al. produced the first AlGaN/GaN high electron mobility transistor (HEMT) in 1993, the horizontal structure of GaN HEMT devices is superior to Si devices. Its electrical performance and lower energy consumption have attracted widespread attention. In 2005, Nitronex launched the first commercial depletion mode RF GaN HEMT device grown on a Si substrate. In 2009, EPC launched the first enhancement mode Si-based GaN HEMT devices.
虽然GaN HEMT器件具有优于传统Si器件的性能，但依然存在一些问题制约着GaN HEMT器件的应用，比如目前主流的P GaN增强型器件需要刻蚀AlGaN上方P GaN层，刻蚀产生的界面态问题会严重影响器件在高频下的性能，引起严重的电流崩塌效应，其它诸如F离子注入增强型GaN HEMT、共源共栅混合增强型GaN HEMT也存在工艺条件难以控制等缺点。Although GaN HEMT devices have better performance than traditional Si devices, there are still some problems that restrict the application of GaN HEMT devices. For example, the current mainstream P GaN enhancement-mode devices require etching of the P GaN layer above AlGaN, and the interface states generated by etching The problem will seriously affect the performance of the device at high frequencies and cause serious current collapse effects. Other disadvantages such as F ion implantation enhanced GaN HEMT and cascode hybrid enhancement GaN HEMT also have disadvantages such as difficult to control process conditions.
发明内容Contents of the invention
本发明针对以上问题，提供了一种有效减小了刻蚀P GaN产生的界面态问题、提高器件散热性能的一种Si基GaN-HEMT器件的制备方法。In view of the above problems, the present invention provides a method for preparing a Si-based GaN-HEMT device that effectively reduces the interface state problem caused by etching P GaN and improves the heat dissipation performance of the device.
本发明的技术方案是：一种Si基GaN-HEMT器件的制备方法，包括以下步骤:The technical solution of the present invention is: a preparation method of Si-based GaN-HEMT devices, which includes the following steps:
S100，在外延片上制备U型槽；S100, prepare U-shaped groove on the epitaxial wafer;
S200，在U型槽内从下而上依次制备P型Si和N型Si；S200, prepare P-type Si and N-type Si from bottom to top in a U-shaped groove;
S300，在U型槽内制备SiO2薄膜；S300, prepare SiO 2 film in U-shaped groove;
S400，在U型槽中制备多晶硅；S400, preparation of polysilicon in U-shaped groove;
S500，在多晶硅的上方制备栅电极；S500, prepare the gate electrode on the polysilicon;
S600，刻蚀漏电极区域，并制备漏电极；S600, etch the drain electrode area and prepare the drain electrode;
S700，背面处理，并制备源电极。 S700, backside processing, and source electrode preparation.
进一步，步骤S100中，所述外延片包括在Si衬底上依次形成的缓冲层、GaN本征层和AlGaN势垒层。Further, in step S100, the epitaxial wafer includes a buffer layer, a GaN intrinsic layer and an AlGaN barrier layer sequentially formed on the Si substrate.
进一步，步骤S100中U型槽制备方法包括：Further, the U-shaped groove preparation method in step S100 includes:
对外延片依次进行清洗、涂光刻胶、光刻和显影工艺，随后用ICP干法刻蚀在外延片上刻蚀出设计深度的U型槽，最后清洗掉光刻胶。The epitaxial wafer is cleaned, coated with photoresist, photolithography and development processes in sequence, and then ICP dry etching is used to etch a U-shaped groove with a designed depth on the epitaxial wafer, and the photoresist is finally washed away.
进一步，步骤S200中P型Si和N型Si制备方法包括：Further, the preparation method of P-type Si and N-type Si in step S200 includes:
S210，通过涂胶、光刻和显影工艺将U型槽外区域用光刻胶保护；S210, protect the area outside the U-shaped groove with photoresist through glue coating, photolithography and development processes;
S220，使用CVD工艺先在U型槽中沉积一层设计厚度的P型Si；S220, use the CVD process to first deposit a layer of P-type Si with a designed thickness in the U-shaped groove;
S230，然后在P型Si上继续使用CVD工艺沉积一层设计厚度的N型Si；S230, then continue to use the CVD process to deposit a layer of N-type Si with a designed thickness on the P-type Si;
S240，清洗掉步骤S210中的光刻胶后重新依次进行涂胶、光刻和显影工艺，将U型槽外区域、U型槽内需要保留的P型Si和N型Si进行保护；随后使用ICP干法刻蚀去除U型槽内多余的P型Si和N型Si后清洗掉光刻胶。S240, clean the photoresist in step S210 and then perform the glue coating, photolithography and development processes in sequence to protect the P-type Si and N-type Si that need to be retained in the area outside the U-shaped groove and in the U-shaped groove; then use ICP dry etching removes excess P-type Si and N-type Si in the U-shaped groove and then cleans the photoresist.
进一步，步骤S300中SiO2薄膜的制备方法包括：Further, the preparation method of SiO 2 thin film in step S300 includes:
S310，通过涂胶、光刻和显影将U型槽外区域和U型槽内已制备P型Si和N型Si区域用光刻胶保护；S310, protect the area outside the U-shaped groove and the prepared P-type Si and N-type Si areas in the U-shaped groove with photoresist through glue coating, photolithography and development;
S320，使用CVD工艺在U型槽内剩余区域沉积设计厚度的SiO2，清洗掉步骤S310中的光刻胶后重新涂胶、光刻和显影，将U型槽外区域、U型槽内需要保留的P型Si、N型Si和SiO2薄膜保护，随后使用ICP干法刻蚀去除U型槽内多余的SiO2后清洗掉光刻胶。S320, use the CVD process to deposit SiO 2 with a designed thickness in the remaining area in the U-shaped groove. Clean the photoresist in step S310 and then re-coat, photolithography and develop. The remaining P-type Si, N-type Si and SiO 2 films are protected, and then ICP dry etching is used to remove excess SiO 2 in the U-shaped groove and then the photoresist is cleaned.
进一步，步骤S400中多晶硅的制备方法包括：Further, the method for preparing polysilicon in step S400 includes:
S410，通过涂胶、光刻和显影工艺将U型槽外区域、U型槽内已制备P型Si区域、N型Si区域和SiO2薄膜10区域用光刻胶进行保护；S410, through glue coating, photolithography and development processes, the area outside the U-shaped groove, the prepared P-type Si area, the N-type Si area and the SiO 2 film 10 area in the U-shaped groove are protected with photoresist;
S420，使用CVD工艺在U型槽内剩余区域沉积设计厚度的多晶硅后清洗掉光刻胶。S420, use the CVD process to deposit polysilicon of the designed thickness in the remaining area of the U-shaped groove and then clean the photoresist.
进一步，步骤S500中栅电极的制备方法包括：Further, the preparation method of the gate electrode in step S500 includes:
S510，通过涂胶、光刻和显影工艺将除栅电极所在区域用光刻胶保护；S510, protect the area where the gate electrode is located with photoresist through glue coating, photolithography and development processes;
S520，使用MOCVD或金属离子溅射沉积工艺在多晶硅上设计区域制备栅电极，随后清洗掉光刻胶。S520, use MOCVD or metal ion sputtering deposition process to prepare a gate electrode in a designed area on polysilicon, and then clean off the photoresist.
进一步，步骤S600中漏电极的制备方法包括：Further, the preparation method of the drain electrode in step S600 includes:
S610，通过涂胶、光刻和显影工艺对除漏电极所在区域用光刻胶进行保护；S610, protect the area where the drain electrode is located with photoresist through glue coating, photolithography and development processes;
S620，使用ICP干法刻蚀在外延片上刻蚀出设计深度的漏电极槽；S620, use ICP dry etching to etch the drain electrode groove with the designed depth on the epitaxial wafer;
S630，清洗掉步骤S610中的光刻胶后重新进行涂胶、光刻和显影工艺将除漏电极所在区域用光刻胶保护；S630, clean the photoresist in step S610 and then re-perform the glue coating, photolithography and development processes to protect the area where the drain electrode is located with photoresist;
S640，使用MOCVD或金属离子溅射沉积工艺在漏电极槽区域制备漏电极，随后清洗掉光刻胶。S640, use MOCVD or metal ion sputtering deposition process to prepare the drain electrode in the drain electrode trench area, and then clean the photoresist.
进一步，步骤S700中源电极的制备方法包括：Further, the preparation method of the source electrode in step S700 includes:
S710，使用UV膜将芯片正面保护；S710, use UV film to protect the front side of the chip;
S720，通过研磨和抛光工艺将芯片背面减薄；S720, which thins the backside of the chip through grinding and polishing processes;
S730，使用MOCVD或金属离子溅射沉积工艺在芯片背面制备源电极，随后将UV膜去除，制备完成。S730, use MOCVD or metal ion sputtering deposition process to prepare the source electrode on the back of the chip, and then remove the UV film to complete the preparation.
本发明提出的栅极结构是一种U型槽复合栅极结构，复合栅极结构位于U型槽中，和衬底中n型Si形成一个类MOS结构，通过控制类MOS结构沟道的通断来控制GaN HEMT的通断，该发明具有以下优点：将器件源极置于底部，节约了芯片表面源极PAD区域面积；避免了目前主流的P-GaN增强型器件刻蚀引起的界面态问题和高频电流崩塌效应，从而推动Si基GaN HEMT在电力电子领域的发展和应用。The gate structure proposed by the present invention is a U-shaped groove composite gate structure. The composite gate structure is located in the U-shaped groove and forms a MOS-like structure with the n-type Si in the substrate. By controlling the channel passage of the MOS-like structure, This invention has the following advantages: placing the device source at the bottom, saving the source PAD area on the chip surface; avoiding the interface state caused by the current mainstream P-GaN enhancement device etching problems and high-frequency current collapse effects, thereby promoting the development and application of Si-based GaN HEMTs in the field of power electronics.
附图说明Description of drawings
图1是本发明的工艺流程图，Figure 1 is a process flow diagram of the present invention,
图2是步骤S100的示意图，Figure 2 is a schematic diagram of step S100,
图3是步骤S200的示意图，Figure 3 is a schematic diagram of step S200.
图4是步骤S300的示意图，Figure 4 is a schematic diagram of step S300.
图5是步骤S400的示意图，Figure 5 is a schematic diagram of step S400.
图6是步骤S500的示意图，Figure 6 is a schematic diagram of step S500.
图7是步骤S600的示意图，Figure 7 is a schematic diagram of step S600.
图8是步骤S700的示意图，Figure 8 is a schematic diagram of step S700.
图9是高频下电流崩塌效应发生后，样品1、样品2和本案器件实际电流和饱和电流的比值测试结果图，Figure 9 is a graph showing the ratio test results of the actual current and saturation current of Sample 1, Sample 2 and the device in this case after the current collapse effect occurs at high frequency.
图10是100％占空比条件下样品1、样品2和本案器件结到壳的热阻测试结果图；Figure 10 is the thermal resistance test result chart of sample 1, sample 2 and the device in this case from junction to case under 100% duty cycle condition;
图中1是源电极、2是Si衬底、3是缓冲层、4是GaN本征层、5是漏电极、6是AlGaN势垒层、7是N型Si、8是栅电极、9是多晶硅、10是SiO2薄膜、11是P型Si。In the figure, 1 is the source electrode, 2 is the Si substrate, 3 is the buffer layer, 4 is the GaN intrinsic layer, 5 is the drain electrode, 6 is the AlGaN barrier layer, 7 is N-type Si, 8 is the gate electrode, and 9 is Polycrystalline silicon, 10 is SiO 2 thin film, and 11 is P-type Si.
具体实施方式Detailed ways
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and cannot be understood as limiting the present invention.
本发明如图1-10所示；一种Si基GaN-HEMT器件的制备方法，包括以下步骤:The present invention is shown in Figures 1-10; a method for preparing Si-based GaN-HEMT devices, including the following steps:
S100，在外延片上制备U型槽；参照图2所示；S100, prepare a U-shaped groove on the epitaxial wafer; refer to Figure 2;
进一步，步骤S100中，所述外延片包括在Si衬底2上依次形成的缓冲层3、GaN本征层4和AlGaN势垒层60。Further, in step S100, the epitaxial wafer includes a buffer layer 3, a GaN intrinsic layer 4 and an AlGaN barrier layer 60 formed sequentially on the Si substrate 2.
进一步，步骤S100中U型槽制备方法包括：Further, the U-shaped groove preparation method in step S100 includes:
对外延片依次进行清洗、涂光刻胶、光刻和显影工艺，随后用ICP干法刻蚀在外延片上刻蚀出设计深度的U型槽，最后清洗掉光刻胶。The epitaxial wafer is cleaned, coated with photoresist, photolithography and development processes in sequence, and then ICP dry etching is used to etch a U-shaped groove with a designed depth on the epitaxial wafer, and the photoresist is finally washed away.
S200，在U型槽内从下而上依次制备P型Si11和N型Si7；参照图3所示；S200, prepare P-type Si11 and N-type Si7 from bottom to top in the U-shaped groove; refer to Figure 3;
进一步，步骤S200中P型Si11和N型Si7制备方法包括：Further, the preparation method of P-type Si11 and N-type Si7 in step S200 includes:
S210，通过涂胶、光刻和显影工艺将U型槽外区域用光刻胶保护；S210, protect the area outside the U-shaped groove with photoresist through glue coating, photolithography and development processes;
S220，使用CVD工艺先在U型槽中沉积一层设计厚度的P型Si11；S220, use the CVD process to first deposit a layer of P-type Si11 with a designed thickness in the U-shaped groove;
S230，然后在P型Si11上继续使用CVD工艺沉积一层设计厚度的N型Si7；S230, then continue to use the CVD process to deposit a layer of N-type Si7 with a designed thickness on P-type Si11;
S240，清洗掉步骤S210中的光刻胶后重新依次进行涂胶、光刻和显影工艺，将U型槽外区域、U型槽内需要保留的P型Si11和N型Si7进行保护；随后使用ICP干法刻蚀去除U型槽内多余的P型Si 11和N型Si 7后清洗掉光刻胶，制备获得如图3所示的P型Si11和N型Si7器件形貌。S240, clean the photoresist in step S210 and then perform the glue coating, photolithography and development processes in sequence to protect the P-type Si11 and N-type Si7 that need to be retained in the area outside the U-shaped groove and in the U-shaped groove; then use ICP dry etching removes the excess P-type Si11 and N-type Si7 in the U-shaped groove and then cleans the photoresist to prepare the P-type Si11 and N-type Si7 device morphology as shown in Figure 3.
S300，在U型槽内制备SiO2薄膜10；参照图4所示；S300, prepare SiO 2 thin film 10 in a U-shaped groove; refer to Figure 4;
进一步，步骤S300中SiO2薄膜10的制备方法包括：Further, the preparation method of SiO 2 thin film 10 in step S300 includes:
S310，通过涂胶、光刻和显影将U型槽外区域和U型槽内已制备P型Si11和N型Si 7区域用光刻胶保护；S310, protect the area outside the U-shaped groove and the prepared P-type Si11 and N-type Si7 areas with photoresist through glue coating, photolithography and development;
S320，使用CVD工艺在U型槽内剩余区域沉积设计厚度的SiO2，清洗掉步骤S310中的光刻胶后重新涂胶、光刻和显影，将U型槽外区域、U型槽内需要保留的P型Si 11、N型Si7和SiO2薄膜10保护，随后使用ICP干法刻蚀去除U型槽内多余的SiO2后清洗掉光刻胶，图4为在U型槽中制备SiO2薄膜10后的器件形貌。S320, use the CVD process to deposit SiO 2 with a designed thickness in the remaining area in the U-shaped groove. Clean the photoresist in step S310 and then re-coat, photoetch and develop. The remaining P-type Si 11, N-type Si7 and SiO 2 films 10 are protected, and then ICP dry etching is used to remove excess SiO 2 in the U-shaped groove and then the photoresist is cleaned. Figure 4 shows the preparation of SiO in the U-shaped groove. 2 Device morphology after film 10.
S400，在U型槽中制备多晶硅9；参照图5所示；S400, prepare polysilicon 9 in a U-shaped groove; refer to Figure 5;
进一步，步骤S400中多晶硅9的制备方法包括：Further, the preparation method of polysilicon 9 in step S400 includes:
S410，通过涂胶、光刻和显影工艺将U型槽外区域、U型槽内已制备P型Si 11区域、N型Si 7区域和SiO2薄膜10区域用光刻胶进行保护；S410, protect the area outside the U-shaped groove and the prepared P-type Si 11 area, N-type Si 7 area and SiO 2 film 10 area with photoresist through glue coating, photolithography and development processes;
S420，使用CVD工艺在U型槽内剩余区域沉积设计厚度的多晶硅9后清洗掉光刻胶，图5显示了在U型槽中制备多晶硅9后的器件形貌。S420, use the CVD process to deposit polysilicon 9 with a designed thickness in the remaining area of the U-shaped groove and then clean the photoresist. Figure 5 shows the device morphology after preparing polysilicon 9 in the U-shaped groove.
S500，在多晶硅9的上方制备栅电极8；参照图6所示；S500, prepare gate electrode 8 above polysilicon 9; refer to Figure 6;
进一步，步骤S500中栅电极8的制备方法包括：Further, the preparation method of gate electrode 8 in step S500 includes:
S510，通过涂胶、光刻和显影工艺将除栅电极8所在区域用光刻胶保护；S510, protect the area where the gate electrode 8 is located with photoresist through glue coating, photolithography and development processes;
S520，使用MOCVD或金属离子溅射沉积工艺在多晶硅9上设计区域制备栅电极8，随后清洗掉光刻胶，图6为在U型槽中制备栅电极8后的器件形貌。S520, use MOCVD or metal ion sputtering deposition process to prepare the gate electrode 8 in the designed area on the polysilicon 9, and then clean off the photoresist. Figure 6 shows the device morphology after the gate electrode 8 is prepared in the U-shaped groove.
S600，刻蚀漏电极区域，并制备漏电极5；参照图7所示；S600, etch the drain electrode area and prepare the drain electrode 5; refer to Figure 7;
进一步，步骤S600中漏电极5的制备方法包括：Further, the preparation method of drain electrode 5 in step S600 includes:
S610，通过涂胶、光刻和显影工艺对除漏电极5所在区域用光刻胶进行保护；S610, protect the area where the drain electrode 5 is located with photoresist through glue coating, photolithography and development processes;
S620，使用ICP干法刻蚀在外延片上刻蚀出设计深度的漏电极槽；S620, use ICP dry etching to etch the drain electrode groove with the designed depth on the epitaxial wafer;
S630，清洗掉步骤S610中的光刻胶后重新进行涂胶、光刻和显影工艺将除漏电极5所在区域用光刻胶保护；S630, clean off the photoresist in step S610 and then perform the glue coating, photolithography and development processes again to protect the area where the drain electrode 5 is located with photoresist;
S640，使用MOCVD或金属离子溅射沉积工艺在漏电极槽区域制备漏电极5，随后清洗掉光刻胶，图7显示了刻蚀漏电极区域，并制备漏电极5后的器件形貌。S640, use MOCVD or metal ion sputtering deposition process to prepare drain electrode 5 in the drain electrode trench area, and then clean off the photoresist. Figure 7 shows the device morphology after etching the drain electrode area and preparing drain electrode 5.
S700，背面处理，并制备源电极1；参照图8所示。S700, backside processing, and source electrode 1 is prepared; see Figure 8.
进一步，步骤S700中源电极1的制备方法包括：Further, the preparation method of source electrode 1 in step S700 includes:
S710，使用UV膜将芯片正面保护；S710, use UV film to protect the front side of the chip;
S720，通过研磨和抛光工艺将芯片背面减薄；S720, which thins the backside of the chip through grinding and polishing processes;
S730，使用MOCVD或金属离子溅射沉积工艺在芯片背面制备源电极1，随后将UV膜去除，制备本发明提出的Si基GaN HEMT新型栅极结构器件完成，图8显示了背面处理，并制备源电极1后的器件形貌。S730, use MOCVD or metal ion sputtering deposition process to prepare the source electrode 1 on the back of the chip, and then remove the UV film to prepare the new Si-based GaN HEMT gate structure device proposed by the present invention. Figure 8 shows the backside processing and preparation Device morphology behind source electrode 1.
参照图8所示，Si基GaN-HEMT器件，包括从下而上依次连接的源电极1、Si衬底2、缓冲层3、GaN本征层4和AlGaN势垒层6；Referring to Figure 8, the Si-based GaN-HEMT device includes a source electrode 1, a Si substrate 2, a buffer layer 3, a GaN intrinsic layer 4 and an AlGaN barrier layer 6 connected in sequence from bottom to top;
所述漏电极5位于器件的端部，从上而下通过AlGaN势垒层6后，伸入GaN本征层4，确保与二维电子气形成良好的连接；The drain electrode 5 is located at the end of the device. After passing through the AlGaN barrier layer 6 from top to bottom, it extends into the GaN intrinsic layer 4 to ensure a good connection with the two-dimensional electron gas;
器件的中部设有从AlGaN势垒层6延伸至衬底2的U型槽；There is a U-shaped groove extending from the AlGaN barrier layer 6 to the substrate 2 in the middle of the device;
所述U型槽内设有SiO2薄膜10；SiO 2 film 10 is provided in the U-shaped groove;
所述SiO2薄膜10与U型槽的内侧壁之间从下而上依次设有P型Si 11和N型Si 7；P-type Si 11 and N-type Si 7 are arranged in sequence from bottom to top between the SiO 2 film 10 and the inner wall of the U-shaped groove;
所述SiO2薄膜10的中部设有多晶硅9；Polysilicon 9 is provided in the middle of the SiO 2 film 10;
所述多晶硅9的顶部设有向上延伸的栅电极8。栅电极8位于多晶硅9的上方，其下表面与多晶硅9上表面接触，形成欧姆接触，栅电极可以是任意可以和多晶硅形成欧姆接触的材料。栅电极8为Ti/Al金属层，确保栅电极8与多晶硅9形成良好的欧姆接触。A gate electrode 8 extending upward is provided on the top of the polysilicon 9 . The gate electrode 8 is located above the polysilicon 9, and its lower surface is in contact with the upper surface of the polysilicon 9 to form an ohmic contact. The gate electrode can be any material that can form an ohmic contact with the polysilicon. The gate electrode 8 is a Ti/Al metal layer, ensuring good ohmic contact between the gate electrode 8 and the polysilicon 9 .
本案中U型槽和槽内的复合栅极(包括多晶硅9、SiO2薄膜10和P型Si 11)构成了器件的栅极结构，U型槽通过刻蚀的方式形成，提供器件垂直导电通道，U型槽深度刻蚀到外延片Si衬底层并过刻，复合栅极结构位于凹槽栅内。In this case, the U-shaped groove and the composite gate in the groove (including polysilicon 9, SiO2 film 10 and P-type Si 11) constitute the gate structure of the device. The U-shaped groove is formed by etching to provide a vertical conductive channel for the device. The U-shaped groove is deeply etched into the Si substrate layer of the epitaxial wafer and over-etched, and the composite gate structure is located in the groove gate.
其中U型槽需要刻蚀到外延片的Si衬底层，U型槽底部根据实际工艺条件和电性参数设计可位于Si衬底层任一水平面，U型槽宽度为100nm-5um，可根据具体工艺条件和机器精度确定。The U-shaped groove needs to be etched into the Si substrate layer of the epitaxial wafer. The bottom of the U-shaped groove can be located at any level of the Si substrate layer according to the actual process conditions and electrical parameters. The width of the U-shaped groove is 100nm-5um, which can be determined according to the specific process. Conditions and machine accuracy determined.
进一步限定P型Si 11；Further qualifying P-type Si 11;
P型Si 11与U型槽内侧壁连接，下表面与U型槽的底部齐平，上表面低于GaN本征层4的上表面。The P-type Si 11 is connected to the inner wall of the U-shaped groove, the lower surface is flush with the bottom of the U-shaped groove, and the upper surface is lower than the upper surface of the GaN intrinsic layer 4.
以图8方向为参考方向，P型Si11从U型槽的内侧壁到SiO2薄膜10的水平方向厚度为10nm-1um。靠近SiO2薄膜表面的P型Si 11在正偏栅极电压条件下能形成反型层，反型层厚度一般只能达到10nm，为确保反型层能在P型Si11内部完全展开，设定P型Si11水平方向厚度为10nm-1um。Taking the direction of Figure 8 as the reference direction, the thickness of P-type Si11 in the horizontal direction from the inner wall of the U-shaped groove to the SiO 2 film 10 is 10nm-1um. P-type Si 11 close to the surface of the SiO 2 film can form an inversion layer under forward-biased gate voltage conditions. The thickness of the inversion layer can generally only reach 10nm. In order to ensure that the inversion layer can be fully expanded inside the P-type Si11, it is set The horizontal thickness of P-type Si11 is 10nm-1um.
进一步限定N型Si 7；Further define N-type Si 7;
N型Si 7的下表面与P型Si 11上表面接触，上表面与AlGaN势垒层6齐平。The lower surface of N-type Si7 is in contact with the upper surface of P-type Si11, and the upper surface is flush with the AlGaN barrier layer 6.
N型Si 7的水平方向的厚度与P型Si 11相同。The horizontal thickness of N-type Si 7 is the same as that of P-type Si 11.
P型Si11和N型Si7的水平方向厚度分别为10nm-1um，确保P型Si11在栅极正向偏压条件下可以形成饱和电流通道，P型Si11和N型Si7垂直方向高度之和为U型槽刻蚀深度，P型Si11上表面低于GaN HEMT器件二维电子气所在水平面，N型Si7上表面与AlGaN层上表面齐平。The horizontal thickness of P-type Si11 and N-type Si7 is 10nm-1um respectively, ensuring that P-type Si11 can form a saturated current channel under gate forward bias condition. The sum of the vertical heights of P-type Si11 and N-type Si7 is U The groove etching depth is that the upper surface of P-type Si11 is lower than the level of the two-dimensional electron gas of the GaN HEMT device, and the upper surface of N-type Si7 is flush with the upper surface of the AlGaN layer.
进一步限定SiO2薄膜10；further defining SiO 2 film 10;
SiO2薄膜10的下表面与P型Si 11下表面齐平，上表面与AlGaN势垒层6齐平，厚度为5nm-100nm，确保栅极漏电流小于1A/cm2。The lower surface of the SiO 2 film 10 is flush with the lower surface of the P-type Si 11, and the upper surface is flush with the AlGaN barrier layer 6. The thickness is 5nm-100nm, ensuring that the gate leakage current is less than 1A/cm 2 .
进一步限定多晶硅9；further defining polysilicon 9;
多晶硅9填充在SiO2薄膜10的内部，上表面与AlGaN势垒层6齐平。Polycrystalline silicon 9 is filled inside the SiO 2 film 10, and the upper surface is flush with the AlGaN barrier layer 6.
多晶硅9位于SiO2薄膜10围成的凹槽内部，即多晶硅9内部无空隙和明显缺陷，确保良好的导电能力。The polysilicon 9 is located inside the groove surrounded by the SiO 2 film 10, that is, there are no gaps or obvious defects inside the polysilicon 9, ensuring good electrical conductivity.
本发明提出了一种新型Si基GaN HEMT新型栅极结构，该栅极结构避免了P GaN增强型器件需要的P GaN刻蚀步骤，有效减小了刻蚀P GaN产生的界面态问题，刻蚀产生的界面态问题会严重影响器件在高频下的性能，引起严重的电流崩塌效应，参照图9所示(图中竖向坐标代表高频下电流崩塌效应发生后，实际电流和饱和电流的百分比)，市面上P GaN增强型器件(图中sample1和sample2)高频下电流一般为静态条件下的50％-85％，本发明提出的新型Si基GaN HEMT新型栅极结构器件(图中The device)电流崩塌效应极低，高频下电流能达到静态条件下的95％。而且该栅极采用垂直导电结构，源极位于芯片下方，并与封装框架直接相连，增强了器件的散热能力，解决了目前主流的GaN HEMT器件大多数都是水平结构器件，在大功率条件下容易产生自热效应，热量不能很好的散发的问题，参照图10所示，相同功率和同一封装条件(DFN5*6)下，本发明提出的新型Si基GaN HEMT新型栅极结构器件结到封装表面的热阻Rthjc典型值为0.5℃/W，市面上的P GaN增强型器件的热阻Rthjc在1.1-1.6之间，本发明提出的新型Si基GaN HEMT新型栅极结构器件的热阻Rthjc改善明显。The present invention proposes a new Si-based GaN HEMT new gate structure. This gate structure avoids the P GaN etching step required for P GaN enhancement-mode devices, effectively reduces the interface state problems caused by etching P GaN, and etches The interface state problems caused by corrosion will seriously affect the performance of the device at high frequencies and cause serious current collapse effects. Refer to Figure 9 (the vertical coordinates in the figure represent the actual current and saturation current after the current collapse effect occurs at high frequencies. percentage), the high-frequency current of P GaN enhancement-mode devices on the market (sample1 and sample2 in the figure) is generally 50%-85% of that under static conditions. The new Si-based GaN HEMT novel gate structure device proposed by the present invention (figure The device) has extremely low current collapse effect, and the current at high frequency can reach 95% of that under static conditions. Moreover, the gate adopts a vertical conductive structure, and the source is located under the chip and directly connected to the packaging frame, which enhances the heat dissipation capability of the device and solves the problem that most of the current mainstream GaN HEMT devices are horizontal structure devices. Under high power conditions It is easy to produce self-heating effects and the heat cannot be dissipated well. As shown in Figure 10, under the same power and the same packaging conditions (DFN5*6), the new Si-based GaN HEMT new gate structure device proposed by the present invention is connected to the package. The typical value of the thermal resistance Rthjc on the surface is 0.5°C/W. The thermal resistance Rthjc of P GaN enhancement-mode devices on the market is between 1.1-1.6. The thermal resistance Rthjc of the new Si-based GaN HEMT new gate structure device proposed by the present invention The improvement is obvious.
对于本案所公开的内容，还有以下几点需要说明：Regarding the disclosed content of this case, there are still several points that need to be explained:
(1)、本案所公开的实施例附图只涉及到与本案所公开实施例所涉及到的结构，其他结构可参考通常设计；(1) The drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case, and other structures can refer to common designs;
(2)、在不冲突的情况下，本案所公开的实施例及实施例中的特征可以相互组合以得到新的实施例；(2) If there is no conflict, the embodiments disclosed in this case and the features in the embodiments can be combined with each other to obtain new embodiments;
以上，仅为本案所公开的具体实施方式，但本公开的保护范围并不局限于此，本案所公开的保护范围应以权利要求的保护范围为准。 The above are only the specific implementation modes disclosed in this case, but the protection scope of this disclosure is not limited thereto. The protection scope disclosed in this case should be subject to the protection scope of the claims.

Claims (9)

  1. 一种Si基GaN-HEMT器件的制备方法，其特征在于，包括以下步骤:A method for preparing Si-based GaN-HEMT devices, which is characterized by comprising the following steps:
    S100，在外延片上制备U型槽；S100, prepare U-shaped groove on the epitaxial wafer;
    S200，在U型槽内从下而上依次制备P型Si(11)和N型Si(7)；S200, prepare P-type Si(11) and N-type Si(7) sequentially from bottom to top in a U-shaped groove;
    S300，在U型槽内制备SiO2薄膜(10)；S300, prepare SiO 2 thin film (10) in U-shaped groove;
    S400，在U型槽中制备多晶硅(9)；S400, preparation of polysilicon (9) in U-shaped groove;
    S500，在多晶硅(9)的上方制备栅电极(8)；S500, prepare the gate electrode (8) above the polysilicon (9);
    S600，刻蚀漏电极区域，并制备漏电极(5)；S600, etch the drain electrode area and prepare the drain electrode (5);
    S700，背面处理，并制备源电极(1)。S700, backside processing and preparation of source electrode (1).
  2. [根据细则91更正 11.05.2023]
    根据权利要求1所述的一种Si基GaN-HEMT器件的制备方法，其特征在于，步骤S100中，所述外延片包括在Si衬底(2)上依次形成的缓冲层(3)、GaN本征层(4)和AlGaN势垒层(60)。    [Correction 11.05.2023 under Rule 91]
    A method for preparing a Si-based GaN-HEMT device according to claim 1, characterized in that, in step S100, the epitaxial wafer includes a buffer layer (3), a GaN Intrinsic layer (4) and AlGaN barrier layer (60).
  3. [根据细则91更正 11.05.2023]
    根据权利要求1所述的一种Si基GaN-HEMT器件的制备方法，其特征在于，步骤S100中U型槽制备方法包括：    [Correction 11.05.2023 under Rule 91]
    A method for preparing a Si-based GaN-HEMT device according to claim 1, wherein the U-shaped groove preparation method in step S100 includes:
    对外延片依次进行清洗、涂光刻胶、光刻和显影工艺，随后用ICP干法刻蚀在外延片上刻蚀出设计深度的U型槽，最后清洗掉光刻胶。The epitaxial wafer is cleaned, coated with photoresist, photolithography and development processes in sequence, and then ICP dry etching is used to etch a U-shaped groove with a designed depth on the epitaxial wafer, and the photoresist is finally washed away.
  4. [根据细则91更正 11.05.2023]
    根据权利要求1所述的一种Si基GaN-HEMT器件的制备方法，其特征在于，步骤S200中P型Si(11)和N型Si(7)制备方法包括：    [Correction 11.05.2023 under Rule 91]
    A method for preparing Si-based GaN-HEMT devices according to claim 1, characterized in that in step S200, the preparation method of P-type Si (11) and N-type Si (7) includes:
    S210，通过涂胶、光刻和显影工艺将U型槽外区域用光刻胶保护；S210, protect the area outside the U-shaped groove with photoresist through glue coating, photolithography and development processes;
    S220，使用CVD工艺先在U型槽中沉积一层设计厚度的P型Si(11)；S220, use the CVD process to first deposit a layer of P-type Si (11) with a designed thickness in the U-shaped groove;
    S230，然后在P型Si(11)上继续使用CVD工艺沉积一层设计厚度的N型Si(7)；S230, then continue to use the CVD process to deposit a layer of N-type Si (7) with a designed thickness on the P-type Si (11);
    S240，清洗掉步骤S210中的光刻胶后重新依次进行涂胶、光刻和显影工艺，将U型槽外区域、U型槽内需要保留的P型Si(11)和N型Si(7)进行保护；随后使用ICP干法刻蚀去除U型槽内多余的P型Si(11)和N型Si(7)后清洗掉光刻胶。S240, clean the photoresist in step S210 and then re-perform the glue coating, photolithography and development processes in sequence, and remove the P-type Si (11) and N-type Si (7) that need to be retained in the area outside the U-shaped groove and in the U-shaped groove. ) for protection; then use ICP dry etching to remove excess P-type Si (11) and N-type Si (7) in the U-shaped groove and then clean off the photoresist.
  5. [根据细则91更正 11.05.2023]
    根据权利要求1所述的一种Si基GaN-HEMT器件的制备方法，其特征在于，步骤S300中SiO2薄膜(10)的制备方法包括：    [Correction 11.05.2023 under Rule 91]
    A method for preparing a Si-based GaN-HEMT device according to claim 1, wherein the method for preparing the SiO 2 film (10) in step S300 includes:
    S310，通过涂胶、光刻和显影将U型槽外区域和U型槽内已制备P型Si(11)和N型Si(7)区域用光刻胶保护；S310, protect the area outside the U-shaped groove and the prepared P-type Si (11) and N-type Si (7) areas with photoresist through glue coating, photolithography and development;
    S320，使用CVD工艺在U型槽内剩余区域沉积设计厚度的SiO2，清洗掉步骤S310中的光刻胶后重新涂胶、光刻和显影，将U型槽外区域、U型槽内需要保留的P型Si(11)、N型Si(7)和SiO2薄膜(10)保护，随后使用ICP干法刻蚀去除U型槽内多余的SiO2后清洗掉光刻胶。S320, use the CVD process to deposit SiO 2 with a designed thickness in the remaining area in the U-shaped groove. Clean the photoresist in step S310 and then re-coat, photoetch and develop. The remaining P-type Si (11), N-type Si (7) and SiO 2 films (10) are protected, and then ICP dry etching is used to remove excess SiO 2 in the U-shaped groove and then the photoresist is cleaned.
  6. [根据细则91更正 11.05.2023]
    根据权利要求1所述的一种Si基GaN-HEMT器件的制备方法，其特征在于，步骤S400中多晶硅(9)的制备方法包括：    [Correction 11.05.2023 under Rule 91]
    A method for preparing Si-based GaN-HEMT devices according to claim 1, characterized in that the method for preparing polysilicon (9) in step S400 includes:
    S410，通过涂胶、光刻和显影工艺将U型槽外区域、U型槽内已制备P型Si(11)区域、N型Si(7)区域和SiO2薄膜10区域用光刻胶进行保护；S410, use photoresist to process the area outside the U-shaped groove, the prepared P-type Si (11) area, the N-type Si (7) area and the SiO 2 film 10 area in the U-shaped groove through glue coating, photolithography and development processes. Protect;
    S420，使用CVD工艺在U型槽内剩余区域沉积设计厚度的多晶硅(9)后清洗掉光刻胶。S420, use a CVD process to deposit polysilicon (9) with a designed thickness in the remaining area of the U-shaped groove and then clean the photoresist.
  7. [根据细则91更正 11.05.2023]
    根据权利要求1所述的一种Si基GaN-HEMT器件的制备方法，其特征在于，步骤S500中栅电极(8)的制备方法包括：    [Correction 11.05.2023 under Rule 91]
    A method for preparing a Si-based GaN-HEMT device according to claim 1, characterized in that the preparation method of the gate electrode (8) in step S500 includes:
    S510，通过涂胶、光刻和显影工艺将除栅电极(8)所在区域用光刻胶保护；S510, protect the area where the gate electrode (8) is located with photoresist through glue coating, photolithography and development processes;
    S520，使用MOCVD或金属离子溅射沉积工艺在多晶硅(9)上设计区域制备栅电极(8)，随后清洗掉光刻胶。S520, use MOCVD or metal ion sputtering deposition process to prepare a gate electrode (8) in a designed area on the polysilicon (9), and then clean the photoresist.
  8. [根据细则91更正 11.05.2023]
    根据权利要求1所述的一种Si基GaN-HEMT器件的制备方法，其特征在于，步骤S600中漏电极(5)的制备方法包括：    [Correction 11.05.2023 under Rule 91]
    The preparation method of a Si-based GaN-HEMT device according to claim 1, characterized in that the preparation method of the drain electrode (5) in step S600 includes:
    S610，通过涂胶、光刻和显影工艺对除漏电极(5)所在区域用光刻胶进行保护；S610, protect the area where the drain electrode (5) is located with photoresist through glue coating, photolithography and development processes;
    S620，使用ICP干法刻蚀在外延片上刻蚀出设计深度的漏电极槽；S620, use ICP dry etching to etch the drain electrode groove with the designed depth on the epitaxial wafer;
    S630，清洗掉步骤S610中的光刻胶后重新进行涂胶、光刻和显影工艺将除漏电极(5)所在区域用光刻胶保护；S630, clean off the photoresist in step S610 and then perform the glue coating, photolithography and development processes again to protect the area where the drain electrode (5) is located with photoresist;
    S640，使用MOCVD或金属离子溅射沉积工艺在漏电极槽区域制备漏电极(5)，随后清洗掉光刻胶。S640, use MOCVD or metal ion sputtering deposition process to prepare the drain electrode (5) in the drain electrode groove area, and then clean the photoresist.
  9. [根据细则91更正 11.05.2023]
    根据权利要求1所述的一种Si基GaN-HEMT器件的制备方法，其特征在于，步骤S700中源电极(1)的制备方法包括：    [Correction 11.05.2023 under Rule 91]
    A method for preparing a Si-based GaN-HEMT device according to claim 1, wherein the method for preparing the source electrode (1) in step S700 includes:
    S710，使用UV膜将芯片正面保护；S710, use UV film to protect the front side of the chip;
    S720，通过研磨和抛光工艺将芯片背面减薄；S720, which thins the backside of the chip through grinding and polishing processes;
    S730，使用MOCVD或金属离子溅射沉积工艺在芯片背面制备源电极(1)，随后将UV膜去除，制备完成。S730, use MOCVD or metal ion sputtering deposition process to prepare the source electrode (1) on the back of the chip, and then remove the UV film to complete the preparation.
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