CN217641347U - Novel Si-based GaN groove grid type vertical conductive device - Google Patents
Novel Si-based GaN groove grid type vertical conductive device Download PDFInfo
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- CN217641347U CN217641347U CN202221629766.2U CN202221629766U CN217641347U CN 217641347 U CN217641347 U CN 217641347U CN 202221629766 U CN202221629766 U CN 202221629766U CN 217641347 U CN217641347 U CN 217641347U
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Abstract
A novel Si-based GaN groove grid type vertical conductive device. Relates to a semiconductor device, in particular to a novel Si-based GaN groove gate type vertical conductive device. The GaN-based light-emitting diode comprises a source electrode, a Si substrate, a buffer layer, a GaN intrinsic layer and an AlGaN barrier layer which are sequentially connected from bottom to top; the drain electrode is positioned at the end part of the device, passes through the AlGaN barrier layer from top to bottom and then extends into the GaN intrinsic layer; the middle part of the device is provided with a U-shaped groove extending from the AlGaN barrier layer to the substrate; the U-shaped grooveIs internally provided with SiO 2 A film; the SiO 2 P-type Si and N-type Si are sequentially arranged between the film and the inner side wall of the U-shaped groove from bottom to top; the SiO 2 The middle part of the film is provided with polycrystalline silicon. The utility model has the advantages of it is following: the device source is arranged at the bottom, so that the area of a PAD region of the source on the surface of the chip is saved; the interface state problem and the high-frequency current collapse effect caused by the current mainstream P-GaN enhancement type device etching are avoided, and therefore the development and the application of the Si-based GaN HEMT in the field of power electronics are promoted.
Description
Technical Field
The utility model relates to a semiconductor device especially relates to a novel perpendicular conducting device of Si base gaN recess grid type.
Background
In the technical field of power electronic devices, as the current mainstream Si devices are approaching the performance limit determined by the material characteristics, the third generation semiconductors represented by GaN and SiC are more and more emphasized by people, gaN has the advantages of large forbidden bandwidth, high critical breakdown field strength and high electron mobility, and has strong application potential in the markets of power devices such as fast charging, data centers, OBCs, solar inverters and the like.
At present, the main application form of GaN in a power device is a GaN HEMT device, a first AlGaN/GaN High Electron Mobility Transistor (HEMT) is manufactured by Khan and the like in 1993 years, the GaN HEMT device with a horizontal structure is widely concerned by people due to the electrical performance superior to that of a Si device and lower energy consumption, a first commercial depletion type radio frequency GaN HEMT device growing on a Si substrate is introduced by nitiron in 2005, and a first enhancement type Si-based GaN HEMT device is introduced by EPC in 2009.
Although the GaN HEMT device has performance superior to that of a traditional Si device, problems still exist to restrict application of the GaN HEMT device, for example, a P GaN layer above AlGaN needs to be etched in a currently mainstream P GaN enhancement type device, the performance of the device under high frequency can be seriously affected by interface state problems generated by etching, a serious current collapse effect is caused, and other defects such as an F ion implantation enhancement type GaN HEMT and a cascode hybrid enhancement type GaN HEMT also have the defects that process conditions are difficult to control and the like.
SUMMERY OF THE UTILITY MODEL
The utility model provides a to above problem, provide a novel perpendicular conductive device of Si base GaN recess grid type that has effectively reduced the interface state problem that sculpture P GaN produced, has improved the device heat dispersion.
The technical scheme of the utility model is that: a novel Si-based GaN groove grid type vertical conductive device comprises a source electrode, a Si substrate, a buffer layer, a GaN intrinsic layer and an AlGaN barrier layer which are sequentially connected from bottom to top;
the drain electrode is positioned at the end part of the device, passes through the AlGaN barrier layer from top to bottom and then extends into the GaN intrinsic layer;
the middle part of the device is provided with a U-shaped groove extending from the AlGaN barrier layer to the substrate;
SiO is arranged in the U-shaped groove 2 A film;
the SiO 2 P-type Si and N-type Si are sequentially arranged between the film and the inner side wall of the U-shaped groove from bottom to top;
the SiO 2 Polycrystalline silicon is arranged in the middle of the film;
and the top of the polysilicon is provided with an upwardly extending gate electrode.
Specifically, the P-type Si is connected with the inner side wall of the U-shaped groove, the lower surface of the P-type Si is flush with the bottom of the U-shaped groove, and the upper surface of the P-type Si is lower than the upper surface of the GaN intrinsic layer.
Specifically, the thickness of the P-type Si from the inner side wall of the U-shaped groove to the horizontal direction of the SiO2 film is 10nm-1um.
Specifically, the lower surface of the N-type Si is in contact with the upper surface of the P-type Si, and the upper surface of the N-type Si is flush with the AlGaN barrier layer.
Specifically, the lower surface of the SiO2 film is flush with the lower surface of the P-type Si, and the upper surface of the SiO2 film is flush with the AlGaN barrier layer.
Specifically, the polysilicon is filled in the SiO2 film, and the upper surface of the polysilicon is flush with the AlGaN barrier layer.
The utility model provides a grid structure is a U type groove composite grid structure, and composite grid structure is arranged in U type groove, forms a class MOS structure with n type Si in the substrate, controls the break-make of gaN HEMT through the break-make of control class MOS structure channel, and the invention has following advantage: the device source is arranged at the bottom, so that the area of a PAD region of the source on the surface of the chip is saved; the interface state problem and the high-frequency current collapse effect caused by the current mainstream P-GaN enhancement type device etching are avoided, and therefore the development and the application of the Si-based GaN HEMT in the field of power electronics are promoted.
Drawings
Figure 1 is a process flow diagram of the present invention,
figure 2 is a schematic view of step S100,
figure 3 is a schematic view of step S200,
figure 4 is a schematic view of step S300,
figure 5 is a schematic view of step S400,
figure 6 is a schematic view of step S500,
figure 7 is a schematic view of step S600,
fig. 8 is a schematic diagram of step S700;
in the figure, 1 is a source electrode, 2 is a Si substrate, 3 is a buffer layer, 4 is a GaN intrinsic layer, 5 is a drain electrode, 6 is an AlGaN barrier layer, 7 is N-type Si, 8 is a gate electrode, 9 is polysilicon, and 10 is SiO 2 The thin film 11 is P-type Si.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
The present invention is illustrated in FIGS. 1-8; a preparation method of a Si-based GaN-HEMT device comprises the following steps:
s100, preparing a U-shaped groove on the epitaxial wafer; as shown with reference to FIG. 2;
further, in step S100, the epitaxial wafer includes a buffer layer 3, a GaN intrinsic layer 4, and an AlGaN barrier layer 60 formed in this order on a Si substrate 2.
Further, the method for preparing the U-shaped groove in the step S100 includes:
and cleaning the epitaxial wafer, coating photoresist, photoetching and developing processes in sequence, etching a U-shaped groove with the designed depth on the epitaxial wafer by using ICP dry etching, and finally cleaning the photoresist.
S200, preparing P-type Si11 and N-type Si7 in the U-shaped groove from bottom to top in sequence; as shown with reference to FIG. 3;
further, the method for preparing P-type Si11 and N-type Si7 in step S200 includes:
s210, protecting the area outside the U-shaped groove by using photoresist through the processes of gluing, photoetching and developing;
s220, depositing a layer of P-type Si11 with designed thickness in the U-shaped groove by using a CVD (chemical vapor deposition) process;
s230, continuously depositing a layer of N-type Si7 with the designed thickness on the P-type Si11 by using a CVD (chemical vapor deposition) process;
s240, cleaning the photoresist in the step S210, then sequentially performing gluing, photoetching and developing processes again, and protecting the P-type Si11 and the N-type Si7 which are required to be reserved in the area outside the U-shaped groove and in the U-shaped groove; and then removing redundant P-type Si11 and N-type Si7 in the U-shaped groove by ICP dry etching, and cleaning the photoresist to prepare and obtain the device shapes of the P-type Si11 and N-type Si7 shown in the figure 3.
S300, preparing SiO in a U-shaped groove 2 A film 10; as shown with reference to FIG. 4;
further, siO in step S300 2 The method of making the film 10 includes:
s310, protecting the areas outside the U-shaped groove and the areas inside the U-shaped groove, which are prepared with P-type Si11 and N-type Si7, with photoresist through gluing, photoetching and developing;
s320, depositing SiO with designed thickness in the residual area in the U-shaped groove by using CVD process 2 Cleaning the photoresist in the step S310, then coating, photoetching and developing again, and reserving the P-type Si11, N-type Si7 and SiO in the region outside the U-shaped groove and the region inside the U-shaped groove 2 Film 10 protection, followed by removal of excess SiO in the U-grooves using ICP dry etch 2 The photoresist is cleaned off, FIG. 4 is a process for preparing SiO in a U-shaped groove 2 Device topography behind film 10.
S400, preparing polycrystalline silicon 9 in the U-shaped groove; as shown with reference to FIG. 5;
further, the method for preparing the polycrystalline silicon 9 in the step S400 includes:
s410, 1Gluing, photoetching and developing to prepare a P-type Si11 region, an N-type Si7 region and SiO in the region outside the U-shaped groove and in the U-shaped groove 2 The region of the film 10 is protected by photoresist;
and S420, depositing polysilicon 9 with the designed thickness in the residual area in the U-shaped groove by using a CVD (chemical vapor deposition) process, and then cleaning the photoresist, wherein the device appearance after the polysilicon 9 is prepared in the U-shaped groove is shown in figure 5.
S500, preparing a gate electrode 8 above the polycrystalline silicon 9; as shown with reference to FIG. 6;
further, the method for preparing the gate electrode 8 in step S500 includes:
s510, protecting the region where the gate electrode removing 8 is located by using photoresist through the processes of coating, photoetching and developing;
s520, preparing a gate electrode 8 on the polycrystalline silicon 9 in the designed area by using an MOCVD (metal organic chemical vapor deposition) or metal ion sputtering deposition process, and then cleaning away the photoresist, wherein the appearance of the device after the gate electrode 8 is prepared in the U-shaped groove is shown in FIG. 6.
S600, etching the drain electrode area and preparing a drain electrode 5; as shown with reference to FIG. 7;
further, the method for preparing the drain electrode 5 in step S600 includes:
s610, protecting the photoresist in the region where the drain electrode 5 is located through gluing, photoetching and developing processes;
s620, etching a drain electrode groove with a designed depth on the epitaxial wafer by using ICP dry etching;
s630, cleaning the photoresist in the step S610, and then performing the processes of coating, photoetching and developing again to protect the region where the drain electrode 5 is located by the photoresist;
s640, preparing the drain electrode 5 in the drain electrode groove area by using MOCVD or metal ion sputtering deposition technology, and then cleaning away the photoresist, wherein the appearance of the device after etching the drain electrode area and preparing the drain electrode 5 is shown in FIG. 7.
S700, carrying out back processing and preparing a source electrode 1; as shown with reference to fig. 8.
Further, the method for preparing the source electrode 1 in step S700 includes:
s710, protecting the front surface of the chip by using a UV film;
s720, thinning the back of the chip by grinding and polishing processes;
s730, preparing a source electrode 1 on the back of the chip by using MOCVD or metal ion sputtering deposition technology, and then removing the UV film to complete the preparation of the novel grid structure device of the Si-based GaN HEMT, wherein the appearance of the device after back treatment and preparation of the source electrode 1 is shown in FIG. 8.
Referring to fig. 8, the Si-based GaN-HEMT device includes a source electrode 1, a Si substrate 2, a buffer layer 3, a GaN intrinsic layer 4, and an AlGaN barrier layer 6 connected in this order from the bottom;
the drain electrode 5 is positioned at the end part of the device, passes through the AlGaN barrier layer 6 from top to bottom and then extends into the GaN intrinsic layer 4 to ensure good connection with two-dimensional electron gas;
the middle part of the device is provided with a U-shaped groove extending from the AlGaN barrier layer 6 to the substrate 2;
SiO is arranged in the U-shaped groove 2 A film 10;
the SiO 2 A P-type Si11 and an N-type Si7 are sequentially arranged between the film 10 and the inner side wall of the U-shaped groove from bottom to top;
the SiO 2 The middle part of the film 10 is provided with polycrystalline silicon 9;
the top of the polysilicon 9 is provided with an upwardly extending gate electrode 8. The gate electrode 8 is located above the polysilicon 9, and the lower surface thereof is in contact with the upper surface of the polysilicon 9 to form an ohmic contact. The gate electrode 8 is a Ti/Al metal layer to ensure that the gate electrode 8 forms a good ohmic contact with the polysilicon 9.
According to the scheme, a U-shaped groove and a composite grid electrode (comprising polycrystalline silicon 9, a SiO2 film 10 and P-type Si 11) in the groove form a grid electrode structure of a device, the U-shaped groove is formed in an etching mode and provides a vertical conductive channel of the device, the U-shaped groove is deeply etched to an epitaxial wafer Si substrate layer and is etched excessively, and the composite grid electrode structure is located in a groove grid.
The U-shaped groove needs to be etched to a Si substrate layer of an epitaxial wafer, the bottom of the U-shaped groove can be located on any horizontal plane of the Si substrate layer according to actual process conditions and electrical parameter design, the width of the U-shaped groove is 100nm-5 microns, and the U-shaped groove can be determined according to specific process conditions and machine precision.
Further defining P-type Si11;
the P-type Si11 is connected with the inner side wall of the U-shaped groove, the lower surface of the P-type Si11 is flush with the bottom of the U-shaped groove, and the upper surface of the P-type Si11 is lower than the upper surface of the GaN intrinsic layer 4.
Taking the direction of FIG. 8 as a reference direction, the P-type Si11 is from the inner side wall of the U-shaped groove to SiO 2 The thickness of the film 10 in the horizontal direction is 10nm to 1um. Close to SiO 2 The P-type Si11 on the surface of the film can form an inversion layer under the condition of forward bias grid voltage, the thickness of the inversion layer can only reach 10nm generally, and in order to ensure that the inversion layer can be completely spread in the P-type Si11, the thickness of the P-type Si11 in the horizontal direction is set to be 10nm-1um.
Further defining N-type Si7;
the lower surface of the N-type Si7 is in contact with the upper surface of the P-type Si11, and the upper surface is flush with the AlGaN barrier layer 6.
The thickness of the N-type Si7 in the horizontal direction is the same as that of the P-type Si 11.
The thicknesses of the P-type Si11 and the N-type Si7 in the horizontal direction are respectively 10nm-1um, a saturated current channel can be formed by the P-type Si11 under the condition that the grid is forward biased, the sum of the heights of the P-type Si11 and the N-type Si7 in the vertical direction is the etching depth of the U-shaped groove, the upper surface of the P-type Si11 is lower than the horizontal plane where two-dimensional electron gas of a GaN HEMT device is located, and the upper surface of the N-type Si7 is flush with the upper surface of the AlGaN layer.
Further define SiO 2 A film 10;
SiO 2 the lower surface of the film 10 is flush with the lower surface of the P-type Si11, the upper surface of the film is flush with the AlGaN barrier layer 6, the thickness of the film is 5nm-100nm, and the grid leakage current is ensured to be less than 1A/cm 2 。
Further defining the polysilicon 9;
Claims (6)
1. A novel Si-based GaN groove grid type vertical conductive device is characterized by comprising a source electrode, a Si substrate, a buffer layer, a GaN intrinsic layer and an AlGaN barrier layer which are sequentially connected from bottom to top;
the drain electrode is positioned at the end part of the device, passes through the AlGaN barrier layer from top to bottom and then extends into the GaN intrinsic layer;
the middle part of the device is provided with a U-shaped groove extending from the AlGaN barrier layer to the substrate;
SiO is arranged in the U-shaped groove 2 A film;
the SiO 2 P-type Si and N-type Si are sequentially arranged between the film and the inner side wall of the U-shaped groove from bottom to top;
the SiO 2 Polycrystalline silicon is arranged in the middle of the film;
and the top of the polycrystalline silicon is provided with an upwardly extending gate electrode.
2. The new Si-based GaN groove-gated vertical conduction device of claim 1, wherein the P-type Si is connected to the inner sidewall of the U-shaped groove, the lower surface is flush with the bottom of the U-shaped groove, and the upper surface is lower than the upper surface of the GaN intrinsic layer.
3. The novel Si-based GaN groove gate type vertical conduction device according to claim 1, wherein the thickness of the P-type Si in the horizontal direction from the inner side wall of the U-shaped groove to the SiO2 film is 10nm-1um.
4. The new Si-based GaN groove-gate type vertical conduction device as claimed in claim 1, wherein the lower surface of N-type Si is in contact with the upper surface of P-type Si, and the upper surface is flush with the AlGaN barrier layer.
5. The device of claim 1, wherein the lower surface of the SiO2 thin film is flush with the lower surface of the P-type Si, and the upper surface is flush with the AlGaN barrier layer.
6. The device of claim 1, wherein the polysilicon is filled in the SiO2 film, and the upper surface of the polysilicon is flush with the AlGaN barrier layer.
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| CN202221629766.2U CN217641347U (en) | 2022-06-28 | 2022-06-28 | Novel Si-based GaN groove grid type vertical conductive device |
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| CN202221629766.2U CN217641347U (en) | 2022-06-28 | 2022-06-28 | Novel Si-based GaN groove grid type vertical conductive device |
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