WO2010038150A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2010038150A1
WO2010038150A1 PCT/IB2009/007033 IB2009007033W WO2010038150A1 WO 2010038150 A1 WO2010038150 A1 WO 2010038150A1 IB 2009007033 W IB2009007033 W IB 2009007033W WO 2010038150 A1 WO2010038150 A1 WO 2010038150A1
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WO
WIPO (PCT)
Prior art keywords
layer
semiconductor device
current blocking
semiconductor
based compound
Prior art date
Application number
PCT/IB2009/007033
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French (fr)
Inventor
Daigo Kikuta
Tetsuo Narita
Narumasa Soejima
Masahiro Sugimoto
Original Assignee
Toyota Jidosha Kabushiki Kaisha
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Publication of WO2010038150A1 publication Critical patent/WO2010038150A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • the invention relates to a semiconductor device formed from a group III nitride-based compound semiconductor.
  • JP-A-2007-5764 Semiconductor devices realized by group III nitride-based compound semiconductors are currently under development, and an example thereof is disclosed in Japanese Patent Application Publication No. 2007-5764 (JP-A-2007-5764).
  • the semiconductor device described in JP-A-2007-5764 is structured by laminating an upper layer formed from a p-type group III nitride-based compound semiconductor onto a lower layer formed from an n-type group III nitride-based compound semiconductor. An aperture is penetrated through the upper layer of the p-type upper layer, and an n-type or i-type group III nitride-based compound semiconductor is charged into the aperture.
  • a depletion layer ought to extend from the p-type group III nitride-based compound semiconductor toward the n-type or i-type group III nitride-based compound semiconductor charged into the aperture and the n-type group III nitride-based compound semiconductor forming the lower layer. It is assumed that when the depletion layer extends to the aperture, voltage resistance to a high voltage applied between a front surface side electrode and a rear surface side electrode will be secured by the depletion layer. In actuality, however, it is difficult to secure resistance to high voltages for the following reasons.
  • the structure described above is a laminated structure realized by laminating the upper layer formed from a p-type group III nitride-based compound semiconductor onto the lower layer formed from an n-type group III nitride-based compound semiconductor.
  • the aperture penetrated through the upper layer is manufactured by etching a part of the front surface of the upper layer. To manufacture the aperture penetrated through the upper layer, etching is performed from the front surface of the upper layer to a rear surface of the upper layer. In other words, the etching is continued until the n-type lower layer is exposed to a bottom surface of the aperture. A front surface of the n-type lower layer exposed to the bottom surface of the aperture is also etched.
  • the n-type or i-type group III nitride-based compound semiconductor is formed through crystal growth from the front surface of the n-type lower layer exposed to the bottom surface of the aperture, whereupon the n-type or i-type group HI nitride-based compound semiconductor is charged into the aperture.
  • a highly doped n-type region is formed between the n-type or i-type group III nitride-based compound semiconductor charged into the aperture and the n-type group HI nitride-based compound semiconductor positioned therebelow.
  • the depletion layer cannot extend widely toward the group III nitride-based compound semiconductor charged into the aperture while the semiconductor device is switched OFF.
  • voltage resistance cannot be secured by a depletion layer that extends widely toward the group ⁇ i nitride-based compound semiconductor charged into the aperture when the semiconductor device is switched OFF.
  • Various semiconductor structures are created on the p-type group HI nitride-based compound semiconductor layer formed with the aperture in accordance with the characteristics of the semiconductor device.
  • a heterostructure is formed by laminating a surface side lower layer formed from a group III nitride-based compound semiconductor and a surface side upper layer formed from a group III nitride-based compound semiconductor having a wider band gap than the surface side lower layer onto the p-type group III nitride-based compound semiconductor layer.
  • HEMT High Electron Mobility Transistor
  • MOSFET Metal-Oxide Semiconductor Field-Effect Transistor
  • the invention has been developed with the aim of improving voltage resistance in a semiconductor device having a group III nitride-based compound semiconductor layer formed with an aperture.
  • a first aspect of the invention relates to a semiconductor device including: a lower layer formed from an n-type group III nitride-based compound semiconductor; and an upper layer formed from a p-type group III nitride-based compound semiconductor laminated onto the lower layer. An aperture is penetrated through the upper layer. An n-type or i-type group III nitride-based compound semiconductor is charged into the aperture. A suspended current blocking region is formed in a part of the lower layer.
  • the suspended current blocking region is formed in a part of the n-type lower layer, as in the aspect described above, a depletion layer extends from the suspended current blocking region to the n-type lower layer.
  • a voltage applied to the n-type or i-type group III nitride-based compound semiconductor charged into the aperture decreases, thereby ensuring that a high voltage is not applied to a semiconductor structure formed on an upper portion of the p-type group III nitride-based compound semiconductor layer.
  • an improvement in the voltage resistance of the semiconductor device is achieved.
  • the voltage resistance of the semiconductor device is improved by forming the suspended current blocking region in a part of the n-type lower layer even when a heterostructure is formed on the p-type upper layer.
  • a Field-effect Transistor (FET) structure constituted by a surface side layer formed from a group III nitride-based compound semiconductor, a gate insulation layer covering a surface of the surface side layer, and a gate electrode formed on an upper surface of the gate insulation layer may be formed.
  • FET Field-effect Transistor
  • the voltage resistance of the semiconductor device is improved by forming the suspended current blocking region in a part of the n-type lower layer even when a FET structure is formed on the p-type upper layer.
  • a MOSFET structure constituted by a gate insulation layer and a gate electrode formed on an upper surface of the gate insulation layer may be formed on the upper layer.
  • a formation range of the suspended current blocking region when the semiconductor substrate is seen from above.
  • a formation range of the suspended current blocking region and a formation range of the aperture may overlap in a semiconductor device mounting direction.
  • the voltage applied to the n-type group III nitride-based compound semiconductor charged into the aperture decreases dramatically, and therefore the voltage resistance of the semiconductor device is improved effectively.
  • a formation range of the suspended current blocking region may be extended wider than a formation range of the aperture in a semiconductor device mounting direction.
  • a plurality of formation ranges of the suspended current blocking region may be disposed discretely, and intervals between adjacent suspended current blocking regions may be set at a length at which depletion layers extending toward the upper layer from the suspended current blocking regions when the semiconductor device is switched off.
  • the suspended current blocking region may be formed from a single layer or a plurality of layers.
  • the suspended current blocking region When the semiconductor that exists in a part of the n-type lower layer, or in other words the suspended current blocking region, has a deeper level located further toward a valence band side than an intermediate value between a conduction band and the valence band, the semiconductor having this deeper level prevents a current from flowing.
  • the semiconductor that exists in a part of the n-type lower layer is a p-type semiconductor
  • the p-type semiconductor prevents a current from flowing.
  • the suspended current blocking region may have a deeper level located further toward a valence band side than an intermediate value between a conduction band of the semiconductor and the valence band.
  • the suspended current blocking region may be formed from a p-type semiconductor.
  • the level of the suspended current blocking region may enter a band gap by 0.2 to 1.7 eV from the valence band.
  • the upper layer may have a thickness of approximately 10 ⁇ m in a lamination direction
  • the suspended current blocking region (8) may have a thickness of approximately 500 nm in the lamination direction.
  • a second aspect of the invention relates to a manufacturing method for a semiconductor device.
  • the manufacturing method for a semiconductor device includes: preparing a substrate formed from an n-type group III nitride-based compound semiconductor; forming a lower layer by crystal growth from an n-type group III nitride-based compound semiconductor on an upper surface of the substrate in a semiconductor device mounting direction using a metalorganic chemical vapor deposition (MOCVD) method; forming a suspended current blocking layer by crystal growth on an upper surface of the lower layer; forming a first mask layer over an entire upper surface of the suspended current blocking layer in the semiconductor device mounting direction; performing photolithography and etching on the first mask layer to remove the entire first mask layer except for a part of the first mask layer in which a suspended current blocking region is to be formed; implementing chlorine-based plasma etching using the partially remaining first mask layer as a mask to remove a part of the suspended current blocking layer that is exposed from the first mask layer; forming the lower layer again by crystal growth on the lower
  • the aperture may be formed by forming a second mask layer over the entire upper surface of the upper layer in the semiconductor device mounting direction, removing a part of the second mask layer in which the aperture is to be formed through photolithography and etching, implementing dry etching using the remaining second mask layer as a mask, and removing a part of the upper layer that is exposed from the second mask layer.
  • the aspect described above may further include: forming an n-type or i-type group III nitride-based compound first semiconductor layer by crystal growth in a part exposed to the upper surface of the upper layer in the semiconductor device mounting direction and forming an n-type or i-type group III nitride-based compound semiconductor charging layer by crystal growth on a front surface of the lower layer that is exposed to a bottom surface of the aperture; laminating a second semiconductor layer formed from a group III nitride-based compound semiconductor having a wider band gap than the semiconductor layer; selectively etching the second semiconductor layer and the i-type first semiconductor layer to expose a part of the upper layer and a front surface of the semiconductor layer; forming a contact region and a source contact region; and forming a gate insulation layer, a gate electrode, a source electrode, and a drain electrode.
  • a third aspect of the invention relates to a manufacturing method for a semiconductor device.
  • the manufacturing method for a semiconductor device includes: preparing a substrate formed from an n-type group III nitride-based compound semiconductor; forming a lower layer by crystal growth from an n-type group III nitride-based compound semiconductor on an upper surface of the substrate using an MOCVD method; forming a mask layer over an entire upper surface of the lower layer; removing a part of the mask layer in which a suspended current blocking region is to be formed by photolithography and etching; ion-implanting one or more impurities selected from Al, C, Fe, Mg, and Zn using the remaining mask layer as a mask; forming the lower layer again by crystal growth on the upper surface of the lower layer in which the suspended current blocking region is formed; forming an upper layer by crystal growth from a p-type group III nitride-based compound semiconductor on the upper surface of the lower layer in a semiconductor device mounting direction; and forming the lower layer
  • FIG 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment
  • FIG 2 shows an equipotential line distribution of a semiconductor device not formed with a suspended current blocking region
  • FIG 3 shows an equipotential line distribution of a semiconductor device formed with a suspended current blocking region
  • FIG. 4 shows a cross-section of the semiconductor device according to the first embodiment in a state where a manufacturing process has been partially been implemented
  • FIG 5 shows a cross-section following FIG 4 in a state where the manufacturing process has been further implemented
  • FIG 6 shows a cross-section following FIG. 5 in a state where the manufacturing process has been further implemented
  • FIG. 7 shows a cross-section following FIG. 6 in a state where the manufacturing process has been further implemented
  • FIG 8 shows a cross-section following FIG. 7 in a state where the manufacturing process has been further implemented
  • FIG 9 shows a cross-section following FIG 8 in a state where the manufacturing process has been further implemented
  • FIG 10 shows a cross-section following FIG 9 in a state where the manufacturing process has been further implemented
  • FIG 11 shows a cross-section following FIG. 10 in a state where the manufacturing process has been further implemented
  • FIG 12 shows a cross-section following FIG 11 in a state where the manufacturing process has been further implemented
  • FIG 13 is a view showing another manufacturing process of the semiconductor device according to the first embodiment, and shows a cross-section thereof in a state where the manufacturing process has been partially implemented;
  • FIG 14 shows a cross-section following FIG. 13 in a state where the manufacturing process has been further implemented
  • FIG. 15 shows a cross-section following FIG 14 in a state where the manufacturing process has been further implemented
  • FIG 16 shows a cross-section following FIG 15 in a state where the manufacturing process has been further implemented
  • FIG. 17 shows a cross-section following FIG. 16 in a state where the manufacturing process has been further implemented
  • FIG 18 shows a cross-section following FIG. 17 in a state where the manufacturing process has been further implemented
  • FIG. 19 shows a cross-section following FIG 18 in a state where the manufacturing process has been further implemented
  • FIG. 20 shows a cross-section following FIG 19 in a state where the manufacturing process has been further implemented
  • FIG. 21 shows a cross-section following FIG. 20 in a state where the manufacturing process has been further implemented
  • FIG 22 is a sectional view of a semiconductor device according to a second embodiment
  • FIG 23 is a sectional view of a semiconductor device according to a third embodiment.
  • FIG 24 is a sectional view of a semiconductor device according to a fourth embodiment.
  • Gallium nitride may be used as a group HI nitride-based compound semiconductor employed to implement the invention.
  • Aluminum (Aluminium) gallium nitride AlGaN
  • AlGaN Aluminum gallium nitride
  • a current block layer formed from GaN is formed by implementing a GaN epitaxial growth method while introducing an impurity such as AI, Mg, C, Ze, or Fe.
  • an impurity such as AI, Mg, C, Ze, or Fe.
  • a current block region which is removed (insulated) from the periphery of the n-type GaN lower layer and in which a voltage varies in accordance with a peripheral voltage is formed in the n-type GaN lower layer.
  • a suspended current blocking region is formed.
  • the processing for forming the n-type GaN lower layer is halted midway and an impurity such as Al, Mg, C, Ze, or Fe is ion-injected into a part of the region thereof, whereupon the processing for forming the n-type GaN lower layer is resumed.
  • an impurity such as Al, Mg, C, Ze, or Fe
  • FIG 1 is a sectional view of a semiconductor device 30 according to a first embodiment.
  • the semiconductor device according to the first embodiment is a HEMT using a heterojunction between GaN and AlGaN.
  • the semiconductor device is a vertical semiconductor device in which a source electrode 14 and a drain electrode 2 are formed separately on a front surface and a rear surface.
  • the drain electrode 2 In order from a rear surface side, the drain electrode 2, an n + -type GaN layer 4, an n " -type GaN layer 6, a p-type GaN layer 10 formed with an aperture 28, an i-type GaN layer 24, an AlGaN layer 22, a gate insulation layer 20, and a gate electrode 18 are laminated.
  • a GaN layer 26 is charged into the aperture 28.
  • the GaN layer 26 is manufactured in an identical process to the i-type GaN layer 24 under i-type GaN crystal growth conditions. However, in a site where a periphery is surrounded by a wall surface, such as the interior of the aperture, impurities are more likely to be introduced during crystal growth than when crystal growth is performed on a plane not surrounded by a wall surface.
  • the GaN layer 26 grown in the aperture 28 is more likely to be formed as a high density n-type layer due to residual impurities in a reactor.
  • the n + -type GaN layer 4 functions as a drain contact layer, while the n -type GaN layer 6 functions as a drift layer.
  • a p + -type GaN region 12 is formed on either side of the aperture 28.
  • the p + -type GaN region 12 is formed in a part of the p-type GaN layer 10.
  • the p + -type GaN region 12 functions as a p contact region 12.
  • An n + -type GaN region 16 is formed on either side of the aperture 28.
  • the n + -type GaN region 16 contacts the i-type GaN layer 24 and the AlGaN layer 22.
  • the n*-type GaN region 16 functions as a source contact region 16.
  • a source electrode 14 is formed on either side of the aperture 28.
  • the source electrode 14 contacts the source contact region 16 and the p contact region 12.
  • a suspended current blocking region 8 is buried in the n -type GaN layer 6.
  • the suspended current blocking region 8 is formed in a range overlapping the aperture 28 when the semiconductor device 30 is seen from the above. More specifically, the suspended current blocking region 8 extends beyond a range overlapping the aperture 28 lengthwise.
  • the formation range of the suspended current blocking region 8 may exceed an intended range as long as the suspended current blocking region 8 exists in a range overlapping the aperture 28.
  • the semiconductor device 30 is used by connecting the drain electrode 2 to a high potential side of a direct current power supply and grounding the source electrode 14.
  • a depletion layer extends from an interface between the p-type GaN layer 10 and the i-type GaN layer 24 toward the i-type GaN layer 24.
  • the depletion layer also extends to a heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22.
  • a carrier does not exist on the heterojunction interface between the i-type GaN layer 24 and the AJGaN layer 22 unless a positive voltage is applied to the gate electrode 18, and therefore a current does not flow from the drain electrode 2 to the source electrode 14.
  • the semiconductor device 30 has a normally OFF characteristic.
  • Electrons supplied from the source electrode 14 move along the heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22 at high speed, flow through the i-type GaN layer 24 in a vertical direction in a position on an upper portion of the aperture 28, flow vertically through the GaN layer 26 charged into the aperture 28, flow vertically through the n " -type GaN layer 6, and then flow vertically through the n + -type GaN layer 4 to reach the drain electrode 2.
  • a positive voltage is applied to the gate electrode 18, a current flows from the drain electrode 2 to the source electrode 14.
  • the suspended current blocking region 8 exists directly below the aperture 28, and therefore, when electrons flow vertically through the n ' -type GaN layer 6, the electrons flow vertically through the n ' -type GaN layer 6 while bypassing the suspended current blocking region 8. Since the electrons flow while bypassing the suspended current blocking region 8, an increase in resistance occurring when the semiconductor device 30 is switched ON can be made negligible.
  • n + -type GaN layer 4 When a positive voltage is not applied to the gate electrode 18, a high potential is applied to the drain electrode 2 and the source electrode 14 is grounded.
  • the resistance of the n + -type GaN layer 4 is low, and substantially the entire region of the n + -type GaN layer 4 is equal to the high potential of the drain electrode 2.
  • the resistance of the p-type GaN layer 10 is also low, and since the source electrode 14 is grounded, substantially the entire region of the p-type GaN layer 10 is maintained at a ground voltage.
  • FIG. 2 shows a distribution of an equipotential line "a" in a range indicated by II in FIG 1. Note that a case in which the suspended current blocking region 8 does not exist is illustrated. It can be seen that the GaN layer 26 charged into the aperture 28 and the parts of the i-type GaN layer 24 and AlGaN layer 22 positioned above the aperture 28 all reach a high voltage such that a large voltage difference is applied between a front surface and a rear surface of the gate insulation layer 20.
  • a threshold voltage employed when a positive voltage is applied to the gate electrode 18 to switch ON the semiconductor device 30 is preferably low, and therefore the thickness of the gate insulation layer 20 must be reduced.
  • the gate insulation layer 20 breaks.
  • the semiconductor device 30 is not provided with the suspended current blocking region 8, a voltage resistance thereof is low.
  • the gate insulation layer 20 must be increased in thickness, leading to an increase in the threshold voltage employed when the semiconductor device 30 is switched ON.
  • FIG. 3 is similar to FIG. 2, but shows a case in which the suspended current blocking region 8 is formed.
  • an equipotential line "b" runs beneath the suspended current blocking region 8 such that the potential of the GaN layer 26 charged into the aperture 28 and the parts of the i-type GaN layer 24 and AlGaN layer 22 positioned above the aperture 28 decreases.
  • the suspended current blocking region 8 it is possible to prevent a large voltage difference from being applied between the front surface and rear surface of the gate insulation layer 20.
  • the voltage resistance of the semiconductor device 30 is improved.
  • the thickness of the gate insulation layer 20 need not be increased, and therefore the threshold voltage employed when the semiconductor device 30 is switched ON does not increase.
  • FIG. 4 shows a stage reached by preparing a substrate to serve as the n + -type GaN layer 4, forming the n " -type GaN layer 6 by crystal growth on an upper surface of the n + -type GaN layer 4 using an MOCVD method, and then forming a suspended current blocking layer 8a by crystal growth on an upper surface of the n " -type GaN layer 6.
  • the n " -type GaN layer 6 has a thickness of 10 ⁇ m and an impurity concentration of 2 x 10 16 cm “3 .
  • the suspended current blocking layer 8a is not patterned, and therefore extends evenly.
  • the suspended current blocking layer 8a is formed by forming a GaN layer through crystal growth while introducing an impurity such as Al, C, or Fe.
  • an impurity such as Al, C, or Fe
  • a deeper level (quantum state having an energy) located further toward a valence band side than an intermediate value between a conduction band and the valence band is formed, and this deeper level blocks a current flow by trapping electrons.
  • a level that enters the band gap by 0.2 to 1.7 eV from the valence band is formed. Impurities are added in an amount at which the density of the level reaches 10 1 " cm "3 .
  • the suspended current blocking layer 8a is formed at a thickness of approximately 500 nm.
  • the suspended current blocking layer 8a may be formed by forming a GaN layer through crystal growth while introducing an impurity such as Mg or Zn.
  • a p-type GaN layer is formed by crystal growth.
  • the p-type GaN layer also functions as the suspended current blocking layer 8a.
  • FIG. 5 shows a state arrived at by forming a silicon dioxide (SiO 2 ) mask layer 32 over the entire upper surface of the suspended current blocking layer 8a formed from GaN crystal and then performing photolithography and etching on the mask layer 32 to remove the entire mask layer 32 except for a part in which the suspended current blocking region 8 is to be formed subsequently.
  • FIG. 6 shows a state arrived at by implementing chlorine-based plasma etching using the partially remaining mask layer 32 as a mask to remove a part of the suspended current blocking layer 8a that is exposed from the mask layer 32. At this stage, the suspended current blocking region 8 is formed.
  • FIG. 7 shows a state arrived at by removing the mask layer 32.
  • the n -type GaN layer 6 is formed by crystal growth at a thickness of 2 ⁇ m on the upper surface of the suspended current blocking region 8.
  • the impurity concentration of the n " -type GaN layer 6 is set at approximately 2 x 10 16 cm '3 .
  • the p-type GaN layer 10 has a thickness of 0.5 ⁇ m and an impurity concentration of approximately 10 ' cm '3 .
  • FIG 9 shows a state arrived at by forming an SiO 2 mask layer 34 over the entire upper surface of the p-type GaN layer 10 and then removing a part of the mask layer 34 in which the aperture 28 is to be formed subsequently through photolithography and etching.
  • FIG. 10 shows a state arrived at by implementing dry etching (chlorine-based plasma etching) using the partially remaining mask layer 34 as a mask to remove a part of the p-type GaN layer 10 that is exposed from the mask layer 34.
  • the aperture 28 is formed in the p-type GaN layer 10.
  • n ' -type GaN layer 6 exposed to a bottom surface of the aperture 28 is also etched, and as a result, various types of damage occur thereon. Moreover, this damage causes the n ' -type GaN layer 6 to become higher doped n-type.
  • FIG. 11 shows a stage reached by forming the i-type GaN layers 26, 24 by crystal growth on the front surface of the p-type GaN layer 10 and the front surface of the n ' -type GaN layer 6 exposed to the bottom surface of the aperture 28 and forming the AlGaN layer 22 by crystal growth on a front surface of the i-type GaN layer 24.
  • the GaN layer 26 formed in the aperture 28 is formed by crystal growth under the crystal growth conditions of the i-type GaN layer 24, the GaN layer 26 is an n-type layer.
  • the suspended current blocking region 8 is used, and therefore a reduction in voltage resistance does not occur even when the GaN layer 26 formed in the aperture 28 is an n-type layer.
  • n-type GaN layers 26, 24 may be formed by crystal growth.
  • p-type GaN layers 26, 24 may be formed by crystal growth. Note, however, that when p-type layers are used, the layers have a lower density than the p-type GaN layer 10.
  • the GaN layer 26 formed in the aperture 28 may be an i-type layer. In this case also, a highly doped n-type region is formed on the interface between the n ' -type GaN layer 6 and the i-type GaN layer 26, leading to a reduction in the voltage resistance of the semiconductor device.
  • FIG. 12 shows a stage reached by selectively etching the AlGaN layer 22 and the i-type GaN layer 24 to expose a part of the front surfaces of the p-type GaN layer 10 and the i-type GaN layer 24, forming the p contact region 12 and the source contact region 16, and forming the gate insulation layer 20, the gate electrode 18, the source electrode 14, and the drain electrode 2.
  • the semiconductor device 30 is manufactured.
  • FIGS. 13 to 21 show a second embodiment of the manufacturing method.
  • FIG 13 shows a stage reached by preparing a substrate to serve as the n + -type GaN layer 4 and forming the n -type GaN layer 6 by crystal growth on the upper surface of the n + -type GaN layer 4.
  • FIG. 14 shows a state arrived at by forming an SiO 2 mask layer 36 over the entire upper surface of the n -type GaN layer 6 and then performing photolithography and etching on the mask layer 32 to remove a part of the mask layer 36 in which the suspended current blocking region 8 is to be formed subsequently.
  • FIG. 15 shows a stage reached by ion-implanting an impurity such as Al, C, Fe, Mg, or Zn using the partially remaining mask layer 36 as a mask.
  • an impurity such as Al, C, Fe, Mg, or Zn
  • a deeper level located further toward the valence band side than an intermediate value between the conduction band and the valence band is formed, and this deeper level blocks a current flow by trapping electron holes.
  • a level that enters the band gap by 0.2 to 1.7 eV from the valence band is formed. Impurities are added in an amount at which the density of the deeper level reaches 1O 18'20 cm '3 .
  • the suspended current blocking region 8 is formed at a thickness of approximately 500 nm.
  • FIG 16 shows a state arrived at by removing the mask layer 36.
  • FIG. 17 shows a stage reached by forming the n " -type GaN layer 6 again by crystal growth on the upper surface of the n " -type GaN layer 6, a part of which is formed with the suspended current blocking region 8, and then forming the p-type GaN layer 10 by crystal growth.
  • the n -type GaN layer 6 is formed by crystal growth at a thickness of 2 ⁇ m on the upper surface of the suspended current blocking region 8.
  • the impurity concentration of the n " -type GaN layer 6 is set at approximately 2 x 10 16 cm '3 .
  • the p-type GaN layer 10 has a thickness of 0.5 ⁇ m and an impurity concentration of approximately 10 l9 cm '3 .
  • the aperture 28 is not formed in the p-type GaN layer 10, and therefore the p-type GaN layer 10 extends evenly.
  • FIGS. 18 to 21 are identical to FIGS. 9 to 12, and duplicate description thereof has been omitted.
  • FIG. 22 shows a semiconductor device 40 according to the second embodiment.
  • suspended current blocking regions 8b are disposed discretely within a drift layer 6 formed from n " -type GaN crystal.
  • intervals between adjacent suspended current blocking regions 8b are managed to a length at which depletion layers extending toward the n-type drift layer 6 from the suspended current blocking regions 8b when the semiconductor device 40 is switched OFF contact each other.
  • a range in which the suspended current blocking regions 8b are not formed may be provided below the aperture 28.
  • FIG 23 shows a semiconductor device 50 according to a third embodiment.
  • suspended current blockings 8c are disposed discretely in two layers.
  • the suspended current blocking regions may be disposed discretely in three or more layers.
  • FIG. 24 shows a semiconductor device 60 according to a fourth embodiment.
  • the AlGaN layer 22 does not exist.
  • the gate insulation layer 20 is formed directly on the i-type GaN layer 24, and the gate electrode 18 is formed on the front surface of the gate insulation layer 20.
  • the semiconductor device 60 formed without the AlGaN layer 22 operates as a MOSFET. In this case also, the voltage resistance is improved by the suspended current blocking region 8.

Abstract

A p-type GaN layer (10) is laminated on an if -type GaN layer (6), an aperture (28) that penetrates the p-type GaN layer (10) is formed in the p-type GaN layer (10), and an n-type GaN layer (26) is formed in the aperture (28). A suspended current blocking region (8) is formed in a part of the n-type GaN layer (6). When a semiconductor device is switched OFF, a depletion layer extends from the suspended current blocking region (8) toward the n-type GaN layer (6), leading to a reduction in the potential of the n-type GaN layer (26) formed in the aperture (28) and a reduction in a potential difference between a front surface and a rear surface of a gate insulation film (20). As a result, a voltage resistance of the semiconductor device is improved. The suspended current blocking region (8) may be a p-type region and a region having a deep level.

Description

SEMICONDUCTOR DEVICE
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0001] The invention relates to a semiconductor device formed from a group III nitride-based compound semiconductor.
2. Description of the Related Art
[0002] Semiconductor devices realized by group III nitride-based compound semiconductors are currently under development, and an example thereof is disclosed in Japanese Patent Application Publication No. 2007-5764 (JP-A-2007-5764). The semiconductor device described in JP-A-2007-5764 is structured by laminating an upper layer formed from a p-type group III nitride-based compound semiconductor onto a lower layer formed from an n-type group III nitride-based compound semiconductor. An aperture is penetrated through the upper layer of the p-type upper layer, and an n-type or i-type group III nitride-based compound semiconductor is charged into the aperture. When the semiconductor device is switched ON, a current flows through the group III nitride-based compound semiconductor charged into the aperture and the n-type group III nitride-based compound semiconductor positioned therebelow. The current flows through the semiconductor layers in a vertical direction via the aperture.
[0003] When the semiconductor device is switched OFF, a depletion layer ought to extend from the p-type group III nitride-based compound semiconductor toward the n-type or i-type group III nitride-based compound semiconductor charged into the aperture and the n-type group III nitride-based compound semiconductor forming the lower layer. It is assumed that when the depletion layer extends to the aperture, voltage resistance to a high voltage applied between a front surface side electrode and a rear surface side electrode will be secured by the depletion layer. In actuality, however, it is difficult to secure resistance to high voltages for the following reasons. [0004] (1) The structure described above is a laminated structure realized by laminating the upper layer formed from a p-type group III nitride-based compound semiconductor onto the lower layer formed from an n-type group III nitride-based compound semiconductor. The aperture penetrated through the upper layer is manufactured by etching a part of the front surface of the upper layer. To manufacture the aperture penetrated through the upper layer, etching is performed from the front surface of the upper layer to a rear surface of the upper layer. In other words, the etching is continued until the n-type lower layer is exposed to a bottom surface of the aperture. A front surface of the n-type lower layer exposed to the bottom surface of the aperture is also etched. (2) The n-type or i-type group III nitride-based compound semiconductor is formed through crystal growth from the front surface of the n-type lower layer exposed to the bottom surface of the aperture, whereupon the n-type or i-type group HI nitride-based compound semiconductor is charged into the aperture. (3) Since the front surface of the n-type lower layer exposed to the bottom surface of the aperture is etched, various types of damage occur thereon, causing the lower layer to become highly doped n-type.
[0005] In the technique described above, a highly doped n-type region is formed between the n-type or i-type group III nitride-based compound semiconductor charged into the aperture and the n-type group HI nitride-based compound semiconductor positioned therebelow. When this region is formed, the depletion layer cannot extend widely toward the group III nitride-based compound semiconductor charged into the aperture while the semiconductor device is switched OFF. In other words, voltage resistance cannot be secured by a depletion layer that extends widely toward the group πi nitride-based compound semiconductor charged into the aperture when the semiconductor device is switched OFF.
[0006] Various semiconductor structures are created on the p-type group HI nitride-based compound semiconductor layer formed with the aperture in accordance with the characteristics of the semiconductor device. In the technique described in JP-A-2007-5764, a heterostructure is formed by laminating a surface side lower layer formed from a group III nitride-based compound semiconductor and a surface side upper layer formed from a group III nitride-based compound semiconductor having a wider band gap than the surface side lower layer onto the p-type group III nitride-based compound semiconductor layer. As a result, a High Electron Mobility Transistor (HEMT) is realized. Alternatively, a Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) structure may be realized.
[0007] When voltage resistance cannot be secured by the depletion layer that extends widely toward the aperture while the semiconductor device is switched OFF, a high voltage is applied to the semiconductor structure formed on the upper portion of the p-type group III nitride-based compound semiconductor layer. As a result, a high voltage is applied between a front surface and a rear surface of a gate insulation layer, for example, causing damage to the gate insulation layer.
SUMMARY OF THE INVENTION
[0008] The invention has been developed with the aim of improving voltage resistance in a semiconductor device having a group III nitride-based compound semiconductor layer formed with an aperture.
[0009] A first aspect of the invention relates to a semiconductor device including: a lower layer formed from an n-type group III nitride-based compound semiconductor; and an upper layer formed from a p-type group III nitride-based compound semiconductor laminated onto the lower layer. An aperture is penetrated through the upper layer. An n-type or i-type group III nitride-based compound semiconductor is charged into the aperture. A suspended current blocking region is formed in a part of the lower layer.
[0010] When the suspended current blocking region is formed in a part of the n-type lower layer, as in the aspect described above, a depletion layer extends from the suspended current blocking region to the n-type lower layer. As a result, a voltage applied to the n-type or i-type group III nitride-based compound semiconductor charged into the aperture decreases, thereby ensuring that a high voltage is not applied to a semiconductor structure formed on an upper portion of the p-type group III nitride-based compound semiconductor layer. According to the aspect described above, by forming the suspended current blocking region in a part of the n-type lower layer, an improvement in the voltage resistance of the semiconductor device is achieved.
[0011] There are no limitations on the semiconductor structure formed on the upper portion of the p-type group III nitride-based compound semiconductor layer. In the aspect described above, a heterostructure in which a surface side upper layer formed from a group III nitride-based compound semiconductor having a wider band gap than a surface side lower layer formed from a group III nitride-based compound semiconductor is laminated on the surface side lower layer may be formed.
[0012] According to this aspect, the voltage resistance of the semiconductor device is improved by forming the suspended current blocking region in a part of the n-type lower layer even when a heterostructure is formed on the p-type upper layer.
[0013] In the aspect described above, a Field-effect Transistor (FET) structure constituted by a surface side layer formed from a group III nitride-based compound semiconductor, a gate insulation layer covering a surface of the surface side layer, and a gate electrode formed on an upper surface of the gate insulation layer may be formed.
[0014] According to this aspect, the voltage resistance of the semiconductor device is improved by forming the suspended current blocking region in a part of the n-type lower layer even when a FET structure is formed on the p-type upper layer.
[0015] In the aspect described above, a MOSFET structure constituted by a gate insulation layer and a gate electrode formed on an upper surface of the gate insulation layer may be formed on the upper layer.
[0016] There are no particular limitations on the formation range of the suspended current blocking region when the semiconductor substrate is seen from above. In the aspect described above, a formation range of the suspended current blocking region and a formation range of the aperture may overlap in a semiconductor device mounting direction.
[0017] According to this aspect, the voltage applied to the n-type group III nitride-based compound semiconductor charged into the aperture decreases dramatically, and therefore the voltage resistance of the semiconductor device is improved effectively.
[0018] In the aspect described above, a formation range of the suspended current blocking region may be extended wider than a formation range of the aperture in a semiconductor device mounting direction.
[0019] According to this aspect, a relationship whereby the formation range of the aperture is covered by the suspended current blocking region is secured even when the formation range of the suspended current blocking region and the formation range of the aperture are offset from each other. Hence, positional precision requirements during manufacture are alleviated.
[0020] In the aspect described above, a plurality of formation ranges of the suspended current blocking region may be disposed discretely, and intervals between adjacent suspended current blocking regions may be set at a length at which depletion layers extending toward the upper layer from the suspended current blocking regions when the semiconductor device is switched off.
[0021] In the aspect described above, the suspended current blocking region may be formed from a single layer or a plurality of layers.
[0022] When the semiconductor that exists in a part of the n-type lower layer, or in other words the suspended current blocking region, has a deeper level located further toward a valence band side than an intermediate value between a conduction band and the valence band, the semiconductor having this deeper level prevents a current from flowing. Alternatively, when the semiconductor that exists in a part of the n-type lower layer is a p-type semiconductor, the p-type semiconductor prevents a current from flowing. In other words, the suspended current blocking region may have a deeper level located further toward a valence band side than an intermediate value between a conduction band of the semiconductor and the valence band. Alternatively, the suspended current blocking region may be formed from a p-type semiconductor.
[0023] In the aspect described above, the level of the suspended current blocking region may enter a band gap by 0.2 to 1.7 eV from the valence band. [0024] In the aspect described above, the upper layer may have a thickness of approximately 10 μm in a lamination direction , and the suspended current blocking region (8) may have a thickness of approximately 500 nm in the lamination direction.
[0025] A second aspect of the invention relates to a manufacturing method for a semiconductor device. The manufacturing method for a semiconductor device includes: preparing a substrate formed from an n-type group III nitride-based compound semiconductor; forming a lower layer by crystal growth from an n-type group III nitride-based compound semiconductor on an upper surface of the substrate in a semiconductor device mounting direction using a metalorganic chemical vapor deposition (MOCVD) method; forming a suspended current blocking layer by crystal growth on an upper surface of the lower layer; forming a first mask layer over an entire upper surface of the suspended current blocking layer in the semiconductor device mounting direction; performing photolithography and etching on the first mask layer to remove the entire first mask layer except for a part of the first mask layer in which a suspended current blocking region is to be formed; implementing chlorine-based plasma etching using the partially remaining first mask layer as a mask to remove a part of the suspended current blocking layer that is exposed from the first mask layer; forming the lower layer again by crystal growth on the lower layer and an upper surface of the suspended current blocking region; forming an upper layer by crystal growth from a p-type group III nitride-based compound semiconductor laminated onto the lower layer; and forming an aperture in the upper layer.
[0026] In the aspect described above, the aperture may be formed by forming a second mask layer over the entire upper surface of the upper layer in the semiconductor device mounting direction, removing a part of the second mask layer in which the aperture is to be formed through photolithography and etching, implementing dry etching using the remaining second mask layer as a mask, and removing a part of the upper layer that is exposed from the second mask layer.
[0027] The aspect described above may further include: forming an n-type or i-type group III nitride-based compound first semiconductor layer by crystal growth in a part exposed to the upper surface of the upper layer in the semiconductor device mounting direction and forming an n-type or i-type group III nitride-based compound semiconductor charging layer by crystal growth on a front surface of the lower layer that is exposed to a bottom surface of the aperture; laminating a second semiconductor layer formed from a group III nitride-based compound semiconductor having a wider band gap than the semiconductor layer; selectively etching the second semiconductor layer and the i-type first semiconductor layer to expose a part of the upper layer and a front surface of the semiconductor layer; forming a contact region and a source contact region; and forming a gate insulation layer, a gate electrode, a source electrode, and a drain electrode.
[0028] A third aspect of the invention relates to a manufacturing method for a semiconductor device. The manufacturing method for a semiconductor device includes: preparing a substrate formed from an n-type group III nitride-based compound semiconductor; forming a lower layer by crystal growth from an n-type group III nitride-based compound semiconductor on an upper surface of the substrate using an MOCVD method; forming a mask layer over an entire upper surface of the lower layer; removing a part of the mask layer in which a suspended current blocking region is to be formed by photolithography and etching; ion-implanting one or more impurities selected from Al, C, Fe, Mg, and Zn using the remaining mask layer as a mask; forming the lower layer again by crystal growth on the upper surface of the lower layer in which the suspended current blocking region is formed; forming an upper layer by crystal growth from a p-type group III nitride-based compound semiconductor on the upper surface of the lower layer in a semiconductor device mounting direction; and forming the lower layer by crystal growth on an upper surface of the suspended current blocking region.
[0029] According to this aspect, it is possible to achieve an improvement in the voltage resistance of a semiconductor device having a laminated structure, in which an upper layer formed from a p-type group III nitride-based compound semiconductor is laminated on a lower layer formed from an n-type group III nitride-based compound semiconductor, and formed with an aperture that penetrates through the p-type upper layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The foregoing and further objects, features and advantages of the invention will become apparent from the following description of preferred embodiments with reference to the accompanying drawings, wherein like numerals are used to represent like elements and wherein:
FIG 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment;
FIG 2 shows an equipotential line distribution of a semiconductor device not formed with a suspended current blocking region;
FIG 3 shows an equipotential line distribution of a semiconductor device formed with a suspended current blocking region;
FIG. 4 shows a cross-section of the semiconductor device according to the first embodiment in a state where a manufacturing process has been partially been implemented;
FIG 5 shows a cross-section following FIG 4 in a state where the manufacturing process has been further implemented;
FIG 6 shows a cross-section following FIG. 5 in a state where the manufacturing process has been further implemented;
FIG. 7 shows a cross-section following FIG. 6 in a state where the manufacturing process has been further implemented;
FIG 8 shows a cross-section following FIG. 7 in a state where the manufacturing process has been further implemented;
FIG 9 shows a cross-section following FIG 8 in a state where the manufacturing process has been further implemented;
FIG 10 shows a cross-section following FIG 9 in a state where the manufacturing process has been further implemented;
FIG 11 shows a cross-section following FIG. 10 in a state where the manufacturing process has been further implemented; FIG 12 shows a cross-section following FIG 11 in a state where the manufacturing process has been further implemented;
FIG 13 is a view showing another manufacturing process of the semiconductor device according to the first embodiment, and shows a cross-section thereof in a state where the manufacturing process has been partially implemented;
FIG 14 shows a cross-section following FIG. 13 in a state where the manufacturing process has been further implemented;
FIG. 15 shows a cross-section following FIG 14 in a state where the manufacturing process has been further implemented;
FIG 16 shows a cross-section following FIG 15 in a state where the manufacturing process has been further implemented;
FIG. 17 shows a cross-section following FIG. 16 in a state where the manufacturing process has been further implemented;
FIG 18 shows a cross-section following FIG. 17 in a state where the manufacturing process has been further implemented;
FIG. 19 shows a cross-section following FIG 18 in a state where the manufacturing process has been further implemented;
FIG. 20 shows a cross-section following FIG 19 in a state where the manufacturing process has been further implemented;
FIG. 21 shows a cross-section following FIG. 20 in a state where the manufacturing process has been further implemented;
FIG 22 is a sectional view of a semiconductor device according to a second embodiment;
FIG 23 is a sectional view of a semiconductor device according to a third embodiment; and
FIG 24 is a sectional view of a semiconductor device according to a fourth embodiment.
DETAILED DESCRIPTION OF EMBODIMENTS [0031] Gallium nitride (GaN) may be used as a group HI nitride-based compound semiconductor employed to implement the invention. Aluminum (Aluminium) gallium nitride (AlGaN) may be used as a group III nitride-based compound semiconductor having a wider band gap than GaN. To manufacture a suspended current blocking region, processing for forming an n-type GaN lower layer is halted midway, whereupon a current block layer formed from GaN is formed by implementing a GaN epitaxial growth method while introducing an impurity such as AI, Mg, C, Ze, or Fe. Next, the current block layer formed from GaN. is partially removed by etching such that a part thereof remains. The processing for forming the n-type GaN lower layer is then resumed. Thus, a current block region which is removed (insulated) from the periphery of the n-type GaN lower layer and in which a voltage varies in accordance with a peripheral voltage is formed in the n-type GaN lower layer. In other words, a suspended current blocking region is formed. Alternatively, the processing for forming the n-type GaN lower layer is halted midway and an impurity such as Al, Mg, C, Ze, or Fe is ion-injected into a part of the region thereof, whereupon the processing for forming the n-type GaN lower layer is resumed. As a result, a suspended current blocking region in which the voltage varies in accordance with the peripheral voltage is formed in the π-type GaN lower layer.
[0032] (First Embodiment) FIG 1 is a sectional view of a semiconductor device 30 according to a first embodiment. The semiconductor device according to the first embodiment is a HEMT using a heterojunction between GaN and AlGaN. The semiconductor device is a vertical semiconductor device in which a source electrode 14 and a drain electrode 2 are formed separately on a front surface and a rear surface.
[0033] In order from a rear surface side, the drain electrode 2, an n+-type GaN layer 4, an n"-type GaN layer 6, a p-type GaN layer 10 formed with an aperture 28, an i-type GaN layer 24, an AlGaN layer 22, a gate insulation layer 20, and a gate electrode 18 are laminated. A GaN layer 26 is charged into the aperture 28. The GaN layer 26 is manufactured in an identical process to the i-type GaN layer 24 under i-type GaN crystal growth conditions. However, in a site where a periphery is surrounded by a wall surface, such as the interior of the aperture, impurities are more likely to be introduced during crystal growth than when crystal growth is performed on a plane not surrounded by a wall surface. Therefore, the GaN layer 26 grown in the aperture 28 is more likely to be formed as a high density n-type layer due to residual impurities in a reactor. The n+-type GaN layer 4 functions as a drain contact layer, while the n -type GaN layer 6 functions as a drift layer.
[0034] A p+-type GaN region 12 is formed on either side of the aperture 28. The p+-type GaN region 12 is formed in a part of the p-type GaN layer 10. The p+-type GaN region 12 functions as a p contact region 12. An n+-type GaN region 16 is formed on either side of the aperture 28. The n+-type GaN region 16 contacts the i-type GaN layer 24 and the AlGaN layer 22. The n*-type GaN region 16 functions as a source contact region 16. A source electrode 14 is formed on either side of the aperture 28. The source electrode 14 contacts the source contact region 16 and the p contact region 12.
[0035] A suspended current blocking region 8 is buried in the n -type GaN layer 6. The suspended current blocking region 8 is formed in a range overlapping the aperture 28 when the semiconductor device 30 is seen from the above. More specifically, the suspended current blocking region 8 extends beyond a range overlapping the aperture 28 lengthwise. The formation range of the suspended current blocking region 8 may exceed an intended range as long as the suspended current blocking region 8 exists in a range overlapping the aperture 28.
[0036] The semiconductor device 30 is used by connecting the drain electrode 2 to a high potential side of a direct current power supply and grounding the source electrode 14. When a positive voltage is not applied to the gate electrode 18, a depletion layer extends from an interface between the p-type GaN layer 10 and the i-type GaN layer 24 toward the i-type GaN layer 24. The depletion layer also extends to a heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22. A carrier does not exist on the heterojunction interface between the i-type GaN layer 24 and the AJGaN layer 22 unless a positive voltage is applied to the gate electrode 18, and therefore a current does not flow from the drain electrode 2 to the source electrode 14. The semiconductor device 30 has a normally OFF characteristic.
[0037] When a positive voltage is applied to the gate electrode 18, the depletion layer that has extended to the heteroj unction interface between the i-type GaN layer 24 and the AlGaN layer 22 disappears. As a result, a two-dimensional electron gas is generated on the heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22 by a quantum well generated on the heterojunction interface. Thus, a state in which electrons move along the heterojunction interface between the i-type GaN layer 24 and the AIGaN layer 22 at high speed is established. Electrons supplied from the source electrode 14 move along the heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22 at high speed, flow through the i-type GaN layer 24 in a vertical direction in a position on an upper portion of the aperture 28, flow vertically through the GaN layer 26 charged into the aperture 28, flow vertically through the n"-type GaN layer 6, and then flow vertically through the n+-type GaN layer 4 to reach the drain electrode 2. When a positive voltage is applied to the gate electrode 18, a current flows from the drain electrode 2 to the source electrode 14.
[0038] The suspended current blocking region 8 exists directly below the aperture 28, and therefore, when electrons flow vertically through the n'-type GaN layer 6, the electrons flow vertically through the n'-type GaN layer 6 while bypassing the suspended current blocking region 8. Since the electrons flow while bypassing the suspended current blocking region 8, an increase in resistance occurring when the semiconductor device 30 is switched ON can be made negligible.
[0039] When a positive voltage is not applied to the gate electrode 18, a high potential is applied to the drain electrode 2 and the source electrode 14 is grounded. The resistance of the n+-type GaN layer 4 is low, and substantially the entire region of the n+-type GaN layer 4 is equal to the high potential of the drain electrode 2. The resistance of the p-type GaN layer 10 is also low, and since the source electrode 14 is grounded, substantially the entire region of the p-type GaN layer 10 is maintained at a ground voltage. [0040] If the suspended current blocking region 8 did not exist at this time, the GaN layer 26 charged into the aperture 28 would reach a high potential, leading to an increase in the potential of the i-type GaN layer 24 and AlGaN layer 22 positioned above the aperture 28. FIG. 2 shows a distribution of an equipotential line "a" in a range indicated by II in FIG 1. Note that a case in which the suspended current blocking region 8 does not exist is illustrated. It can be seen that the GaN layer 26 charged into the aperture 28 and the parts of the i-type GaN layer 24 and AlGaN layer 22 positioned above the aperture 28 all reach a high voltage such that a large voltage difference is applied between a front surface and a rear surface of the gate insulation layer 20. A threshold voltage employed when a positive voltage is applied to the gate electrode 18 to switch ON the semiconductor device 30 is preferably low, and therefore the thickness of the gate insulation layer 20 must be reduced. When a large voltage difference is applied between the front surface and rear surface of the thin gate insulation layer 20, the gate insulation layer 20 breaks. Hence, when the semiconductor device 30 is not provided with the suspended current blocking region 8, a voltage resistance thereof is low. To increase the voltage resistance, the gate insulation layer 20 must be increased in thickness, leading to an increase in the threshold voltage employed when the semiconductor device 30 is switched ON.
[0041] FIG. 3 is similar to FIG. 2, but shows a case in which the suspended current blocking region 8 is formed. In this case, an equipotential line "b" runs beneath the suspended current blocking region 8 such that the potential of the GaN layer 26 charged into the aperture 28 and the parts of the i-type GaN layer 24 and AlGaN layer 22 positioned above the aperture 28 decreases. When the suspended current blocking region 8 is formed, it is possible to prevent a large voltage difference from being applied between the front surface and rear surface of the gate insulation layer 20. By forming the suspended current blocking region 8, the voltage resistance of the semiconductor device 30 is improved. Moreover, the thickness of the gate insulation layer 20 need not be increased, and therefore the threshold voltage employed when the semiconductor device 30 is switched ON does not increase. [0042] FIGS. 4 to 10 show a manufacturing process of the semiconductor device 30. FIG. 4 shows a stage reached by preparing a substrate to serve as the n+-type GaN layer 4, forming the n"-type GaN layer 6 by crystal growth on an upper surface of the n+-type GaN layer 4 using an MOCVD method, and then forming a suspended current blocking layer 8a by crystal growth on an upper surface of the n"-type GaN layer 6. The n"-type GaN layer 6 has a thickness of 10 μm and an impurity concentration of 2 x 1016 cm"3. At this stage, the suspended current blocking layer 8a is not patterned, and therefore extends evenly. The suspended current blocking layer 8a is formed by forming a GaN layer through crystal growth while introducing an impurity such as Al, C, or Fe. When a GaN layer is formed through crystal growth while introducing an impurity such as AI, C, or Fe, a deeper level (quantum state having an energy) located further toward a valence band side than an intermediate value between a conduction band and the valence band is formed, and this deeper level blocks a current flow by trapping electrons. In actuality, a level that enters the band gap by 0.2 to 1.7 eV from the valence band is formed. Impurities are added in an amount at which the density of the level reaches 101 " cm"3. The suspended current blocking layer 8a is formed at a thickness of approximately 500 nm. The suspended current blocking layer 8a may be formed by forming a GaN layer through crystal growth while introducing an impurity such as Mg or Zn. In this case, a p-type GaN layer is formed by crystal growth. The p-type GaN layer also functions as the suspended current blocking layer 8a.
[0043] FIG. 5 shows a state arrived at by forming a silicon dioxide (SiO2) mask layer 32 over the entire upper surface of the suspended current blocking layer 8a formed from GaN crystal and then performing photolithography and etching on the mask layer 32 to remove the entire mask layer 32 except for a part in which the suspended current blocking region 8 is to be formed subsequently. FIG. 6 shows a state arrived at by implementing chlorine-based plasma etching using the partially remaining mask layer 32 as a mask to remove a part of the suspended current blocking layer 8a that is exposed from the mask layer 32. At this stage, the suspended current blocking region 8 is formed. FIG. 7 shows a state arrived at by removing the mask layer 32. FIG. 8 shows a stage reached by forming the n'-type GaN layer 6 again by crystal growth on the n"-type GaN layer 6 and an upper surface of the suspended current blocking region 8 foπned from GaN crystal, and then forming the p-type GaN layer 10 by crystal growth. The n -type GaN layer 6 is formed by crystal growth at a thickness of 2 μm on the upper surface of the suspended current blocking region 8. The impurity concentration of the n"-type GaN layer 6 is set at approximately 2 x 1016 cm'3. The p-type GaN layer 10 has a thickness of 0.5 μm and an impurity concentration of approximately 10 ' cm'3. At this stage, the aperture 28 is not foπned in the p-type GaN layer 10, and therefore the p-type GaN layer 10 extends evenly. FIG 9 shows a state arrived at by forming an SiO2 mask layer 34 over the entire upper surface of the p-type GaN layer 10 and then removing a part of the mask layer 34 in which the aperture 28 is to be formed subsequently through photolithography and etching. FIG. 10 shows a state arrived at by implementing dry etching (chlorine-based plasma etching) using the partially remaining mask layer 34 as a mask to remove a part of the p-type GaN layer 10 that is exposed from the mask layer 34. At this stage, the aperture 28 is formed in the p-type GaN layer 10. At this stage, a surface of the n'-type GaN layer 6 exposed to a bottom surface of the aperture 28 is also etched, and as a result, various types of damage occur thereon. Moreover, this damage causes the n'-type GaN layer 6 to become higher doped n-type. Once the state shown in FIG 10 has been established, the mask layer 34 is removed.
[0044] FIG. 11 shows a stage reached by forming the i-type GaN layers 26, 24 by crystal growth on the front surface of the p-type GaN layer 10 and the front surface of the n'-type GaN layer 6 exposed to the bottom surface of the aperture 28 and forming the AlGaN layer 22 by crystal growth on a front surface of the i-type GaN layer 24. Even when the GaN layer 26 formed in the aperture 28 is formed by crystal growth under the crystal growth conditions of the i-type GaN layer 24, the GaN layer 26 is an n-type layer. In this embodiment, the suspended current blocking region 8 is used, and therefore a reduction in voltage resistance does not occur even when the GaN layer 26 formed in the aperture 28 is an n-type layer. Instead of the i-type GaN layers 26, 24, n-type GaN layers 26, 24 may be formed by crystal growth. Alternatively, p-type GaN layers 26, 24 may be formed by crystal growth. Note, however, that when p-type layers are used, the layers have a lower density than the p-type GaN layer 10. Depending on the crystal growth conditions, the GaN layer 26 formed in the aperture 28 may be an i-type layer. In this case also, a highly doped n-type region is formed on the interface between the n'-type GaN layer 6 and the i-type GaN layer 26, leading to a reduction in the voltage resistance of the semiconductor device. In this embodiment, the suspended current blocking region 8 is used, and therefore, even when a highly doped n-type region is formed, the voltage resistance does not decrease. FIG. 12 shows a stage reached by selectively etching the AlGaN layer 22 and the i-type GaN layer 24 to expose a part of the front surfaces of the p-type GaN layer 10 and the i-type GaN layer 24, forming the p contact region 12 and the source contact region 16, and forming the gate insulation layer 20, the gate electrode 18, the source electrode 14, and the drain electrode 2. Through the process described above, the semiconductor device 30 is manufactured.
[0045] (Second Embodiment of Manufacturing Method) FIGS. 13 to 21 show a second embodiment of the manufacturing method. FIG 13 shows a stage reached by preparing a substrate to serve as the n+-type GaN layer 4 and forming the n -type GaN layer 6 by crystal growth on the upper surface of the n+-type GaN layer 4. FIG. 14 shows a state arrived at by forming an SiO2 mask layer 36 over the entire upper surface of the n -type GaN layer 6 and then performing photolithography and etching on the mask layer 32 to remove a part of the mask layer 36 in which the suspended current blocking region 8 is to be formed subsequently. FIG. 15 shows a stage reached by ion-implanting an impurity such as Al, C, Fe, Mg, or Zn using the partially remaining mask layer 36 as a mask. When an impurity such as Al, C, Fe, Mg, or Zn is ion-injected, a deeper level located further toward the valence band side than an intermediate value between the conduction band and the valence band is formed, and this deeper level blocks a current flow by trapping electron holes. In actuality, a level that enters the band gap by 0.2 to 1.7 eV from the valence band is formed. Impurities are added in an amount at which the density of the deeper level reaches 1O18'20 cm'3. The suspended current blocking region 8 is formed at a thickness of approximately 500 nm. [0046] FIG 16 shows a state arrived at by removing the mask layer 36. FIG. 17 shows a stage reached by forming the n"-type GaN layer 6 again by crystal growth on the upper surface of the n"-type GaN layer 6, a part of which is formed with the suspended current blocking region 8, and then forming the p-type GaN layer 10 by crystal growth. The n -type GaN layer 6 is formed by crystal growth at a thickness of 2 μm on the upper surface of the suspended current blocking region 8. The impurity concentration of the n"-type GaN layer 6 is set at approximately 2 x 1016 cm'3. The p-type GaN layer 10 has a thickness of 0.5 μm and an impurity concentration of approximately 10 l9 cm'3. At this stage, the aperture 28 is not formed in the p-type GaN layer 10, and therefore the p-type GaN layer 10 extends evenly. FIGS. 18 to 21 are identical to FIGS. 9 to 12, and duplicate description thereof has been omitted.
[0047] (Semiconductor Device of Second Embodiment) FIG. 22 shows a semiconductor device 40 according to the second embodiment. In this embodiment, suspended current blocking regions 8b are disposed discretely within a drift layer 6 formed from n"-type GaN crystal. In this case, intervals between adjacent suspended current blocking regions 8b are managed to a length at which depletion layers extending toward the n-type drift layer 6 from the suspended current blocking regions 8b when the semiconductor device 40 is switched OFF contact each other. In this case, a range in which the suspended current blocking regions 8b are not formed may be provided below the aperture 28.
[0048] (Semiconductor Device of Third Embodiment) FIG 23 shows a semiconductor device 50 according to a third embodiment. In this embodiment, suspended current blockings 8c are disposed discretely in two layers. The suspended current blocking regions may be disposed discretely in three or more layers.
[0049] (Semiconductor Device of Fourth Embodiment) FIG. 24 shows a semiconductor device 60 according to a fourth embodiment. In this embodiment, the AlGaN layer 22 does not exist. The gate insulation layer 20 is formed directly on the i-type GaN layer 24, and the gate electrode 18 is formed on the front surface of the gate insulation layer 20. The semiconductor device 60 formed without the AlGaN layer 22 operates as a MOSFET. In this case also, the voltage resistance is improved by the suspended current blocking region 8.
[0050] While the invention has been described with reference to example embodiments thereof, it should be understood that the invention is not limited to the example embodiments or constructions. To the contrary, the invention is intended to cover various modifications and equivalent arrangements. In addition, while the various elements of the example embodiments are shown in various combinations and configurations, which are exemplary, other combinations and configurations, including more, less or only a single element, are also within the scope of the invention.

Claims

CLAIMS:
1. A semiconductor device characterized by comprising: a lower layer formed from an n-type group III nitride-based compound semiconductor; and an upper layer formed from a p-type group III nitride-based compound semiconductor laminated onto the lower layer, wherein an aperture is penetrated through the upper layer, wherein an n-type or i-type group III nitride-based compound semiconductor is charged into the aperture, and wherein a suspended current blocking region is formed in a part of the lower layer.
2. The semiconductor device according to claim 1, wherein a heterostructure, in which a front surface side upper layer formed from a group III nitride-based compound semiconductor having a wider band gap than a front surface side lower layer formed from a group III nitride-based compound semiconductor is laminated on the front surface side lower layer, is formed on the upper layer.
3. The semiconductor device according to claim 1, wherein a FET structure constituted by a front surface side layer formed from a group III nitride-based compound semiconductor, a gate insulation layer covering an upper front surface of the front surface side layer, and a gate electrode formed on an upper front surface of the gate insulation layer is formed on the upper layer.
4. The semiconductor device according to claim 1, wherein a MOSFET structure constituted by a gate insulation layer and a gate electrode formed on an upper front surface of the gate insulation layer is formed on the upper layer.
5. The semiconductor device according to any one of claims 1 to 4, wherein a formation range of the suspended current blocking region and a formation range of the aperture overlap in a semiconductor device mounting direction.
6. The semiconductor device according to any one of claims 1 to 4, wherein a formation range of the suspended current blocking region extended wider than a formation range of the aperture in a semiconductor device mounting direction.
7. The semiconductor device according to any one of claims 1 to 4, wherein a plurality of formation ranges of the suspended current blocking regions are disposed discretely; and intervals between adjacent suspended current blocking regions are set at a length at which depletion layers extending toward the upper layer from the suspended current blocking regions when the semiconductor device is switched off.
8. The semiconductor device according to claim 7, wherein the suspended current blocking region is formed from a single layer or a plurality of layers.
9. The semiconductor device according to any one of claims 1 to 8, wherein the suspended current blocking region has a deeper level located further toward a valence band side than an intermediate value between a semiconductor conduction band and valence band.
10. The semiconductor device according to claim 9, wherein the level of the suspended current blocking region enters a band gap by 0.2 to 1.7 eV from the valence band.
11. The semiconductor device according to any one of claims 1 to 10, wherein the suspended current blocking region is formed from a p-type semiconductor.
12. The semiconductor device according to any one of claims 1 to 11, wherein the upper layer has a thickness of approximately 10 μm in a lamination direction , and the suspended current blocking region has a thickness of approximately 500 nm in the lamination direction.
13. A manufacturing method for a semiconductor device, characterised by comprising: preparing a substrate formed from an n-type group III nitride-based compound semiconductor; forming a lower layer by crystal growth from an n-type group III nitride-based compound semiconductor on an upper surface of the substrate in a semiconductor device mounting direction in use of an MOCVD method; forming a suspended current blocking layer by crystal growth on an upper surface of the lower layer; forming a first mask layer over an entire upper surface of the suspended current blocking layer in the semiconductor device mounting direction; performing photolithography and etching on the first mask layer to remove the entire first mask layer except for a part of the first mask layer in which a suspended current blocking region is to be formed; implementing chlorine-based plasma etching using the partially remaining first mask layer as a mask to remove a part of the suspended current blocking layer that is exposed from the first mask layer; forming the lower layer again by crystal growth on the lower layer and an upper surface of the suspended current blocking region; forming an upper layer by crystal growth from a p-type group III nitride-based compound semiconductor laminated onto the lower layer; and forming an aperture in the upper layer.
14'. The manufacturing method for a semiconductor device according to claim 13, wherein the aperture is formed by forming a second mask layer over the entire upper surface of the upper layer in a semiconductor device mounting direction, removing a part of the mask layer in which the aperture is to be formed through photolithography and etching, implementing dry etching using the remaining second mask layer as a mask, and removing a part of the upper layer that is exposed from the second mask layer.
15. The manufacturing method for a semiconductor device according to claim 13 or 14, further comprising: forming an n-type or i-type group III nitride-based compound first semiconductor layer by crystal growth in a part exposed to the upper surface of the upper layer in a semiconductor device mounting direction and forming an n-type or i-type group III nitride-based compound semiconductor charging layer by crystal growth on a front surface of the lower layer that is exposed to a bottom surface of the aperture; laminating a second semiconductor layer formed from a group III nitride-based compound semiconductor having a wider band gap than the semiconductor layer; selectively etching the second semiconductor layer and the i-type first semiconductor layer to expose a part of the upper layer and a part of a front surface of the semiconductor layer; forming a contact region and a source contact region; and forming a gate insulation layer, a gate electrode, a source electrode, and a drain electrode.
16. A manufacturing method for a semiconductor device, characterised by comprising: preparing a substrate formed from an n-type group III nitride-based compound semiconductor; forming a lower layer by crystal growth from an n-type group III nitride-based compound semiconductor on an upper surface of the substrate in use of an MOCVD method; forming a mask layer over an entire upper surface of the lower layer; removing a part of the mask layer in which a suspended current blocking region is to be formed by photolithography and etching; ion-implanting one or more impurities selected from Al, C, Fe, Mg, and Zn using the remaining mask layer as a mask; forming the lower layer again by crystal growth on the upper surface of the lower layer in which the suspended current blocking region is formed; forming an upper layer by crystal growth from a p-type group III nitride-based compound semiconductor on the upper surface of the lower layer in a semiconductor device mounting direction; and forming the lower layer by crystal growth on an upper surface of the suspended current blocking region.
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