JP5271022B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5271022B2
JP5271022B2 JP2008256802A JP2008256802A JP5271022B2 JP 5271022 B2 JP5271022 B2 JP 5271022B2 JP 2008256802 A JP2008256802 A JP 2008256802A JP 2008256802 A JP2008256802 A JP 2008256802A JP 5271022 B2 JP5271022 B2 JP 5271022B2
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semiconductor device
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JP2010087374A (en
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大悟 菊田
哲生 成田
成雅 副島
雅裕 杉本
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Abstract

A p-type GaN layer (10) is laminated on an if -type GaN layer (6), an aperture (28) that penetrates the p-type GaN layer (10) is formed in the p-type GaN layer (10), and an n-type GaN layer (26) is formed in the aperture (28). A suspended current blocking region (8) is formed in a part of the n-type GaN layer (6). When a semiconductor device is switched OFF, a depletion layer extends from the suspended current blocking region (8) toward the n-type GaN layer (6), leading to a reduction in the potential of the n-type GaN layer (26) formed in the aperture (28) and a reduction in a potential difference between a front surface and a rear surface of a gate insulation film (20). As a result, a voltage resistance of the semiconductor device is improved. The suspended current blocking region (8) may be a p-type region and a region having a deep level.

Description

本発明は、III族窒化物系化合物半導体で形成した半導体装置に関する。   The present invention relates to a semiconductor device formed of a group III nitride compound semiconductor.

III族窒化物系化合物半導体で半導体装置を実現する開発がおこなわれており、その例が特許文献１に開示されている。
特許文献１に記載の半導体装置は、ｎ型のIII族窒化物系化合物半導体で形成されている下層に、p型のIII族窒化物系化合物半導体で形成されている上層が積層された構造を備えている。ｐ型の上層には、その上層を貫通するアパーチャーが形成されており、そのアパーチャーには、ｎ型またはｉ型のIII族窒化物系化合物半導体が充填されている。
半導体装置がオンすると、アパーチャーを充填しているIII族窒化物系化合物半導体と、その下部に位置しているｎ型のIII族窒化物系化合物半導体を電流が流れる。電流は、アパーチャーを介して半導体層を縦方向に流れる。
特開２００７-５７６４号公報 Developments for realizing semiconductor devices using Group III nitride compound semiconductors have been carried out, and an example thereof is disclosed in Patent Document 1.
The semiconductor device described in Patent Document 1 has a structure in which an upper layer formed of a p-type group III nitride compound semiconductor is stacked on a lower layer formed of an n-type group III nitride compound semiconductor. I have. An aperture penetrating the upper layer is formed in the p-type upper layer, and the aperture is filled with an n-type or i-type group III nitride compound semiconductor.
When the semiconductor device is turned on, a current flows through the group III nitride compound semiconductor filled with the aperture and the n-type group III nitride compound semiconductor located therebelow. Current flows in the semiconductor layer in the vertical direction through the aperture.
Japanese Patent Laid-Open No. 2007-5564

半導体装置のオフ時には、p型のIII族窒化物系化合物半導体から、アパーチャーを充填しているｎ型またはｉ型のIII族窒化物系化合物半導体と、下層を構成しているｎ型のIII族窒化物系化合物半導体に向けて空乏層が広がるはずである。アパーチャーに空乏層が広がれば、表面側電極と裏面側電極の間に高い電圧がかかっても、その空乏層で耐圧を確保できるはずである。ところが実際には、高い耐圧を確保することが難しい。   When the semiconductor device is turned off, the p-type group III nitride compound semiconductor, the n-type or i-type group III nitride compound semiconductor filling the aperture, and the n-type group III group constituting the lower layer The depletion layer should spread toward the nitride compound semiconductor. If the depletion layer spreads in the aperture, even if a high voltage is applied between the front-side electrode and the back-side electrode, the depletion layer should be able to secure a breakdown voltage. However, in practice, it is difficult to ensure a high breakdown voltage.

その原因を追究したところ、その原因は下記であろうと推定できるに至った。
(1)上記構造を製造する場合、ｎ型のIII族窒化物系化合物半導体で形成されている下層に、p型のIII族窒化物系化合物半導体で形成されている上層が積層された積層構造を製造する。ついで、上層の表面の一部からエッチングして上層を貫通するアパーチャーを製造する。上層を貫通するアパーチャーを製造するために、上層の表面から上層の裏面に達するまでエッチングを続ける。すなわち、アパーチャーの底面にｎ型の下層が露出するまでエッチングを続ける。アパーチャーの底面に露出したｎ型の下層の表面もまたエッチングされる。
(2) アパーチャーの底面に露出したｎ型の下層の表面からｎ型またはｉ型のIII族窒化物系化合物半導体を結晶成長し、アパーチャーにｎ型またはｉ型のIII族窒化物系化合物半導体を充填する。
(3) アパーチャーの底面に露出したｎ型の下層の表面はエッチングされており、各種の損傷が生じており、強くｎ型化している。 After investigating the cause, it was possible to estimate that the cause would be as follows.
(1) When manufacturing the above structure, a laminated structure in which an upper layer formed of a p-type group III nitride compound semiconductor is stacked on a lower layer formed of an n-type group III nitride compound semiconductor Manufacturing. Next, an aperture penetrating the upper layer is manufactured by etching from a part of the surface of the upper layer. In order to manufacture an aperture penetrating the upper layer, etching is continued from the surface of the upper layer to the back surface of the upper layer. That is, the etching is continued until the n-type lower layer is exposed on the bottom surface of the aperture. The n-type underlying surface exposed at the bottom of the aperture is also etched.
(2) Crystal growth of an n-type or i-type group III nitride compound semiconductor from the surface of the n-type lower layer exposed on the bottom surface of the aperture, and an n-type or i-type group III nitride compound semiconductor to the aperture Fill.
(3) The surface of the n-type lower layer exposed on the bottom surface of the aperture is etched, causing various damages and becoming strongly n-type.

現状の技術では、アパーチャーを充填しているｎ型またはｉ型のIII族窒化物系化合物半導体と、その下方に位置しているｎ型のIII族窒化物系化合物半導体の間に、強くｎ型化した領域が形成されてしまう。この領域が形成されると、半導体装置のオフ時に、アパーチャーを充填しているIII族窒化物系化合物半導体に向けて空乏層が広く広がることができない。すなわち、現状の技術では、半導体装置のオフ時にアパーチャーを充填しているIII族窒化物系化合物半導体に向けて広く広がる空乏層によって耐圧を確保することができない。   In the current technology, an n-type or i-type group III nitride compound semiconductor that is filled with an aperture and an n-type group III nitride compound semiconductor located below the n-type group III nitride compound semiconductor are strongly n-type. As a result, a region is formed. When this region is formed, the depletion layer cannot spread widely toward the group III nitride compound semiconductor filled with the aperture when the semiconductor device is turned off. That is, with the current technology, the breakdown voltage cannot be ensured by the depletion layer that spreads widely toward the group III nitride compound semiconductor that is filled with the aperture when the semiconductor device is off.

アパーチャーが形成されているp型のIII族窒化物系化合物半導体層の上には、半導体装置の特性に合わせて種々の半導体構造が作られる。特許文献１の技術では、III族窒化物系化合物半導体で形成されている表面側下層と、その表面側下層よりもバンドギャップが広いIII族窒化物系化合物半導体で形成されている表面側上層が積層されているヘテロ構造を形成することによって、ＨＥＭＴを実現している。そのほかに、ＭＯＳＦＥＴ構造を実現することもできる。   Various semiconductor structures are formed on the p-type group III nitride compound semiconductor layer in which the aperture is formed, in accordance with the characteristics of the semiconductor device. In the technique of Patent Document 1, a surface side lower layer formed of a group III nitride compound semiconductor and a surface side upper layer formed of a group III nitride compound semiconductor having a wider band gap than the surface side lower layer are provided. HEMT is realized by forming stacked heterostructures. In addition, a MOSFET structure can be realized.

半導体装置のオフ時にアパーチャーに向けて広く広がる空乏層によって耐圧を確保することができなければ、p型のIII族窒化物系化合物半導体層の上部に形成されている半導体構造に高い電圧がかかってしまう。この結果、例えばゲート絶縁層の表面と裏面の間に高い電圧がかかってゲート絶縁層が損傷する結果が生じる。
本発明は、アパーチャーが形成されているIII族窒化物系化合物半導体層を有する半導体装置の耐圧を向上することを目的に開発されたものである。 If the breakdown voltage cannot be secured by the depletion layer that spreads widely toward the aperture when the semiconductor device is off, a high voltage is applied to the semiconductor structure formed on the p-type group III nitride compound semiconductor layer. End up. As a result, for example, a high voltage is applied between the front and back surfaces of the gate insulating layer, resulting in damage to the gate insulating layer.
The present invention was developed for the purpose of improving the breakdown voltage of a semiconductor device having a group III nitride compound semiconductor layer in which an aperture is formed.

本発明の半導体装置は、ｎ型のIII族窒化物系化合物半導体で形成されている下層に、p型のIII族窒化物系化合物半導体で形成されている上層が積層されている積層構造を備えている。上層には、上層を貫通するアパーチャーが形成されており、そのアパーチャーには、ｎ型またはｉ型のIII族窒化物系化合物半導体が充填されている。
本発明の半導体装置は、ｎ型の下層の一部に、浮遊電流ブロック領域が形成されていることを特徴とする。その浮遊電流ブロック領域は、伝導帯と価電子帯の中間値よりも価電子帯側の深い準位を持っている。 The semiconductor device of the present invention has a stacked structure in which an upper layer formed of a p-type group III nitride compound semiconductor is stacked on a lower layer formed of an n-type group III nitride compound semiconductor. ing. An aperture penetrating the upper layer is formed in the upper layer, and the aperture is filled with an n-type or i-type group III nitride compound semiconductor.
The semiconductor device of the present invention is characterized in that a floating current block region is formed in a part of an n-type lower layer. The floating current block region has a deeper level on the valence band side than the intermediate value between the conduction band and the valence band.

ｎ型の下層の一部に浮遊電流ブロック領域が形成されていると、浮遊電流ブロック領域からｎ型の下層に向けて空乏層が伸びる。この結果、アパーチャーを充填しているｎ型またはｉ型のIII族窒化物系化合物半導体にかかる電圧が減少し、p型のIII族窒化物系化合物半導体層の上部に形成されている半導体構造に高い電圧がかからないようになる。
ｎ型の下層の一部に浮遊電流ブロック領域が形成されていると、半導体装置の耐圧能力が向上する。 When the floating current block region is formed in a part of the n-type lower layer, the depletion layer extends from the floating current block region toward the n-type lower layer. As a result, the voltage applied to the n-type or i-type group III nitride compound semiconductor filling the aperture is reduced, and the semiconductor structure formed on the p-type group III nitride compound semiconductor layer is reduced. High voltage is not applied.
When the floating current block region is formed in a part of the n-type lower layer, the withstand voltage capability of the semiconductor device is improved.

p型のIII族窒化物系化合物半導体層の上部に形成されている半導体構造は制約されない。例えば、III族窒化物系化合物半導体で形成されている表面側下層に、その表面側下層よりもバンドギャップが広いIII族窒化物系化合物半導体で形成されている表面側上層が積層されているヘテロ構造が形成されていてもよい。p型の上層の上にヘテロ構造が形成されている場合でも、ｎ型の下層の一部に浮遊電流ブロック領域を形成することによって、半導体装置の耐圧能力が向上する。   The semiconductor structure formed on the p-type group III nitride compound semiconductor layer is not limited. For example, a heterojunction in which a surface-side lower layer formed of a group III nitride compound semiconductor is laminated with a surface-side upper layer formed of a group III nitride compound semiconductor having a wider band gap than the surface-side lower layer. A structure may be formed. Even when the heterostructure is formed on the p-type upper layer, the withstand voltage capability of the semiconductor device is improved by forming the floating current block region in a part of the n-type lower layer.

あるいは、III族窒化物系化合物半導体で形成されている表面側層と、その表面側層の表面を覆っているゲート絶縁層と、そのゲート絶縁層の表面に形成されているゲート電極で構成されているＦＥＴ構造が形成されていてもよい。p型の上層の上にＦＥＴ構造が形成されている場合でも、ｎ型の下層の一部に浮遊電流ブロック領域を形成することによって、半導体装置の耐圧能力が向上する。   Alternatively, it is composed of a surface side layer formed of a group III nitride compound semiconductor, a gate insulating layer covering the surface of the surface side layer, and a gate electrode formed on the surface of the gate insulating layer. An FET structure may be formed. Even when the FET structure is formed on the p-type upper layer, the withstand voltage capability of the semiconductor device is improved by forming the floating current block region in a part of the n-type lower layer.

半導体基板を平面視した状態における浮遊電流ブロック領域の形成範囲は、特に制約されるものではないが、浮遊電流ブロック領域の形成範囲と、アパーチャーの形成範囲が重複することが好ましい。
この場合、アパーチャーを充填しているｎ型のIII族窒化物系化合物半導体にかかる電圧が顕著に低下し、半導体装置の耐圧能力が効果的に向上する。 The formation range of the floating current block region in a state in which the semiconductor substrate is viewed in plan is not particularly limited, but it is preferable that the formation range of the floating current block region and the formation range of the aperture overlap.
In this case, the voltage applied to the n-type group III nitride compound semiconductor filled with the aperture is significantly reduced, and the withstand voltage capability of the semiconductor device is effectively improved.

浮遊電流ブロック領域の形成範囲が、アパーチャーの形成範囲よりも広く広がっていることが好ましい。この場合、浮遊電流ブロック領域の形成範囲とアパーチャーの形成範囲の間にずれが生じても、アパーチャーの形成範囲を浮遊電流ブロック領域で覆っておく関係が確保される。製造時の位置精度に関する要求が緩和される。   It is preferable that the formation range of the floating current block region is wider than the formation range of the aperture. In this case, even if a deviation occurs between the formation range of the floating current block region and the formation range of the aperture, the relationship in which the formation range of the aperture is covered with the floating current block region is ensured. The demand for positional accuracy during manufacturing is relaxed.

ｎ型の下層の一部に存在している半導体が、伝導帯と価電子帯の中間値よりも価電子帯側の深い準位を持っていれば、その深い準位を持っている半導体が、電流が流れることを阻止する。 If the semiconductor that exists in a part of the n-type lower layer has a deep level on the valence band side than the intermediate value between the conduction band and the valence band, the semiconductor having the deep level is , it prevents the current from flowing.

本発明によると、ｎ型のIII族窒化物系化合物半導体で形成されている下層に、p型のIII族窒化物系化合物半導体で形成されている上層が積層されている積層構造を備えているとともに、ｐ型の上層を貫通するアパーチャーが形成されている型式の半導体装置の耐圧能力を向上させることができる。   According to the present invention, a laminated structure in which an upper layer formed of a p-type group III nitride compound semiconductor is stacked on a lower layer formed of an n-type group III nitride compound semiconductor is provided. At the same time, it is possible to improve the withstand voltage capability of the type semiconductor device in which the aperture penetrating the p-type upper layer is formed.

本発明を実施する場合、III族窒化物系化合物半導体にＧａＮを用いることができる。それよりもバンドギャップが広いIII族窒化物系化合物半導体にはＡｌＧａＮを用いることができる。
浮遊電流ブロック領域を製造するためには、ｎ型のＧａＮ下層の形成処理を途中で停止し、Ａｌ，Ｍｇ，Ｃ，Ｚｅ，Ｆｅなどの不純物を取り込みながらＧａＮをエピタキシャル成長する方法を実施してＧａＮによって形成されている電流ブロック層を形成する。次にＧａＮで形成されている電流ブロック層の一部を残してエッチングして除去する。その後にｎ型のＧａＮ下層の形成処理を再開する。それによってｎ型のＧａＮ下層のなかに、周囲から隔離（絶縁）されており、電圧が周囲の電圧によって変動する電流ブロック領域が形成される。すなわち、浮遊電流ブロック領域が形成される。
あるいは、ｎ型のＧａＮ下層の形成処理を途中で停止し、その一部の領域にＡｌ，Ｍｇ，Ｃ，Ｚｅ，Ｆｅなどの不純物をイオン注入し、その後にｎ型のＧａＮ下層の形成処理を再開する。それによってｎ型のＧａＮ下層のなかに、電圧が周囲の電圧によって変動する浮遊電流ブロック領域を形成する。 In practicing the present invention, GaN can be used for the group III nitride compound semiconductor. AlGaN can be used for a group III nitride compound semiconductor having a wider band gap.
In order to manufacture the floating current block region, the formation process of the n-type GaN lower layer is stopped halfway, and a method of epitaxially growing GaN while incorporating impurities such as Al, Mg, C, Ze, Fe, etc. The current blocking layer formed by is formed. Next, etching is performed while leaving a part of the current blocking layer formed of GaN. Thereafter, the formation process of the n-type GaN lower layer is resumed. As a result, a current blocking region is formed in the n-type GaN lower layer, which is isolated (insulated) from the surroundings and whose voltage varies depending on the surrounding voltage. That is, a floating current block region is formed.
Alternatively, the n-type GaN lower layer forming process is stopped halfway, and impurities such as Al, Mg, C, Ze, Fe, etc. are ion-implanted into a part of the region, and then the n-type GaN lower layer forming process is performed. Resume. As a result, a floating current block region in which the voltage varies depending on the surrounding voltage is formed in the n-type GaN lower layer.

(第１実施例)
図1は、第１実施例の半導体装置３０の断面図を示している。第１実施例の半導体装置は、ＧａＮとＡｌＧａＮのヘテロ接合を利用するＨＥＭＴであり、ソース電極１４とドレイン電極２が表裏両面に別れて形成されている。縦型の半導体装置である。 (First embodiment)
FIG. 1 shows a cross-sectional view of the semiconductor device 30 of the first embodiment. The semiconductor device of the first embodiment is a HEMT that uses a heterojunction of GaN and AlGaN, and the source electrode 14 and the drain electrode 2 are formed separately on the front and back surfaces. This is a vertical semiconductor device.

裏面側から順に、ドレイン電極２、ｎ＋型のＧａＮ層４、ｎ−型のＧａＮ層６、アパーチャー２８が形成されているｐ型のＧａＮ層１０、ｉ型のＧａＮ層２４、ＡｌＧａＮ層２２、ゲート絶縁層２０、ゲート電極１８が積層されている。アパーチャー２８には、ＧａＮ層２６が充填されている。ＧａＮ層２６は、ｉ型のＧａＮ層２４と同一工程で製造されており、ｉ型のＧａＮが結晶成長する条件で製造している。しかしながら、アパーチャー内のように周囲を壁面で囲まれた部位では、壁面で囲まれていない平面上で結晶成長する場合に比して、結晶成長時に不純物が取り込まれやすい。そのために、アパーチャー２８内に成長するＧａＮ層２６は、リアクタ内の残留不純物によって、高濃度のｎ型になりやすい。ｎ＋型のＧａＮ層４はドレインコンタクト層として機能し、ｎ−型のＧａＮ層６はドリフト層として機能する。 In order from the back surface side, the drain electrode 2, the n + -type GaN layer 4, the n − -type GaN layer 6, the p-type GaN layer 10 in which the aperture 28 is formed, the i-type GaN layer 24, the AlGaN layer 22, A gate insulating layer 20 and a gate electrode 18 are stacked. The aperture 28 is filled with a GaN layer 26. The GaN layer 26 is manufactured in the same process as the i-type GaN layer 24, and is manufactured under the condition that the i-type GaN grows. However, in a portion surrounded by a wall surface as in the aperture, impurities are more easily taken in during crystal growth than in the case of crystal growth on a plane not surrounded by the wall surface. For this reason, the GaN layer 26 grown in the aperture 28 tends to be a high concentration n-type due to residual impurities in the reactor. The n + -type GaN layer 4 functions as a drain contact layer, and the n − -type GaN layer 6 functions as a drift layer.

アパーチャー２８を挟む両サイドに、ｐ＋型のＧａＮ領域１２が形成されている。ｐ＋型のＧａＮ領域１２は、ｐ型のＧａＮ層１０の一部に形成されている。ｐ＋型のＧａＮ層１２は、ｐコンタクト領域１２として機能する。
アパーチャー２８を挟む両サイドに、ｎ＋型のＧａＮ領域１６が形成されている。ｎ＋型のＧａＮ領域１６は、ｉ型のＧａＮ層２４とＡｌＧａＮ層２２に接している。ｎ＋型のＧａＮ領域１６は、ソースコンタクト領域１６として機能する。
アパーチャー２８を挟む両サイドに、ソース電極１４が形成されている。ソース電極１４は、ソースコンタクト領域１６とｐコンタクト領域１２に接している。 P + -type GaN regions 12 are formed on both sides sandwiching the aperture 28. The p + -type GaN region 12 is formed in a part of the p-type GaN layer 10. The p + -type GaN layer 12 functions as the p contact region 12.
N + -type GaN regions 16 are formed on both sides sandwiching the aperture 28. The n + -type GaN region 16 is in contact with the i-type GaN layer 24 and the AlGaN layer 22. The n + -type GaN region 16 functions as the source contact region 16.
The source electrode 14 is formed on both sides sandwiching the aperture 28. Source electrode 14 is in contact with source contact region 16 and p contact region 12.

ｎ−型のＧａＮ層６の中に、浮遊電流ブロック領域８が埋め込まれている。浮遊電流ブロック領域８は、半導体装置３０を平面視したときに、アパーチャー２８とオーバラップする範囲に形成されている。正確にいうと、浮遊電流ブロック領域８は、アパーチャー２８とオーバラップする範囲を超えて広がっており、浮遊電流ブロック領域８の形成範囲が意図するものからずれても、アパーチャー２８とオーバラップする範囲には必ず浮遊電流ブロック領域８が存在する関係を満たしている。 A floating current blocking region 8 is embedded in the n − -type GaN layer 6. The floating current block region 8 is formed in a range that overlaps the aperture 28 when the semiconductor device 30 is viewed in plan. To be exact, the floating current block region 8 extends beyond the range overlapping with the aperture 28, and even if the formation range of the floating current block region 8 deviates from the intended range, the range overlapping with the aperture 28 is obtained. Always satisfy the relationship in which the floating current block region 8 exists.

半導体装置３０は、ドレイン電極２を直流電源の高電位側に接続し、ソース電極１４を接地して用いる。
ゲート電極１８に正電圧を印加しない状態では、ｐ型のＧａＮ層１０とｉ型のＧａＮ層２４の界面からｉ型のＧａＮ層２４に向けて空乏層が広がる。その空乏層は、ｉ型のＧａＮ層２４とＡｌＧａＮ層２２のヘテロ接合界面にも広がる。ゲート電極１８に正電圧を印加しないと、ｉ型のＧａＮ層２４とＡｌＧａＮ層２２のヘテロ接合界面にキャリアが存在せず、ドレイン電極２からソース電極１４に電流が流れない。半導体装置３０は、ノーマリオフの特性を備えている。 The semiconductor device 30 is used with the drain electrode 2 connected to the high potential side of the DC power supply and the source electrode 14 grounded.
In a state where no positive voltage is applied to the gate electrode 18, a depletion layer spreads from the interface between the p-type GaN layer 10 and the i-type GaN layer 24 toward the i-type GaN layer 24. The depletion layer also extends to the heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22. Unless a positive voltage is applied to the gate electrode 18, carriers do not exist at the heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22, and no current flows from the drain electrode 2 to the source electrode 14. The semiconductor device 30 has normally-off characteristics.

ゲート電極１８に正電圧を印加すると、ｉ型のＧａＮ層２４とＡｌＧａＮ層２２のヘテロ接合界面に広がっていた空乏層が消失する。すると、ｉ型のＧａＮ層２４とＡｌＧａＮ層２２のヘテロ接合界面に生じる量子井戸によって、その接合界面に２次元の電子ガスが発生する。電子がｉ型のＧａＮ層２４とＡｌＧａＮ層２２のヘテロ接合界面を高速に移動する状態となる。ソース電極１４から供給された電子は、ｉ型のＧａＮ層２４とＡｌＧａＮ層２２のヘテロ接合界面を高速に移動し、アパーチャー２８の上部の位置において、ｉ型のＧａＮ層２４を縦方向に流れ、アパーチャー２８を充填しているＧａＮ層２６を縦に流れ、ｎ−型のＧａＮ層６を縦に流れ、ｎ＋型のＧａＮ層４を縦に流れてドレイン電極２に至る。ゲート電極１８に正電圧を印加すると、ドレイン電極２からソース電極１４に電流が流れる。 When a positive voltage is applied to the gate electrode 18, the depletion layer spreading at the heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22 disappears. Then, a two-dimensional electron gas is generated at the junction interface by the quantum well generated at the heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22. The electrons move at a high speed through the heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22. Electrons supplied from the source electrode 14 move at a high speed through the heterojunction interface between the i-type GaN layer 24 and the AlGaN layer 22, and flow in the i-type GaN layer 24 in the vertical direction at a position above the aperture 28. The GaN layer 26 filled with the aperture 28 flows vertically, the n − -type GaN layer 6 flows vertically, the n + -type GaN layer 4 flows vertically and reaches the drain electrode 2. When a positive voltage is applied to the gate electrode 18, a current flows from the drain electrode 2 to the source electrode 14.

電子がｎ−型のＧａＮ層６を縦に流れるときに、アパーチャー２８の直下には浮遊電流ブロック領域８が存在するので、電子は、浮遊電流ブロック領域８を迂回しながら、ｎ−型のＧａＮ層６を縦に流れる。電子が浮遊電流ブロック領域８を迂回して流れることによって半導体装置３０のオン抵抗は若干増加するが、特段の問題はない。 When electrons flow vertically through the n − -type GaN layer 6, the floating current blocking region 8 exists immediately below the aperture 28, so that the electrons bypass the floating current blocking region 8 and bypass the n − -type GaN. Flows vertically through layer 6. Although the on-resistance of the semiconductor device 30 slightly increases as electrons flow around the floating current block region 8, there is no particular problem.

ゲート電極１８に正電圧を印加しない状態では、ドレイン電極２に高電位が印加され、ソース電極１４が接地されている。ｎ＋型のＧａＮ層４は低抵抗であり、ｎ＋型のＧａＮ層４のほぼ全域がドレイン電極２の高電位に等しくなる。ｐ型のＧａＮ層１０も低抵抗であり、ソース電極１４が接地されているので、ｐ型のＧａＮ層１０のほぼ全域が接地電圧に維持される。その一方において、ｉ型のＧａＮ層２４とＡｌＧａＮ層２２は高抵抗なので、ソース電極１４が接地されていても、その全域が接地電位となるわけでない。特に、アパーチャー２８の上部に位置する範囲のｉ型のＧａＮ層２４とＡｌＧａＮ層２２は、ソース電極１４から離れているので、接地電位とならない。 In a state where no positive voltage is applied to the gate electrode 18, a high potential is applied to the drain electrode 2, and the source electrode 14 is grounded. The n + -type GaN layer 4 has a low resistance, and almost the entire area of the n + -type GaN layer 4 is equal to the high potential of the drain electrode 2. The p-type GaN layer 10 also has a low resistance, and since the source electrode 14 is grounded, almost the entire area of the p-type GaN layer 10 is maintained at the ground voltage. On the other hand, since the i-type GaN layer 24 and the AlGaN layer 22 have high resistance, even if the source electrode 14 is grounded, the entire region does not become the ground potential. In particular, since the i-type GaN layer 24 and the AlGaN layer 22 in the range located above the aperture 28 are separated from the source electrode 14, they are not at ground potential.

このとき、浮遊電流ブロック領域８が存在しないと、アパーチャー２８を充填しているＧａＮ層２６が高電位となり、アパーチャー２８の上部に位置しているｉ型のＧａＮ層２４とＡｌＧａＮ層２２の電位が上昇してしまう。図２は、図１のIIに示す範囲の等電位線ａの分布を示す。ただし、浮遊電流ブロック領域８が存在しない場合を図示している。アパーチャー２８を充填しているＧａＮ層２６、アパーチャー２８の上部に位置している範囲のｉ型のＧａＮ層２４とＡｌＧａＮ層２２のいずれも高電圧となり、ゲート絶縁層２０の表面と裏面の間に大きな電圧差が印加されることが分る。ゲート絶縁層２０は、ゲート電極１８に正電圧を印加して半導体装置３０をオンする際の閾値電圧を低くしたいことから、薄くする必要がある。薄いゲート絶縁層２０の表面と裏面の間に大きな電圧差が印加されと、ゲート絶縁層２０が破壊されてしまう。浮遊電流ブロック領域８が存在しない半導体装置３０では、耐圧能力が低い。耐圧能力を上げようとすると、ゲート絶縁層２０を厚くする必要があり、半導体装置３０をオンする際の閾値電圧が上がってしまう。   At this time, if the floating current block region 8 does not exist, the GaN layer 26 filled with the aperture 28 becomes a high potential, and the potentials of the i-type GaN layer 24 and the AlGaN layer 22 located above the aperture 28 are increased. It will rise. FIG. 2 shows the distribution of equipotential lines a in the range indicated by II in FIG. However, the case where the floating current block region 8 does not exist is illustrated. Both the GaN layer 26 filled with the aperture 28 and the i-type GaN layer 24 and the AlGaN layer 22 in the range located above the aperture 28 are at a high voltage, and between the front and back surfaces of the gate insulating layer 20. It can be seen that a large voltage difference is applied. The gate insulating layer 20 needs to be thin because it is desired to reduce the threshold voltage when the semiconductor device 30 is turned on by applying a positive voltage to the gate electrode 18. When a large voltage difference is applied between the front and back surfaces of the thin gate insulating layer 20, the gate insulating layer 20 is destroyed. In the semiconductor device 30 in which the floating current block region 8 does not exist, the withstand voltage capability is low. In order to increase the withstand voltage capability, it is necessary to increase the thickness of the gate insulating layer 20, and the threshold voltage when the semiconductor device 30 is turned on increases.

図３は、図２と同じ図であるが、浮遊電流ブロック領域８が形成されている場合を示す。この場合、等電位線ｂが浮遊電流ブロック領域８の下にまわり込み、アパーチャー２８を充填しているＧａＮ層２６と、アパーチャー２８の上部に位置している範囲のｉ型のＧａＮ層２４とＡｌＧａＮ層２２の電位が低下する。浮遊電流ブロック領域８を形成すると、ゲート絶縁層２０の表面と裏面の間に大きな電圧差が印加されるのを防止できる。浮遊電流ブロック領域８を形成すると、半導体装置３０の耐圧能力が改善される。ゲート絶縁層２０を厚くする必要がなく、半導体装置３０をオンする際の閾値電圧が上昇してしまうことがない。   FIG. 3 is the same view as FIG. 2, but shows a case where the floating current block region 8 is formed. In this case, the equipotential line b wraps under the floating current block region 8, the GaN layer 26 filling the aperture 28, the i-type GaN layer 24 in the range located above the aperture 28, and the AlGaN The potential of the layer 22 decreases. When the floating current block region 8 is formed, it is possible to prevent a large voltage difference from being applied between the front surface and the back surface of the gate insulating layer 20. When the floating current block region 8 is formed, the withstand voltage capability of the semiconductor device 30 is improved. It is not necessary to increase the thickness of the gate insulating layer 20, and the threshold voltage when the semiconductor device 30 is turned on does not increase.

図４から図１０は、半導体装置３０の製造工程を示す。図４は、ｎ＋型のＧａＮ層４となる基板を用意し、ｎ＋型のＧａＮ層４の上面にＭＯＣＶＤ法によってｎ−型のＧａＮ層６を結晶成長し、ｎ−型のＧａＮ層６の上面に浮遊電流ブロック層８ａを結晶成長した段階を示す。ｎ−型のＧａＮ層６の厚みは10μｍであり、不純物濃度は２×１０１６ｃｍ−３である。この段階の浮遊電流ブロック層８ａはパターニングされておらず、一様に広がっている。
浮遊電流ブロック層８ａは、Ａｌ，Ｃ，Ｆｅなどの不純物を取り込みながら、ＧａＮ層を結晶成長することで形成する。Ａｌ，Ｃ，Ｆｅなどの不純物を取り込みながらＧａＮ層を結晶成長すると、伝導体と価電子帯の中間値よりも価電子帯側に準位を持つ深い準位が形成され、その深い準位が電子をトラップして電流が流れるのをブロックする。実際には、価電子帯から0.2〜1.7ｅｖだけ禁制帯域に入り込んだ準位が形成される。深い準位の密度が１０１８〜２０ｃｍ−３となる程度の量の不純物を添加する。浮遊電流ブロック層８ａは、約５００ｎｍの厚みに形成する。
ＭｇまたはＺｎなどの不純物を取り込みながら、ＧａＮ層を結晶成長することで浮遊電流ブロック層８ａ形成してもよい。この場合は、ｐ型のＧａＮ層が結晶成長する。ｐ型のＧａＮ層も浮遊電流ブロック層８ａとして機能する。 4 to 10 show the manufacturing process of the semiconductor device 30. FIG. 4, providing a substrate comprising an n + -type GaN layer 4, n by the MOCVD method on the upper surface of the GaN layer 4 of n + -type - -type GaN layers 6 crystal growth, n - -type GaN layer 6 A stage in which the floating current blocking layer 8a is crystal-grown on the upper surface of FIG. The n − -type GaN layer 6 has a thickness of 10 μm and an impurity concentration of 2 × 10 16 cm −3 . The floating current blocking layer 8a at this stage is not patterned and spreads uniformly.
The floating current blocking layer 8a is formed by crystal growth of a GaN layer while taking in impurities such as Al, C, and Fe. When a GaN layer is grown while incorporating impurities such as Al, C, and Fe, a deep level having a level closer to the valence band side than the intermediate value between the conductor and the valence band is formed. Blocks current flow by trapping electrons. In practice, a level is formed that enters the forbidden band by 0.2 to 1.7 ev from the valence band. An impurity is added in such an amount that the deep level density is 10 18 to 20 cm −3 . The floating current blocking layer 8a is formed to a thickness of about 500 nm.
The floating current blocking layer 8a may be formed by crystal growth of the GaN layer while taking in impurities such as Mg or Zn. In this case, the p-type GaN layer grows. The p-type GaN layer also functions as the floating current blocking layer 8a.

図５は、ＧａＮ結晶で形成されている浮遊電流ブロック層８ａの上面の全域にＳｉＯ２のマスク層３２を形成し、後で浮遊電流ブロック領域８を形成する範囲のマスク層３２を残存し、それ以外の範囲のマスク層３２をフォトリソグラフィーとエッチングによって除去した状態を示す。
図６は、局所的に残存したマスク層３２をマスクにして塩素系プラズマエッチングを実施し、マスク層３２から露出している範囲の浮遊電流ブロック層８ａを除去した状態を示す。この段階で、浮遊電流ブロック領域８が形成される。
図７は、マスク層３２を除去した状態を示す。
図８は、ｎ−型のＧａＮ層６とＧａＮ結晶で形成されている浮遊電流ブロック領域８の上面に、ｎ−型のＧａＮ層６を再び結晶成長し、ついでｐ型のＧａＮ層１０を結晶成長した段階を示す。浮遊電流ブロック領域８の上面に、厚さ２μｍのｎ−型のＧａＮ層６を結晶成長する。ｎ−型のＧａＮ層６の不純物濃度は、２×１０１６ｃｍ−３程度とする。ｐ型のＧａＮ層１０の厚みは０．５μｍとし、不純物濃度は、１０１９ｃｍ−３程度とする。この段階のｐ型のＧａＮ層１０にはアパーチャー２８が形成されておらず、一様に広がっている。
図９は、ｐ型のＧａＮ層１０の上面の全域にＳｉＯ２のマスク層３４を形成し、フォトリソグラフィーとエッチングによって、後でアパーチャー２８を形成する範囲のマスク層３４を除去した状態を示す。
図１０は、局所的に残存したマスク層３４をマスクにしてドライエッチング（塩素系プラズマエッチング）を実施し、マスク層３４から露出している範囲のｐ型のＧａＮ層１０を除去した状態を示す。この段階で、ｐ型のＧａＮ層１０にアパーチャー２８が形成される。この段階では、アパーチャー２８の底面に露出するｎ−型のＧａＮ層６の表面もエッチングされ、各種の損傷が生じる。また強くｎ型化する。図１０の状態が得られた後に、マスク層３４を除去する。 FIG. 5 shows that the mask layer 32 of SiO 2 is formed over the entire upper surface of the floating current block layer 8a formed of GaN crystal, and the mask layer 32 in the range where the floating current block region 8 is formed later remains. A state in which the mask layer 32 in the other range is removed by photolithography and etching is shown.
FIG. 6 shows a state in which chlorine plasma etching is performed using the mask layer 32 that remains locally as a mask, and the floating current blocking layer 8a in a range exposed from the mask layer 32 is removed. At this stage, the floating current block region 8 is formed.
FIG. 7 shows a state where the mask layer 32 is removed.
8, n - the upper surface of the type GaN layer 6 and the floating are formed in the GaN crystal current blocking region 8, n - type of crystal growth again GaN layer 6, and then the GaN layer 10 of p-type crystals Indicates the stage of growth. On the upper surface of the floating current block region 8, an n − -type GaN layer 6 having a thickness of 2 μm is crystal-grown. The impurity concentration of the n − -type GaN layer 6 is about 2 × 10 16 cm −3 . The p-type GaN layer 10 has a thickness of 0.5 μm and an impurity concentration of about 10 19 cm −3 . The apertures 28 are not formed in the p-type GaN layer 10 at this stage, and are spread uniformly.
FIG. 9 shows a state in which a mask layer 34 of SiO 2 is formed over the entire upper surface of the p-type GaN layer 10 and the mask layer 34 in a range where the aperture 28 is later formed is removed by photolithography and etching.
FIG. 10 shows a state where dry etching (chlorine plasma etching) is performed using the locally remaining mask layer 34 as a mask, and the p-type GaN layer 10 in a range exposed from the mask layer 34 is removed. . At this stage, the aperture 28 is formed in the p-type GaN layer 10. At this stage, the surface of the n − -type GaN layer 6 exposed on the bottom surface of the aperture 28 is also etched, causing various damages. In addition, it is strongly n-type. After the state of FIG. 10 is obtained, the mask layer 34 is removed.

図１１は、ｐ型のＧａＮ層１０の表面と、アパーチャー２８の底面に露出するｎ−型のＧａＮ層６の表面に、ｉ型のＧａＮ層２６，２４を結晶成長し、ｉ型のＧａＮ層２４の表面にＡｌＧａＮ層２２を結晶成長した段階を示す。ｉ型のＧａＮ層２４が結晶成長する条件で結晶成長しても、アパーチャー２８内に形成されるＧａＮ層２６はｎ型となる。本実施例では、浮遊電流ブロック領域８を利用するので、アパーチャー２８内に形成されるＧａＮ層２６がｎ型となっても、耐圧が低下することがない。ｉ型のＧａＮ層２６，２４の代わりにｎ型のＧａＮ層２６，２４を結晶成長してもよい。あるいはｐ型のＧａＮ層２６，２４を結晶成長してもよい。ただしｐ型を利用する場合には、ｐ型のＧａＮｓ層１０よりも低濃度とする。
結晶成長の条件によっては、アパーチャー２８内に形成されるＧａＮ層２６をｉ型とすることができる。その場合でも、ｎ−型のＧａＮ層６とｉ型のＧａＮ層２６の界面に強くｎ型化した領域が発生し、その領域が半導体装置の耐圧を低下させる。本実施例では、浮遊電流ブロック領域８を利用するので、強くｎ型化した領域が形成されても、耐圧が低下することがない。
図１２は、ＡｌＧａＮ層２２とｉ型のＧａＮ層２４を選択的にエッチングしてｐ型のＧａＮ層１０とｉ型のＧａＮ層２４の表面の一部を露出し、ｐコンタクト領域１２とソースコンタクト領域１６を形成し、ゲート絶縁層２０、ゲート電極１８、ソース電極１４、ドレイン電極２を形成した段階を示す。以上によって、半導体装置３０が製造される。 FIG. 11 shows i-type GaN layers 26, 24 grown on the surface of the p-type GaN layer 10 and the surface of the n − -type GaN layer 6 exposed on the bottom surface of the aperture 28. The stage in which the AlGaN layer 22 is crystal-grown on the surface of 24 is shown. Even if the i-type GaN layer 24 is crystal-grown under crystal growth conditions, the GaN layer 26 formed in the aperture 28 is n-type. In this embodiment, since the floating current block region 8 is used, the breakdown voltage does not decrease even if the GaN layer 26 formed in the aperture 28 is n-type. Instead of the i-type GaN layers 26 and 24, the n-type GaN layers 26 and 24 may be crystal-grown. Alternatively, the p-type GaN layers 26 and 24 may be crystal-grown. However, when p-type is used, the concentration is lower than that of the p-type GaN layer 10.
Depending on the crystal growth conditions, the GaN layer 26 formed in the aperture 28 can be i-type. Even in that case, a strongly n-type region is generated at the interface between the n − -type GaN layer 6 and the i-type GaN layer 26, and this region reduces the breakdown voltage of the semiconductor device. In this embodiment, since the floating current block region 8 is used, the withstand voltage does not decrease even if a strongly n-type region is formed.
In FIG. 12, the AlGaN layer 22 and the i-type GaN layer 24 are selectively etched to expose part of the surfaces of the p-type GaN layer 10 and the i-type GaN layer 24, and the p-contact region 12 and the source contact are exposed. A stage where the region 16 is formed and the gate insulating layer 20, the gate electrode 18, the source electrode 14, and the drain electrode 2 are formed is shown. Thus, the semiconductor device 30 is manufactured.

（製造方法の第２実施例）
図１３から図２１に製造方法の第２実施例を示す。
図１３は、ｎ＋型のＧａＮ層４となる基板を用意し、ｎ＋型のＧａＮ層４の上面にｎ−型のＧａＮ層６を結晶成長した段階を示す。
図１４は、ｎ−型のＧａＮ層６の上面の全域にＳｉＯ２のマスク層３６を形成し、後で浮遊電流ブロック領域８を形成する範囲のマスク層３６をフォトリソグラフィーとエッチングによって除去した状態を示す。
図１５は、局所的に残存したマスク層３６をマスクにしてＡｌ，Ｃ，Ｆｅ，Ｍｇ，Ｚｎなどの不純物をイオン注入した段階を示す。Ａｌ，Ｃ，Ｆｅ，Ｍｇ，Ｚｎなどの不純物をイオン注入すると、伝導体と価電子帯の中間値よりも価電子帯側に準位を持つ深い準位が形成され、電子をトラップして電流が流れるのをブロックする。実際には、価電子帯よりも０．２〜１．７ｅｖだけ禁制帯域に入り込んだ準位が形成される。深い準位が１０１８〜２０ｃｍ−３の密度が得られる程度に不純物を添加する。浮遊電流ブロック領域８は、約５００ｎｍの厚みに形成する。 (Second Example of Manufacturing Method)
13 to 21 show a second embodiment of the manufacturing method.
FIG. 13 shows a stage in which a substrate to be the n + -type GaN layer 4 is prepared and an n − -type GaN layer 6 is crystal-grown on the upper surface of the n + -type GaN layer 4.
FIG. 14 shows a state in which a mask layer 36 of SiO 2 is formed over the entire upper surface of the n − -type GaN layer 6 and the mask layer 36 in a range where a floating current blocking region 8 is formed later is removed by photolithography and etching. Indicates.
FIG. 15 shows a stage in which impurities such as Al, C, Fe, Mg, Zn are ion-implanted using the mask layer 36 that remains locally as a mask. When an impurity such as Al, C, Fe, Mg, Zn is ion-implanted, a deep level having a level closer to the valence band side than the intermediate value between the conductor and the valence band is formed, trapping electrons and Block the flow. In practice, a level is formed that enters the forbidden band by 0.2 to 1.7 ev from the valence band. Impurities are added to such an extent that a deep level of 10 18 to 20 cm −3 can be obtained. The floating current block region 8 is formed to a thickness of about 500 nm.

図１６は、マスク層３６を除去した状態を示す。
図１７は、一部に浮遊電流ブロック領域８が形成されているｎ−型のＧａＮ層６の上面に、ｎ−型のＧａＮ層６を再び結晶成長し、ついでｐ型のＧａＮ層１０を結晶成長した段階を示す。浮遊電流ブロック領域８の上面に、厚さ２μｍのｎ−型のＧａＮ層６を結晶成長する。ｎ−型のＧａＮ層６の不純物濃度は、２×１０１６ｃｍ−３程度とする。ｐ型のＧａＮ層１０の厚みは０．５μｍとし、不純物濃度は、１０１９ｃｍ−３程度とする。この段階のｐ型のＧａＮ層１０にはアパーチャー２８が形成されておらず、一様に広がっている。
図１８〜２１は、図９〜１２に同じであり、重複記載を省略する。 FIG. 16 shows a state where the mask layer 36 is removed.
17, n floating current blocking region 8 in a part are formed - on the upper surface of the GaN layer 6 of the mold, n - type of crystal growth again GaN layer 6, and then the GaN layer 10 of p-type crystals Indicates the stage of growth. On the upper surface of the floating current block region 8, an n − -type GaN layer 6 having a thickness of 2 μm is crystal-grown. The impurity concentration of the n − -type GaN layer 6 is about 2 × 10 16 cm −3 . The p-type GaN layer 10 has a thickness of 0.5 μm and an impurity concentration of about 10 19 cm −3 . The apertures 28 are not formed in the p-type GaN layer 10 at this stage, and are spread uniformly.
18 to 21 are the same as FIGS. 9 to 12 and redundant description is omitted.

(第２実施例の半導体装置)
図２２は、第２実施例の半導体装置４０を示す。この実施例では、ｎ−型のＧａＮ結晶で形成されているドリフト層６内に、浮遊電流ブロック領域８ｂが分散して配置されている。この場合、隣接する浮遊電流ブロック８ｂ同士の間隔が、半導体装置４０のオフ時に浮遊電流ブロック８ａからｎ型のドリフト層６に向けて伸びる空乏層同士がコンタクトする長さに管理されている。この場合、アパーチャー２８の下方に、浮遊電流ブロック領域８ｂが形成されていない範囲があってもよい。
(第３実施例の半導体装置)
図２３は、第３実施例の半導体装置５０を示す。この実施例では、浮遊電流ブロック８ｃが２層に分かれて分散配置されている。浮遊電流ブロック領域が３層以上に分かれて分散配置されていてもよい。 (Semiconductor device of the second embodiment)
FIG. 22 shows a semiconductor device 40 of the second embodiment. In this embodiment, floating current blocking regions 8b are distributed and arranged in the drift layer 6 formed of n − type GaN crystal. In this case, the interval between the adjacent floating current blocks 8b is managed so as to contact the depletion layers extending from the floating current block 8a toward the n-type drift layer 6 when the semiconductor device 40 is turned off. In this case, there may be a range below the aperture 28 where the floating current block region 8b is not formed.
(Semiconductor device of the third embodiment)
FIG. 23 shows a semiconductor device 50 of the third embodiment. In this embodiment, the floating current block 8c is distributed in two layers. The floating current block region may be divided and arranged in three or more layers.

（第4実施例の半導体装置）
図２４は、第４実施例の半導体装置６０を示す。この実施例では、ＡｌＧａＮ層２２が存在しない。ｉ型のＧａＮ層２４の上に直接にゲート絶縁層２０が形成されており、その表面にゲート電極１８が形成されている。
ＡｌＧａＮ層２２が存在しない半導体装置６０は、ＭＯＳＦＥＴとして動作する。この場合も浮遊電流ブロック領域８によって耐圧能力が向上する。 (Semiconductor device of the fourth embodiment)
FIG. 24 shows a semiconductor device 60 of the fourth embodiment. In this embodiment, the AlGaN layer 22 does not exist. A gate insulating layer 20 is formed directly on the i-type GaN layer 24, and a gate electrode 18 is formed on the surface thereof.
The semiconductor device 60 without the AlGaN layer 22 operates as a MOSFET. Also in this case, the withstand voltage capability is improved by the floating current block region 8.

以上、本発明の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。   Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時の請求項に記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。   The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

第１実施例の半導体装置の縦断面図を示す。1 is a longitudinal sectional view of a semiconductor device according to a first embodiment. 浮遊電流ブロック領域が形成されていない半導体装置の等電位線の分布を示す。2 shows a distribution of equipotential lines of a semiconductor device in which a floating current block region is not formed. 浮遊電流ブロック領域が形成されている半導体装置の等電位線の分布を示す。2 shows a distribution of equipotential lines of a semiconductor device in which a floating current block region is formed. 第１実施例の半導体装置の製造工程の一部を実施した状態の断面を示す。The cross section of the state which implemented a part of manufacturing process of the semiconductor device of the 1st example is shown. 図４に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 5 shows a cross section in a state where a part of the manufacturing process is further performed following FIG. 4. 図５に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 6 shows a cross-section in a state where a part of the manufacturing process is further performed following FIG. 5. 図６に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 7 shows a cross section in a state where a part of the manufacturing process is further performed following FIG. 6. 図７に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 8 shows a cross section in a state where a part of the manufacturing process is further carried out following FIG. 図８に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 9 shows a cross section in a state where a part of the manufacturing process is further carried out following FIG. 8. 図９に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 10 shows a cross section in a state where a part of the manufacturing process is further carried out following FIG. 9. 図１０に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 10 shows a cross section in a state where a part of the manufacturing process is further performed following FIG. 図１１に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 12 shows a cross section in a state where a part of the manufacturing process is further carried out following FIG. 第１実施例の半導体装置の別の製造工程を示す図であり、製造工程の一部を実施した状態の断面を示す。It is a figure which shows another manufacturing process of the semiconductor device of 1st Example, and shows the cross section of the state which implemented a part of manufacturing process. 図１３に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 14 shows a cross section in a state where a part of the manufacturing process is further performed following FIG. 図１４に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 15 shows a cross section in a state where a part of the manufacturing process is further carried out following FIG. 図１５に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 16 shows a cross section in a state where a part of the manufacturing process is further performed following FIG. 図１６に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 17 shows a cross section in a state where a part of the manufacturing process is further performed following FIG. 16. 図１７に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 18 shows a cross section in a state where a part of the manufacturing process is further carried out following FIG. 図１８に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 19 shows a cross section in a state where a part of the manufacturing process is further carried out following FIG. 図１９に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 19 shows a cross section in a state where a part of the manufacturing process is further performed following FIG. 図２０に続いて製造工程の一部をさらに実施した状態の断面を示す。FIG. 21 shows a cross section in a state where a part of the manufacturing process is further carried out following FIG. 第２実施例の半導体装置の断面図を示す。Sectional drawing of the semiconductor device of 2nd Example is shown. 第３実施例の半導体装置の断面図を示す。Sectional drawing of the semiconductor device of 3rd Example is shown. 第４実施例の半導体装置の断面図を示す。Sectional drawing of the semiconductor device of 4th Example is shown.

符号の説明Explanation of symbols

２：ドレイン電極
４：ドレインコンタクト層（ｎ＋型ＧａＮ層）
６：ドリフト層（ｎ−型ＧａＮ層）
８：浮遊電流ブロック領域（深い準位を持つＧａＮ領域またはｐ型のＧａＮ領域）
１０：ｐ型ＧａＮ層
１２：ｐ型コンタクト領域
１４：ソース電極
１６：ソースコンタクト領域
１８：ゲート電極
２０：ゲート絶縁層
２２：ＡｌＧａＮ層
２４：ｉ型のＧａＮ層
２６：アパーチャーを充填しているＧａＮ層
２８：アパーチャー
３０:半導体装置
３２，３４，３６：マスク
４０，５０，６０：半導体装置 2: Drain electrode 4: Drain contact layer (n + type GaN layer)
6: Drift layer (n - type GaN layer)
8: Floating current block region (a GaN region having a deep level or a p-type GaN region)
10: p-type GaN layer 12: p-type contact region 14: source electrode 16: source contact region 18: gate electrode 20: gate insulating layer 22: AlGaN layer 24: i-type GaN layer 26: GaN filled with an aperture Layer 28: Aperture 30: Semiconductor devices 32, 34, 36: Masks 40, 50, 60: Semiconductor device

Claims (7)

ｎ型のIII族窒化物系化合物半導体で形成されている下層に、p型のIII族窒化物系化合物半導体で形成されている上層が積層されており、
その上層を貫通するアパーチャーが形成されており、
そのアパーチャーにｎ型またはｉ型のIII族窒化物系化合物半導体が充填されており、
前記下層の一部に、伝導帯と価電子帯の中間値よりも価電子帯側の深い準位を持っている浮遊電流ブロック領域が形成されていることを特徴とする半導体装置。 An upper layer formed of a p-type group III nitride compound semiconductor is stacked on a lower layer formed of an n-type group III nitride compound semiconductor,
An aperture that penetrates the upper layer is formed,
The aperture is filled with an n-type or i-type group III nitride compound semiconductor,
A semiconductor device, wherein a floating current block region having a deeper level on the valence band side than an intermediate value between a conduction band and a valence band is formed in a part of the lower layer. III族窒化物系化合物半導体で形成されている表面側下層の表面に、その表面側下層よりもバンドギャップが広いIII族窒化物系化合物半導体で形成されている表面側上層が積層されているヘテロ構造が、前記上層の上に形成されていることを特徴とする請求項１の半導体装置。   A heterojunction in which a surface-side upper layer formed of a group III nitride compound semiconductor having a wider band gap than the surface-side lower layer is laminated on the surface of the surface-side lower layer formed of the group III nitride compound semiconductor The semiconductor device according to claim 1, wherein a structure is formed on the upper layer. III族窒化物系化合物半導体で形成されている表面側層と、その表面側層の表面を覆っているゲート絶縁層と、そのゲート絶縁層の表面に形成されているゲート電極で構成されているＦＥＴ構造が、前記上層の上に形成されていることを特徴とする請求項１の半導体装置。   It is composed of a surface side layer formed of a group III nitride compound semiconductor, a gate insulating layer covering the surface of the surface side layer, and a gate electrode formed on the surface of the gate insulating layer. 2. The semiconductor device according to claim 1, wherein an FET structure is formed on the upper layer. 半導体基板を平面視した状態において、前記浮遊電流ブロック領域の形成範囲と、前記アパーチャーの形成範囲が重複することを特徴とする請求項１から３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein a formation range of the floating current block region and a formation range of the aperture overlap in a state in which the semiconductor substrate is viewed in plan. 5. 半導体基板を平面視した状態において、前記浮遊電流ブロック領域の形成範囲が、前記アパーチャーの形成範囲よりも広く広がっていることを特徴とする請求項１から３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein a formation range of the floating current block region is wider than a formation range of the aperture in a state in which the semiconductor substrate is viewed in plan. 5. . 前記浮遊電流ブロック領域が、前記下層内に分散して配置されていることを特徴とする請求項１から５のいずれか１項に記載の半導体装置。 6. The semiconductor device according to claim 1, wherein the floating current block regions are distributed in the lower layer . 前記浮遊電流ブロック領域が、前記下層内に多層に分かれて分散配置されていることを特徴とする請求項１から５のいずれか１項に記載の半導体装置。 6. The semiconductor device according to claim 1, wherein the floating current block region is distributed in multiple layers in the lower layer .
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