CN209199933U - Semiconductor device with electrode - Google Patents
Semiconductor device with electrode Download PDFInfo
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- CN209199933U CN209199933U CN201821977145.7U CN201821977145U CN209199933U CN 209199933 U CN209199933 U CN 209199933U CN 201821977145 U CN201821977145 U CN 201821977145U CN 209199933 U CN209199933 U CN 209199933U
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Abstract
A kind of semiconductor device with electrode, semiconductor device include multiple grooves；Electrode has flat site and contact area, and contact area accommodates in the trench, and flat site is arranged on contact area；Wherein, the projection of shape of flat site on the first plane is rectangle, and the projection of shape of contact area on the first plane is that have multiple arcs, and whereby, the contact resistance value of electrode can reduce by 20~50% compared with the resistance value of conventional semiconductor device.
Description
Technical field
The utility model provides a semiconductor device with electrode, especially with the three-five semiconductor of trench electrode
Device.
Background technique
Dimensions of semiconductor devices continue it is miniature be semiconductor technology trend.Moreover, three-five device is (such as: gallium nitride
High speed transistor) it is applied to the trend that radio frequency (RF) and high power (high power) device is future.Meanwhile in RF device
Part field, constantly miniature device carrys out improving performance and has been inevitable trend.But it as device size is lasting miniature, connects
Touching impedance is related with resistance coefficient and contact area, and therefore, the contact impedance of the ohmic region in electrode accounts for integral device impedance
Ratio it is bigger.For high-power component, the power dissipation that will cause electric current in electrode rises, and influences device active region
The efficiency in domain；And for radio-frequency devices, the impedance rise of electrode can further influence the device reaction time, cause RF device
Part cutoff frequency and reaction time decline.
Utility model content
In order to improve missing mentioned by the prior art, with electrode partly led the purpose of the utility model is to provide a kind of
Body device includes multiple grooves；And electrode has flat site and contact area, contact area accommodates in the trench, flat
Region is arranged on contact area；Wherein, the projection of shape of flat site on the first plane is rectangle, and contact area exists
Projection of shape in first plane is arc, and whereby, the contact resistance value of electrode, can be with compared with the resistance value of conventional semiconductor device
Reduce by 20~50%.
Preferably, semiconductor device is made of gallium nitride, silicon, silicon carbide or n-type semiconductor material.
Preferably, electrode is the grid of semiconductor devices.
Preferably, semiconductor device is provided with multiple grooves, and contact area accommodates in the trench.
Preferably, in the electrodes, flat site is metal layer, and contact area has metal silicide.
Preferably, the radius of arc is between 1nm-100nm.
The utility model uses simple processing procedure, without too complicated technology, need to only increase by one of lithographic and etching, allow partly
Conductor apparatus surface forms the big groove of subsequent corrosion non-infinite.Surface compared to traditional electrode and semiconductor device is one
Plane (subsequent corrosion be infinitely great), the big groove of subsequent corrosion non-infinite set by the utility model, can expand electrode
With the contact area of semiconductor device, with can achieve the purpose that reduce device contacts impedance to form small semiconductor devices,
To achieve the effect that reduce contact impedance.Contact area is bigger, and impedance will be smaller, and electrical performance is better.This utility model exists
In utilizing simple process design, increase by one lithographic and etching, the equal schools contact area of the ohmic region Lai Tigao allows the connecing of device
Touching impedance can be effectively reduced, and then promote its electrical performance.
Detailed description of the invention
Fig. 1 be it is provided by the utility model, the iii v compound semiconductor device of multiple epitaxial layers is formed on substrate
Schematic diagram；
Fig. 2 is to indicate that the utility model provides one kind and is formed in semiconductor dress according to technology provided by the utility model
The schematic diagram of the electrode set on the first plane；
Fig. 3 is to indicate to be conventionally formed electrode on semiconductor devices the according to technology provided by the utility model
Schematic diagram in one plane；
Fig. 4 (a)-Fig. 4 (d) is to indicate the work that electrode in semiconductor device is formed according to technology provided by the utility model
Skill process, the schematic diagram in the second plane；And
Fig. 5 (a)-Fig. 5 (d) is to indicate active region on semiconductor devices according to technology provided by the utility model
Domain forms the execution step of multiple grooves, the schematic diagram in the second plane.
Specific embodiment
In order to make the purpose of this utility model, technical characteristic and advantage, can more correlative technology field personnel understood, and
It is carried out the utility model, cooperates appended schema herein, specifically illustrate the technical characteristics of the utility model and embodiment,
And enumerate preferred embodiment further explanation.It is related with the utility model feature to express with the schema hereinafter compareed
Signal does not need completely to draw according to practical situation.And the those skilled in the art involved in the explanation of this case embodiment
Technology contents known to member, are also no longer stated.
In the present invention, the X-axis, Y-axis and Z axis system use the cassette coordinate system (Cartesian of dextrorotation
coordinate system).X-axis, Y-axis, Z axis and origin detailed direction in the present invention, be according in each schema
Appearance is indicated, and it be axially second direction, Z axis is axially third direction that wherein X-axis, which is axially first direction, Y-axis,.X-axis is defined again
It is the first plane with the plane that Y-axis is constituted, the plane that X-axis and Z axis are constituted is the second plane, and Y-axis and Z axis are constituted flat
Face is third plane.
Firstly, please refer to Fig. 1, Fig. 1 be it is provided by the utility model, the three-five of multiple epitaxial layers is formed on the substrate
The schematic diagram of compound semi-conductor device.As shown in Figure 1, the semiconductor device 1 that is proposed of the utility model includes substrate and outer
Prolong layer.Wherein.Substrate can be a kind of silicon substrate (Si substrate).Then, epitaxial layer includes buffer layer 120, active
Layer 130, AlGaN barrier layer 140 and GaN coating 141.Buffer layer 120 is formed on substrate 110, wherein buffer layer 120
It can be and formed by nitride multilayer aluminium layer (AlN).And in the preferred embodiment of the utility model, buffer layer 120 can be
It is alternatively formed by one layer of aln layer (AlN) 120a and one layer of aluminum gallium nitride (AlGaN) 120b, wherein aluminum gallium nitride
(AlGaN) 120b is a kind of buffer layer of gradual formula superlattices, is formed on aln layer (AlN) 120a, so that gradual formula
Super-lattice buffer layer 120 and substrate 110 can balance internal stress, and eliminate line caused by GaN/AlN lattice mismatch and lack
It falls into.Followed by active layers 130 are formed on gradual formula super-lattice buffer layer 120, wherein active layers 130 are sequentially to grow up
C-GaN layers of (i.e. carbon-doped-GaN layers) 130a and i-GaN layer (the i.e. intrinsic- of undoped not being implanted into
GaN layer) 130b.Then, successively grow up above active layers 130 AlGaN barrier layer 140 and GaN coating 141, it is outer to be formed
Prolong layer.
It is to indicate a kind of electricity being formed on semiconductor device 1 provided by the utility model next referring to Fig. 2, Fig. 2
Pole 2.Wherein, electrode 2 includes flat site 21 and contact area 22.And have on a surface of semiconductor device 1 multiple
Groove 11.In another embodiment, this groove 11 can be multiple recess (recesses) or multiple moat canals
(trenches) or inverted pyramid (Inverted pyramids).Preferably, in order to allow electric current uniformly to flow, in this reality
In novel, groove 11 is multiple recess or multiple moat canals.In addition, recess (recess) and moat canal (trench) difference are in ditch
The difference of 11 depth of slot, and the projection of shape of a recess on the first plane is only an arc, and a moat canal is first
Projection of shape in plane is the combination of line segment and arc.In this embodiment, time, ditch are formed in order to shorten groove
The type that slot uses is recess, and being formed by groove 11 is depth H range one of value between 1nm-100nm.And it is electric
In pole 2, flat site 21 and contact area 22 are located on semiconductor device 1 through semiconductor process technique with folded.This semiconductor
Technology can be located at semiconductor device 1 by the way that physical vapour deposition (PVD) device (PVD) or chemical vapor deposition device (CVD) are folded
On.Contact area 22 in electrode 2 is folded between flat site 21 and semiconductor device 1.Electrode 2 be for conduction, so
Flat site 21 in electrode 2 is to be made of conductive material with contact area 22, such as metal layer or mixed with impurity
Polysilicon constitute.In order to increase conductivity, in the present invention, it is preferred that use metal, and be conductivity compared with
High gold, silver or copper.In addition, preferable conduction property is formed in order to allow between metal and semiconductor, in conductive layer, with half
The contact area 22 that conductor device 1 contacts must be metal silicide, so that promoting electric current is passing through metal and semiconductor junction
When conduction property, that is, promoted conductivity.
Please continue to refer to Fig. 2.Wherein, the material of semiconductor device 1 can be made of gallium nitride, silicon or silicon carbide,
It is also possible to be made of n-type semiconductor material.The convenience that etches for groove 11 and it can make to be formed by arcuate shape complete
It is whole, cooperate completed semiconductor devices type, in this embodiment, the type of selected semiconductor device 1 compared with
Good is the gallium nitride wafer in N-shaped<111>direction, so that this groove 11 can be in the high electron mobility of gallium nitride semiconductor devices 1
It is realized in rate transistor.In addition, in a specific embodiment, this electrode 2 can be grid, source electrode in semiconductor devices
Or drain electrode, the e.g. grid in insulated gate bipolar transistor (IGBT), the grid in high electron mobility transistor (HEMT)
The source electrode of pole metal oxide semiconductcor field effect transistor (MOSFET) or drain electrode etc..If moreover, will be as half
When grid in conductor device, cooperate the semiconductor device 1 of n-type semiconductor material, the metal material of this grid needs to select material
Expect that work function is lower than the metal of 5.5eV, such as gold, silver, copper or aluminium, so that electrode 2 and semiconductor device 1 form Ohmic contact
(ohmic contact), to lower the resistivity that grid is contacted with semiconductor alloy.
It is subsequent, please also refer to Fig. 2 and Fig. 3.Wherein, Fig. 3 is the tradition for indicating to be formed in conventional semiconductor device 10
Electrode 20.In Fig. 1, all projection of shape is rectangle, contact area 22 to the metallic region of the utility model on the first plane
Projection of shape on the first plane is multiple arcs.The purpose for forming groove 11 is to increase electrode 2 and semiconductor device 1
Contact surface area.According to Ohm's law, electrode 2 and the contact surface area of semiconductor device 1 are bigger, then metal-semiconductor contact is made
At contact resistance it is anti-then smaller.According to above-mentioned theory, so being devised on some surface of semiconductor device 1 multiple
Groove 11 with arcuate shape in one plane, with the tradition electricity being formed in conventional semiconductor device 10 compared to such as Fig. 2
Pole 20 is straight line between 10 junction of traditional electrode 20 and conventional semiconductor device, there is lesser contact area.Conjunction with semiconductors
1 material of device and contact resistance design, preferably, the depth H of groove 11 is best when 1 material of semiconductor device is gallium nitride
It is designed to 1nm-100nm, when so that electrode 2 and semiconductor device 1 having electric current to pass through, the contact resistance value of electrode is more traditional partly to be led
The resistance value of body device can reduce by 20~50%.
One specific embodiment of the subsequent formation process for illustrating how the electrode on semiconductor device 12.It please refers to
Fig. 4 (a)-Fig. 4 (d) is the process flow for showing electrode in semiconductor device 2 and being formed on semiconductor device 1, in the second plane
On schematic diagram.Fig. 4 (a)-Fig. 4 (d) be formed by electrode 2 be located at semiconductor devices be high electron mobility quartz crystal
It manages on (HEMT), there is first grid 23A, the first source electrode 23B and the first drain electrode 23C.Execution step described below:
Step 1: obtaining semiconductor device 1, and define active region on semiconductor device 1.Please also refer to Fig. 4
(a).Wherein, semiconductor device 1 can be the silicon chip in<111>direction of N-shaped type or<1111>direction of N-shaped type
Gallium nitride chip.In this embodiment, it is not intended to limit the direction of chip.Active area (also known as plateau region Mesa)
It is to be formed by plateau through after a variety of etch process, doping process and Patternized technique.Active area is that semiconductor devices exists
After activation, electric current flows through region.In a first direction, and electric current can be in the surface region stream of semiconductor device 1 for current direction
It is dynamic, as represented by the arrow of Fig. 4 (a).It connects and carries out step 2.
Step 2: the active area on semiconductor device 1 forms multiple grooves 11.Please also refer to Fig. 4 (b).Wherein,
Active area on semiconductor device 1 is formed by by the first smooth mask (Fig. 4 (b) is not disclosed).First smooth mask has
First pattern, and the multiple rectangles of projection of shape of the multiple grooves 11 in the second plane.This multiple rectangle marshalling, two
Two length and width are all equal.Multiple grooves 11 are divided into two parts, left part part and right part part.Left part part is formed in user's crystal to be formed
In the source region of pipe；Right part part is formed in the drain region of user's transistor to be formed.It connects and carries out step 3.
Step 3: covering electrode 2 on multiple grooves 11, and connect the thermal annealing of alloy to electrode 2.Please also refer to Fig. 4
(c).The subsequent region respectively for user's transistor source to be formed and drain electrode passes through in a manner of physical vapour deposition (PVD) PVD
Two smooth masks (Fig. 4 (c) is not disclosed) distinguish deposited metal in two regions.Second smooth mask has the second pattern.In addition, heavy
When product, metal can first fill up 11 region of groove, can then be covered on the surface of semiconductor device 1, eventually form such as Fig. 4 (c) institute
The pattern in the second plane disclosed.Finally, the semiconductor device 1 for completing to have metal layer is pushed into oven, to carry out
Conventional silication technique for metal, that is, the thermal anneal process of alloy.After completing conventional silication technique for metal, two electrodes 2
(the first source electrode 23B is just completed with the first drain electrode 23C).And the electrode 2 after silication technique for metal can have flat region
Domain 21 and contact area 22.Contact area 22 just contains metal silicide.It connects and carries out step 4.
Step 4: forming first grid 23A.Using third light mask, in the predetermined region for forming transistor gate of user
In.By Pvd equipment, with stacked on gate metal.Please also refer to Fig. 4 (d).This completes semiconductor dresses
Set the formation process of the electrode 2 on 1.In another embodiment, identical third light can be used in first grid 23A
Mask, in the predetermined region for forming transistor gate of user.By chemical vapor depsotition equipment, with stacked on comprising mixed with impurity
Polysilicon gate grade.Mixed with the polysilicon gate grade of impurity, there is no restriction in the present invention with type for impurity profiles, only wants
It is matched with the work function of the material of semiconductor device 1, Ohmic contact can be reached, and reach the due function of grid in the transistor
Energy.In this way, entire transistor just completes.
Fig. 1 and Fig. 2 are gone back to, Fig. 1 institute's art is the diagrammatic cross-section after the stacked on electrode 2 of transistor.It can from Fig. 1 and Fig. 2
, it is evident that the junction length for being different from conventional process only has straight line.New processing procedure due to there is the structure of undaform, it etc.
Junction length is imitated obviously than a wire length of conventional process, also therefore better contact impedance is had, facilitates entire device
Electrical performance.
The utility model is that semiconductor device surface is provided with the big groove of multiple subsequent corrosion non-infinite, compared to biography
The surface of system electrode and semiconductor device is a plane (subsequent corrosion is infinitely great), multiple songs set by the utility model
The big groove of radius surface non-infinite, can expand the contact area of electrode and semiconductor device, can reach reduction device contacts
The purpose of impedance is to form small semiconductor devices, to achieve the effect that reduce contact impedance.
Finally, will be explained in each thin portion step that the active area on semiconductor device 1 forms multiple grooves 11,
Please also refer to Fig. 5 (a)-Fig. 5 (d).The active area that Fig. 5 (a)-Fig. 5 (d) is shown on semiconductor device 1 forms multiple ditches
The execution step of slot 11, the schematic diagram in the second plane.
Step 2-1: coating photoresist layer 3 is on semiconductor device 1.Please also refer to Fig. 5 (a).Using coating process,
The predetermined two region coating photoresists for forming the drain electrode of the first source electrode 23B and first 23C of above-mentioned user.The use type of photoresist
And coating thickness can be stipulated according to user demand itself.It in this embodiment, is 1nm- to form depth H
The groove 11 of 100nm, preferably, palpus coating thickness is 1um (non-emphasis, general photoresist, such as say 1um), type is negative
The photoresist layer 3 of shape.Also, coating photoresist layer 3 can preferably enter baking box and toast after semiconductor device 1, will
Solvent removal in photoresist layer 3, to solidify photoresist layer 3, and increases sticking together for photoresist layer 3 and semiconductor device 1
Property.It connects and carries out step 2-2.
Step 2-2: carrying out Patternized technique to photoresist layer 3, patterns photoresist 31 to be formed.Please also refer to Fig. 5
(b).Semiconductor device 1 with photoresist layer 3 is put into conventional exposure machine, second light with the second pattern is cooperated to hide
Cover, the second pattern is copied on photoresist layer 3 from the second smooth mask, patterns photoresist 31 to be formed.It is specific real at this
It applies in mode, photoresist layer 3 has the first space D of 0.5um-20um.It connects and carries out step 2-3.
Step 2-3: through patterning photoresist 31 when being used as mask, to etch semiconductor device 1.Please also refer to Fig. 5
(c), in the way of etching, such as wet etching or dry ecthing, etching solution or etch ion will be towards semiconductor devices 1
It is mobile, and go deep into semiconductor device 1, to be reacted with the progress physical reactions of semiconductor device 1 or chemical erosion, and eat
The groove 11 of certain shapes.11 depth bounds of groove are in the range of 5~30 nanometers.Using wet etching or dry ecthing, have not
The groove 11 of similar shape.In this embodiment, it in order to etch the groove 11 for being on the first plane arc, etches
Can use can be with the wet etch method of isotropic etching, and the acid system being e.g. mixed to form using ingredients such as hydrofluoric acid, nitric acid is lost
Liquid is carved, or with the alkali system etching solution being mixed to form with potassium hydroxide, tetramethylammonium hydroxide etc. ingredient.
Step 2-4: removal patterning photoresist 31.Please also refer to Fig. 5 (d).By complete step 2-4, have pattern
Change 31 semiconductor device 1 of photoresist and impregnate single ethylether propylene glycol and propylene glycol methyl ether acetate, to remove patterning photoetching
Glue 31.Finally, can be obtained as the surface that Fig. 4 (d) is revealed, projection on the first plane is similar undaform is tied
Structure.If using microscope in the multiple grooves 11 of the second plan view, then it can be seen that the presentation of 1 surface of semiconductor device is similar
In the striped of zebra lines.Wherein, because groove 11 can absorb light, in zebra lines, belong in the place of black streaking
11 region of groove, and belong in the place of informal voucher line and be not etched plateau region.
Generally speaking, the electrode 2 provided by the utility model being formed on semiconductor device 1, it is only necessary to using simple
Processing procedure is only needed compared with traditional 2 technique of semi-conducting electrode using twice light mask, and the utility model only needs one light of more increases
Mask, that is, one of patterning process is had more, groove can be formed, just to achieve the effect that reduce contact impedance.Contact area
Bigger, impedance will be smaller, and electrical performance is better.This utility model is to increase by one of lithographic using simple process design
With etching, the contact impedance of device can be effectively reduced for the equivalent contact area of Lai Tigao source electrode and drain region, and then is promoted
Its electrical performance.
The foregoing is merely the preferred embodiment of the utility model, the interest field that is not intended to limit the utility model；
Above description simultaneously, should can be illustrated and implement for the special personage of correlative technology field, therefore other are practical without departing from this
The lower equivalent change or modification completed of novel disclosed spirit, should be included in claim.
Claims (8)
1. a kind of semiconductor device with electrode, which is characterized in that the semiconductor device includes multiple grooves；The electrode
With flat site and contact area, in the trench, the flat site is arranged described for the contact area accommodating
On contact area；The projection of shape of the flat site on the first plane is rectangle, also, the contact area is first
Projection of shape in plane is arc.
2. semiconductor device with electrode as described in claim 1, which is characterized in that the semiconductor device is by nitrogenizing
Gallium, silicon or silicon carbide are constituted.
3. semiconductor device with electrode as described in claim 1, which is characterized in that the semiconductor device is N-shaped half
Conductive material.
4. semiconductor device with electrode as described in claim 1, which is characterized in that the electrode is semiconductor devices
Grid.
5. semiconductor device with electrode as described in claim 1, which is characterized in that the radius of the arc exists
Between 1nm-100nm.
6. semiconductor device as described in claim 1, which is characterized in that the flat site is metal layer.
7. semiconductor device as described in claim 1, which is characterized in that the contact area has metal silicide.
8. semiconductor device as described in claim 1, which is characterized in that the groove is by multiple recess or moat canal institute structure
At.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821977145.7U CN209199933U (en) | 2018-11-28 | 2018-11-28 | Semiconductor device with electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821977145.7U CN209199933U (en) | 2018-11-28 | 2018-11-28 | Semiconductor device with electrode |
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| CN209199933U true CN209199933U (en) | 2019-08-02 |
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| CN201821977145.7U Active CN209199933U (en) | 2018-11-28 | 2018-11-28 | Semiconductor device with electrode |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112485607A (en) * | 2020-09-11 | 2021-03-12 | 浙江三君电力工程有限公司 | Novel cable alternating current withstand voltage test device |
| CN112582414A (en) * | 2019-09-30 | 2021-03-30 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
-
2018
- 2018-11-28 CN CN201821977145.7U patent/CN209199933U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582414A (en) * | 2019-09-30 | 2021-03-30 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
| CN112582414B (en) * | 2019-09-30 | 2022-12-09 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
| CN112485607A (en) * | 2020-09-11 | 2021-03-12 | 浙江三君电力工程有限公司 | Novel cable alternating current withstand voltage test device |
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Effective date of registration: 20191121 Address after: Room 01, 13 / F, central city, 11 Haisheng Road, Tsuen Wan, New Territories, Hong Kong, China Patentee after: Gemini semiconductor manufacturing (Hong Kong) Co., Ltd Address before: Second floor, No.38 Keyi street, Zhunan Town, miaoso County, Taiwan, China Patentee before: JET TECHNOLOGY AND TECHNOLOGY CO., LTD. |
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Effective date of registration: 20210918 Address after: Room 2208, New Technology Plaza, 34 Dayou street, San Po Kong, Kowloon, China Patentee after: Huipu Co.,Ltd. Address before: Room 01, 13 / F, central city, 11 Haisheng Road, Tsuen Wan, New Territories, Hong Kong, China Patentee before: Gemini semiconductor manufacturing (Hong Kong) Co.,Ltd. |