WO2024000516A1 - 为目标信号线分配宽度的方法、布线基板、发光基板及显示装置 - Google Patents

为目标信号线分配宽度的方法、布线基板、发光基板及显示装置 Download PDF

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Publication number
WO2024000516A1
WO2024000516A1 PCT/CN2022/103126 CN2022103126W WO2024000516A1 WO 2024000516 A1 WO2024000516 A1 WO 2024000516A1 CN 2022103126 W CN2022103126 W CN 2022103126W WO 2024000516 A1 WO2024000516 A1 WO 2024000516A1
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WIPO (PCT)
Prior art keywords
target signal
signal line
width
signal lines
fan
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PCT/CN2022/103126
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English (en)
French (fr)
Inventor
罗宁雨
许邹明
吴信涛
王杰
徐佳伟
韩停伟
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/103126 priority Critical patent/WO2024000516A1/zh
Priority to CN202280001961.7A priority patent/CN117897750A/zh
Publication of WO2024000516A1 publication Critical patent/WO2024000516A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a method of allocating widths to target signal lines, a wiring substrate, a light-emitting substrate including the wiring substrate, and a display device.
  • Display devices are generally divided into two categories: liquid crystal display devices and organic light-emitting diode display devices.
  • Liquid crystal display devices are widely used due to their advantages such as thinness, lightness, good shock resistance, wide viewing angle, and high contrast.
  • a liquid crystal display device usually includes a display panel and a backlight source.
  • the backlight source is usually arranged on the non-display side of the display panel to provide a light source for display of the display panel.
  • Characteristics such as contrast, brightness uniformity, and stability of a liquid crystal display device are related to the structure and performance of the backlight.
  • sub-millimeter light-emitting diodes Mini-LEDs
  • Mini-LEDs sub-millimeter light-emitting diodes
  • a method for allocating widths to target signal lines including: numbering at least one target signal line respectively; performing the following steps at least once until the number of target signal lines to be allocated widths in the set is 0: Determine the set of target signal lines whose widths are to be allocated; determine the plane based on the voltage drop V and temperature rise T of each of the target signal lines whose widths are to be allocated, and the conditions met by the width W of the target signal lines whose widths are to be allocated.
  • the voltage drop V is a function V(L, W) of the length L and the width W.
  • the length L refers to the sub-portion of each target signal line located in the fan-out area and extending along the first direction.
  • the length of the direction, the width W refers to the width of the sub-portion of each target signal line located in the fan-out area and extending along the first direction along the second direction, the second direction intersects the first direction; determine the set The number i of the target signal line with the largest voltage drop among the target signal lines to be allocated in width; substitute the known length Li of the target signal line numbered i into V(L, W) to obtain V(L i , W), Wi is obtained based on the intersection point of V(L i , W) and the boundary of the region R.
  • the Wi is a sub-section where the target signal line numbered i is located in the fan-out area and extends along the first direction. a width along the second direction; and removing the target signal line to which the width Wi has been allocated from the set.
  • the number of target signal lines is N, N is a positive integer greater than or equal to 2, the N target signal lines have N widths, and the N target signal lines with the largest voltage drop The width of a target signal line is the maximum value among the N widths.
  • the temperature rise T is a function T(L, W) of the length L and the width W
  • the voltage drop V and temperature of each of the target signal lines based on the width to be allocated are The step of determining the plane region R satisfies the conditions satisfied by T and the width W of the target signal line to be allocated a width, including: based on the voltage drop V(L, W) of each of the target signal lines to be allocated a width being less than the voltage drop threshold, the temperature rise T (L, W) of each of the target signal lines to be allocated with a width is less than the temperature rise threshold, and the sum of the widths W of the target signal lines to be allocated with a width is less than the dynamic width threshold.
  • the planar area R is based on the voltage drop V(L, W) of each of the target signal lines to be allocated a width being less than the voltage drop threshold, the temperature rise T (L, W) of each of the target signal lines to be allocated with a width is less than the temperature rise threshold, and the sum of the widths
  • the step of determining the number i of the target signal line with the largest voltage drop among the target signal lines whose width is to be allocated in the set includes: substituting W 0 into V(L, W) to obtain V (L, W 0 ), W 0 is associated with the dynamic width threshold; substitute the known length of each target signal line whose width is to be allocated in the set into V (L, W 0 ) to obtain different A set of voltage drops; selecting the maximum voltage drop from the set of different voltage drops; and determining the number i of the target signal line with the maximum voltage drop based on the known length corresponding to the maximum voltage drop.
  • R(L, W) R s *L/W
  • Rs is the sheet resistance of the target signal line
  • E k*(k+1)/2*I 0 *R pixel
  • F k*I 0 *R s .
  • the temperature rise T(L, W) of each target signal line satisfies the following formula:
  • T(L, W) [(1/(L*W*X) Y )/(I/C)] 1/Q , where I is the current transmitted by each target signal line, X, Y, C, Q are all constants.
  • a wiring substrate including: a substrate including a fan-out area; at least one target signal line located on the substrate and at least within the fan-out area, the at least A sub-portion of each of the target signal lines located in the fan-out area and extending along the first direction has a length L along the first direction, and each of the at least one target signal lines is located in the fan-out area and extends along the first direction.
  • the sub-section extending in one direction has a width W along a second direction that intersects the first direction, and the width W of each target signal line is determined according to the method described in any of the previous embodiments.
  • the number of target signal lines is N, N is a positive integer greater than or equal to 2, the N target signal lines have N widths, and the N target signal lines with the largest voltage drop The width of a target signal line is the maximum value among the N widths.
  • the wiring substrate further includes bonding electrodes arranged in the fan-out area, and each target signal line is electrically connected to at least two bonding electrodes.
  • the target signal line includes at least one of a driving voltage signal line, a common voltage signal line, and a power supply voltage signal line.
  • a light-emitting substrate includes: the wiring substrate described in any of the previous embodiments, the substrate further includes a functional area, and the functional area includes a plurality of array-arranged Partitions; a plurality of light-emitting elements arranged in the plurality of partitions in the functional area; and a circuit board arranged in the fan-out area.
  • the plurality of partitions are arranged into multiple rows and columns, the number of target signal lines is N, N is a positive integer greater than or equal to 2, and the N target signal lines are also along the second The direction is arranged in the functional area, and the N target signal lines are located in the same column partition or in adjacent M column partitions, where M is a positive integer greater than or equal to 2.
  • the circuit board includes a chip-on-chip film, and the N target signal lines are electrically connected to the same circuit board via bonding electrodes.
  • each of the plurality of light emitting elements includes a sub-millimeter light emitting diode.
  • a display device which includes the wiring substrate described in any of the previous embodiments or the light-emitting substrate described in any of the previous embodiments.
  • Figure 1 shows the arrangement of signal lines in the fan-out area in the related art
  • FIG. 2 shows a flowchart of a method for allocating widths to target signal lines according to an embodiment of the present disclosure
  • Figure 3 shows the arrangement of target signal lines in the fan-out area according to an embodiment of the present disclosure
  • FIG. 4 shows a partial plan view of a wiring substrate according to an embodiment of the present disclosure
  • FIG. 5 shows a partial plan view of a wiring substrate according to another embodiment of the present disclosure.
  • FIG. 6 shows a partial plan view of a light emitting substrate according to an embodiment of the present disclosure.
  • FIG. 7 shows a block diagram of a display device according to an embodiment of the present disclosure.
  • a plurality of signal lines are usually arranged on the wiring substrate to transmit signals, such as electrical signals. Since each signal line has resistance, when an electrical signal is passed in the signal line, a voltage drop occurs between the two ends of the signal line. In order to ensure that the voltage drop between the two ends of the signal line does not exceed the safety threshold, there are usually certain requirements for the resistance of the resistor of the signal line. In the related art, in order to reduce the resistance of signal lines, there must be a certain width of space between adjacent signal lines due to limitations in the size of the wiring substrate and to avoid signal crosstalk due to too close distance between adjacent signal lines. Therefore, there is an upper limit to the line width size of each signal line.
  • the wiring substrate includes a functional area and a fan-out area.
  • the functional area includes multiple partitions arranged in the array.
  • the fan-out area can be arranged with structures such as bonding electrodes and circuit boards. Each signal line receives the circuit board through the bonding electrode in the fan-out area. Provide electrical signals and extend to functional areas to transmit corresponding electrical signals to each partition.
  • the fan-out area of the wiring substrate usually has a smaller size along the extension direction of the signal line, and multiple signal lines are collected in the fan-out area.
  • the part of the signal line located in the fan-out area is better than the part of the signal line located in the functional area, such as
  • Dimensional parameters related to voltage drop such as line width and line length, are more restrictive, which often results in the thickness of the conductive layer having to be increased.
  • a thickened conductive layer places more stringent requirements on the process, which often results in a decrease in product yield and increases production costs.
  • FIG. 1 shows a schematic diagram of the layout of signal lines in the fan-out area of the wiring substrate 10 in the related art.
  • the fan-out area includes multiple signal lines, such as signal lines 11 , signal lines 12 , and signal lines 13 .
  • the size of the portion of the signal line 11 along the first direction D1 is S1
  • the size along the second direction D2 is G1.
  • the second direction D2 intersects the first direction D1; the signal line 12
  • the size of the portion of the signal line 13 along the first direction D1 along the first direction D1 is S2, and the size along the second direction D2 is G2; the size of the portion of the signal line 13 along the first direction D1 along the first direction D1 is S3, and the size along the second direction D2 is G2.
  • the size of the second direction D2 is G3. Sizes S1 and S2 are much smaller than size S3, but sizes G1, G2, and G3 are basically the same.
  • FIG. 2 shows a flow chart of the method 100.
  • the method 100 includes:
  • Step S101 Number at least one target signal line respectively;
  • Step S102 Execute steps S103-S107 at least once until the number of target signal lines whose widths are to be allocated in the set is 0;
  • Step S103 Determine the set of target signal lines whose widths are to be allocated
  • Step S104 Determine the planar area R based on the voltage drop V and temperature rise T of each of the target signal lines to be allocated with a width and the conditions satisfied by the width W of the target signal line to be allocated with a width.
  • the voltage drop V is the length L and The function V(L, W) of the width W.
  • the length L refers to the length of the sub-portion of each target signal line located in the fan-out area and extending along the first direction along the first direction.
  • the width W refers to the length of each target signal line in the fan-out area. The width of the sub-portion of the fan-out area located in the fan-out area and extending along the first direction along a second direction, the second direction intersecting the first direction;
  • Step S105 Determine the number i of the target signal line with the largest voltage drop among the target signal lines whose width is to be allocated in the set;
  • Step S106 Substitute the known length Li of the target signal line numbered i into V(L, W) to obtain V(L i , W), based on the boundary between V(L i , W) and the plane area R Wi is obtained at the intersection of
  • Step S107 Remove the target signal line to which the width Wi has been allocated from the set.
  • the term “voltage drop” refers to the voltage or potential difference. When the current flows through the target signal line, a certain voltage drop will be generated in each section of the target signal line. The voltage drop represents the charge transferred by the signal line. The potential difference caused by moving one end of a certain section to the other end.
  • temperature rise refers to the increase in temperature of the target signal line when operating at a non-zero fixed electrical power for a period of time compared to the temperature at zero electrical power.
  • fan-out area refers to the area used to connect signal lines to the circuit board.
  • the fan-out area is usually arranged with signal lines, bonding electrodes, circuit boards and other structures.
  • the signal lines are located in the fan-out area.
  • the part of the outgoing area is connected to the circuit board through bonding electrodes, thereby receiving signals from the circuit board.
  • planar region R is a two-dimensional planar region defined by L and W.
  • the planar region R can be understood as a mathematical set composed of L and W.
  • each step S101-S107 the width can be allocated to the sub-section of the target signal line with the maximum voltage drop in the set that is located in the fan-out area and extends along the first direction, until A width is allocated to a sub-portion of each target signal line in the set that is located in the fan-out area and extends along the first direction.
  • the sub-sections of each signal line located in the fan-out area and extending along the first direction have different lengths but have substantially the same line width.
  • each The allocated width of the sub-portion of the target signal line located in the fan-out area and extending along the first direction is related to the length, voltage drop, temperature rise, etc.
  • the method 100 dynamically allocates width to each target signal line, so that the voltage drop of all target signal lines, especially the maximum voltage drop, is less than the voltage drop threshold, and the voltage drop of all target signal lines is less than the wiring substrate 10 The voltage drop of the signal line 13 can thereby increase the overall voltage drop level of the wiring substrate.
  • Figure 3 shows a schematic diagram of the layout of a portion of signal lines in the fan-out area of the wiring substrate 200 according to an embodiment of the present disclosure
  • Figure 4 shows a partial plan view of the wiring substrate 200. Each step of the method 100 is described in detail below with reference to FIGS. 2 to 4 .
  • Step S101 Number at least one target signal line respectively.
  • a plurality of signal lines are usually arranged. Among these multiple signal lines, some of the signal lines have low resistance requirements for signal lines due to transmitting digital signals.
  • the size design of such signal lines in the fan-out area is not within the scope of the discussion of the embodiments of the present disclosure, that is, "Non-target signal lines"; while another part of the multiple signal lines transmits electrical signals with constant amplitude, such as constant voltage signals or constant current signals, and the design of their size parameters has an impact on the overall voltage drop of the wiring substrate 200
  • the level has a significant impact, and the width of this part of the signal line in the fan-out area is within the discussion scope of the embodiments of the present disclosure.
  • This part of the signal line is the "target signal line” in this article.
  • the target signal line refers to a signal line that transmits an electrical signal of constant amplitude and includes a plurality of sequentially connected sub-sections in the fan-out area, wherein only one sub-section among the multiple sub-sections of the target signal line is along the first One direction D1 extends, and at most two of the plurality of sub-sections extend along the second direction D2.
  • One end of one of the sub-sections extending along the second direction D2 is connected with one end of the sub-section along the first direction D1 to form an integrated structure. , the other end is connected to at least one binding electrode in the binding area.
  • the signal line 103 transmits a constant amplitude voltage signal, and includes three sequentially connected sub-sections 1031 , 1032 , 1033 in the fan-out area. Only one sub-section 1032 extends along the first direction D1, and two sub-sections 1031 and 1033 among the three sub-sections 1031, 1032, 1033 extend along the second direction D2. The sub-sections 1031 and 1033 are respectively connected with two parts of the sub-section 1032. form an integrated structure. Therefore, the signal line 103 is a target signal line, and similarly, the signal lines 101 and 102 are also target signal lines. In addition, it should be noted that within the fan-out area, signal lines that only have sub-portions extending along the second direction D2 are non-target signal lines.
  • a signal line or a sub-portion of a signal line extends in a certain direction means that a signal line or a sub-portion of a signal line is in a roughly strip-like structure, and the extension direction of the longer side of the strip-like structure is parallel to this direction.
  • the extension direction of the signal line or the sub-portion of the signal line can be considered to be parallel to the extension direction of the side with the maximum length in the strip structure.
  • the signal line 201 has a roughly strip-like structure in the sub-portion 2011 located in the fan-out area and extending along the first direction.
  • the side 202 with the largest length in the strip-like structure only extends along The second direction D2 extends. Therefore, the sub-section 2011 of the signal line 201 located in the fan-out area and extending along the first direction can be considered as extending only along the second direction D2. Therefore, the signal line 201 is not the target signal line referred to herein, but is a non-target signal line.
  • FIG. 3 shows eight signal lines, which include target signal lines 101, target signal lines 102, target signal lines 103, and other non-target signal lines. These eight signal lines are electrically connected to the same circuit board 106 (such as chip-on-chip film) in the bonding area.
  • the circuit board 106 includes multiple gold finger structures. The gold finger structures are connected to multiple bonding electrodes in the bonding area one by one. corresponding and electrically connected. As shown in FIG. 3 , taking the center line of the circuit board 106 parallel to the second direction D2 as the reference line, all target signal lines (including the target signal lines 101 , 102 , and 103 ) located on the first side of the reference line are on the reference line.
  • the first side of the reference line is electrically connected to the circuit board 106, and all the signal lines located on the second side of the reference line are electrically connected to the circuit board 106 on the second side of the reference line.
  • all the signal lines located on the second side of the reference line are electrically connected to the circuit board 106 on the second side of the reference line.
  • the orthographic projections of the multiple target signal lines located on one side of the reference line overlap with each other on a plane parallel to the first direction D1
  • the multiple target signal lines located on one side of the reference line overlap with each other.
  • the intervals are set so that the width of the fan-out area along the second direction D2 is positively related to the sum of the widths of the target signal lines on either side of the reference line.
  • the set of target signal lines targeted by the method 100 refers to the set of target signal lines located on one side of the reference line.
  • the set of target signal lines is the set of target signal lines 101 , 102 , and 103 located on the first side of the reference line.
  • the three target signal lines 101, 102, and 103 are numbered respectively.
  • the number of the target signal line 101 may be 1
  • the number of the target signal line 102 may be 2
  • the number of the target signal line 103 may be 3.
  • the target signal lines 101 and 103 may be a driving voltage signal line VLED configured to transmit the first constant voltage signal; the target signal line 102 may be a common voltage signal line GND.
  • the signal line GND is configured to transmit the second constant voltage signal.
  • Step S102 Perform steps S103-S107 at least once until the number of target signal lines whose widths are to be allocated in the set is 0.
  • steps S103-S107 are performed is equal to the number of target signal lines.
  • the number of target signal lines is 3. Therefore, steps S103 - S107 are performed three times, so that the number of target signal lines whose widths are to be allocated in the final set is 0.
  • steps S103 - S107 are performed three times, so that the number of target signal lines whose widths are to be allocated in the final set is 0.
  • the term "width to be allocated” refers to the line width of the sub-portion of the target signal line located in the fan-out area and extending along the first direction D1.
  • the width to be allocated of the target signal line 103 refers to the line width of the sub-portion 1032 of the target signal line 103 that is located in the fan-out area and extends along the first direction D1.
  • Step S103 Determine a set of target signal lines whose widths are to be allocated.
  • the set of target signal lines whose widths are to be allocated is a set composed of target signal lines 101 , target signal lines 102 , and target signal lines 103 .
  • Step S104 Determine the planar area R based on the voltage drop V and temperature rise T of each of the target signal lines to be allocated with a width and the conditions satisfied by the width W of the target signal line to be allocated with a width.
  • the voltage drop V is the length L and Function V(L, W) of width W.
  • the length L refers to the length of each target signal line in the sub-section of the fan-out area along the first direction D1.
  • the width W refers to the length of each target signal line in the sub-section of the fan-out area.
  • the target signal line 101 has a length L 1 along a first direction D1 in a sub-portion of the fan-out area and a width to be allocated W 1 along a second direction D2 that intersects the first direction D1 , for example, the second direction D2 Perpendicular to the first direction D1;
  • the sub-portion of the target signal line 102 located in the fan-out area and extending along the first direction has a length L2 along the first direction D1 and a width to be allocated W2 along the second direction D2;
  • the target signal The sub-portion of the line 103 located in the fan-out area and extending along the first direction has a length L 3 along the first direction D1 and a width to be distributed W 3 along the second direction D2.
  • the lengths L 1 , L 2 , and L 3 are known, and the widths W 1 , W 2 , and W 3 are unknown and are to be allocated.
  • the lengths L 1 , L 2 , and L 3 may have various appropriate values, and the embodiments of the present disclosure do not specifically limit this.
  • the length L 1 of the target signal line 101 is approximately 12882 um
  • the length L 2 of the target signal line 102 is approximately 13010 um
  • the length L 3 of the target signal line 103 is approximately 23380 um.
  • the maximum length in direction D1 the sub-section of the target signal line located in the fan-out area and extending along the first direction D1 is directly connected to the sub-section of the target signal line closest to the binding area and extending along the second direction D2, where, The sub-portion of the target signal line closest to the bonding area and extending along the second direction D2 is in direct contact with and electrically connected to the corresponding at least one bonding electrode 104.
  • the bonding electrode 104 extends along the second direction D2. Specifically, taking the target signal line 103 in FIG.
  • the length L 3 of the sub-portion of the target signal line 103 located in the fan-out area and extending along the first direction in the first direction D1 refers to the length L 3 of the target signal line 103 located in the fan-out area and extending along the first direction.
  • the voltage drop V is a function of length L and width W V(L, W)
  • the temperature rise T is also a function of length L and width W T(L, W).
  • the step of determining the planar area R based on the voltage drop V and the temperature rise T of each of the target signal lines to be allocated a width and the conditions satisfied by the width W of the target signal line to be allocated a width may include the following: Sub-step: Based on the fact that the voltage drop V(L, W) of each of the target signal lines 101, 102, 103 is less than the voltage drop threshold V limit , the temperature rise T(L) of each of the target signal lines 101, 102, 103 , W) is less than the temperature rise threshold T limit , and the sum of the widths W of the target signal lines 101, 102, and 103 is less than the dynamic width threshold W allow1 to determine the plane region R.
  • the plane area R determined by this set of inequalities is a two-dimensional plane area defined by L and W.
  • the two-dimensional plane area is an area delineated by L within a certain numerical range and W within a certain numerical range.
  • the values of i are 1, 2, and 3
  • the values of j are 1, 2, and 3.
  • Ti(L i , Wi ) represents the temperature rise of the target signal line numbered i.
  • T 1 (L 1 , W 1 ) represents the temperature rise of the target signal line numbered 1 (i.e., the target signal line 101), and T 2 (L 2 , W 2 ) represents the target signal line numbered 2 (i.e., the target signal line 101).
  • the temperature rise of the signal line 102), T 3 (L 3 , W 3 ) represents the temperature rise of the target signal line numbered 3 (that is, the target signal line 103).
  • V 1 (L 1 , W 1 ) represents the voltage drop of the target signal line numbered 1 (ie, the target signal line 101), and V 2 (L 2 , W 2 ) represents the target signal line numbered 2 (ie, the target signal line 101).
  • the voltage drop of the target signal line 102), V 3 (L 3 , W 3 ) represents the voltage drop of the target signal line numbered 3 (that is, the target signal line 103).
  • Temperature rise T (L, W) involves many electrical and thermal parameters, and its physical model is relatively complex.
  • the temperature rise threshold T limit represents the upper limit of the allowable temperature rise. Its value is related to factors such as structural thermal expansion and product specification requirements. The value may be different in different projects.
  • the temperature rise threshold T limit usually ranges from 10 to 20°C. In some embodiments, T limit is equal to 15°C.
  • the wiring substrate 200 also includes a functional area.
  • the functional area includes a plurality of partitions arranged in an array.
  • the multiple partitions are arranged in a manner of multiple rows and columns.
  • Each partition may be arranged with a light-emitting element and a light-emitting element related to the light-emitting element.
  • Each of the target signal lines 101, 102, and 103 is arranged in the functional area and the fan-out area.
  • R pixel represents the resistance of the section of each target signal line corresponding to a single partition, k is the number of rows of the partition, I 0 is the current flowing through a single partition during operation, and R s is the square of each target signal line. Resistance, which is the actual measured value.
  • the wiring substrate 200 includes k rows of partitions, and the portion of each target signal line located in the functional area extends from the 1st row partition to the k-th row partition along the second direction D2. Therefore, the portion of each target signal line located in the functional area
  • a single partition can be divided into k sections according to the size of a single partition along the second direction D2.
  • the section corresponding to the first row of partitions is the first section, and the section corresponding to the k-th row of partitions is the k-th section. part.
  • the current carried on each segment is I 0 and the segments are connected in parallel with each other. Therefore, I j represents the sum of currents transmitted on the first j segments of each target signal line.
  • R pixel , k, I 0 , and R s can all be regarded as constants.
  • the voltage drop threshold V limit represents the upper limit of the allowable voltage drop. Its size is related to the amplitude of the signal transmitted by the target signal line and its purpose. Different target signal lines may have different V limit .
  • the V limit of the driving voltage signal line VLED and the common voltage signal line GND is usually about 0.5mV. In some embodiments, V limit is equal to 0.45mV.
  • the dynamic width threshold W allow1 represents the threshold value of the sum of the total widths that can be allocated to the three target signal lines 101, 102, and 103. This threshold value needs to be greater than W 1 + W 2 + W 3 .
  • the value of W allow1 is related to factors such as the frame size of the wiring substrate 200, the distance between the light-emitting element and the fan-out area, and the minimum distance between each target signal line.
  • W allow1 H-H1-H2-(H3+H4+H5)-H6, where H represents the light-emitting element closest to the binding area in the last row (i.e., k-th row) partition of the wiring substrate 200
  • H1 represents the length of the binding electrode 104 along the second direction D2
  • H2 represents the distance between the first end of the binding electrode 104 close to the side 1051 and the side 1051
  • the distance of The distance, H4 represents the distance between the sub-portion of the target signal line 102 located in the fan-out area and extending along the first direction D1 and the sub-portion of the adjacent target signal line 103 located in the fan-out area and extending along the first direction D1.
  • H5 represents the distance between the sub-portion of the target signal line 103 located in the fan-out area and extending along the first direction D1 and the second end of the bonding electrode 104 opposite to the first end
  • H6 represents the kth end of the wiring substrate 200 The distance between the center of the light emitting element 305 in the row partition and the boundary of the fan-out area.
  • W allow1 can be flexibly changed according to product design requirements, and the embodiments of the present disclosure do not specifically limit this. In one example, W allow1 equals 2.8mm.
  • Step S105 Determine the number i of the target signal line with the largest voltage drop among the target signal lines whose width is to be allocated in the set.
  • this step S105 may include the following sub-steps:
  • W 0 is associated with the dynamic width threshold W allow1 .
  • W 0 can be reasonably set according to the amplitude of the signal transmitted by the target signal line whose width needs to be allocated and its use.
  • W 0 W allow1 /N
  • W 0 W allow1 /N
  • V(L, W 0 ) k*(k+1)/2*I 0 *R pixel +k*I 0 *R s *L*3/W allow1 .
  • the length L 2 of the target signal line 103 along the first direction D1 and the length L 3 of the sub-portion of the target signal line 103 located in the fan-out area and extending along the first direction D1 along the first direction D1 are both known, L 1 , L 2 ,
  • the value of L 3 can be determined according to the amplitude of the signal transmitted by the target signal line and its use, as well as the design requirements of the product. In this embodiment, L 1 is approximately 12882um, L 2 is approximately 13010um, and L 3 is approximately 23380um. Substituting the values of L 1 , L 2 and L 3 into V(L, W 0 ) respectively, we can get
  • V 1 (L 1 , W 0 ) k*(k+1)/2*I 0 *R pixel +k*I 0 *R s *12882*3/W allow1 ,
  • V 2 (L 2 , W 0 ) k*(k+1)/2*I 0 *R pixel +k*I 0 *R s *13010*3/W allow1 ,
  • V 3 (L 3 , W 0 ) k*(k+1)/2*I 0 *R pixel +k*I 0 *R s *23380*3/W allow1 .
  • the set includes three different voltage drops, namely V 1 (L 1 , W 0 ), V 2 (L 2 , W 0 ), and V 3 (L 3 , W 0 ).
  • V 3 (L 3 , W 0 ) has the largest voltage drop.
  • the known length corresponding to V 3 (L 3 , W 0 ) is L 3 . Since each target signal line has been assigned a number in advance in step S101, and each target signal line with a corresponding number is in the fan-out area. The length of the part is known, so it can be known from the known length L 3 that the corresponding target signal line is numbered 3, that is, the target signal line with the largest voltage drop is the target signal line 103 numbered 3.
  • Step S107 Remove the target signal line 103 to which the width W 3 has been allocated from the set.
  • the width W 3 can be dynamically allocated to the target signal line 103 with the largest voltage drop among the three target signal lines, so that the allocated width W 3 is equal to 1036 ⁇ m.
  • Step S103 Determine a set of target signal lines whose widths are to be allocated. Since the target signal line 103 with the allocated width W 3 has been removed from the set when step S107 is performed for the first time, in step S103 this time, the updated set is the target signal line 101 and the target signal line 102 .
  • the horizontal and vertical coordinate values (L and W) corresponding to the boundary of the updated plane area R' determined in step S104 this time are compared with the horizontal and vertical coordinate values corresponding to the boundary of the plane area R determined in step S104 last time.
  • the ordinate value has also changed.
  • Step S105 Determine the number i of the target signal line with the largest voltage drop among the target signal line 101 and the target signal line 102.
  • this step S105 may include the following sub-steps:
  • V 1 (L 1 , W 0 ′) k*(k+1)/2*I 0 *R pixel +k*I 0 *R s *12882*2/W allow2 ,
  • V 2 (L 2 , W 0 ′) k*(k+1)/2*I 0 *R pixel +k*I 0 *R s *13010*2/W allow2 . That is, the set includes two different voltage drops, namely V 1 (L 1 , W 0 ′) and V 2 (L 2 , W 0 ′).
  • V 1 (L 1 , W 0 ′) and V 2 (L 2 , W 0 ′) By comparing V 1 (L 1 , W 0 ′) and V 2 (L 2 , W 0 ′), it can be known that V 2 (L 2 , W 0 ′) has the largest voltage drop among the two.
  • Step S106 Substitute the known length L 2 of the target signal line 102 numbered 2 into V (L, W) to obtain V 2 (L 2 , W), that is
  • V 2 (L 2 , W) k*(k+1)/2*I 0 *R pixel +k*I 0 *R s *13010/W, based on V 2 (L 2 , W) and the updated
  • W 2 is the width of the sub-portion of the target signal line 102 numbered 2 that is located in the fan-out area and extends along the first direction along the second direction D2.
  • W equals 710 ⁇ m.
  • Step S107 Remove the target signal line 102 to which the width W 2 has been allocated from the set.
  • the width W 2 can be dynamically allocated to the target signal line 102 with the largest voltage drop among the remaining two target signal lines 101 and 102 in the set, so that the allocated width W 2 is equal to 710 ⁇ m.
  • Step S103 Determine a set of target signal lines whose widths are to be allocated. Since the target signal line 102 to which the width W 2 has been allocated has been removed from the set when step S107 is performed for the second time, in step S103 this time, the updated set only includes the target signal line 101 .
  • the abscissa and ordinate values (L and W) corresponding to the boundary of the updated plane area R′′ determined in step S104 this time have also changed.
  • the abscissa and ordinate values corresponding to the boundary have also changed.
  • the dynamic width threshold is a dynamic value associated with the number of executions of method 100 (or the number of target signal lines), rather than a constant.
  • W allow2 W allow1 - W 1 .
  • W allow3 W allow1 -W 1 -W 2 , and so on, Where n is a positive integer greater than or equal to 1 and less than or equal to N, N is the number of target signal lines, and W allown represents the dynamic width threshold selected when step S104 is executed for the nth time.
  • Step S105 Determine the number i of the target signal line 101.
  • this step S105 may include the following sub-steps:
  • Step S107 Remove the target signal line 101 to which the width W 1 has been allocated from the set.
  • the width W 1 can be dynamically allocated to the remaining target signal lines 101 in the set, so that the allocated width W 1 is equal to 710 ⁇ m.
  • the width G1 of the portion of the signal line 11 in the fan-out area in the second direction D2 is equal to 810 ⁇ m
  • the width G2 of the portion of the signal line 12 in the fan-out area in the second direction D2 is equal to 810 ⁇ m
  • the width G3 of the portion of the signal line 13 in the fan-out area in the second direction D2 is equal to 836um
  • G1, G2, and G3 are substantially equal
  • G1+G2+G3 2456um.
  • the voltage drop of the signal line 13 is much larger than the voltage drop of the signal line 11 and the signal line 12 and has exceeded the voltage drop threshold V limit .
  • the overall voltage drop level of the wiring substrate 10 is limited by the voltage drop of the signal line 13 .
  • the method 100 provided by the embodiment of the present disclosure dynamically allocates widths to the three target signal lines 101, 102, and 103 respectively, so that the sub-section of the target signal line 103 with the largest voltage drop is located in the fan-out area and extends along the first direction.
  • the width W 3 of the portion in the second direction D2 is equal to 1036 ⁇ m
  • the width W 2 of the sub-portion of the target signal line 102 with the intermediate voltage drop located in the fan-out area and extending along the first direction in the second direction D2 is equal to 710 ⁇ m
  • the width W 3 of the sub-portion of the target signal line 101 with the minimum voltage drop located in the fan-out area and extending along the first direction in the second direction D2 is equal to 710 ⁇ m
  • W 1 + W 2 + W 3 2456 ⁇ m
  • the sum of G1+G2+G3 in is the same.
  • the three target signal lines 101, 102, and 103 are located in the fan-out area and along the first
  • the widths of the directionally extending subsections have differentiated values according to their respective lengths and voltage drops, and the three no longer have a uniform width.
  • the width W3 of the target signal line 103 with the maximum voltage drop is significantly increased.
  • the voltage drop of the target signal line 103 is significantly reduced and is lower than Voltage drop threshold V limit .
  • the voltage drop of the target signal line 101 and the target signal line 102 is slightly increased due to the slight increase in the width of the fan-out area, due to the overall voltage of the wiring substrate 200
  • the voltage drop level is limited by the maximum voltage drop, and the voltage drop value of the target signal line 103 with the maximum voltage drop is lower than the voltage drop value of the signal line 13 in the related art and lower than the voltage drop threshold V limit , so the wiring substrate 200
  • the overall voltage drop level actually achieves a significant improvement.
  • the line width of the sub-portion of the target signal line in the fan-out area extending along the first direction D1 is the same as the line width of the sub-portion of the target signal line located in the fan-out area and extending along the second direction D2 and closest to the functional area.
  • the distance of the reference line is positively related.
  • among the plurality of target signal lines located on the same side of the reference line there are at least two target signal lines, wherein the first target signal line of the at least two target signal lines is located in the functional area and the sector.
  • the distance between the junction of the outgoing area and the reference line is greater than the distance between the second target signal line and the reference line at the junction of the functional area and the fan-out area of at least two target signal lines, while the first target signal line
  • the line width of the sub-portion extending along the first direction D1 in the fan-out area is at least 1.5 times, for example, 1.8 times, the line width of the sub-portion of the second target signal line extending along the first direction D1 in the fan-out area. 2x, 3x, 3.5x etc.
  • the distance between the target signal line 103 at the junction of the functional area and the fan-out area and the reference line is greater than the distance between the target signal line 102 at the junction of the functional area and the fan-out area.
  • the distance of the reference line, the line width W 3 of the sub-portion of the target signal line 103 extending along the first direction D1 in the fan-out area is equal to 1036 ⁇ m
  • the line width of the sub-portion of the target signal line 102 extending along the first direction D1 in the fan-out area W 2 is equal to 710 ⁇ m
  • W 3 is about 1.5 times larger than W 2 .
  • Figures 3 and 4 take the number N of target signal lines equal to 3 as an example to describe the steps of the method 100.
  • the number N of target signal lines can be any appropriate value. In this regard, embodiments of the present disclosure No specific restrictions are made.
  • FIG. 5 shows a partial plan view of the wiring substrate 300, which shows a plurality of target signal lines that transmit electrical signals to four column partitions respectively. Multiple target signal lines are connected to the same circuit board 106 in a bonding area, and a plurality of bonding electrodes arranged at intervals are provided in the bonding area.
  • FIG. 5 shows a four-column partition of the wiring substrate 300. If such a four-column partition is used as a repeating unit, in some embodiments, the wiring substrate 300 includes a plurality of such repeating units. As shown in FIG. 5 , the center line of the circuit board 106 parallel to the second direction D2 is used as a reference line.
  • the C-th column partition and the C+1-th column partition are arranged on the first side of the reference line.
  • the second side of the reference line There are column C+2 partitions and column C+3 partitions arranged.
  • the signal line located on the first side of the reference line is electrically connected to the circuit board 106 on the first side of the reference line
  • the signal line located on the second side of the reference line is electrically connected to the circuit board 106 on the second side of the reference line. Since the width of the fan-out area along the second direction D2 is positively related to the sum of the widths of the target signal lines on either side of the reference line, the set of target signal lines targeted by the method 100 refers to the set of target signal lines located on one side of the reference line. A collection of target signal lines.
  • the set of target signal lines is the set of target signal lines 301 , 302 , 303 , and 304 located on the first side of the reference line.
  • the signal line 305 and 306 are connected to the circuit board 106 in an almost straight line, that is, the signal lines 305 and 306 have almost no sub-section extending along the first direction D1 in the fan-out area.
  • the signal line 305 and the signal line 306 are non-target signal lines.
  • the signal lines 301-304 all include sequentially connected sub-sections extending along the first direction D1 and a sub-section extending along the second direction D2 in the fan-out area, and the signal lines 301-304 all transmit electrical signals of constant amplitude. Therefore, signal lines 301-304 are target signal lines.
  • the target signal lines 301, 302, and 303 are arranged in the C-th column partition, and the target signal line 304 is arranged in the C+1-th column partition. That is, four target signal lines are arranged on the first side of the reference line.
  • the four target signal lines 301, 302, 303, and 304 are numbered respectively.
  • the number of the target signal line 301 can be 1, the number of the target signal line 302 can be 2, the number of the target signal line 303 can be 3, and the number of the target signal line 303 can be 3.
  • the number of line 304 may be 4.
  • the target signal lines 301 and 304 may be driving voltage signal lines VLED, the target signal line 301 is configured to provide a first constant voltage to the light-emitting unit 601 in the C-th column partition, and the target signal line 304 is configured to provide a first constant voltage to the light-emitting unit 601 in the C-th column partition.
  • the light-emitting unit 601 in the C+1 column partition provides a third constant voltage;
  • the target signal line 302 may be a power supply voltage signal line Pwr, and the target signal line 302 is electrically connected to the power terminal of the driving circuit (not shown) in the C-th column partition.
  • Connection; the target signal line 303 may be a common voltage signal line GND, and the target signal line 303 is configured to provide a second constant voltage (eg, ground voltage) to the driving circuit in the C-th column partition.
  • the method 100 is also applicable to allocating widths to the target signal lines shown in Figure 5.
  • the following steps can be used to allocate widths to the target signal lines 301-304 respectively:
  • Step S101 Number the four target signal lines 301-304 as 1-4 respectively;
  • Step S102 Execute steps S103-S107 four times until the number of target signal lines whose widths are to be allocated in the set is 0;
  • Step S103 Determine the set of target signal lines whose widths are to be allocated
  • Step S104 Determine the planar area R based on the voltage drop V and temperature rise T of each of the target signal lines to be allocated with a width and the conditions satisfied by the width W of the target signal line to be allocated with a width.
  • the voltage drop V is the length L and Function V(L, W) of width W.
  • the length L refers to the length of each target signal line in the sub-section of the fan-out area along the first direction D1.
  • the width W refers to the length of each target signal line in the sub-section of the fan-out area.
  • Step S105 Determine the number i of the target signal line with the largest voltage drop among the target signal lines whose width is to be allocated in the set;
  • Step S106 Substitute the known length Li of the target signal line numbered i into V(L, W) to obtain V(L i , W), based on the boundary between V(L i , W) and the plane area R Wi is obtained at the intersection of
  • Step S107 Remove the target signal line to which the width Wi has been allocated from the set.
  • the initial dynamic width threshold W allow1 corresponding to the embodiment of Figure 5 is equal to 3.4 mm.
  • the sub-portion of the target signal line 301 located in the fan-out area and extending along the first direction has a known length L4 along the first direction D1, which is 20100 ⁇ m; the sub-portion of the target signal line 302 located in the fan-out area and The sub-portion extending along the first direction has a known length L 5 along the first direction D1, which is 9730 ⁇ m; the sub-portion of the target signal line 303 located in the fan-out area and extending along the first direction has a known length L 5 along the first direction D1.
  • the length L 6 is known to be 11840 ⁇ m; the sub-portion of the target signal line 304 located in the fan-out area and extending along the first direction has a known length L 7 along the first direction D1 to be 9720 ⁇ m.
  • the sub-portions of the target signal lines 301-304 located in the fan-out area and extending along the first direction are allocated widths respectively, so that the sub-portions of the target signal line 301 located in the fan-out area and extending along the first direction are in the first direction.
  • the width W 4 in the two directions D2 is equal to 996 ⁇ m.
  • the width W 5 of the sub-portion of the target signal line 302 located in the fan-out area and extending along the first direction in the second direction D2 is equal to 200 ⁇ m.
  • the width W 5 of the target signal line 303 is located in the fan-out area.
  • the width W 6 of the sub-portion in the fan-out area and extending along the first direction in the second direction D2 is equal to 776 ⁇ m, and the width of the sub-portion of the target signal line 304 located in the fan-out area and extending along the first direction in the second direction D2 W 7 is equal to 690 ⁇ m.
  • the target signal line 301 has the largest voltage drop, so its allocated width W4 is the maximum value among W1 - W4 .
  • the four target signal lines 301, 302, 303, and 304 are located in the fan-out area without occupying more width of the fan-out area, causing the frame to become wider or increasing the thickness of the target signal lines.
  • the widths of the sub-sections extending along the first direction have differentiated values depending on their respective lengths and voltage drops, instead of having a uniform width.
  • the width W 4 of the target signal line 301 with the maximum voltage drop is significantly increased, so that the voltage drop of the target signal line 301 is significantly reduced and is lower than the voltage drop threshold V limit , so that the wiring
  • the overall voltage drop level of the substrate 300 is significantly improved.
  • the wiring substrate includes: a substrate 105 including a fan-out area; at least one target signal line located on the substrate 105 and at least In the fan-out area, the sub-portion of each of the at least one target signal line located in the fan-out area and extending along the first direction has a length L along the first direction D1, and the sub-portion of each of the at least one target signal line located in the fan-out area is The sub-section that exits the area and extends along the first direction has a width W along the second direction D2, the second direction D2 intersects the first direction D1, and the width W of each target signal line is according to the method 100 described in any previous embodiment. to make sure.
  • a plurality of signal lines are usually arranged. Among these multiple signal lines, some of them transmit digital signals and have low resistance requirements for signal lines.
  • the size design of such signal lines in the fan-out area is not within the scope of the embodiments of the present disclosure, that is, "Non-target signal lines"; while another part of the multiple signal lines transmits electrical signals with constant amplitude, such as constant voltage signals or constant current signals, and the design of their size parameters has an impact on the overall voltage drop of the wiring substrate 200
  • the level has a significant impact, and the width of this part of the signal line in the fan-out area is within the discussion scope of the embodiments of the present disclosure.
  • This part of the signal line is the "target signal line” in this article.
  • the target signal line includes a driving voltage signal line VLED and a common voltage signal line GND.
  • the target signal lines 101 and 103 may be the driving voltage signal line VLED.
  • the target signal line 102 may be the common voltage signal line GND.
  • the target signal lines 101 and 102 may be located in the same column partition, and the target signal line 103 may be located in the partition of an adjacent column.
  • the target signal lines include a driving voltage signal line VLED, a power supply voltage signal line PWR, and a common voltage signal line GND.
  • the target signal line 301 can be the driving voltage signal line VLED
  • the target signal line 302 can be the power voltage signal line PWR
  • the target signal line 303 can be the common voltage signal line GND
  • the target signal lines 301, 302, and 303 are located in column C. within the partition.
  • the target signal line 304 may be a driving voltage signal line VLED
  • the target signal line 304 is located in the C+1th column partition.
  • the target signal line 301 is configured to provide a first constant voltage to the light-emitting unit 601 in the C-th column partition
  • the target signal line 304 is configured to provide a first constant voltage to the light-emitting unit 601 in the C+1-th column partition
  • the target signal line 302 Connected to the power terminal of the driving circuit (not shown) in the C-th column partition
  • the target signal line 303 is configured to provide a second constant voltage (eg, ground voltage) to the driving circuit in the C-th column partition.
  • the wiring substrate further includes bonding electrodes 104 arranged in the fan-out area, and the portion of each target signal line located in the fan-out area is electrically connected to at least two bonding electrodes 104 .
  • the number of target signal lines is N, N is a positive integer greater than or equal to 2, and the sub-portion of the fan-out area of the N target signal lines extending along the first direction D1 has N line widths.
  • the largest line width among the N line widths corresponds to the target signal line with the largest voltage drop among the N target signal lines. Since the overall voltage drop level of the wiring substrate is limited by the maximum voltage drop, by making the target signal line with the largest voltage drop have the largest line width in the fan-out area, the voltage drop of the target signal line can be significantly reduced, making the target signal line The voltage of the target signal line is lowered than the voltage drop threshold V limit , thereby significantly increasing the overall voltage drop level of the wiring substrate.
  • FIG. 6 shows a schematic plan view of the light-emitting substrate 600.
  • the light-emitting substrate 600 includes: the wiring substrate described in any of the previous embodiments.
  • the substrate 105 of the wiring substrate also includes a functional area.
  • the functional area includes a plurality of partitions P arranged in an array.
  • the term "functional area" refers to the An area to arrange functional components (such as light-emitting elements); a plurality of light-emitting elements arranged in a plurality of partitions P in the functional area; and a circuit board 603 arranged in the fan-out area.
  • each light-emitting unit 601 is arranged in each partition P, and optionally, a driving circuit 602 electrically connected to the light-emitting unit 601.
  • the driving circuit 602 can control the light-emitting performance of the light-emitting unit 601.
  • each light-emitting unit 601 may include multiple light-emitting units, and the multiple light-emitting units may be connected in series, in parallel, or in combination with each other in series and parallel.
  • Each light-emitting unit may be composed of at least one light-emitting element such as a light-emitting diode (LED), a sub-millimeter light-emitting diode (Mini LED) or a micro light-emitting diode (Mirco LED).
  • LED light-emitting diode
  • Mini LED sub-millimeter light-emitting diode
  • Mirco LED micro light-emitting diode
  • the light-emitting element is a Mini LED or Mirco LED, it has a smaller size than an LED, so it can make each partition P of the light-emitting substrate 600 have a smaller size or the signal line wiring space on the light-emitting substrate 600 can be larger. sufficient, the light-emitting unit 601 in each partition P can be individually addressed and powered, thereby making the light-emitting brightness of the light-emitting substrate 600 more accurate.
  • the light-emitting substrate 600 using Mini LED or Mirco LED as the light source can achieve regional dimming within a smaller range, thereby achieving better brightness uniformity, higher color contrast and being thinner and lighter product appearance.
  • this wiring substrate 600 is applied to a display device, the display effect of the display device is equivalent to that of the OLED display device, but the cost is only about 60% of the OLED display device, and the service life of the product is compared to the OLED display device. The display device has been greatly improved.
  • FIG. 6 shows a partition of k rows*3 columns as an example, which is only a partial schematic diagram of the light-emitting substrate 600.
  • the light-emitting substrate 600 should include multiple rows*multiple column partitions.
  • two target signal lines are arranged in each column partition.
  • the target signal line 108 and the target signal line 109 are arranged in the first column partition.
  • the target signal line 108 is electrically connected to all the light-emitting units 601 in the first column partition.
  • the target signal line 108 can be a driving voltage signal line VLED; the target signal line 109 is electrically connected to all drive circuits 602 in the first column partition, and the target signal line 109 may be a common voltage signal line GND.
  • the target signal line 101 and the target signal line 107 are arranged in the second column partition.
  • the target signal line 101 is electrically connected to all the light-emitting units 601 in the second column partition.
  • the target signal line 101 can be the driving voltage signal line VLED;
  • the target signal line 107 is electrically connected to all the driving circuits 602 in the second column partition, and the target signal line 107 may be a common voltage signal line GND.
  • the target signal line 102 and the target signal line 103 are arranged in the third column partition.
  • the target signal line 103 is electrically connected to all the light-emitting units 601 in the third column partition.
  • the target signal line 103 can be a driving voltage signal line VLED; the target signal line 102 is electrically connected to all drive circuits 602 in the third column partition, and the target signal line 102 may be a common voltage signal line GND.
  • Each of the target signal lines 101, 102, 103, 107, 108, 109 is arranged in the functional area and the fan-out area.
  • each of the target signal lines 101, 102, 103, 107, 108, and 109 extends substantially in a straight line along the second direction D2; in the fan-out area, the target signal lines 101, 102, and 103
  • Each of , 107, 108, and 109 includes a sub-portion extending along the first direction D1, and the sub-portion of each target signal line has a length L along the first direction and a width along the second direction D2 as mentioned above. W.
  • the length L 1 of the sub-portion of the target signal line 101 located in the fan-out area and extending along the first direction D1 in the first direction D1 is approximately 12882um.
  • the width W 1 of the extended sub-portion in the second direction D2 is approximately 710um; the length L 2 of the sub-portion of the target signal line 102 located in the fan-out area and extending along the first direction D1 in the first direction D1 is approximately 13010um.
  • the width W 2 of the sub-portion of the target signal line 102 located in the fan-out area and extending along the first direction D1 in the second direction D2 is approximately 710um; the sub-portion of the target signal line 103 located in the fan-out area and extending along the first direction D1
  • the length L 3 of the sub-portion of the target signal line 103 in the first direction D1 is approximately 23380 um, and the width W 3 of the sub-portion of the target signal line 103 located in the fan-out area and extending along the first direction D1 in the second direction D2 is approximately 1036 um.
  • the widths of the three target signal lines 101, 102, and 103 in the fan-out area are determined according to their respective widths.
  • the length and voltage drop in the fan-out area have differentiated values, rather than having a uniform width.
  • the width W 3 of the target signal line 103 with the maximum voltage drop is the maximum value among W 1 , W 2 , and W 3 .
  • the voltage drop of the target signal line 103 is significantly reduced and is lower than the voltage drop threshold. V limit .
  • the overall voltage drop level of the light-emitting substrate 600 is limited by the maximum voltage drop, and the voltage drop of the target signal line 103 has been significantly reduced, the overall voltage drop level of the light-emitting substrate 600 is actually significantly improved.
  • the target signal lines 101 , 102 , 103 , 107 , 108 , and 109 are electrically connected to the same circuit board 603 via a plurality of bonding electrodes 104 .
  • the circuit board 603 may be chip on film. Taking the center line of the circuit board 603 parallel to the second direction D2 as a reference line, the target signal lines 101, 102, and 103 located on the first side of the reference line are electrically connected to the circuit board via the bonding electrode 104 on the first side of the reference line. 603.
  • the target signal lines 107, 108, and 109 located on the second side of the reference line are electrically connected to the circuit board 603 via the bonding electrodes 104 on the second side of the reference line.
  • the fan-out area of the light emitting substrate 600 may also include a flexible circuit board (FPC) and a printed circuit board (PCBA). One end of the FPC is connected to the circuit board 603, and the other end of the FPC is connected to the PCBA. The control signals of the IC on the PCBA are passed to the bonding electrode 104 via the FPC and circuit board 603 .
  • the sub-portions of the multiple target signal lines (eg, target signal lines 101, 103, 108) on the light-emitting substrate 600 located in the fan-out area are bound to the binding electrodes 104.
  • the multiple target signal lines (eg, the target signal lines) on the light-emitting substrate 600 The portions of the signal lines 101, 103, 108) located in the functional area are electrically connected to the light-emitting unit 601. Therefore, the control signal of the IC on the PCBA can be transmitted to the light-emitting unit 601 via the target signal line to control the light-emitting unit 601 to emit light.
  • FIG. 6 takes the example that the target signal line 101 is located in the 2nd column partition and the target signal lines 102 and 103 are located in the adjacent 3rd column partition, this is only an example. According to the design requirements of the product and the target signal The amplitude of the signal transmitted by the line and its use can be selected, and the position of the target signal line can be flexibly changed.
  • FIG. 7 shows a block diagram of a display device 700, which includes the wiring substrate or the light-emitting substrate described in any of the previous embodiments.
  • the display device 700 may be a liquid crystal display device, which includes a liquid crystal panel and a backlight source disposed on the non-display side of the liquid crystal panel.
  • the backlight source includes the wiring substrate described in any of the previous embodiments.
  • the backlight can be used to implement HDR dimming for display operation.
  • the liquid crystal display device can have more uniform backlight brightness and better display contrast.
  • the display device 700 can be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators, e-books, and any other product or component with a display function.
  • the display device 700 may have substantially the same technical effects as the wiring substrate or light-emitting substrate described in the previous embodiments, for the purpose of brevity, the technical effects of the display device 700 will not be repeated here.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed above could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the disclosure. Because of this, variations in the shapes illustrated may be expected, for example, as a result of manufacturing techniques and/or tolerances. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure.

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Abstract

一种为目标信号线分配宽度的方法、布线基板、发光基板及显示装置。方法包括: 对目标信号线编号(S101)；执行以下步骤至少一次，直到集合中目标信号线的数量为0(S102): 确定目标信号线的集合(S103)；基于目标信号线的压降V、温升T及宽度W满足的条件确定区域R，压降V是函数V(L，W)，长度L和宽度W分别指每条目标信号线在扇出区的子部的长度和宽度(S104)；确定集合中具有最大压降的目标信号线的编号i(S105)；将编号为i的目标信号线的已知长度L i代入到V(L，W)以得到V(L i，W)，基于V(L i，W)与区域R的边界的交点得到W i(S106)；从集合中去除宽度为W i的目标信号线(S107)。

Description

为目标信号线分配宽度的方法、布线基板、发光基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种为目标信号线分配宽度的方法、布线基板、包括该布线基板的发光基板和显示装置。
背景技术
显示装置通常分为液晶显示装置和有机发光二极管显示装置两大类，液晶显示装置由于具有轻薄化、抗震性好、视角广、对比度高等优点而得到广泛应用。液晶显示装置通常包括显示面板和背光源，背光源通常布置在显示面板的非显示侧以为显示面板的显示提供光源。液晶显示装置的对比度、亮度均匀性以及稳定性等特性与背光源的结构和性能相关联。近几年，次毫米发光二极管(Mini-LED)由于其优异的性能而得到广泛的关注，并被越来越多地应用到背光源中。
发明内容
根据本公开的一方面，提供了一种为目标信号线分配宽度的方法，包括：对至少一条目标信号线分别编号；执行以下步骤至少一次，直到集合中待分配宽度的目标信号线的数量为0：确定待分配宽度的目标信号线的集合；基于待分配宽度的目标信号线中的每一条的电压降V和温升T以及待分配宽度的目标信号线的宽度W满足的条件来确定平面区域R，所述电压降V是长度L和宽度W的函数V(L，W)，所述长度L指每条目标信号线的位于扇出区且沿第一方向延伸的子部沿第一方向的长度，所述宽度W指每条目标信号线的位于扇出区且沿第一方向延伸的子部沿第二方向的宽度，所述第二方向与所述第一方向交叉；确定集合中待分配宽度的目标信号线中的具有最大电压降的目标信号线的编号i；将编号为i的目标信号线的已知长度L i代入到V(L，W)中以得到V(L i，W)，基于V(L i，W)与所述区域R的边界的交点得到W i，所述W i为编号为i的目标信号线位于扇出区且沿第一方向延伸的子部沿所述第二方向的宽度；以及从所述集合中去除已分配宽度W i的目标信号线。
在一些实施例中，所述目标信号线的数量为N，N为大于或等于2 的正整数，N条目标信号线具有N个宽度，所述N条目标信号线中的具有最大电压降的一条目标信号线的宽度是所述N个宽度中的最大值。
在一些实施例中，所述温升T是所述长度L和所述宽度W的函数T(L，W)，所述基于待分配宽度的目标信号线中的每一条的电压降V和温升T以及待分配宽度的目标信号线的宽度W满足的条件来确定平面区域R的步骤包括：基于由待分配宽度的目标信号线中的每一条的电压降V(L，W)小于电压降阈值、待分配宽度的目标信号线中的每一条的温升T(L，W)小于温升阈值、以及待分配宽度的目标信号线的宽度W之和小于动态宽度阈值构成的不等式组来确定所述平面区域R。
在一些实施例中，所述确定集合中待分配宽度的目标信号线中的具有最大电压降的目标信号线的编号i的步骤包括：将W 0代入到V(L，W)中以得到V(L，W 0)，W 0与所述动态宽度阈值相关联；将集合中待分配宽度的目标信号线中的每一条的已知长度分别代入到V(L，W 0)中以得到不同电压降的集合；从所述不同电压降的集合中选择最大电压降；以及根据所述最大电压降对应的已知长度来确定所述具有最大电压降的目标信号线的编号i。
在一些实施例中，每条目标信号线的电压降V(L，W)满足如下公式：V(L，W)＝E+F*L/W，其中E和F均为常数。
在一些实施例中，
Figure PCTCN2022103126-appb-000001
所述目标信号线还布置在功能区，所述功能区包括阵列布置的多个分区，R pixel为每条目标信号线的位于单个分区内的区段的电阻，k为分区的行数，I j＝j*I 0，I k＝k*I 0，I 0为单个分区的电流。
在一些实施例中，R(L，W)＝R s*L/W，R s为目标信号线的方块电阻，E＝k*(k+1)/2*I 0*R pixel，F＝k*I 0*R s。
在一些实施例中，每条目标信号线的温升T(L，W)满足如下公式：
T(L，W)＝[(1/(L*W*X) Y)/(I/C)] 1/Q，其中I为每条目标信号线传输的电流，X、Y、C、Q均为常数。
根据本公开的另一方面，提供了一种布线基板，包括：衬底，包括扇出区；至少一条目标信号线，位于所述衬底上且至少位于所述扇出区内，所述至少一条目标信号线中的每一条的位于扇出区且沿第一 方向延伸的子部具有沿第一方向的长度L，所述至少一条目标信号线中的每一条的位于扇出区且沿第一方向延伸的子部具有沿第二方向的宽度W，所述第二方向与所述第一方向交叉，每条目标信号线的宽度W根据前面任一实施例描述的方法确定。
在一些实施例中，所述目标信号线的数量为N，N为大于或等于2的正整数，N条目标信号线具有N个宽度，所述N条目标信号线中的具有最大电压降的一条目标信号线的宽度是所述N个宽度中的最大值。
在一些实施例中，所述布线基板还包括布置在所述扇出区内的绑定电极，每条目标信号线与至少两个绑定电极电连接。
在一些实施例中，所述目标信号线包括驱动电压信号线、公共电压信号线、电源电压信号线中的至少一种。
根据本公开的又一方面，提供了一种发光基板，该发光基板包括：根据前面任一实施例描述的布线基板，所述衬底还包括功能区，所述功能区包括阵列布置的多个分区；多个发光元件，布置在所述功能区内的多个分区内；以及电路板，布置在所述扇出区内。
在一些实施例中，所述多个分区布置成多行和多列，所述目标信号线的数量为N，N为大于或等于2的正整数，N条目标信号线还沿所述第二方向布置在所述功能区内，并且所述N条目标信号线位于同一列分区内或者位于相邻的M列分区内，M为大于或等于2的正整数。
在一些实施例中，所述电路板包括覆晶薄膜，并且所述N条目标信号线经由绑定电极与同一个电路板电连接。
在一些实施例中，所述多个发光元件中的每一个包括次毫米发光二极管。
根据本公开的再一方面，提供了一种显示装置，该显示装置包括在前面任一实施例描述的布线基板或前面任一实施例描述的发光基板。
附图说明
为了更清楚地描述本公开实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了相关技术中的信号线在扇出区的布置方式；
图2示出了根据本公开实施例的为目标信号线分配宽度的方法的流程图；
图3示出了根据本公开实施例的目标信号线在扇出区的布置方式；
图4示出了根据本公开实施例的布线基板的局部平面示意图；
图5示出了根据本公开另一实施例的布线基板的局部平面示意图；
图6示出了根据本公开实施例的发光基板的局部平面示意图；以及
图7示出了根据本公开实施例的显示装置的框图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
布线基板上通常布置有多条信号线，以用来传递信号，例如电信号。由于每条信号线具有电阻，当电信号在信号线中传递时，在信号线的两个端部之间会产生电压降。为保证信号线的两端之间的电压降不超过安全阈值，通常对信号线的电阻的阻值具有一定的要求。在相关技术中，为了降低信号线的电阻，在受限于布线基板的尺寸以及为避免相邻信号线之间距离太近而发生信号串扰，相邻信号线之间必须具有一定宽度的间隔，因此各条信号线的线宽尺寸存在上限。因此，通常选择通过增加信号线的厚度以增大信号线的截面积，进而降低信号线的电阻。位于同一层的多条信号线可以由一次成膜工艺经过图案化同时形成，而同一层的多条信号线的厚度受对厚度需求最大的信号线的限制。
布线基板包括功能区和扇出区，功能区包括阵列布置的多个分区，扇出区可以布置有绑定电极和电路板等结构，各个信号线在扇出区分别通过绑定电极接收电路板提供的电信号，并延伸到功能区以向各个分区传输相应的电信号。为了实现窄边框甚至无边框的产品需求，布线基板的扇出区在沿信号线的延伸方向上通常具有较小的尺寸，而多条信号线在扇出区内进行收线，多条信号线从相互之间可以具有较大 间隔的状态变化到相互之间具有基本一致且较小的间隔状态，因此相较于信号线的位于功能区的部分，信号线的位于扇出区的部分在诸如线宽以及线长等与电压降相关的尺寸参数方面具有更大的限制性，因而往往成为导致导电层的厚度不得不增大的原因。然而，加厚的导电层对工艺提出了更为严苛的要求，因此常常会导致产品良率下降，并且增加生产成本。
图1示出了相关技术中的布线基板10的信号线在扇出区的布置示意图。如图1所示，扇出区包括多条信号线，例如信号线11、信号线12以及信号线13等。扇出区内，信号线11的沿第一方向D1的部分沿第一方向D1的尺寸为S1，沿第二方向D2的尺寸为G1，第二方向D2与第一方向D1交叉；信号线12的沿第一方向D1的部分沿第一方向D1的尺寸为S2，沿第二方向D2的尺寸为G2；信号线13的沿第一方向D1的部分沿第一方向D1的尺寸为S3，沿第二方向D2的尺寸为G3。尺寸S1和S2远远小于尺寸S3，但是尺寸G1、G2、G3却基本相等。这导致信号线13的电压降远远大于信号线11和信号线12的电压降，且已经超出了安全阈值，使得布线基板10的整体电压降水平受限于信号线13的电压降，从而使得布线基板10具有较差的电学性能。
为了解决相关技术中存在的技术问题，本公开的实施例提供了一种为目标信号线分配宽度的方法，图2示出了该方法100的流程图。参考图2，该方法100包括：
步骤S101：对至少一条目标信号线分别编号；
步骤S102：执行步骤S103-S107至少一次，直到集合中待分配宽度的目标信号线的数量为0；
步骤S103：确定待分配宽度的目标信号线的集合；
步骤S104：基于待分配宽度的目标信号线中的每一条的电压降V和温升T以及待分配宽度的目标信号线的宽度W满足的条件来确定平面区域R，电压降V是长度L和宽度W的函数V(L，W)，长度L指每条目标信号线的位于扇出区且沿第一方向延伸的子部沿第一方向的长度，宽度W指每条目标信号线在扇出区的位于扇出区且沿第一方向延伸的子部沿第二方向的宽度，第二方向与第一方向交叉；
步骤S105：确定集合中待分配宽度的目标信号线中的具有最大电压降的目标信号线的编号i；
步骤S106：将编号为i的目标信号线的已知长度L i代入到V(L，W)中以得到V(L i，W)，基于V(L i，W)与平面区域R的边界的交点得到W i，W i为编号为i的目标信号线的位于扇出区且沿第一方向延伸的子部沿第二方向的宽度；
步骤S107：从集合中去除已分配宽度W i的目标信号线。
需要说明的是，术语“电压降”是指电压或电位差，当电流流过目标信号线时，将在目标信号线的每一区段中产生一定的电压降，电压降表示电荷由信号线的某一区段的一端移动到另一端所带来的电位差。术语“温升”是指目标信号线在一段时间内以非零的固定电功率工作所具有的温度相较于零电功率时的温度的上升值。
另外，需要说明的是，术语“扇出区”是指用来使信号线与电路板连接的区域，扇出区通常布置有信号线、绑定电极以及电路板等结构，例如信号线位于扇出区的部分通过绑定电极连接到电路板，从而接收来自电路板的信号。
需要指出的是，术语“待分配宽度”指的是目标信号线的位于扇出区且沿第一方向延伸的子部的线宽。术语“平面区域R”是由L和W限定的二维平面区域，该平面区域R可以理解为是由L和W构成的数学集合。
通过该方法100，在每次执行完步骤S101-S107之后，都可以为集合中具有最大电压降的那条目标信号线的位于扇出区且沿第一方向延伸的子部分配宽度，直至为集合中的每一条目标信号线的位于扇出区且沿第一方向延伸的子部分配宽度。相比于相关技术中各条信号线的位于扇出区且沿第一方向延伸的子部具有不同的长度但却具有基本相同的线宽，在本公开的实施例提供的方法100中，每条目标信号线的位于扇出区且沿第一方向延伸的子部所分配的宽度与该条信号线在位于扇出区且沿第一方向延伸的子部的长度、电压降和温升等相关联，因此实现了各条目标信号线的宽度的动态分配。另外，通过该方法100为各条目标信号线动态分配宽度，使得所有目标信号线的电压降，尤其是最大电压降，均小于电压降阈值，并且所有目标信号线的电压降均小于布线基板10的信号线13的电压降，从而可以提升布线基板的整体电压降水平。
图3示出了根据本公开实施例的布线基板200的一部分信号线在 扇出区的布置示意图，图4示出了布线基板200的局部平面示意图。下面结合图2至图4详细地描述方法100的各个步骤。
步骤S101：对至少一条目标信号线分别编号。
在布线基板200的扇出区内，通常布置有多条信号线。在这些多条信号线中，其中一部分信号线由于传输数字信号，其对于信号线的电阻要求低，此类信号线在扇出区的尺寸设计不在本公开实施例的讨论范围之内，即为“非目标信号线”；而多条信号线中的另一部分信号线由于传输幅值恒定的电信号，例如传输恒压信号或者恒流信号，其尺寸参数的设计对布线基板200的整体电压降水平具有显著的影响，该部分信号线在扇出区的宽度在本公开实施例的讨论范围之内，该部分信号线即为本文的“目标信号线”。
换句话说，目标信号线是指传输恒定幅值的电信号且在扇出区包括多个顺次连接的子部的信号线，其中，目标信号线的多个子部中只有一个子部沿第一方向D1延伸，多个子部中至多有两个子部沿第二方向D2延伸，其中一个沿第二方向D2延伸的子部的一端，与沿第一方向D1的子部的一端连通构成一体结构，另一端与绑定区的至少一个绑定电极连接。具体地，参考图3的信号线103，信号线103传输恒定幅值的电压信号，且在扇出区包括三个顺次连接的子部1031、1032、1033，三个子部1031、1032、1033中只有一个子部1032沿第一方向D1延伸，三个子部1031、1032、1033中的两个子部1031和1033沿第二方向D2延伸，子部1031和1033分别与子部1032的两部连通构成一体结构。因此，信号线103是目标信号线，类似地，信号线101和102也是目标信号线。另外，需要指出的是，在扇出区内，仅具有沿第二方向D2延伸的子部的信号线为非目标信号线。
信号线或信号线的子部沿某一方向延伸是指，信号线或信号线的子部呈大致的条状结构，该条状结构的侧边中的较长者的延伸方向平行于该方向，该信号线或信号线的子部的延伸方向可以认为是平行于条状结构中具有最大长度的侧边的延伸方向。
具体地，参考图3的信号线201，信号线201在位于扇出区且沿第一方向延伸的子部2011呈大致的条状结构，该条状结构中具有最大长度的侧边202仅沿第二方向D2延伸，因此信号线201在位于扇出区且沿第一方向延伸的子部2011可以认为是仅沿第二方向D2延伸。因此， 信号线201不是本文所指的目标信号线，而是非目标信号线。
图3作为一个示例示出了8条信号线，这8条信号线包括目标信号线101、目标信号线102、目标信号线103以及其他非目标信号线。这8条信号线在绑定区与同一个电路板106(例如覆晶薄膜)电连接，该电路板106包括多个金手指结构，金手指结构与绑定区的多个绑定电极一一对应且电连接。如图3所示，以电路板106的平行于第二方向D2的中心线作为参考线，位于参考线第一侧的目标信号线(包括目标信号线101、102、103)整体均在参考线的第一侧电连接至电路板106，位于参考线第二侧的信号线整体均在参考线的第二侧电连接至电路板106。在一些实施例中，由于位于参考线一侧的多条目标信号线在平行于第一方向D1的平面上的正投影相互交叠，且位于参考线一侧的多条目标信号线之间相互间隔设置，因此扇出区沿第二方向D2的宽度与参考线两侧中的任意一侧的目标信号线的宽度之和正相关。由于扇出区沿第二方向D2的宽度与参考线两侧中的任意一侧的目标信号线的宽度之和正相关，因此，方法100所针对的目标信号线的集合是指位于参考线一侧的各条目标信号线的集合。例如，在图3的示例中，目标信号线的集合是位于参考线第一侧的目标信号线101、102、103的集合。对3条目标信号线101、102、103分别编号，例如目标信号线101的编号可以是1，目标信号线102的编号可以是2，目标信号线103的编号可以是3。在一些实施例中，目标信号线101和103可以是驱动电压信号线VLED，该驱动电压信号线VLED配置为传输第一恒压信号；目标信号线102可以是公共电压信号线GND，该公共电压信号线GND配置为传输第二恒压信号。
步骤S102：执行步骤S103-S107至少一次，直到集合中待分配宽度的目标信号线的数量为0。
执行步骤S103-S107的次数等于目标信号线的数量。在图3的实施例中，目标信号线的数量为3条，因此，执行步骤S103-S107的次数为3次，使得最终集合中待分配宽度的目标信号线的数量为0。换句话说，通过重复执行步骤S103-S107三次，最终可以为3条目标信号线101、102、103中的每一条目标信号线分配对应的宽度。如前文所解释的，术语“待分配宽度”指的是目标信号线的位于扇出区且沿第一方向D1延伸的子部的线宽。例如，在图3中，目标信号线103的待 分配宽度指的是目标信号线103的位于扇出区且沿第一方向D1延伸的子部1032的线宽。
下面描述每次执行步骤S103-S107时对应的操作。
第一次执行步骤S103-S107：
步骤S103：确定待分配宽度的目标信号线的集合。
待分配宽度的目标信号线的集合为目标信号线101、目标信号线102以及目标信号线103构成的集合。
步骤S104：基于待分配宽度的目标信号线中的每一条的电压降V和温升T以及待分配宽度的目标信号线的宽度W满足的条件来确定平面区域R，电压降V是长度L和宽度W的函数V(L，W)，长度L指每条目标信号线在扇出区的子部沿第一方向D1的长度，宽度W指每条目标信号线在扇出区的子部沿第二方向D2的宽度，第二方向D2与第一方向D1交叉。
目标信号线101在扇出区的子部具有沿第一方向D1的长度L 1和沿第二方向D2的待分配宽度W 1，第二方向D2与第一方向D1交叉，例如第二方向D2垂直于第一方向D1；目标信号线102的位于扇出区且沿第一方向延伸的子部具有沿第一方向D1的长度L 2和沿第二方向D2的待分配宽度W 2；目标信号线103的位于扇出区且沿第一方向延伸的子部具有沿第一方向D1的长度L 3和沿第二方向D2的待分配宽度W 3。长度L 1、L 2、L 3是已知的，宽度W 1、W 2、W 3是未知的且是待分配的。长度L 1、L 2、L 3可以具有各种适当的数值，本公开的实施例对此不做具体限制。在一些实施例中，目标信号线101的长度L 1约为12882um，目标信号线102的长度L 2约为13010um，目标信号线103的长度L 3约为23380um。
参考图4，需要说明的是，目标信号线的已知长度L i(i＝1，2，3)是指目标信号线的位于扇出区且沿第一方向D1延伸的子部在第一方向D1上的最大长度，目标信号线的位于扇出区且沿第一方向D1延伸的子部与目标信号线的最靠近绑定区且沿第二方向D2延伸的子部直接相连，其中，目标信号线的最靠近绑定区且沿第二方向D2延伸的子部与对应的至少一个绑定电极104直接接触且电连接，绑定电极104沿第二方向D2延伸。具体地，以图4的目标信号线103为例，目标信号线103在位于扇出区且沿第一方向延伸的子部在第一方向D1上的长 度L 3是指目标信号线103在位于扇出区且沿第一方向延伸的子部1032的第一侧边1034到第二侧边1035之间的距离。
电压降V是长度L和宽度W的函数V(L，W)，温升T也是长度L和宽度W的函数T(L，W)。在一些实施例中，基于待分配宽度的目标信号线中的每一条的电压降V和温升T以及待分配宽度的目标信号线的宽度W满足的条件来确定平面区域R的步骤可以包括以下子步骤：基于目标信号线101、102、103中的每一条的电压降V(L，W)小于电压降阈值V limit、目标信号线101、102、103中的每一条的温升T(L，W)小于温升阈值T limit、以及目标信号线101、102、103的宽度W之和小于动态宽度阈值W allow1构成的不等式组来确定平面区域R。该不等式组可以表达为
Figure PCTCN2022103126-appb-000002
可以看出，由该不等式组确定的平面区域R是由L和W限定的二维平面区域，该二维平面区域是由一定数值范围内的L和一定数值范围内的W圈定的区域。在该不等式组中，i的取值为1、2、3，j的取值为1、2、3。Ti(L i，W i)表示编号为i的目标信号线的温升。例如，T 1(L 1，W 1)表示编号为1的目标信号线(即目标信号线101)的温升，T 2(L 2，W 2)表示编号为2的目标信号线(即目标信号线102)的温升，T 3(L 3，W 3)表示编号为3的目标信号线(即目标信号线103)的温升。类似地，V 1(L 1，W 1)表示编号为1的目标信号线(即目标信号线101)的电压降，V 2(L 2，W 2)表示编号为2的目标信号线(即目标信号线102)的电压降，V 3(L 3，W 3)表示编号为3的目标信号线(即目标信号线103)的电压降。
温升T(L，W)涉及较多的电学和热学参数，其物理模型较为复杂。在一些实施例中，每条目标信号线的温升T(L，W)满足如下公式：T(L，W)＝{(1/(L*W*X) Y)/(I/C)} 1/Q，其中I为每条目标信号线传输的电流，单位为mA，X、Y、C、Q均为常数。温升阈值T limit表示可允许的温升的上限值，其数值与结构热膨胀、产品规格要求等因素有关，在不同项目中数值可能不同。温升阈值T limit的范围通常为10～20℃。在一些实施例中，T limit等于15℃。
在一些实施例中，每条目标信号线的电压降V(L，W)满足如下公式：V(L，W)＝E+F*L/W，其中E和F均为常数。如图4所示，布线基板200还包括功能区，功能区包括阵列布置的多个分区，多个分区以多行*多列的方式布置，每个分区内可以布置有发光元件和与该发光元件电连接的驱动电路。目标信号线101、102、103中的每一条均布置在功能区和扇出区，在功能区内，每列分区内布置有目标信号线101、102、103中的至少一条。进一步地，每条目标信号线的电压降V(L，W)可以满足如下公式：
Figure PCTCN2022103126-appb-000003
R(L，W)为该条目标信号线在扇出区的部分的电阻。在一些实施例中，R(L，W)＝R s*L/W，I j＝j*I 0，I k＝k*I 0。将R(L，W)＝R s*L/W、I j＝j*I 0、I k＝k*I 0代入到V(L，W)中，可得出V(L，W)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*L/W。R pixel表示每条目标信号线的与单个分区相对应的区段的电阻，k为分区的行数，I 0为单个分区在工作时流经的电流，R s为每条目标信号线的方块电阻，其为实测值。布线基板200包括k行分区，每条目标信号线的位于功能区的部分沿着第二方向D2从第1行分区延伸至第k行分区，因此，每条目标信号线的位于功能区的部分可以按照单个分区沿第二方向D2上的尺寸被划分成k个区段，与第1行分区对应的区段 为第一个区段，与第k行分区对应的区段为第k个区段。每个区段上传输的电流均为I 0，并且各个区段之间彼此并联连接。因此，I j表示每条目标信号线的前j个区段上传输的电流之和。在布线基板200的型号已经确定的情况下，R pixel、k、I 0、R s可以均视为常量。在这种情况下，E＝k*(k+1)/2*I 0*R pixel，F＝k*I 0*R s。
电压降阈值V limit表示可允许的电压降的上限值，其大小与目标信号线所传输信号的幅值及其用途相关，不同的目标信号线可能具有不同的V limit。例如，驱动电压信号线VLED和公共电压信号线GND的V limit通常约为0.5mV。在一些实施例中，V limit等于0.45mV。
在不等式
Figure PCTCN2022103126-appb-000004
中，动态宽度阈值W allow1表示能够为3条目标信号线101、102、103分配的总宽度之和的阈值，该阈值需要大于W 1+W 2+W 3。W allow1的数值与布线基板200的边框尺寸、发光元件距扇出区的距离、以及各条目标信号线之间的最小距离等因素有关。参考图4，W allow1＝H-H1-H2-(H3+H4+H5)-H6，其中，H表示布线基板200的最后一行(即第k行)分区内的最靠近绑定区的发光元件305的中心与衬底105的侧边1051之间的距离，H1表示绑定电极104沿第二方向D2的长度，H2表示绑定电极104靠近侧边1051的第一端与侧边1051之间的距离，H3表示目标信号线101的位于扇出区且沿第一方向D1延伸的子部与相邻的目标信号线102的位于扇出区且沿第一方向D1延伸的子部之间的距离，H4表示目标信号线102的位于扇出区且沿第一方向D1延伸的子部与相邻的目标信号线103的位于扇出区且沿第一方向D1延伸的子部之间的距离，H5表示目标信号线103的位于扇出区且沿第一方向D1延伸的子部与绑定电极104的与第一端相对 的第二端之间的距离，H6表示布线基板200的第k行分区内的发光元件305的中心与扇出区的边界之间的距离。通过使相邻目标信号线101和102之间间隔距离H3以及相邻目标信号线102和103之间间隔距离H4，可以避免各条目标信号线的信号彼此发生串扰。另外，通过使第k行分区内的发光元件305的中心与扇出区的边界之间间隔距离H6，可以避免扇出区内的目标信号线的信号与发光元件305的信号发生串扰。W allow1的数值可以根据产品设计需求而灵活地改变，本公开的实施例对此不做具体限定。在一个示例中，W allow1等于2.8mm。
步骤S105：确定集合中待分配宽度的目标信号线中的具有最大电压降的目标信号线的编号i。
具体地，该步骤S105可以包括以下子步骤：
a：将W 0代入到V(L，W)中以得到V(L，W 0)，W 0与动态宽度阈值W allow1相关联。在本公开的实施例中，W 0可以根据需要分配宽度的目标信号线所传输信号的幅值及其用途来合理地取值。一般地，W 0＝W allow1/N，N为集合中待分配宽度的目标信号线的数量，在这里，N＝3。当W 0＝W allow1/N时，V(L，W 0)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*L*3/W allow1。
b：将集合中待分配宽度的目标信号线中的每一条的已知长度分别代入到V(L，W 0)中以得到不同电压降的集合。
如前所述，目标信号线101的位于扇出区且沿第一方向延伸的子部沿第一方向D1的长度L 1、目标信号线102的位于扇出区且沿第一方向延伸的子部沿第一方向D1的长度L 2、以及目标信号线103的位于扇出区且沿第一方向延伸的子部沿第一方向D1的长度L 3都是已知的，L 1、L 2、L 3的数值可以根据目标信号线所传输信号的幅值及其用途以及产品的设计需求而确定。在该实施例中，L 1约为12882um，L 2约为13010um，L 3约为23380um。将L 1、L 2、L 3的数值分别代入到V(L，W 0)中，可得到
V 1(L 1，W 0)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*12882*3/W allow1，
V 2(L 2，W 0)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*13010*3/W allow1，
V 3(L 3，W 0)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*23380*3/W allow1。
也就是说，集合中包括三个不同的电压降，分别是V 1(L 1，W 0)、V 2(L 2，W 0)、V 3(L 3，W 0)。
c：从不同电压降的集合中选择最大电压降。
通过比较V 1(L 1，W 0)、V 2(L 2，W 0)、V 3(L 3，W 0)可以得知，V 3(L 3，W 0)的电压降最大。
d：根据最大电压降对应的已知长度来确定具有最大电压降的目标信号线的编号i。
V 3(L 3，W 0)对应的已知长度为L 3，由于已在步骤S101中预先为各条目标信号线分配了编号，并且具有相应编号的每条目标信号线在扇出区的部分的长度是已知的，因此通过该已知长度L 3即可得知对应的目标信号线的编号为3，即具有最大电压降的目标信号线是编号为3的目标信号线103。
步骤S106：将编号为3的目标信号线的已知长度L 3代入到V(L，W)中以得到V(L 3，W)，即V(L 3，W)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*23380/W，基于V(L 3，W)与平面区域R的边界的交点得到W 3，W 3为编号为3的目标信号线103在扇出区的子部沿第二方向D2的宽度。在该实施例中，W 3等于1036μm。
步骤S107：从集合中去除已分配宽度W 3的目标信号线103。
通过第一次执行步骤S103-S107，可以为三条目标信号线中具有最大电压降的目标信号线103动态地分配宽度W 3，使得分配的宽度W 3等于1036μm。
第二次执行步骤S103-S107：
步骤S103：确定待分配宽度的目标信号线的集合。由于在第一次执行步骤S107时已从集合中去除已分配宽度W 3的目标信号线103，因此，在本次步骤S103中，更新后的集合为目标信号线101和目标信号线102。
步骤S104：基于下述不等式组来确定更新后的平面区域R′：
Figure PCTCN2022103126-appb-000005
相较于第一次执行步骤S104时i、j以及W allow1的取值，在本次执行步骤S104时，i的取值为1和2，j的取值为1和2，W allow2＝W allow1-W 1，其他参数的取值保持不变。由于动态宽度阈值W allow2相较于动态宽度阈值W allow1发生了改变，因此，本次通过步骤S104确定的更新后的平面区域R′相较于上次通过步骤S104确定的平面区域R也发生了改变，相应地，本次通过步骤S104确定的更新后的平面区域R′的边界对应的横纵坐标值(L和W)相较于上次通过步骤S104确定的平面区域R的边界对应的横纵坐标值也发生了改变。
步骤S105：确定目标信号线101和目标信号线102中的具有最大电压降的目标信号线的编号i。
具体地，该步骤S105可以包括以下子步骤：
a：将W 0′代入到V(L，W)中以得到V(L，W 0′)，W 0′与动态宽度阈值W allow2相关联，W 0′＝W allow2/(N-1)，即W 0′＝W allow2/2。将W 0′＝W allow2/2代入到V(L，W)中，可以得到V(L，W 0′)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*L*2/W allow2。
b：将目标信号线101的已知长度L 1和目标信号线102的已知长度L 2分别代入到V(L，W 0′)中以得到不同电压降的集合。L 1约为12882um，L 2约为13010um。将L 1、L 2的数值分别代入到V(L，W 0′)中，可得到
V 1(L 1，W 0′)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*12882*2/W allow2，
V 2(L 2，W 0′)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*13010*2/W allow2。也就是说，集合中包括两个不同的电压降，分别是V 1(L 1，W 0′)和V 2(L 2，W 0′)。
c：通过比较V 1(L 1，W 0′)和V 2(L 2，W 0′)可以得知，两者中V 2(L 2，W 0′)的电压降最大。
d：根据最大电压降V 2(L 2，W 0′)对应的已知长度L 2来确定具有最大电压降的目标信号线的编号为2，即目标信号线101和目标信号线102中具有最大电压降的是编号为2的目标信号线102。
步骤S106：将编号为2的目标信号线102的已知长度L 2代入到V(L，W)中以得到V 2(L 2，W)，即
V 2(L 2，W)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*13010/W，基于V 2(L 2，W)与更新后的平面区域R′的边界的交点得到W 2，W 2为编号为2的目标信号线102的位于扇出区且沿第一方向延伸的子部沿第二方向D2的宽度。在该实施例中，W 2等于710μm。
步骤S107：从集合中去除已分配宽度W 2的目标信号线102。
通过第二次执行步骤S103-S107，可以为集合中剩余两条目标信号线101和102中具有最大电压降的目标信号线102动态地分配宽度W 2，使得分配的宽度W 2等于710μm。
第三次执行步骤S103-S107：
步骤S103：确定待分配宽度的目标信号线的集合。由于在第二次执行步骤S107时已从集合中去除已分配宽度W 2的目标信号线102，因此，在本次步骤S103中，更新后的集合仅包括目标信号线101。
步骤S104：基于下述不等式组来确定更新后的平面区域R″：
Figure PCTCN2022103126-appb-000006
相较于第一次执行步骤S104时i、j以及W allow1的取值，在本次执行步骤S104时，i的取值为1，j的取值为1，W allow3＝W allow1-W 1-W 2，其他参数的取值保持不变。由于动态宽度阈值W allow3相较于动态宽度阈值W allow1和W allow2均发生了改变，因此，本次通过步骤S104确定的更新后的平面区域R″相较于第一次通过步骤S104确定的平面区域R和第二次通过步骤S104确定的平面区域R′也发生了改变，相应地，本次通过步骤S104确定的更新后的平面区域R″的边界对应的横纵坐标值(L和W)相较于第一次通过步骤S104确定的平面区域R和第二次通过步骤S104确定的平面区域R′的边界对应的横纵坐标值也发生了改变。可以看出，动态宽度阈值是与方法100 的执行次数(或者说目标信号线的数量)相关联的动态值，而不是一个常数。在第一次执行步骤S103-S107时，W allow1等于初始值2.8mm。在第二次执行步骤S103-S107时，W allow2＝W allow1-W 1。在第三次执行步骤S103-S107时，W allow3＝W allow1-W 1-W 2，以此类推，
Figure PCTCN2022103126-appb-000007
其中n为大于等于1且小于等于N的正整数，N为目标信号线的数量，W allown表示第n次执行步骤S104时选取的动态宽度阈值。
步骤S105：确定目标信号线101的编号i。
具体地，该步骤S105可以包括以下子步骤：
a：将W 0″代入到V(L，W)中以得到V(L，W 0″)，W 0″与动态宽度阈值W allow3相关联，W 0″＝W allow3/(N-2)，即W 0″＝W allow3。将W 0″＝W allow3代入到V(L，W)中，可以得到V(L，W 0″)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*L/W allow3。
b：将目标信号线101的已知长度L 1代入到V(L，W 0″)中以得到电压降的集合，L 1约为12882um。将L 1数值代入到V(L，W 0″)中，可得到V 1(L 1，W 0″)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*12882/W allow3。也就是说，集合中仅包括-个电压降，即V 1(L 1，W 0″′)。
d：根据电压降V 1(L 1，W 0″′)对应的已知长度L 1来确定目标信号线的编号为1，即，待分配宽度的目标信号线是编号为1的目标信号线101。
步骤S106：将编号为1的目标信号线101的已知长度L 1代入到V(L，W)中以得到V 1(L 1，W)，即V(L 1，W)＝k*(k+1)/2*I 0*R pixel+k*I 0*R s*12882/W，基于V 1(L 1，W)与更新后的平面区域R″的边界的交点得到W 1，W 1为编号为1的目标信号线101的位于扇出区且沿第一方向延伸的子部沿第二方向D2的宽度。在该实施例中，W 1等于710μm。
步骤S107：从集合中去除已分配宽度W 1的目标信号线101。
通过第三次执行步骤S103-S107，可以为集合中剩余的目标信号线101动态地分配宽度W 1，使得分配的宽度W 1等于710μm。
至此，集合中待分配宽度的目标信号线的数量变为0，步骤结束。
参考图1，在相关技术中，信号线11在扇出区的部分在第二方向D2上的宽度G1等于810μm，信号线12在扇出区的部分在第二方向D2上的宽度G2等于810μm，信号线13在扇出区的部分在第二方向D2上的宽度G3等于836um，G1、G2、G3大体相等且G1+G2+G3＝2456um。信号线13的电压降远远大于信号线11和信号线12的电压降且已经超出了电压降阈值V limit，布线基板10的整体电压降水平受信号线13的电压降的限制。然而，通过本公开实施例提供的方法100为三条目标信号线101、102、103分别动态地分配宽度，使得具有最大电压降的目标信号线103的位于扇出区且沿第一方向延伸的子部在第二方向D2上的宽度W 3等于1036μm，具有中间电压降的目标信号线102的位于扇出区且沿第一方向延伸的子部在第二方向D2上的宽度W 2等于710μm，具有最小电压降的目标信号线101的位于扇出区且沿第一方向延伸的子部在第二方向D2上的宽度W 3等于710μm，W 1+W 2+W 3＝2456um，与相关技术中的G1+G2+G3的和相同。相比于相关技术，在没有占用扇出区的更多宽度造成边框变宽或者增大目标信号线的厚度的前提下，三条目标信号线101、102、103的位于扇出区且沿第一方向延伸的子部的宽度依据其各自的长度和电压降而具有差异化的数值，三者不再具有均一的宽度。通过该方法100，使得具有最大电压降的目标信号线103的宽度W 3得到了显著增大，相比于相关技术中的信号线13，目标信号线103的电压降得以显著降低，并且低于电压降阈值V limit。另外，需要说明的是，相较于相关技术，虽然目标信号线101和目标信号线102由于在扇出区的宽度略微增大而导致其电压降略有增加，但是由于布线基板200的整体电压降水平受最大电压降的限制，而具有最大电压降的目标信号线103的电压降数值低于相关技术中的信号线13的电压降数值且低于电压降阈值V limit，因此布线基板200的整体电压降水平实际上实现了显著的提升。
在一些实施例中，目标信号线在扇出区的沿第一方向D1延伸的子部的线宽与目标信号线位于扇出区且沿第二方向D2延伸且最靠近功能区的子部和参考线的距离正相关。在替代的实施例中，在位于参考线同一侧的多条目标信号线中，至少存在两条目标信号线，其中至少两条目标信号线中的第一条目标信号线的位于功能区和扇出区交界的 位置与参考线的距离，大于至少两条目标信号线中的第二条目标信号线的位于功能区和扇出区交界的位置与参考线的距离，而第一条目标信号线在扇出区沿第一方向D1延伸的子部的线宽至少为第二条目标信号线在扇出区沿第一方向D1延伸的子部的线宽的1.5倍，例如可以为1.8倍，2倍，3倍，3.5倍等。具体地，以目标信号线102和103为例，目标信号线103的位于功能区和扇出区交界的位置与参考线的距离大于目标信号线102的位于功能区和扇出区交界的位置与参考线的距离，目标信号线103在扇出区沿第一方向D1延伸的子部的线宽W 3等于1036μm，目标信号线102在扇出区沿第一方向D1延伸的子部的线宽W 2等于710μm，W 3约是W 2的1.5倍。
图3和图4以目标信号线的数量N等于3为示例来描述方法100的各个步骤，但是如前所述，目标信号线的数量N可以是任意适当的数值，本公开的实施例对此不做具体限定。
图5示出了布线基板300的局部平面示意图，其示出了多条目标信号线，多条目标信号线分别向四列分区传输电信号。多条目标信号线在绑定区域同一个电路板106连接，该绑定区内设置有多个间隔排布的绑定电极。图5示出了布线基板300的四列分区，如果以这样的四列分区作为一个重复单元，在一些实施例中，布线基板300包括多个这样的重复单元。如图5所示，以电路板106的平行于第二方向D2的中心线作为参考线，参考线的第一侧布置有第C列分区和第C+1列分区，参考线的第二侧布置有第C+2列分区和第C+3列分区。位于参考线第一侧的信号线在参考线的第一侧电连接至电路板106，位于参考线第二侧的信号线在参考线的第二侧电连接至电路板106。由于扇出区沿第二方向D2的宽度与参考线两侧中的任意一侧的目标信号线的宽度之和正相关，因此，方法100所针对的目标信号线的集合是指位于参考线一侧的各条目标信号线的集合。例如，在图5的示例中，目标信号线的集合是位于参考线第一侧的目标信号线301、302、303、304的集合。需要说明的是，如图5所示，虽然在参考线的第一侧布置有6条信号线，但是由于位于C+1列分区内的信号线305和306非常靠近参考线，因此信号线305和306以近乎直线的方式连接到电路板106，即，信号线305和306在扇出区几乎没有沿第一方向D1延伸的子部。因此，可以认为信号线305的位于扇出区且沿第一方向D1延伸的子部 的长度为0，信号线306的位于扇出区沿第一方向D1延伸的子部的长度也为0。因此，按照前文的定义，信号线305和信号线306为非目标信号线。而信号线301-304在扇出区均包括顺次连接的沿第一方向D1延伸的子部和沿第二方向D2延伸的子部且信号线301-304均传输恒定幅值的电信号，因此，信号线301-304是目标信号线。第C列分区布置有目标信号线301、302、303，第C+1列分区布置有目标信号线304，即参考线的第一侧布置有4条目标信号线。对这4条目标信号线301、302、303、304分别编号，例如目标信号线301的编号可以是1，目标信号线302的编号可以是2，目标信号线303的编号可以是3，目标信号线304的编号可以是4。在一些实施例中，目标信号线301和304可以是驱动电压信号线VLED，目标信号线301配置为向第C列分区内的发光单元601提供第一恒定电压，目标信号线304配置为向第C+1列分区内的发光单元601提供第三恒定电压；目标信号线302可以是电源电压信号线Pwr，目标信号线302与第C列分区内的驱动电路(未示出)的电源端子电连接；目标信号线303可以是公共电压信号线GND，目标信号线303配置为向第C列分区内的驱动电路提供第二恒定电压(例如接地电压)。
方法100同样适用于为图5示出的目标信号线分配宽度，例如，可以通过如下步骤来为目标信号线301-304分别分配宽度：
步骤S101：对4条目标信号线301-304分别编号1-4；
步骤S102：执行步骤S103-S107四次，直到集合中待分配宽度的目标信号线的数量为0；
步骤S103：确定待分配宽度的目标信号线的集合；
步骤S104：基于待分配宽度的目标信号线中的每一条的电压降V和温升T以及待分配宽度的目标信号线的宽度W满足的条件来确定平面区域R，电压降V是长度L和宽度W的函数V(L，W)，长度L指每条目标信号线在扇出区的子部沿第一方向D1的长度，宽度W指每条目标信号线在扇出区的子部沿第二方向D2的宽度，第二方向D2与第一方向D1交叉；
步骤S105：确定集合中待分配宽度的目标信号线中的具有最大电压降的目标信号线的编号i；
步骤S106：将编号为i的目标信号线的已知长度L i代入到V(L， W)中以得到V(L i，W)，基于V(L i，W)与平面区域R的边界的交点得到W i，W i为编号为i的目标信号线的位于扇出区且沿第一方向延伸的子部沿第二方向D2的宽度；
步骤S107：从集合中去除已分配宽度W i的目标信号线。
步骤S103-S107中的每一个步骤的具体操作可以参考关于图2-4的描述，为了简洁起见，此处不再赘述。需要注意的是，图5的实施例对应的初始的动态宽度阈值W allow1等于3.4mm。
如图5所示，目标信号线301的位于扇出区且沿第一方向延伸的子部具有沿第一方向D1的已知长度L 4，为20100μm；目标信号线302的位于扇出区且沿第一方向延伸的子部具有沿第一方向D1的已知长度L 5，为9730μm；目标信号线303的位于扇出区且沿第一方向延伸的子部具有沿第一方向D1的已知长度L 6，为11840μm；目标信号线304的位于扇出区且沿第一方向延伸的子部具有沿第一方向D1的已知长度L 7，为9720μm。通过上述方法100为目标信号线301-304的位于扇出区且沿第一方向延伸的子部分别分配宽度，使得目标信号线301的位于扇出区且沿第一方向延伸的子部在第二方向D2上的宽度W 4等于996μm，目标信号线302的位于扇出区且沿第一方向延伸的子部在第二方向D2上的宽度W 5等于200μm，目标信号线303的位于扇出区且沿第一方向延伸的子部在第二方向D2上的宽度W 6等于776μm，以及目标信号线304的位于扇出区且沿第一方向延伸的子部在第二方向D2上的宽度W 7等于690μm。在目标信号线301-304中，目标信号线301的电压降最大，因此其分配的宽度W 4是W 1-W 4中的最大值。
相比于相关技术，在没有占用扇出区的更多宽度造成边框变宽或者增大目标信号线的厚度的前提下，使得四条目标信号线301、302、303、304的位于扇出区且沿第一方向延伸的子部的宽度依据其各自的长度和电压降而具有差异化的数值，而不再是具有均一的宽度。通过该方法100，使得具有最大电压降的目标信号线301的宽度W 4得到了显著增大，从而使得目标信号线301的电压降得以显著降低，并且低于电压降阈值V limit，从而使得布线基板300的整体电压降水平实现了显著的提升。
在其他未描述的实施例中，可能会存在相邻两列分区共用某一条(或某几条)信号线的情况。在这种情况下，目标信号线的数量会相 应地减少。
根据本公开的另一方面，提供了一种布线基板，参考图3-图5，该布线基板包括：衬底105，包括扇出区；至少一条目标信号线，位于衬底105上且至少位于扇出区内，至少一条目标信号线中的每一条的位于扇出区且沿第一方向延伸的子部具有沿第一方向D1的长度L，至少一条目标信号线中的每一条的位于扇出区且沿第一方向延伸的子部具有沿第二方向D2的宽度W，第二方向D2与第一方向D1交叉，每条目标信号线的宽度W根据前面任一实施例描述的方法100来确定。
在布线基板200的扇出区内，通常布置有多条信号线。在这些多条信号线中，其中一部分信号线由于传输数字信号，其对于信号线的电阻要求低，此类信号线在扇出区的尺寸设计不在本公开实施例的讨论范围之内，即为“非目标信号线”；而多条信号线中的另一部分信号线由于传输幅值恒定的电信号，例如传输恒压信号或者恒流信号，其尺寸参数的设计对布线基板200的整体电压降水平具有显著的影响，该部分信号线在扇出区的宽度在本公开实施例的讨论范围之内，该部分信号线即为本文的“目标信号线”。在一些实施例中，如图3和图4所示，目标信号线包括驱动电压信号线VLED和公共电压信号线GND，例如，目标信号线101和103可以是驱动电压信号线VLED，目标信号线102可以是公共电压信号线GND。目标信号线101和102可以位于同一列分区内，目标信号线103可以位于相邻列的分区内。在替代的实施例中，如图5所示，目标信号线包括驱动电压信号线VLED、电源电压信号线PWR和公共电压信号线GND。例如，目标信号线301可以是驱动电压信号线VLED，目标信号线302可以是电源电压信号线PWR，目标信号线303可以是公共电压信号线GND，目标信号线301、302、303位于第C列分区内。目标信号线304可以是驱动电压信号线VLED，目标信号线304位于第C+1列分区内。目标信号线301配置为向第C列分区内的发光单元601提供第一恒定电压，目标信号线304配置为向第C+1列分区内的发光单元601提供第一恒定电压；目标信号线302与第C列分区内的驱动电路(未示出)的电源端子连接；目标信号线303配置为向第C列分区内的驱动电路提供第二恒定电压(例如接地电压)。
如图4所示，在一些实施例中，布线基板还包括布置在扇出区内 的绑定电极104，每条目标信号线的位于扇出区的部分与至少两个绑定电极104电连接。
目标信号线的数量为N，N为大于或等于2的正整数，N条目标信号线的扇出区沿第一方向D1延伸的子部具有N个线宽。如前文所描述的，N个线宽中最大的一个线宽对应的是N条目标信号线中的具有最大电压降的一条目标信号线。由于布线基板的整体电压降水平受最大电压降的限制，通过使具有最大电压降的目标信号线在扇出区具有最大的线宽，可以显著降低该条目标信号线的电压降，使得该条目标信号线的电压降低于电压降阈值V limit，从而可以明显提高布线基板的整体电压降水平。
布线基板的技术效果可以参考前面各个实施例描述的方法100的技术效果，出于简洁的目的，此处不再重复描述布线基板的技术效果。
根据本公开的另一方面，提供了一种发光基板，图6示出了发光基板600的平面示意图。该发光基板600包括：前面任一个实施例描述的布线基板，布线基板的衬底105还包括功能区，功能区包括阵列布置的多个分区P，术语“功能区”是指衬底105上用来布置功能元器件(例如发光元件)的区域；多个发光元件，布置在功能区内的多个分区P内；以及电路板603，布置在扇出区内。
如图6所示，发光基板600的功能区内布置多个分区，图中的每个虚线矩形框表示一个分区P。每个分区P内布置有一个发光单元601，以及可选地，与该发光单元601电连接的驱动电路602，驱动电路602可以控制发光单元601的发光性能。在一些实施例中，每个发光单元601可以包括多个发光单元，该多个发光单元彼此可以串联、并联或者串并联结合。每个发光单元可以是由至少一个发光二极管(LED)、次毫米发光二极管(Mini LED)或微型发光二极管(Mirco LED)等发光元件构成。当发光元件为Mini LED或Mirco LED时，其相较于LED具有更小的尺寸，因此其可以使发光基板600的每个分区P具有更小的尺寸或发光基板600上的信号线布线空间更充裕，每个分区P内的发光单元601可以单独寻址供电，从而使得发光基板600的发光亮度更为精准。相比于传统的发光基板，使用Mini LED或Mirco LED作为发光源的发光基板600能够实现更小范围内的区域调光，从而能够实现更好的亮度均一性，更高的色彩对比度以及更轻薄的产品外形。当 这种布线基板600应用到显示装置中时，该显示装置的显示效果与OLED显示装置的显示效果表现相当，但成本仅为OLED显示装置的60％左右，而产品的使用寿命相较于OLED显示装置却有大幅度的提高。
图6作为示例示出了k行*3列的分区，这仅是发光基板600的局部示意图，事实上，如本领域技术人员所知晓的，发光基板600应当包括多行*多列分区。如图6所示，每列分区内布置有两条目标信号线。第1列分区内布置有目标信号线108和目标信号线109，目标信号线108与第1列分区内的所有发光单元601电连接，目标信号线108可以是驱动电压信号线VLED；目标信号线109与第1列分区内的所有驱动电路602电连接，目标信号线109可以是公共电压信号线GND。类似地，第2列分区内布置有目标信号线101和目标信号线107，目标信号线101与第2列分区内的所有发光单元601电连接，目标信号线101可以是驱动电压信号线VLED；目标信号线107与第2列分区内的所有驱动电路602电连接，目标信号线107可以是公共电压信号线GND。第3列分区内布置有目标信号线102和目标信号线103，目标信号线103与第3列分区内的所有发光单元601电连接，目标信号线103可以是驱动电压信号线VLED；目标信号线102与第3列分区内的所有驱动电路602电连接，目标信号线102可以是公共电压信号线GND。目标信号线101、102、103、107、108、109中的每一条布置在功能区和扇出区内。在功能区内，目标信号线101、102、103、107、108、109中的每一条沿第二方向D2基本上以直线的形式延伸；在扇出区内，目标信号线101、102、103、107、108、109中的每一条包括沿第一方向D1延伸的子部，每条目标信号线的子部具有如前文所述的沿第一方向的长度L和沿第二方向D2的宽度W。例如，目标信号线101的位于扇出区且沿第一方向D1延伸的子部在第一方向D1上的长度L 1约为12882um，目标信号线101的位于扇出区且沿第一方向D1延伸的子部在第二方向D2上的宽度W 1约为710um；目标信号线102的位于扇出区且沿第一方向D1延伸的子部在第一方向D1上的长度L 2约为13010um，目标信号线102的位于扇出区且沿第一方向D1延伸的子部在第二方向D2上的宽度W 2约为710um；目标信号线103的位于扇出区且沿第一方向D1延伸的子部在第一方向D1上的长度L 3约为23380um， 目标信号线103的位于扇出区且沿第一方向D1延伸的子部在第二方向D2上的宽度W 3约为1036um。相比于相关技术，在没有占用扇出区的更多宽度造成边框变宽或者增大目标信号线的厚度的前提下，三条目标信号线101、102、103在扇出区的宽度依据其各自在扇出区的长度和电压降而具有差异化的数值，不再是具有均一的宽度。具有最大电压降的目标信号线103的宽度W 3是W 1、W 2、W 3中的最大值，相比于相关技术，目标信号线103的电压降得以显著降低，并且低于电压降阈值V limit。另外，由于发光基板600的整体电压降水平受最大电压降的限制，而目标信号线103的电压降已经被显著减小，因此发光基板600的整体电压降水平实际上实现了显著的提升。
如图6所示，目标信号线101、102、103、107、108、109经由多个绑定电极104与同一个电路板603电连接。在一些实施例中，电路板603可以是覆晶薄膜(chip on film)。以电路板603的平行于第二方向D2的中心线作为参考线，位于参考线第一侧的目标信号线101、102、103在参考线的第一侧经由绑定电极104电连接至电路板603，位于参考线第二侧的目标信号线107、108、109在参考线的第二侧经由绑定电极104电连接至电路板603。虽然图6中未示出，但是发光基板600的扇出区还可以包括柔性电路板(FPC)和印刷电路板(PCBA)。FPC的一端与电路板603连接，FPC的另一端与PCBA连接。PCBA上的IC的控制信号经由FPC和电路板603传递到绑定电极104。发光基板600上的多条目标信号线(例如目标信号线101、103、108)的位于扇出区的子部与绑定电极104绑定，发光基板600上的多条目标信号线(例如目标信号线101、103、108)的位于功能区的部分与发光单元601电连接。因此，PCBA上的IC的控制信号可以经由目标信号线传递到发光单元601以控制发光单元601发光。
虽然图6以目标信号线101位于第2列分区内而目标信号线102和103位于相邻的第3列分区内为例来描述，但这仅是一个示例，根据产品的设计需求以及目标信号线所传输信号的幅值及其用途选择，目标信号线的位置可以灵活地改变。
发光基板600的其他技术效果可以参考前文关于方法100的技术效果，出于简洁的目的，此处不再重复描述发光基板600的技术效果。
根据本公开的再一方面，提供了一种显示装置，图7示出了显示 装置700的框图，该显示装置700包括在前面任一个实施例中描述的布线基板或发光基板。在一些实施例中，该显示装置700可以为液晶显示装置，其包括液晶面板和设置在该液晶面板的非显示侧的背光源，背光源包括在前面任一个实施例中描述的布线基板，该背光源可以用于实现HDR调光以用于显示操作。该液晶显示装置可以具有更均匀的背光亮度，具有更好的显示对比度。显示装置700可以为任意适当的显示装置，包括但不限于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子书等任何具有显示功能的产品或部件。
由于显示装置700可以与前面各个实施例描述的布线基板或发光基板具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述显示装置700的技术效果。
将理解的是，尽管术语第一、第二、第三等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，上面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“行”、“列”、“在…之下”、“在…之上”、“左”、“右”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在…之下”可以涵盖在…之上和在…之下的取向两者。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述特征、整体、步骤、操作、 元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在…上”或“直接在…上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此。任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种为目标信号线分配宽度的方法，包括：
    对至少一条目标信号线分别编号；
    执行以下步骤至少一次，直到集合中待分配宽度的目标信号线的数量为0：
    确定待分配宽度的目标信号线的集合；
    基于待分配宽度的目标信号线中的每一条的电压降V和温升T以及待分配宽度的目标信号线的宽度W满足的条件来确定平面区域R，所述电压降V是长度L和宽度W的函数V(L，W)，所述长度L指每条目标信号线的位于所述扇出区且沿第一方向延伸的子部沿第一方向的长度，所述宽度W指每条目标信号线的位于所述扇出区且沿第一方向延伸的子部沿第二方向的宽度，所述第二方向与所述第一方向交叉；
    确定集合中待分配宽度的目标信号线中的具有最大电压降的目标信号线的编号i；
    将编号为i的目标信号线的已知长度L i代入到V(L，W)中以得到V(L i，W)，基于V(L i，W)与所述平面区域R的边界的交点得到W i，所述W i为编号为i的目标信号线的位于扇出区且沿第一方向延伸的子部沿所述第二方向的宽度；以及
    从所述集合中去除已分配宽度W i的目标信号线。
  2. 根据权利要求1所述的方法，其中，所述目标信号线的数量为N，N为大于或等于2的正整数，N条目标信号线具有N个宽度，所述N条目标信号线中的具有最大电压降的一条目标信号线的宽度是所述N个宽度中的最大值。
  3. 根据权利要求1或2所述的方法，其中，所述温升T是所述长度L和所述宽度W的函数T(L，W)，所述基于待分配宽度的目标信号线中的每一条的电压降V和温升T以及待分配宽度的目标信号线的宽度W满足的条件来确定平面区域R的步骤包括：
    基于由待分配宽度的目标信号线中的每一条的电压降V(L，W)小于电压降阈值、待分配宽度的目标信号线中的每一条的温升T(L，W)小于温升阈值、以及待分配宽度的目标信号线的宽度W之和小于动态宽度阈值构成的不等式组来确定所述平面区域R。
  4. 根据权利要求3所述的方法，其中，所述确定集合中待分配宽度的目标信号线中的具有最大电压降的目标信号线的编号i的步骤包括：
    将W 0代入到V(L，W)中以得到V(L，W 0)，W 0与所述动态宽度阈值相关联；
    将集合中待分配宽度的目标信号线中的每一条的已知长度分别代入到V(L，W 0)中以得到不同电压降的集合；
    从所述不同电压降的集合中选择最大电压降；以及
    根据所述最大电压降对应的已知长度来确定所述具有最大电压降的目标信号线的编号i。
  5. 根据权利要求1-4中任一项所述的方法，其中，每条目标信号线的电压降V(L，W)满足如下公式：
    V(L，W)＝E+F*L/W，其中E和F均为常数。
  6. 根据权利要求5所述的方法，其中，
    Figure PCTCN2022103126-appb-100001
    所述目标信号线还布置在功能区，所述功能区包括阵列布置的多个分区，R pixel为每条目标信号线的对应单个分区的区段的电阻，k为分区的行数，I j＝j*I 0，I k＝k*I 0，I 0为单个分区的电流。
  7. 根据权利要求6所述的方法，其中，R(L，W)＝R s*L/W，R s为目标信号线的方块电阻，E＝k*(k+1)/2*I 0*R pixel，F＝k*I 0*R s。
  8. 根据权利要求3-7中任一项所述的方法，其中，每条目标信号线的温升T(L，W)满足如下公式：
    T(L，W)＝[(1/(L*W*X) Y)/(I/C)] 1/Q，其中I为每条目标信号线传输的电流，X、Y、C、Q均为常数。
  9. 一种布线基板，包括：
    衬底，包括扇出区；
    至少一条目标信号线，位于所述衬底上且至少位于所述扇出区内，所述至少一条目标信号线中的每一条的位于扇出区且沿第一方向延伸的子部具有沿第一方向的长度L，所述至少一条目标信号线中的每一条的位于扇出区且沿第一方向延伸的子部具有沿第二方向的宽度W，所 述第二方向与所述第一方向交叉，
    其中，每条目标信号线的宽度W根据权利要求1-8中任一项所述的方法确定。
  10. 根据权利要求9所述的布线基板，其中，所述目标信号线的数量为N，N为大于或等于2的正整数，N条目标信号线具有N个宽度，所述N条目标信号线中的具有最大电压降的一条目标信号线的宽度是所述N个宽度中的最大值。
  11. 根据权利要求9或10所述的布线基板，还包括布置在所述扇出区内的绑定电极，其中，每条目标信号线与至少两个绑定电极电连接。
  12. 根据权利要求9-11中任一项所述的布线基板，其中，所述目标信号线包括驱动电压信号线、公共电压信号线、电源电压信号线中的至少一种。
  13. 一种发光基板，包括：
    根据权利要求9-12中任一项所述的布线基板，其中，所述衬底还包括功能区，所述功能区包括阵列布置的多个分区；
    多个发光元件，布置在所述功能区内的多个分区内；以及
    电路板，布置在所述扇出区内。
  14. 根据权利要求13所述的发光基板，其中，所述多个分区布置成多行和多列，所述目标信号线的数量为N，N为大于或等于2的正整数，N条目标信号线还沿所述第二方向布置在所述功能区内，并且所述N条目标信号线位于同一列分区内或者位于相邻的M列分区内，M为大于或等于2的正整数。
  15. 根据权利要求14所述的发光基板，其中，所述电路板包括覆晶薄膜，并且所述N条目标信号线经由绑定电极与同一个电路板电连接。
  16. 根据权利要求13-15中任一项所述的发光基板，其中，所述多个发光元件中的每一个包括次毫米发光二极管。
  17. 一种显示装置，包括根据权利要求9-12中任一项所述的布线基板或权利要求13-16中任一项所述的发光基板。
PCT/CN2022/103126 2022-06-30 2022-06-30 为目标信号线分配宽度的方法、布线基板、发光基板及显示装置 WO2024000516A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60180857A (ja) * 1984-02-28 1985-09-14 Kyocera Corp 熱印刷装置
CN107608104A (zh) * 2017-11-03 2018-01-19 惠科股份有限公司 显示面板及其应用的显示装置
CN111564456A (zh) * 2020-05-20 2020-08-21 深圳莱宝高科技股份有限公司 信号线结构及电子装置
CN112861467A (zh) * 2021-02-03 2021-05-28 深圳华大九天科技有限公司 线宽补偿方法及装置、服务器和存储介质
CN215451419U (zh) * 2021-02-22 2022-01-07 京东方科技集团股份有限公司 显示基板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60180857A (ja) * 1984-02-28 1985-09-14 Kyocera Corp 熱印刷装置
CN107608104A (zh) * 2017-11-03 2018-01-19 惠科股份有限公司 显示面板及其应用的显示装置
CN111564456A (zh) * 2020-05-20 2020-08-21 深圳莱宝高科技股份有限公司 信号线结构及电子装置
CN112861467A (zh) * 2021-02-03 2021-05-28 深圳华大九天科技有限公司 线宽补偿方法及装置、服务器和存储介质
CN215451419U (zh) * 2021-02-22 2022-01-07 京东方科技集团股份有限公司 显示基板和显示装置

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