WO2024000380A1 - 一种像素驱动电路及其控制方法、显示装置 - Google Patents

一种像素驱动电路及其控制方法、显示装置 Download PDF

Info

Publication number
WO2024000380A1
WO2024000380A1 PCT/CN2022/102760 CN2022102760W WO2024000380A1 WO 2024000380 A1 WO2024000380 A1 WO 2024000380A1 CN 2022102760 W CN2022102760 W CN 2022102760W WO 2024000380 A1 WO2024000380 A1 WO 2024000380A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
node
signal line
electrode
Prior art date
Application number
PCT/CN2022/102760
Other languages
English (en)
French (fr)
Inventor
赵旭亮
皇甫鲁江
朱健超
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/102760 priority Critical patent/WO2024000380A1/zh
Priority to CN202280001975.9A priority patent/CN117651991A/zh
Publication of WO2024000380A1 publication Critical patent/WO2024000380A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present application relates to the field of display technology, and in particular, to a pixel driving circuit, a control method thereof, and a display device.
  • embodiments of the present application provide a pixel driving circuit configured to drive a light-emitting diode to emit light at different refresh frequencies, including:
  • a first control module and a second control module the first control module is electrically connected to the first gate line, the first initial signal line and the first node, and is configured to be under the control of the gate signal of the first gate line , write the initial signal of the first initial signal line into the first node, and maintain the potential of the first node at different refresh frequencies;
  • the second control module is electrically connected to the second gate line, the first The voltage signal line and the second node are configured to write the voltage signal of the first voltage signal line into the second node under the control of the gate signal of the second gate line, and at different refresh frequencies. maintain the potential of the second node;
  • the compensation module is electrically connected to the reset signal line, the fourth node and the first node, and under the control of the reset signal of the reset signal line, conducts the path between the fourth node and the first node. , and maintain the potential of the first node at different refresh frequencies;
  • a refresh module electrically connected to the first gate line, the data signal line and the third node, and configured to write the data signal of the data signal line into the data signal under the control of the gate signal of the first gate line.
  • the first reset module is electrically connected to the reset signal line, the first initial signal line and the anode of the light-emitting diode, and is configured to pass the first initial signal under the control of the reset signal of the reset signal line.
  • the initial signal of the signal line resets the anode;
  • the first lighting control module is electrically connected to the first lighting control signal line, the second voltage signal line, the third node and the first node, and is configured to control the control signal of the first lighting control signal line. Next, write the voltage signal of the second voltage signal line into the third node;
  • a driving module and a second lighting control module The driving module is electrically connected to the first node, the first voltage signal line and the fourth node.
  • the second lighting control module is electrically connected to the second lighting control module.
  • signal line, the fourth node and the anode, the driving module and the second lighting control module are respectively configured to use the signal line under the control of the first node and the second lighting control signal line.
  • the electrical signal that causes the light-emitting diode to emit light is transmitted to the anode.
  • the pixel driving circuit also includes:
  • the second reset module is electrically connected to the scanning signal line, the second initial signal line and the sixth node, and is configured to pass the initial signal of the second initial signal line under the control of the scanning signal of the scanning signal line. Reset the drive module;
  • a third lighting control module is electrically connected to a third lighting control signal line, the first voltage signal line and the sixth node, and is configured to be controlled by a third lighting control signal of the third lighting control signal line. , writing the first voltage signal of the first voltage signal line into the driving module.
  • the compensation module includes a second transistor
  • the control electrode of the second transistor is electrically connected to the reset signal line, the first electrode is electrically connected to the fourth node, and the second electrode is electrically connected to the first node.
  • the compensation module includes a second transistor and a ninth transistor;
  • the control electrode of the second transistor is electrically connected to the reset signal line, the first electrode is electrically connected to the fourth node, and the second electrode is electrically connected to the first electrode of the ninth transistor;
  • the control electrode of the ninth transistor is electrically connected to the second gate line, and the second electrode is electrically connected to the first node.
  • the second control module includes a fifth transistor
  • the control electrode of the fifth transistor is electrically connected to the second gate line, the first electrode is electrically connected to the first voltage signal line, and the second electrode is electrically connected to the second node.
  • the second control module includes a tenth transistor and an eleventh transistor
  • the control electrode of the tenth transistor is electrically connected to the first and second gate lines, the first electrode is electrically connected to the first voltage signal line, and the second electrode is electrically connected to the second node;
  • the control electrode of the eleventh transistor is electrically connected to the second gate line, the first electrode is electrically connected to the first voltage signal line, and the second electrode is electrically connected to the second node.
  • the first control module includes a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the first gate line, the first electrode is electrically connected to the first initial signal line, and the second electrode is electrically connected to the first node.
  • the refresh module includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first gate line, the first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the third node.
  • the first reset module includes a sixth transistor
  • the control electrode of the sixth transistor is electrically connected to the reset signal line, the first electrode is electrically connected to the first initial signal line, and the second electrode is electrically connected to the anode.
  • the first lighting control module includes a seventh transistor, a first capacitor and a second capacitor;
  • the control electrode of the seventh transistor is electrically connected to the first light-emitting control signal line, the first electrode is electrically connected to the second voltage signal line, and the second electrode is electrically connected to the third node;
  • the first pole of the first capacitor is electrically connected to the third node, and the second pole is electrically connected to the second node;
  • the first pole of the second capacitor is electrically connected to the second node, and the second pole is electrically connected to the first node.
  • the driving module includes a third transistor
  • the control electrode of the third transistor is electrically connected to the first node, the first electrode is electrically connected to the first voltage signal line, and the second electrode is electrically connected to the fourth node.
  • the second lighting control module includes an eighth transistor
  • the control electrode of the eighth transistor is electrically connected to the second light emitting control signal line, the first electrode is electrically connected to the fourth node, and the second electrode is electrically connected to the anode.
  • the second reset module includes twelve transistors; the control electrode of the twelfth transistor is electrically connected to the scanning signal line, the first electrode is electrically connected to the second initial signal line, and the second electrode is electrically connected to The sixth node;
  • the third lighting control module includes thirteen transistors; the control electrode of the thirteenth transistor is electrically connected to the third lighting control signal line, the first electrode is electrically connected to the first voltage signal line, and the second electrode is electrically connected.
  • the sixth node is electrically connected.
  • the second transistor includes an oxide transistor.
  • the ninth transistor includes an oxide transistor, and the second transistor includes a non-oxide transistor.
  • the fifth transistor includes an oxide transistor.
  • At least one of the tenth transistor and the eleventh transistor includes an oxide transistor.
  • the fourth transistor includes an oxide transistor.
  • embodiments of the present application provide a display device including the above-mentioned pixel driving circuit.
  • embodiments of the present application provide a control method for the above-mentioned pixel driving circuit, the method includes:
  • the refresh of the one frame of display picture is achieved through the first reset stage, the writing stage, the compensation stage and the first lighting stage.
  • embodiments of the present application provide a control method for the above-mentioned pixel driving circuit, the method includes:
  • the refresh of the one frame of display picture is achieved through the first reset stage, the writing stage, the compensation stage and the first lighting stage;
  • the first refresh of the one frame of display picture is achieved through the first reset stage, the writing stage, the compensation stage and the first lighting stage, and the first refresh of the one frame of display picture is achieved through the second reset stage.
  • the first stage and the second light-emitting stage realize the refreshing of the one-frame display picture except the first refresh.
  • Figure 1 is a schematic diagram of a pixel driving circuit provided by an embodiment of the present application.
  • Figure 2 is a schematic diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 3 is a schematic diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 4 is a driving timing diagram of a pixel driving circuit provided by an embodiment of the present application.
  • Figure 5 is a driving timing diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 6 is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present application.
  • Figures 7-10 are schematic diagrams of the driving principle of the pixel driving circuit of Figure 1 under the driving timing sequence of Figure 4;
  • FIGS 11 to 14 are schematic diagrams of the driving principle of the pixel driving circuit of Figure 3 under the driving timing sequence of Figure 6;
  • Figure 15 is a schematic diagram of yet another pixel driving circuit provided by an embodiment of the present application.
  • Figure 16 is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present application.
  • FIG. 17 is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present application.
  • the gate electrode of the transistor is called a control electrode
  • one of the source electrode and the drain electrode is called a first electrode
  • the other is called a second electrode
  • the first electrode of all transistors is called the drain electrode
  • the second electrode is called the source electrode.
  • electrical connection may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.
  • Embodiments of the present application provide a pixel driving circuit configured to drive a light emitting diode to emit light at different refresh frequencies.
  • the pixel driving circuit includes:
  • the first control module 11 is electrically connected to the first gate line Gate_P, the first initial signal line Vinit1 and the first node N1, and is configured to generate a gate signal on the first gate line Gate_P.
  • Under the control of The voltage signal line VDD and the second node N2 are configured to write the voltage signal of the first voltage signal line VDD into the second node N2 under the control of the gate signal of the second gate line Gate_N, and at different refresh frequencies. The potential of the second node N2 is maintained.
  • the pixel driving circuit when the pixel driving circuit operates at a high refresh frequency (for example, a refresh frequency of 120HZ), the potential of the first node and the second node can be maintained, and there is basically no current leakage between the first node and the second node.
  • a high refresh frequency for example, a refresh frequency of 120HZ
  • the pixel driving circuit operates at a low refresh frequency (for example: below 30Hz, such as 10HZ, 1Hz or lower refresh frequency)
  • the first node and the second node are prone to occur Leakage makes it impossible to achieve normal display. Therefore, it is necessary to enable the pixel drive circuit to maintain the potential of the first node and the second node at a low refresh frequency, so that the pixel drive circuit can achieve normal display at a low refresh frequency.
  • At least one transistor connected to the first node and the second node can be configured as an oxide transistor to reduce the leakage current of the first node and the second node during the light emitting stage, for example, reduce the leakage current to 1e-15A. Therefore, the potential of the first node and the second node can be better maintained during the light-emitting stage to avoid display defects.
  • Figure 1 illustrates an example in which both the fifth transistor T5 and the ninth transistor T9 are oxide transistors.
  • FIG. 2 illustrates an example in which the fifth transistor T5, the second transistor T2, and the fourth transistor T4 are all oxide transistors, so that the potential of the second node N2 in the light-emitting phase can be maintained through the fifth transistor T5, and the potential of the second node N2 in the light-emitting phase can be maintained through the fifth transistor T5.
  • T2 and the fourth transistor T4 maintain the potential of the first node N1 in the light-emitting phase.
  • the tenth transistor T10 , the eleventh transistor T11 , the second transistor T2 and the fourth transistor T4 are all oxide transistors. Therefore, the tenth transistor T10 and the eleventh transistor T11 can maintain the second transistor.
  • the potential of the node N2 in the light-emitting phase maintains the potential of the first node N1 in the light-emitting phase through the second transistor T2 and the fourth transistor T4.
  • the material of the active layer in the above-mentioned oxide transistor is not specifically limited.
  • the material of the active layer in the above-mentioned oxide transistor may include IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide), ITZO (Indium Tin Zinc Oxide, indium tin zinc oxide), IZO (Indium Zinc Oxide, oxide Indium zinc) and so on.
  • the second control module 12 includes a fifth transistor T5.
  • the fifth transistor T5 is an oxide transistor, so that the second node N2 can be kept in the light-emitting phase through the fifth transistor T5.
  • the second control module 12 includes a tenth transistor T10 and an eleventh transistor T11.
  • the tenth transistor T10 and the eleventh transistor T11 are both oxide transistors, so that the tenth transistor T10 can pass and the eleventh transistor T11 maintains the potential of the second node N2 in the light-emitting phase.
  • the compensation module 2 is electrically connected to the reset signal line AZ (the first reset signal line AZ_P in Figure 1), the fourth node N4 and the first node N1, and is connected to the reset signal line AZ (the first reset signal line AZ_P in Figure 1). Under the control of the reset signal, the path between the fourth node N4 and the first node N1 is turned on, and the potential of the first node N1 is maintained at different refresh frequencies.
  • the reset signal line AZ includes a first reset signal line AZ_P; or, as shown in FIGS. 2 and 3 , the reset signal line AZ includes a first reset signal line AZ_P and a second reset signal line AZ_N. .
  • the pixel driving circuit when the pixel driving circuit operates at a high refresh frequency (for example, a refresh frequency of 120HZ), it can maintain the potential of the first node, and there is basically no current leakage at the first node.
  • a high refresh frequency for example, a refresh frequency of 120HZ
  • the pixel drive circuit works at a low refresh frequency (for example, below 30Hz, such as 10HZ, 1Hz or lower refresh frequency)
  • the first node is prone to leakage, resulting in failure.
  • the compensation module 2 includes a second transistor T2 and a ninth transistor T9.
  • the ninth transistor T9 is an oxide transistor, so that the first node N1 can be maintained in the light-emitting phase through the ninth transistor T9.
  • the second transistor T2 is an oxide transistor
  • the fourth transistor is also an oxide transistor, so that the second transistor T9 and the fourth transistor can be used.
  • the four-transistor T4 maintains the potential of the first node N1 in the light-emitting phase.
  • the refresh module 3 is electrically connected to the first gate line Gate_P, the data signal line Data and the third node N3, and is configured to write the data signal of the data signal line Data into the third node N3 under the control of the gate signal of the first gate line Gate_P.
  • the first reset module 4 is electrically connected to the reset signal line AZ (the first reset signal line AZ_P in Figure 1 ), the first initial signal line Vinit1 and the anode of the light-emitting diode, and is configured to connect the reset signal line AZ (the first reset signal line AZ_P in Figure 1 Under the control of the reset signal of the first reset signal line AZ_P), the anode is reset through the initial signal of the first initial signal line Vinit1.
  • the first lighting control module 5 is electrically connected to the first lighting control signal line EM1, the second voltage signal line Vref, the third node N3 and the first node N1, and is configured to control the control signal of the first lighting control signal line EM1.
  • the voltage signal of the second voltage signal line Vref is written into the third node N3.
  • the driving module 61 and the second lighting control module 62 are respectively configured to transmit the electrical signal for causing the light emitting diode to emit light to the anode under the control of the first node N1 and the first light emitting control signal line EM2 .
  • the anode of the above-mentioned light-emitting diode can be electrically connected to the fifth node N5, and the cathode of the light-emitting diode can be electrically connected to the ground terminal VSS.
  • first control module second control module
  • compensation module refresh module
  • first reset module first lighting control module
  • third lighting control module third lighting control module
  • first node, second node, third node, fourth node and fifth node are only defined for the convenience of describing the circuit structure.
  • the first node, second node, third node, fourth node and fifth node are not Not an actual circuit unit.
  • transistors in Figures 1, 2 and 3 can all be non-oxide transistors, such as LTPS (Low Temperature Poly-silicon, low temperature polysilicon) transistors.
  • LTPS Low Temperature Poly-silicon, low temperature polysilicon
  • at least one of the other transistors mentioned above can also be an oxide transistor, and there is no specific limitation here.
  • FIG. 1 shows an example in which the fifth transistor T5 and the ninth transistor T9 share a second gate line Gate_N.
  • the fifth transistor T5 and the ninth transistor T9 can also be provided with their own second gate lines Gate_N respectively. It is subject to actual application.
  • the potential of the first node is maintained at different refresh frequencies through the first control module and the compensation module, and the potential of the second node is maintained at different refresh frequencies through the second control module, and refresh
  • the process of the module writing the signal to the third node and the process of the compensation module performing threshold voltage compensation can be implemented separately. Therefore, on the one hand, by maintaining the potential of the first node and the second node, the pixel driving circuit can be made to work at different refresh frequencies, that is, the pixel driving circuit can switch to different refresh frequency operating states, and has a wider applicable range, and the pixel driving circuit can switch to different refresh frequency operating states.
  • the pixel driving circuit works relatively stably at low refresh frequencies.
  • the Vdt refresh process of writing the Data signal to the third node is separated from the process of detecting the threshold voltage Vth, the problem of insufficient Vth detection time is effectively solved, thereby achieving a more ideal capacitor charging rate and Vth detection. accuracy and achieve better display effects.
  • the light-emitting diodes can be used in different It produces relatively stable light emission at any refresh frequency, and the Vth compensation time is adjustable. The Vth compensation time is sufficient, which can effectively improve short-term afterimage and Mura problems.
  • the pixel driving circuit also includes:
  • the second reset module 7 is electrically connected to the scanning signal line Scan, the second initial signal line Vinit2 and the sixth node N6, and is configured to pass the initial signal of the second initial signal line Vinit2 under the control of the scanning signal of the scanning signal line Scan.
  • the drive module 61 is reset.
  • the third lighting control module 8 is electrically connected to the third lighting control signal line EM3, the first voltage signal line VDD and the sixth node N6, and is configured to be controlled by the third lighting control signal of the third lighting control signal line EM3, Write the first voltage signal of the first voltage signal line VDD into the driving module 61 .
  • sixth node is only defined for the convenience of describing the circuit structure, and the sixth node is not an actual circuit unit.
  • the compensation module 2 includes a second transistor T2; the control electrode of the second transistor T2 is electrically connected to the reset signal line AZ (the second reset signal line AZ_N in Figures 2 and 3).
  • the first pole is electrically connected to the fourth node N4, and the second pole is electrically connected to the first node N1. Therefore, the potential of the first node can be maintained through the second transistor, so that the pixel driving circuit can achieve better display effects at different refresh frequencies.
  • the type of the second transistor is not specifically limited here.
  • the second transistor may be an oxide transistor.
  • the compensation module 2 includes a second transistor T2 and a ninth transistor T9; the control electrode of the second transistor T2 is electrically connected to the reset signal line AZ (the first reset signal line AZ_P in Figure 1), The first electrode is electrically connected to the fourth node N4, and the second electrode is electrically connected to the first electrode of the ninth transistor T9.
  • the control electrode of the ninth transistor T9 is electrically connected to the second gate line Gate_N, and the second electrode is electrically connected to the first node N1. Therefore, the potential of the first node can be maintained through the ninth transistor, so that the pixel driving circuit can achieve better display effects at different refresh frequencies.
  • the type of the ninth transistor is not specifically limited here.
  • the second transistor may be an oxide transistor.
  • the type of the second transistor is not specifically limited here.
  • the second transistor may be a non-oxide transistor, such as a low-temperature polysilicon transistor.
  • the second control module 12 includes a fifth transistor T5; the control electrode of the fifth transistor is electrically connected to the second gate line Gate_N, and the first electrode is electrically connected to the first voltage signal line VDD, The second electrode is electrically connected to the second node N2. Therefore, the potential of the second node can be maintained through the fifth transistor, so that the pixel driving circuit can achieve better display effects at different refresh frequencies.
  • the number of the above-mentioned second gate lines is not specifically limited here, and can be determined according to the number of thin film transistors in the second control module. If the second control module includes one thin film transistor, such as the fifth transistor T5 in Figures 1 and 2, then the number of second gate lines is one; if the second control module includes two thin film transistors, such as the fifth transistor T5 in Figure 3 The tenth transistor T10 and the eleventh transistor T11, then the number of second gate lines at this time is two (the first and second gate lines RST1_N and the second second gate line RST2_N in FIG. 3 respectively).
  • the second control module 12 includes a tenth transistor T10 and an eleventh transistor T11; the control electrode of the tenth transistor T10 is electrically connected to the first and second gate lines RST1_N, and the first electrode is electrically connected to the first and second gate lines RST1_N.
  • a voltage signal line VDD and a second electrode are electrically connected to the second node N2; a control electrode of the eleventh transistor T11 is electrically connected to the second gate line RST2_N, and a first electrode is electrically connected to the first voltage signal line VDD and the second electrode is electrically connected.
  • the first control module 11 includes a fourth transistor T4; the control electrode of the fourth transistor T4 is electrically connected to the first gate line Gate_P, and the first electrode is electrically connected to the first initial gate line Gate_P.
  • the signal line Vinit1 and the second pole are electrically connected to the first node N1.
  • both the fourth transistor T4 and the second transistor T2 are oxide transistors, so that the fourth transistor T4 and the second transistor T2 can be used.
  • the potential of the first node N1 is maintained.
  • the refresh module 3 includes a first transistor T1; the control electrode of the first transistor T1 is electrically connected to the first gate line Gate_P, and the first electrode is electrically connected to the data signal line Data.
  • the second electrode is electrically connected to the third node N3.
  • the first reset module 4 includes a sixth transistor T6; the control electrode of the sixth transistor T6 is electrically connected to the reset signal line AZ (in Figures 1, 2 and 3 The first reset signal line AZ_P), the first electrode is electrically connected to the first initial signal line Vinit1, and the second electrode is electrically connected to the anode.
  • the first light emitting control module 5 includes a seventh transistor T7, a first capacitor Cst and a second capacitor Cvth; the control electrode of the seventh transistor T7 is electrically connected to the first light emitting
  • the first pole of the control signal line EM1 is electrically connected to the second voltage signal line Vref, and the second pole is electrically connected to the third node N3; the first pole of the first capacitor Cst is electrically connected to the third node N3, and the second pole is electrically connected to the second node. N2; the first pole of the second capacitor Cvth is electrically connected to the second node N2, and the second pole is electrically connected to the first node N1.
  • the driving module 61 includes a third transistor T3; the control electrode of the third transistor T3 is electrically connected to the first node N1, and the first electrode is electrically connected to the first voltage signal line VDD. , the second pole is electrically connected to the fourth node N4.
  • the third transistor in the embodiment of the present application has a long hysteresis relaxation time, which can effectively improve short-term afterimage and Mura problems.
  • the second light emitting control module 62 includes an eighth transistor T8; the control electrode of the eighth transistor T8 is electrically connected to the first light emitting control signal line EM2, and the first electrode is electrically connected to the first light emitting control signal line EM2.
  • the fourth node N4 and the second electrode are electrically connected to the anode.
  • the second reset module 7 includes twelve transistors T12; the control electrode of the twelfth transistor T12 is electrically connected to the scanning signal line Scan, the first electrode is electrically connected to the second initial signal line Vinit2, and the second The pole is electrically connected to the sixth node N6.
  • the third lighting control module 8 includes thirteen transistors; the control electrode of the thirteenth transistor T13 is electrically connected to the third lighting control signal line EM3, the first electrode is electrically connected to the first voltage signal line VDD, and the second electrode is electrically connected to the sixth transistor. Node N6.
  • the second transistor includes an oxide transistor.
  • the material of the active layer in the above-mentioned oxide transistor may include IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide), ITZO (Indium Tin Zinc Oxide, indium tin zinc oxide), IZO (Indium Zinc Oxide, oxide Indium zinc) and so on.
  • IGZO Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • ITZO Indium Tin Zinc Oxide, indium tin zinc oxide
  • IZO Indium Zinc Oxide, oxide Indium zinc
  • the second transistor T2 includes an oxide transistor. At this time, the potential of the first node N1 can be maintained through the second transistor T2 .
  • the fourth transistor T4 can also be configured to include an oxide transistor.
  • the potential of the first node N1 can be jointly maintained by the second transistor T2 and the fourth transistor T4 .
  • the ninth transistor includes an oxide transistor, and the second transistor includes a non-oxide transistor.
  • the material of the active layer in the above-mentioned non-oxide transistor may include LTPS or the like.
  • the ninth transistor T9 includes an oxide transistor. At this time, the potential of the first node N1 can be maintained through the ninth transistor T9 .
  • the second transistor and the fourth transistor are not specifically limited at this time.
  • the second transistor and the fourth transistor may be oxide transistors or non-oxide transistors, depending on the actual application.
  • the fifth transistor includes an oxide transistor.
  • the fifth transistor T5 includes an oxide transistor. At this time, the potential of the second node N2 can be maintained through the fifth transistor T5 .
  • At least one of the tenth transistor and the eleventh transistor includes an oxide transistor.
  • the fact that at least one of the tenth transistor and the eleventh transistor includes an oxide transistor means: the tenth transistor includes an oxide transistor; or the eleventh transistor includes an oxide transistor; or the tenth transistor and the tenth transistor include an oxide transistor.
  • a transistor includes an oxide transistor. Referring to FIG. 3 , both the tenth transistor T10 and the eleventh transistor T11 include oxide transistors. At this time, the potential of the second node N2 can be maintained through the tenth transistor T10 and the eleventh transistor T11 .
  • the fourth transistor includes an oxide transistor.
  • the fourth transistor T4 includes an oxide transistor. At this time, the potential of the first node N1 can be maintained through the fourth transistor T4 .
  • the second transistor T2 can also be configured to include an oxide transistor.
  • the potential of the first node N1 can be jointly maintained by the second transistor T2 and the fourth transistor T4.
  • the above-mentioned oxide transistors are all N-type transistors, and the non-oxide transistors are all P-type transistors.
  • the above-mentioned oxide transistors can also be P-type transistors, and the non-oxide transistors can also be all N-type transistors; or all the above-mentioned transistors can also be N-type transistors; or all the above-mentioned transistors can also be P-type
  • the design principle is similar to that of this application and also falls within the scope of protection of this application.
  • transistor there is no limitation on the type of transistor mentioned above. It may be a thin film transistor, and the thin film transistor may be a low-temperature polysilicon thin film transistor or an oxide thin film transistor.
  • the above-mentioned pixel driving circuit is applied to an OLED display device, the above-mentioned light-emitting diode is an organic light-emitting diode. If the above-mentioned pixel driving circuit is applied to a Mini LED display device or a Micro LED display device, the above-mentioned light-emitting diode is a Mini LED or a Micro LED.
  • parasitic capacitances will be generated between the data line and the first node N1, the second node N2 and the third node N3, resulting in writing into the gate of the third transistor T3.
  • the voltage of the poles deviates, resulting in bad crosstalk and affecting the display effect.
  • An embodiment of the present application also provides a display device, including the above-mentioned pixel driving circuit.
  • the above-mentioned display device may be a flexible display device (also called a flexible screen) or a rigid display device (that is, a display screen that cannot be bent), which is not limited here.
  • the above-mentioned display device can be an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display device, a Micro LED display device or a Mini LED display device, as well as any TV, digital camera, mobile phone, tablet computer, etc. including these display devices.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • Micro LED display device or a Mini LED display device, as well as any TV, digital camera, mobile phone, tablet computer, etc. including these display devices.
  • Products or components with display functions; the above display devices can also be used in fields such as identity recognition and medical equipment. Products that have been promoted or have good promotion prospects include security identity authentication, smart door locks, medical image collection, etc.
  • the display device can work at different refresh frequencies, has better display effects at low refresh frequencies, ideal capacitor charging rate and Vth detection accuracy, high die-cutting yield, low cost, good display effect, long life, and stability It has the advantages of high performance, high contrast, good imaging quality, and high product quality.
  • Embodiments of the present application further provide a control method for the above-mentioned pixel driving circuit.
  • the control method includes:
  • one frame of display picture is refreshed through the first reset stage, the writing stage, the compensation stage and the first light-emitting stage.
  • the fifth transistor and the ninth transistor are both N-type oxide transistors, and the first, second, third, fourth, sixth, seventh and eighth transistors are all P-type low-temperature polysilicon.
  • a negative voltage signal is input to the first gate line Gate_P, and a negative voltage signal is input to the first reset signal line AZ_P, the first luminescence control signal line EM1, and the first luminescence control signal Both the line EM2 and the second gate line Gate_N input positive voltage signals.
  • the first transistor T1 , the fifth transistor T5 , the fourth transistor T4 and the ninth transistor T9 are all turned on, and the second transistor T2 , the third transistor T3 , the sixth transistor T6 and the seventh transistor T7 , the eighth transistor T8 are both turned off.
  • the data signal of the data signal line Data can be written into the third node N3, and the third node N3 is refreshed. Since both the fourth transistor T4 and the ninth transistor T9 are turned on, the initial signal of the first initial signal line Vinit1 can be written into the first node N1, and the first node N1 is reset. Since the fifth transistor T5 is turned on, the voltage signal of the first voltage signal line VDD can be written into the second node N2, and the second node N2 is reset.
  • a negative voltage signal is input to the first reset signal line AZ_P, and a negative voltage signal is input to the first gate line Gate_P, the first light-emitting control signal line EM1, the first light-emitting control signal line EM2 and the second gate line.
  • Line Gate_N all inputs positive voltage signals.
  • the first node N1 turns on the third transistor under the control of the initial signal of the first initial signal line Vinit1, and the second transistor is turned on, the voltage signal of the first voltage signal line VDD can be written into the first node N1, and the first node N1 Compensate to VDD+Vth potential. Since the sixth transistor T6 is turned on, the reset signal of the first reset signal line AZ_P can be written into the anode of the light-emitting transistor to reset the anode.
  • stage t31 a negative voltage signal is input to the first light emission control signal line EM1, and a positive voltage signal is input to the first reset signal line AZ_P, the first gate line Gate_P, the first light emission control signal line EM2 and the second gate line Gate_N.
  • stage t31 a negative voltage signal is input to the first light emission control signal line EM1
  • a positive voltage signal is input to the first reset signal line AZ_P, the first gate line Gate_P, the first light emission control signal line EM2 and the second gate line Gate_N.
  • the seventh transistor T7 is turned on, the control signal of the first light-emitting control signal line EM1 can be written to the third node N3, and the potential on the third node N3 jumps from Vdata to Vref, so that the second The potential on the node N2 becomes VDD+(Vref-VData), the potential on the first node N1 becomes VDD+Vth+(Vref-VData), and the third transistor T3 is turned on.
  • stage t32 negative voltage signals are input to both the first light-emitting control signal line EM1 and the first light-emitting control signal line EM2, and positive voltage signals are input to the first reset signal line AZ_P, the first gate line Gate_P and the second gate line Gate_N. .
  • both the third transistor T3 and the eighth transistor T8 are turned on, and the light-emitting diode emits light.
  • the current calculation formula has nothing to do with the voltage signal of the first voltage signal line VDD. That is, the pixel driving circuit provided by the embodiment of the present application can also compensate for the voltage of the first voltage signal line VDD.
  • the fifth, ninth, tenth and eleventh transistors are all N-type oxide transistors, and the first, second, third, fourth, sixth, seventh and As an example, the eighth transistors are all P-type low-temperature polysilicon transistors.
  • the pixel driving circuit shown in Figure 3 provided by the embodiment of the present application operates at the same refresh frequency (high refresh frequency). or low refresh frequency) will be introduced in detail. It should be noted that in Figures 11 to 14, the transistor is turned off and marked with " ⁇ ", and the light-emitting diode does not emit light is also marked with " ⁇ ".
  • negative voltage signals are input to the first gate line Gate_P, the second gate line RST2_N and the second reset signal line AZ_N, and the first and second gate lines Gate_P and the second reset signal line AZ_N are inputted with negative voltage signals.
  • the gate line RST1_N, the first light emission control signal line EM1, the first light emission control signal line EM2 and the first reset signal line AZ_P all input positive voltage signals. At this time, as shown in FIG.
  • the first transistor T1 , the eleventh transistor T11 and the fourth transistor T4 are all turned on, and the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the sixth transistor T6 and the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are all turned off. Since the first transistor T1 is turned on, the data signal of the data signal line Data can be written into the third node N3, and the third node N3 is refreshed. Since the fourth transistor T4 is turned on, the initial signal of the first initial signal line Vinit1 can be written into the first node N1, and the first node N1 is reset. Since the eleventh transistor T11 is turned on, the voltage signal of the first voltage signal line VDD can be written into the second node N2, and the second node N2 is reset.
  • negative voltage signals are input to both the first and second gate lines RST1_N and the first reset signal line AZ_P, and the negative voltage signals are input to the first and second gate lines Gate_P, the second and second gate lines RST2_N, and the second reset signal line AZ_P.
  • the reset signal line AZ_N, the first light emission control signal line EM1 and the first light emission control signal line EM2 all input positive voltage signals.
  • the third node N3 holds the data signal written by the data signal line Data.
  • the second node N2 maintains the voltage signal written by the first voltage signal line VDD. Since the first node N1 turns on the third transistor under the control of the initial signal of the first initial signal line Vinit1, and the second transistor is turned on, the voltage signal of the first voltage signal line VDD can be written into the first node N1, and the first node N1 Compensate to VDD+Vth potential. Since the sixth transistor T6 is turned on, the reset signal of the first reset signal line AZ_P can be written into the anode of the light-emitting transistor to reset the anode.
  • negative voltage signals are input to the first and second gate lines RST1_N, the first light-emitting control signal line EM1, the second and second gate lines RST2_N, and the second reset signal line AZ_N, and the first reset signal line AZ_P and the second reset signal line AZ_N are inputted with negative voltage signals.
  • a gate line Gate_P and a first light emission control signal line EM2 both input positive voltage signals.
  • the seventh transistor T7 is turned on, the control signal of the first light-emitting control signal line EM1 can be written to the third node N3, and the potential on the third node N3 jumps from Vdata to Vref, so that the second The potential on the node N2 becomes VDD+(Vref-VData), the potential on the first node N1 becomes VDD+Vth+(Vref-VData), and the third transistor T3 is turned on.
  • negative voltage signals are input to the first and second gate lines RST1_N, the first and second light-emitting control signal lines EM1, the second and second gate lines RST2_N, the second reset signal line AZ_N, and the first light-emitting control signal line EM2.
  • the first reset signal line AZ_P and the first gate line Gate_P both input positive voltage signals.
  • both the third transistor T3 and the eighth transistor T8 are turned on, and the light-emitting diode emits light.
  • the above process can also be applied to the timing diagram shown in Figure 16 to control the pixel driving circuit diagram shown in Figure 15.
  • Figure 15 adds a twelfth transistor T12 on the basis of Figure 1 and a thirteenth transistor T13. Therefore, as shown in Figure 16, during the first reset stage and writing stage, that is, the t1 stage in Figure 16, the third light-emitting control signal line EM3 inputs a positive voltage signal, and the thirteenth transistor T13 is turned off; the scanning signal line Scan inputs a negative voltage signal. The voltage signal turns on the twelfth transistor T12, thereby performing a source-drain reset on the third transistor T3 (ie, the driving transistor).
  • the scanning signal line Scan inputs a positive voltage signal, and the twelfth transistor T12 is turned off; the third light-emitting control signal line EM3 inputs a negative voltage signal and turns on the thirteenth transistor T13, so that the voltage signal of the first voltage signal line VDD is input to the third transistor T3.
  • This can perform source-drain reset on the driving transistor, keep the driving transistor on in a stable state, and solve the problem of low gray-scale flickering of the pixel driving circuit at low refresh frequency.
  • the first reset signal line to which the control electrode of the sixth transistor in FIG. 15 is electrically connected can be replaced by a scan signal line.
  • the timing in FIG. 17 needs to be changed, which will not be described again here.
  • At least two GOA circuits are required to implement the timing diagram in Figure 6, in which one GOA circuit controls the first reset signal line AZ_P, and other signal lines are controlled by one GOA circuit.
  • the pixel driving circuit shown in Figure 3 can also be controlled through a GOA circuit.
  • corresponding signal lines and timing diagrams are required.
  • the sixth transistor is controlled by the first gate line Gate_P
  • the second transistor is controlled by the first gate line Gate_P.
  • the control of the second gate line RST2_N will not be described again here.
  • the embodiment of the present application provides the first and second gate lines RST1_N, the first light-emitting control signal line EM1, the second second gate line RST2_N, the second reset signal line AZ_N, and the first light-emitting control signal line.
  • the driving timing signals of the line EM2, the first reset signal line AZ_P, and the first gate line Gate_P are just one of the situations. In practical applications, the driving signals of other timings can also be used.
  • n-1 in Figure 4 represents the signal of the previous row, and n represents the signal of this row.
  • the specific relationship between the effective pulse width of the negative voltage signal input to the first reset signal line AZ_P during the above compensation phase and the effective pulse width of the negative voltage signal input to the first gate line Gate_P during the above writing phase can be based on Determine the model and size of the display device.
  • the ratio range between the duration of the negative voltage signal input to the first reset signal line AZ_P in the above compensation phase and the duration of the negative voltage signal input to the first gate line Gate_P in the above writing phase includes 3-32, for example, write
  • the duration of the negative voltage signal input to the first gate line Gate_P in the entry stage is 1H
  • the duration of the negative voltage signal input to the first reset signal line AZ_P in the compensation stage is 3H, 5H, 6H, 7H, 8H, 10H, 12H, 15H. etc.
  • the specific application shall prevail. Therefore, since the Vth detection time in the compensation phase is effectively increased, the Vth detection accuracy can be further improved, and the short-term afterimage and Mura problems can be effectively improved.
  • the above control method can be applied to the pixel driving circuit described in the above embodiment, and the structure of the pixel driving circuit can be as shown in Figure 1, Figure 2 or Figure 3.
  • the pixel driving circuit can refresh one frame of display screen at different frequencies, and the display effects at different frequencies are better.
  • the Vdt refresh process of writing the Data signal to the third node is separated from the process of detecting the threshold voltage Vth, the problem of insufficient Vth detection time is effectively solved, thereby achieving a more ideal capacitor charging rate and Vth Seize accuracy and achieve better display results.
  • An embodiment of the present application further provides a control method for the above-mentioned pixel driving circuit.
  • the control method includes:
  • the above-mentioned first refresh frequency may be a high refresh frequency (for example: a refresh frequency of 100HZ).
  • the timing of the pixel driving circuit when operating at a high refresh frequency may refer to the above embodiment, that is, FIG. 1 and FIG. 2 refer to the timing of FIG. 4.
  • FIG. 3 Refer to the timing sequence in Figure 6, which will not be described again here.
  • the first refresh of one frame of display picture is achieved through the first reset stage, the writing stage, the compensation stage and the first lighting stage, and the first refresh of one frame of display picture is achieved through the second reset stage.
  • the first stage and the second light-emitting stage realize the refresh of one frame of display screen in addition to the first refresh.
  • the above-mentioned second refresh frequency may be a low refresh frequency (for example, a refresh frequency of 10HZ).
  • a low refresh frequency for example, a refresh frequency of 10HZ.
  • the fifth transistor and the ninth transistor are both N-type oxide transistors, and the first, second, third, fourth, sixth, seventh and eighth transistors are all P-type low-temperature polysilicon.
  • the pixel driving circuit shown in Figure 1 provided by the embodiment of the present application operates at the same refresh frequency (high refresh frequency or low refresh frequency). The working principle is introduced in detail.
  • a negative voltage signal is input to the first gate line Gate_P, and a negative voltage signal is input to the first reset signal line AZ_P, the first luminescence control signal line EM1, and the first luminescence control signal Both the line EM2 and the second gate line Gate_N input positive voltage signals.
  • the first transistor T1 , the fifth transistor T5 , the fourth transistor T4 and the ninth transistor T9 are all turned on, and the second transistor T2 , the third transistor T3 , the sixth transistor T6 and the seventh transistor T7 , the eighth transistor T8 are both turned off.
  • the data signal of the data signal line Data can be written into the third node N3, and the third node N3 is refreshed. Since both the fourth transistor T4 and the ninth transistor T9 are turned on, the initial signal of the first initial signal line Vinit1 can be written into the first node N1, and the first node N1 is reset. Since the fifth transistor T5 is turned on, the voltage signal of the first voltage signal line VDD can be written into the second node N2, and the second node N2 is reset.
  • a negative voltage signal is input to the first reset signal line AZ_P, and a negative voltage signal is input to the first gate line Gate_P, the first light-emitting control signal line EM1, the first light-emitting control signal line EM2 and the second gate line.
  • Lines Gate_N all input positive voltage signals.
  • the first node N1 turns on the third transistor under the control of the initial signal of the first initial signal line Vinit1, and the second transistor is turned on, the voltage signal of the first voltage signal line VDD can be written into the first node N1, and the first node N1 Compensate to VDD+Vth potential. Since the sixth transistor T6 is turned on, the reset signal of the first reset signal line AZ_P can be written into the anode of the light-emitting transistor to reset the anode.
  • stage t31 a negative voltage signal is input to the first light emission control signal line EM1, and a positive voltage signal is input to the first reset signal line AZ_P, the first gate line Gate_P, the first light emission control signal line EM2 and the second gate line Gate_N.
  • stage t31 a negative voltage signal is input to the first light emission control signal line EM1
  • a positive voltage signal is input to the first reset signal line AZ_P, the first gate line Gate_P, the first light emission control signal line EM2 and the second gate line Gate_N.
  • the seventh transistor T7 is turned on, the control signal of the first light-emitting control signal line EM1 can be written to the third node N3, and the potential on the third node N3 jumps from Vdata to Vref, so that the second The potential on the node N2 becomes VDD+(Vref-VData), the potential on the first node N1 becomes VDD+Vth+(Vref-VData), and the third transistor T3 is turned on.
  • stage t32 negative voltage signals are input to both the first light-emitting control signal line EM1 and the first light-emitting control signal line EM2, and positive voltage signals are input to the first reset signal line AZ_P, the first gate line Gate_P and the second gate line Gate_N. .
  • both the third transistor T3 and the eighth transistor T8 are turned on, and the light-emitting diode emits light.
  • the current calculation formula has nothing to do with the voltage signal of the first voltage signal line VDD. That is, the pixel driving circuit provided by the embodiment of the present application can also compensate for the voltage of the first voltage signal line VDD.
  • a negative voltage signal is input to the first reset signal line AZ_P, the first light-emitting control signal line EM1, the first light-emitting control signal line EM2, the first gate line Gate_P and the second The gate lines Gate_N all input positive voltage signals.
  • the sixth transistor T6 is turned on, and the reset signal of the first reset signal line AZ_P can be written into the anode of the light-emitting transistor to reset the anode.
  • a negative voltage signal is input to the first light-emitting control signal line EM1, and the first light-emitting control signal line EM2, the first reset signal line AZ_P, the first gate line Gate_P and the Both gate lines Gate_N input positive voltage signals.
  • both the third transistor T3 and the eighth transistor T8 are turned on, and the light-emitting diode emits light.
  • the above control method can be applied to the pixel driving circuit described in the above embodiment, and the structure of the pixel driving circuit can be as shown in Figure 1 or Figure 2.
  • the third light emitting control signal line EM3 first inputs a positive voltage signal, and the thirteenth transistor T13 is turned off; the scanning signal line Scan first inputs a negative voltage signal , the twelfth transistor T12 is turned on, thereby performing a source-drain reset of the third transistor T3 (ie, the driving transistor); then in the t4 stage and t5 stage in Figure 17, the scanning signal line Scan inputs a high voltage signal, and the twelfth transistor T12 Close; the third light emitting control signal line EM3 inputs the third voltage signal and turns on the thirteenth transistor T13, so that the voltage signal of the first voltage signal line VDD is written into the third transistor T3.
  • This can perform source-drain reset on the driving transistor, keep the driving transistor in a stable on-state, and solve the problem of low gray-scale flickering of the pixel driving circuit at low refresh frequency.
  • the first reset signal line to which the control electrode of the sixth transistor in FIG. 15 is electrically connected can be replaced by a scan signal line.
  • the timing in FIG. 17 needs to be changed, which will not be described again here.
  • n-1 in Figure 5 and Figure 17 represents the signal of the previous row, and n represents the signal of this row.
  • the refresh of the next frame display screen at a high refresh frequency can be achieved through the first reset stage, writing stage, compensation stage and first light-emitting stage; at the same time, the anode can be turned on in time sequence through the second reset stage and the second light-emitting stage to perform high-refresh
  • the frame rate is reset, so that the refresh of the next frame display screen at a low refresh frequency is achieved through the first reset stage, writing stage, compensation stage, first light-emitting stage, and the second reset stage and the second light-emitting stage, and enables the pixel driving circuit Leakage can be reduced during the light-emitting maintenance stage, avoiding the flicker phenomenon that occurs when switching is required after the second light-emitting stage is completed, effectively solving the problem of low gray-scale flickering.
  • Embodiments of the present application provide a control method through which the above-mentioned pixel driving circuit can drive the light-emitting diode to emit light; the control method has simple driving timing and is easy to implement.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

本申请提供了一种像素驱动电路及其控制方法、显示装置，涉及显示技术领域，该像素驱动电路被配置为在不同的刷新频率下驱动发光二极管发光，包括：第一控制模块和第二控制模块，补偿模块，刷新模块，第一复位模块，第一发光控制模块，驱动模块和第二发光控制模块。本申请提供的像素驱动电路，通过保持第一节点、第二节点的电位，从而可以使得像素驱动电路在不同的刷新频率下工作，并有效的解决了Vth检获时间不足的问题。

Description

一种像素驱动电路及其控制方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路及其控制方法、显示装置。
背景技术
随着技术的不断发展，用户希望显示装置既可以支持高刷新频率，以避免闪烁，又可以支持低刷新频率，以减小功耗。然而，目前的显示装置无法同时兼顾高刷新频率与低刷新频率的需求，导致不能满足用户要求，用户体验低。
发明内容
本申请的实施例采用如下技术方案：
一方面，本申请的实施例提供了一种像素驱动电路，该像素驱动电路被配置为在不同的刷新频率下驱动发光二极管发光，包括：
第一控制模块和第二控制模块，所述第一控制模块电连接第一栅线、第一初始信号线和第一节点，被配置为在所述第一栅线的栅极信号的控制下，将所述第一初始信号线的初始信号写入所述第一节点，并在不同刷新频率下保持所述第一节点的电位；所述第二控制模块电连接第二栅线、第一电压信号线和第二节点，被配置为在所述第二栅线的栅极信号的控制下，将所述第一电压信号线的电压信号写入所述第二节点，并在不同刷新频率下保持所述第二节点的电位；
补偿模块，电连接复位信号线、第四节点和所述第一节点，在所述复位信号线的复位信号的控制下，将所述第四节点和所述第一节点之间的路径导通，并在不同刷新频率下保持所述第一节点的电位；
刷新模块，电连接所述第一栅线、数据信号线和第三节点，被配置为在所述第一栅线的栅极信号的控制下，将所述数据信号线的数据信号写入所述第三节点；
第一复位模块，电连接所述复位信号线、所述第一初始信号线和所述发光二极管的阳极，被配置为在所述复位信号线的复位信号的控制下，通过所述第一初始信号线的初始信号对所述阳极进行复位；
第一发光控制模块，电连接第一发光控制信号线、第二电压信号线、所述第三节点和所述第一节点，被配置为在所述第一发光控制信号线的 控制信号的控制下，将所述第二电压信号线的电压信号写入所述第三节点；
驱动模块和第二发光控制模块，所述驱动模块电连接所述第一节点、所述第一电压信号线和所述第四节点，所述第二发光控制模块电连接所述第二发光控制信号线、所述第四节点和所述阳极，所述驱动模块和所述第二发光控制模块分别被配置为在所述第一节点和所述第二发光控制信号线的控制下，将用于使所述发光二极管发光的电信号传输至所述阳极。
可选地，所述像素驱动电路还包括：
第二复位模块，电连接扫描信号线、所述第二初始信号线和第六节点，被配置为在所述扫描信号线的扫描信号的控制下，通过所述第二初始信号线的初始信号对所述驱动模块进行复位；
第三发光控制模块，电连接第三发光控制信号线、所述第一电压信号线和所述第六节点，被配置为在所述第三发光控制信号线的第三发光控制信号的控制下，将所述第一电压信号线的第一电压信号写入所述驱动模块。
可选地，所述补偿模块包括第二晶体管；
所述第二晶体管的控制极电连接所述复位信号线、第一极电连接所述第四节点、第二极电连接所述第一节点。
可选地，所述补偿模块包括第二晶体管和第九晶体管；
所述第二晶体管的控制极电连接所述复位信号线、第一极电连接所述第四节点、第二极电连接所述第九晶体管的第一极；
所述第九晶体管的控制极电连接所述第二栅线、第二极电连接所述第一节点。
可选地，所述第二控制模块包括第五晶体管；
所述第五晶体管的控制极电连接所述第二栅线、第一极电连接所述第一电压信号线、第二极电连接所述第二节点。
可选地，所述第二控制模块包括第十晶体管和第十一晶体管；
所述第十晶体管的控制极电连接第一第二栅线、第一极电连接所述第一电压信号线、第二极电连接所述第二节点；
所述第十一晶体管的控制极电连接第二第二栅线、第一极电连接所述第一电压信号线、第二极电连接所述第二节点。
可选地，所述第一控制模块包括第四晶体管；
所述第四晶体管的控制极电连接所述第一栅线、第一极电连接所述第一初始信号线、第二极电连接所述第一节点。
可选地，所述刷新模块包括第一晶体管；
所述第一晶体管的控制极电连接所述第一栅线、第一极电连接所述数据信号线、第二极电连接所述第三节点。
可选地，所述第一复位模块包括第六晶体管；
所述第六晶体管的控制极电连接所述复位信号线、第一极电连接所述第一初始信号线、第二极电连接所述阳极。
可选地，所述第一发光控制模块包括第七晶体管、第一电容和第二电容；
所述第七晶体管的控制极电连接所述第一发光控制信号线、第一极电连接所述第二电压信号线、第二极电连接所述第三节点；
所述第一电容的第一极电连接所述第三节点、第二极电连接所述第二节点；
所述第二电容的第一极电连接所述第二节点、第二极电连接所述第一节点。
可选地，所述驱动模块包括第三晶体管；
所述第三晶体管的控制极电连接所述第一节点、第一极电连接所述第一电压信号线、第二极电连接所述第四节点。
可选地，所述第二发光控制模块包括第八晶体管；
所述第八晶体管的控制极电连接所述第二发光控制信号线、第一极电连接所述第四节点、第二极电连接所述阳极。
可选地，所述第二复位模块包括十二晶体管；所述第十二晶体管的控制极电连接所述扫描信号线、第一极电连接所述第二初始信号线、第二极电连接所述第六节点；
所述第三发光控制模块包括十三晶体管；所述第十三晶体管的控制极电连接所述第三发光控制信号线、第一极电连接所述第一电压信号线、第二极电连接所述第六节点。
可选地，所述第二晶体管包括氧化物晶体管。
可选地，所述第九晶体管包括氧化物晶体管，所述第二晶体管包括非氧化物晶体管。
可选地，所述第五晶体管包括氧化物晶体管。
可选地，所述第十晶体管和所述第十一晶体管中的至少一个包括氧化物晶体管。
可选地，所述第四晶体管包括氧化物晶体管。
另一方面，本申请的实施例提供了一种显示装置，包括上述的像素驱动电路。
又一方面，本申请的实施例提供了一种上述像素驱动电路的控制方法，所述方法包括：
在不同的刷新频率下，在一帧显示画面周期里，通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段实现所述一帧显示画面的刷新。
再一方面，本申请的实施例提供了一种上述像素驱动电路的控制方法，所述方法包括：
在第一刷新频率下，在一帧显示画面周期里，通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段实现所述一帧显示画面的刷新；
在第二刷新频率下，在一帧显示画面周期里，通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段实现所述一帧显示画面的第一次刷新，并通过第二复位阶段和第二发光阶段实现所述一帧显示画面除所述第一次刷新以外的刷新。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请实施例提供的一种像素驱动电路的示意图；
图2为本申请实施例提供的另一种像素驱动电路的示意图；
图3为本申请实施例提供的又一种像素驱动电路的示意图；
图4为本申请实施例提供的一种像素驱动电路的驱动时序图；
图5为本申请实施例提供的另一种像素驱动电路的驱动时序图；
图6为本申请实施例提供的又一种像素驱动电路的驱动时序图；
图7-图10为图1的像素驱动电路在图4的驱动时序下的驱动原理示意图；
图11-图14为图3的像素驱动电路在图6的驱动时序下的驱动原理示意图；
图15为本申请实施例提供的再一种像素驱动电路的示意图；
图16为本申请实施例提供的再一种像素驱动电路的驱动时序图；
图17为本申请实施例提供的还一种像素驱动电路的驱动时序图。
具体实施例
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在图中，相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本申请的示意性图解，并非一定是按比例绘制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本申请的实施例中，采用“第一”、“第二”、“第三”、“第四”、“第五”、“第六”、“第七”、“第八”、“第九”、“第十”、“第十一”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐 含指明所指示的技术特征的数量。
在本申请的实施例中，将晶体管的栅极称为控制极，将源极和漏极中的一个称为第一极、另一个称为第二极。本申请实施例中，以所有晶体管的第一极称为漏极，第二极称为源极为例进行说明。
在本申请的实施例中，术语“电连接”可以是指两个组件直接电连接，也可以是指两个组件之间经由一个或多个其它组件电连接。
本申请的实施例提供了一种像素驱动电路，该像素驱动电路被配置为在不同的刷新频率下驱动发光二极管发光。参考图1所示，该像素驱动电路包括：
第一控制模块11和第二控制模块12，第一控制模块11电连接第一栅线Gate_P、第一初始信号线Vinit1和第一节点N1，被配置为在第一栅线Gate_P的栅极信号的控制下，将第一初始信号线Vinit1的初始信号写入第一节点N1，并在不同刷新频率下保持第一节点N1的电位；第二控制模块12电连接第二栅线Gate_N、第一电压信号线VDD和第二节点N2，被配置为在第二栅线Gate_N的栅极信号的控制下，将第一电压信号线VDD的电压信号写入第二节点N2，并在不同刷新频率下保持第二节点N2的电位。
示例的，像素驱动电路在高刷新频率(例如：120HZ的刷新频率)下工作时，可以保持住第一节点和第二节点的电位，第一节点和第二节点基本不存在漏电的情况。而当像素驱动电路在低刷新频率(例如：30Hz以下，例如10HZ，1Hz或者更低的刷新频率)下工作时，由于低刷新频率下的刷新时间较长，第一节点和第二节点容易发生漏电，导致无法实现正常显示，因此需要使得像素驱动电路在低刷新频率下也能保持住第一节点和第二节点的电位，从而使得像素驱动电路在低刷新频率下也能实现正常的显示。
对于上述像素驱动电路在低刷新频率下如何保持第一节点和第二节点的电位的具体实现方式不做限定。示例的，可以设置与第一节点和第二节点相连的至少一个晶体管为氧化物晶体管，以减小发光阶段下第一节点、第二节点的漏电流，例如将漏电流减小到1e-15A以下，从而可以在发光阶段更好的保持第一节点、第二节点的电位，避免显示不良。图1以第五晶体管T5和第九晶体管T9均为氧化物晶体管为例进行绘示，从而可以通过第五晶体管T5保持第二节点N2在发光阶段的电位、通过第九晶体管T9保持第一节点N1在发光阶段的电位。图2以第五晶体管T5、第二晶体管T2和第四晶体管T4均为氧化物晶体管为例进行绘示，从而可以通过第五晶体管T5 保持第二节点N2在发光阶段的电位、通过第二晶体管T2和第四晶体管T4保持第一节点N1在发光阶段的电位。图3以第十晶体管T10、第十一晶体管T11、第二晶体管T2和第四晶体管T4均为氧化物晶体管为例进行绘示，从而可以通过第十晶体管T10和第十一晶体管T11保持第二节点N2在发光阶段的电位、通过第二晶体管T2和第四晶体管T4保持第一节点N1在发光阶段的电位。
对于上述氧化物晶体管中有源层的材料不做具体限定。示例的，上述氧化物晶体管中有源层的材料可以包括IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)、ITZO(Indium Tin Zinc Oxide，铟锡锌氧化物)、IZO(Indium Zinc Oxide，氧化铟锌)等等。
这里对于上述第二控制模块包括的晶体管的种类和数量均不做具体限定。示例的，参考图1和图2所示，第二控制模块12包括第五晶体管T5，此时第五晶体管T5为氧化物晶体管，从而可以通过第五晶体管T5保持第二节点N2在发光阶段的电位；参考图3所示，第二控制模块12包括第十晶体管T10和第十一晶体管T11，此时第十晶体管T10和第十一晶体管T11均为氧化物晶体管，从而可以通过第十晶体管T10和第十一晶体管T11保持第二节点N2在发光阶段的电位。
补偿模块2，电连接复位信号线AZ(图1中的第一复位信号线AZ_P)、第四节点N4和第一节点N1，在复位信号线AZ(图1中的第一复位信号线AZ_P)的复位信号的控制下，将第四节点N4和第一节点N1之间的路径导通，并在不同刷新频率下保持第一节点N1的电位。
这里对于上述复位信号线的数量不做具体限定。示例的，参考图1所示，复位信号线AZ包括第一复位信号线AZ_P；或者，参考图2和图3所示，复位信号线AZ包括第一复位信号线AZ_P和第二复位信号线AZ_N。
示例的，像素驱动电路在高刷新频率(例如：120HZ的刷新频率)下工作时，可以保持住第一节点的电位，第一节点基本不存在漏电情况。而当像素驱动电路在低刷新频率(例如：30Hz以下，例如10HZ，1Hz或者更低的刷新频率)下工作时，由于低刷新频率下的刷新时间较长，导致第一节点容易漏电，导致无法实现正常显示，因此需要使得像素驱动电路在低刷新频率下也能保持住第一节点的电位，从而使得像素驱动电路在低刷新频率下也能实现正常显示。
这里对于上述补偿模块包括的晶体管的种类和数量均不做具体限定。示 例的，参考图1所示，补偿模块2包括第二晶体管T2和第九晶体管T9，此时第九晶体管T9为氧化物晶体管，从而可以通过第九晶体管T9保持第一节点N1在发光阶段的电位；参考图2和图3所示，补偿模块2包括第二晶体管T2，此时第二晶体管T2为氧化物晶体管、且第四晶体管也为氧化物晶体管，从而可以通过第二晶体管T9和第四晶体管T4保持第一节点N1在发光阶段的电位。
刷新模块3，电连接第一栅线Gate_P、数据信号线Data和第三节点N3，被配置为在第一栅线Gate_P的栅极信号的控制下，将数据信号线Data的数据信号写入第三节点N3。
第一复位模块4，电连接复位信号线AZ(图1中的第一复位信号线AZ_P)、第一初始信号线Vinit1和发光二极管的阳极，被配置为在复位信号线AZ(图1中的第一复位信号线AZ_P)的复位信号的控制下，通过第一初始信号线Vinit1的初始信号对阳极进行复位。
第一发光控制模块5，电连接第一发光控制信号线EM1、第二电压信号线Vref、第三节点N3和第一节点N1，被配置为在第一发光控制信号线EM1的控制信号的控制下，将第二电压信号线Vref的电压信号写入第三节点N3。
驱动模块61和第二发光控制模块62，驱动模块61电连接第一节点N1、第一电压信号线VDD和第四节点N4，第二发光控制模块62电连接第一发光控制信号线EM2、第四节点N4和阳极，驱动模块61和第二发光控制模块62分别被配置为在第一节点N1和第一发光控制信号线EM2的控制下，将用于使发光二极管发光的电信号传输至阳极。
参考图1、图2和图3所示，上述发光二极管的阳极可以电连接第五节点N5，发光二极管的阴极可以电连接接地端VSS。
上述第一控制模块、第二控制模块、补偿模块、刷新模块、第一复位模块、第一发光控制模块、第二发光控制模块和第三发光控制模块的具体电路结构不做限定，只要满足相应功能即可。
上述第一节点、第二节点、第三节点、第四节点和第五节点只是为了便于描述电路结构而定义的，第一节点、第二节点、第三节点、第四节点和第五节点并不是一个实际的电路单元。
需要说明的是，第一，除了上述的氧化物晶体管以外，图1、图2和图3中的其它晶体管可以均为非氧化物晶体管，例如LTPS(Low Temperature Poly-silicon，低温多晶硅)晶体管。当然，上述其它晶体管中的至少一个晶 体管也可以为氧化物晶体管，这里不做具体限定。
第二，图1以第五晶体管T5和第九晶体管T9共用一条第二栅线Gate_N为例进行绘示，当然第五晶体管T5和第九晶体管T9还可以分别设置各自的第二栅线Gate_N，具有以实际应用为准。
本申请实施例提供的像素驱动电路中，通过第一控制模块、补偿模块在不同刷新频率下保持第一节点的电位、通过第二控制模块在不同刷新频率下保持第二节点的电位，且刷新模块对第三节点写入信号的过程与补偿模块进行阈值电压补偿的过程可以分别实现。从而一方面，通过保持第一节点、第二节点的电位，可以使得像素驱动电路在不同的刷新频率下工作，即该像素驱动电路能够切换不同的刷新频率工作状态，适用范围更广，且该像素驱动电路在低刷新频率下工作的状态较为稳定。另一方面，由于将Data信号写入第三节点的Vdt刷新过程与进行阈值电压Vth检获的过程分离，有效的解决了Vth检获时间不足的问题，从而可以实现较理想的电容充电率和Vth检获精度，并实现更好的显示效果。那么通过第一控制模块、第二控制模块、补偿模块、刷新模块、第一复位模块、第一发光控制模块、第二发光控制模块和第三发光控制模块的相互配合，使得发光二极管能够在不同的刷新频率下均进行较为稳定的发光，且Vth补偿时间可调，Vth补偿时间较为充足，可以有效改善短期残像和Mura问题。
可选地，参考图15所示，像素驱动电路还包括：
第二复位模块7，电连接扫描信号线Scan、第二初始信号线Vinit2和第六节点N6，被配置为在扫描信号线Scan的扫描信号的控制下，通过第二初始信号线Vinit2的初始信号对驱动模块61进行复位。
第三发光控制模块8，电连接第三发光控制信号线EM3、第一电压信号线VDD和第六节点N6，被配置为在第三发光控制信号线EM3的第三发光控制信号的控制下，将第一电压信号线VDD的第一电压信号写入驱动模块61。
上述第六节点只是为了便于描述电路结构而定义的，第六节点并不是一个实际的电路单元。
可选地，参考图2和图3所示，补偿模块2包括第二晶体管T2；第二晶体管T2的控制极电连接复位信号线AZ(图2和图3中的第二复位信号线AZ_N)、第一极电连接第四节点N4、第二极电连接第一节点N1。从而可以通过第二晶体管保持第一节点的电位，使得像素驱动电路可以在不同刷新 频率下均实现较好的显示效果。
这里对于上述第二晶体管的类型不做具体限定。示例的，上述第二晶体管可以是氧化物晶体管。
可选地，参考图1所示，补偿模块2包括第二晶体管T2和第九晶体管T9；第二晶体管T2的控制极电连接复位信号线AZ(图1中的第一复位信号线AZ_P)、第一极电连接第四节点N4、第二极电连接第九晶体管T9的第一极；第九晶体管T9的控制极电连接第二栅线Gate_N、第二极电连接第一节点N1。从而可以通过第九晶体管保持第一节点的电位，使得像素驱动电路可以在不同刷新频率下均实现较好的显示效果。
这里对于上述第九晶体管的类型不做具体限定。示例的，上述第二晶体管可以是氧化物晶体管。
这里对于上述第二晶体管的类型不做具体限定。示例的，上述第二晶体管可以是非氧化物晶体管，例如低温多晶硅晶体管。
可选地，参考图1和图2所示，第二控制模块12包括第五晶体管T5；第五晶体管的控制极电连接第二栅线Gate_N、第一极电连接第一电压信号线VDD、第二极电连接第二节点N2。从而可以通过第五晶体管保持第二节点的电位，使得像素驱动电路可以在不同刷新频率下均实现较好的显示效果。
这里对于上述第二栅线的数量不做具体限定，可以根据第二控制模块中薄膜晶体管的数量确定。若第二控制模块包括一个薄膜晶体管，例如图1和图2中的第五晶体管T5，则此时第二栅线的数量为一条；若第二控制模块包括两个薄膜晶体管，例如图3中的第十晶体管T10和第十一晶体管T11，则此时第二栅线的数量为两条(分别为图3中的第一第二栅线RST1_N和第二第二栅线RST2_N)。
可选地，参考图3所示，第二控制模块12包括第十晶体管T10和第十一晶体管T11；第十晶体管T10的控制极电连接第一第二栅线RST1_N、第一极电连接第一电压信号线VDD、第二极电连接第二节点N2；第十一晶体管T11的控制极电连接第二第二栅线RST2_N、第一极电连接第一电压信号线VDD、第二极电连接第二节点N2。从而可以通过第十晶体管和第十一晶体管保持第二节点的电位，使得像素驱动电路可以在不同刷新频率下均实现较好的显示效果。
可选地，参考图1、图2和图3所示，第一控制模块11包括第四晶体管T4；第四晶体管T4的控制极电连接第一栅线Gate_P、第一极电连接第一初 始信号线Vinit1、第二极电连接第一节点N1。
参考图2和图3所示，在补偿模块2仅包括第二晶体管T2的情况下，第四晶体管T4和第二晶体管T2均为氧化物晶体管，从而可以通过第四晶体管T4和第二晶体管T2保持第一节点N1的电位。
可选地，参考图1、图2和图3所示，刷新模块3包括第一晶体管T1；第一晶体管T1的控制极电连接第一栅线Gate_P、第一极电连接数据信号线Data、第二极电连接第三节点N3。
可选地，参考图1、图2和图3所示，第一复位模块4包括第六晶体管T6；第六晶体管T6的控制极电连接复位信号线AZ(图1、图2和图3中的第一复位信号线AZ_P)、第一极电连接第一初始信号线Vinit1、第二极电连接阳极。
可选地，参考图1、图2和图3所示，第一发光控制模块5包括第七晶体管T7、第一电容Cst和第二电容Cvth；第七晶体管T7的控制极电连接第一发光控制信号线EM1、第一极电连接第二电压信号线Vref、第二极电连接第三节点N3；第一电容Cst的第一极电连接第三节点N3、第二极电连接第二节点N2；第二电容Cvth的第一极电连接第二节点N2、第二极电连接第一节点N1。
可选地，参考图1、图2和图3所示，驱动模块61包括第三晶体管T3；第三晶体管T3的控制极电连接第一节点N1、第一极电连接第一电压信号线VDD、第二极电连接第四节点N4。本申请实施例中的第三晶体管的磁滞弛豫时间长，可以有效改善短期残像和Mura问题。
可选地，参考图1、图2和图3所示，第二发光控制模块62包括第八晶体管T8；第八晶体管T8的控制极电连接第一发光控制信号线EM2、第一极电连接第四节点N4、第二极电连接阳极。
可选地，参考图15所示，第二复位模块7包括十二晶体管T12；第十二晶体管T12的控制极电连接扫描信号线Scan、第一极电连接第二初始信号线Vinit2、第二极电连接第六节点N6。
所述第三发光控制模块8包括十三晶体管；第十三晶体管T13的控制极电连接第三发光控制信号线EM3、第一极电连接第一电压信号线VDD、第二极电连接第六节点N6。
可选地，第二晶体管包括氧化物晶体管。
这里对于上述氧化物晶体管中有源层的材料不做具体限定。示例的，上 述氧化物晶体管中有源层的材料可以包括IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)、ITZO(Indium Tin Zinc Oxide，铟锡锌氧化物)、IZO(Indium Zinc Oxide，氧化铟锌)等等。
参考图2和图3所示，第二晶体管T2包括氧化物晶体管，此时通过第二晶体管T2可以保持第一节点N1的电位。
需要说明的是，在图2和图3中，还可以设置第四晶体管T4包括氧化物晶体管，此时通过第二晶体管T2和第四晶体管T4可以共同保持第一节点N1的电位。
可选地，第九晶体管包括氧化物晶体管，第二晶体管包括非氧化物晶体管。
这里对于上述非氧化物晶体管中有源层的材料不做具体限定。示例的，上述非氧化物晶体管中有源层的材料可以包括LTPS等等。
参考图1所示，第九晶体管T9包括氧化物晶体管，此时通过第九晶体管T9可以保持第一节点N1的电位。
需要说明的是，此时对于第二晶体管和第四晶体管的类型不做具体限定，第二晶体管和第四晶体管可以为氧化物晶体管，也可以为非氧化物晶体管，具体以实际应用为准。
可选地，第五晶体管包括氧化物晶体管。
参考图1和图2所示，第五晶体管T5包括氧化物晶体管，此时通过第五晶体管T5可以保持第二节点N2的电位。
可选地，第十晶体管和第十一晶体管中的至少一个包括氧化物晶体管。
上述第十晶体管和第十一晶体管中的至少一个包括氧化物晶体管是指：上述第十晶体管包括氧化物晶体管；或者，上述第十一晶体管包括氧化物晶体管；或者，上述第十晶体管和第十一晶体管均包括氧化物晶体管。参考图3所示，第十晶体管T10和第十一晶体管T11均包括氧化物晶体管，此时通过第十晶体管T10和第十一晶体管T11可以保持第二节点N2的电位。
可选地，所述第四晶体管包括氧化物晶体管。
参考图2和图3所示，第四晶体管T4包括氧化物晶体管，此时通过第四晶体管T4可以保持第一节点N1的电位。
需要说明的是，在图2和图3中，还可以设置第二晶体管T2包括氧化物晶体管，此时通过第二晶体管T2和第四晶体管T4可以共同保持第一节点N1的电位。
为了制作工艺统一，且便于后续电路的驱动方法更简单，上述氧化物晶体管均为N型晶体管，非氧化物晶体管均为P型晶体管。当然，上述氧化物晶体管也可以均为P型晶体管，非氧化物晶体管也可以均为N型晶体管；或者，上述所有晶体管也可以均为N型晶体管；或者，上述所有晶体管也可以均为P型晶体管的情况，设计原理与本申请类似，也属于本申请保护的范围。
上述对于晶体管的类型不做限定，其可以是薄膜晶体管，该薄膜晶体管可以是低温多晶硅薄膜晶体管或者氧化物薄膜晶体管。
需要说明的是，第一，若上述像素驱动电路应用于OLED显示装置，则上述发光二极管为有机发光二极管。若上述像素驱动电路应用于Mini LED显示装置或Micro LED显示装置，则上述发光二极管为Mini LED或者Micro LED。
第二，在进行像素驱动电路的版图(Layout)结构设计时，由于数据线与第一节点N1、第二节点N2和第三节点N3之间会产生寄生电容，导致写入第三晶体管T3栅极的电压出现偏差，产生串扰不良，影响显示效果。那么为了避免该问题发生，需要通过例如增大数据线与各节点之间的距离，以减小数据线与各节点之间的寄生电容。
本申请的实施例还提供了一种显示装置，包括上述的像素驱动电路。
上述显示装置可以是柔性显示装置(又称柔性屏)，也可以是刚性显示装置(即不能折弯的显示屏)，这里不做限定。
上述显示装置可以是OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置，还可以是Micro LED显示装置或者Mini LED显示装置，以及包括这些显示装置的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件；上述显示装置还可以应用于身份识别、医疗器械等领域，已推广或具有很好推广前景的产品包括安防身份认证、智能门锁、医疗影像采集等。该显示装置具有能够在不同的刷新频率下工作、低刷新频率下显示效果较好、较理想的电容充电率和Vth检获精度、模切良率高、成本低、显示效果好、寿命长、稳定性高、对比度高、成像质量好、产品品质高等优点。
本申请的实施例又提供了一种如上述像素驱动电路的控制方法，该控制方法包括：
S1、在不同的刷新频率下，在一帧显示画面周期里，通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段实现一帧显示画面的刷新。
下面以第五晶体管和第九晶体管均为N型氧化物晶体管，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第六晶体管、第七晶体管和第八晶体管均为P型低温多晶硅晶体管为例，结合如图4所示的各信号线的时序图，对本申请实施例提供的如图1所示的像素驱动电路在同一刷新频率(高刷新频率或低刷新频率)下的工作原理进行详细介绍。需要说明的是，图7至图10中，晶体管关闭通过“×”标记，发光二极管不发光也通过“×”标记。
在第一复位阶段和写入阶段，即图4中的t1阶段，向第一栅线Gate_P输入负电压信号，向第一复位信号线AZ_P、第一发光控制信号线EM1、第一发光控制信号线EM2和第二栅线Gate_N均输入正电压信号。此时，参考图7所示，第一晶体管T1、第五晶体管T5、第四晶体管T4和第九晶体管T9均打开，第二晶体管T2、第三晶体管T3、第六晶体管T6、第七晶体管T7、第八晶体管T8均关闭。由于第一晶体管T1打开，数据信号线Data的数据信号可以写入第三节点N3，第三节点N3刷新。由于第四晶体管T4和第九晶体管T9均打开，第一初始信号线Vinit1的初始信号可以写入第一节点N1，第一节点N1复位。由于第五晶体管T5打开，第一电压信号线VDD的电压信号可以写入第二节点N2，第二节点N2复位。
在补偿阶段，即图4中的t2阶段，向第一复位信号线AZ_P输入负电压信号，向第一栅线Gate_P、第一发光控制信号线EM1、第一发光控制信号线EM2和第二栅线Gate_N均输入正电压信号。此时，参考图8所示，由于第七晶体管T7关闭，第三节点N3保持数据信号线Data写入的数据信号。由于第五晶体管T5打开，第二节点N2保持第一电压信号线VDD写入的电压信号。由于第一节点N1在第一初始信号线Vinit1的初始信号的控制下打开第三晶体管，且第二晶体管打开，第一电压信号线VDD的电压信号可以写入第一节点N1，第一节点N1补偿至VDD+Vth电位。由于第六晶体管T6打开，第一复位信号线AZ_P的复位信号可以写入发光晶体管的阳极，对阳极进行复位。
在第一发光阶段，即图4中的t31阶段和t32阶段。在t31阶段，向第一发光控制信号线EM1输入负电压信号，向第一复位信号线AZ_P、第一栅线Gate_P、第一发光控制信号线EM2和第二栅线Gate_N均输入正电压信号。此时，参考图9所示，第七晶体管T7打开，第一发光控制信号线EM1的控制信号可以写入第三节点N3，第三节点N3上的电位从Vdata跳变到Vref，使得第二节点N2上的电位变为VDD+(Vref-VData)，第一节点N1 上的电位变为VDD+Vth+(Vref-VData)，第三晶体管T3打开。
在t32阶段，向第一发光控制信号线EM1和第一发光控制信号线EM2均输入负电压信号，向第一复位信号线AZ_P、第一栅线Gate_P和第二栅线Gate_N均输入正电压信号。此时，参考图10所示，第三晶体管T3和第八晶体管T8均打开，发光二极管发光，此时发光二极管上流过的电流I的计算公式为I＝k(Vgs-Vth) 2，其中，k为常数，Vgs为第三晶体管T3的栅源电压。再代入上述t31阶段中的公式得到最终发光二极管上流过的电流I的计算公式为I＝k(Vref-Vdt) 2。可以看到该电流计算公式与第一电压信号线VDD的电压信号无关，即本申请实施例提供的像素驱动电路还可以补偿第一电压信号线VDD的电压。
下面以第五晶体管、第九晶体管、第十晶体管和第十一晶体管均为N型氧化物晶体管，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第六晶体管、第七晶体管和第八晶体管均为P型低温多晶硅晶体管为例，结合如图6所示的各信号线的时序图，对本申请实施例提供的如图3所示的像素驱动电路在同一刷新频率(高刷新频率或低刷新频率)下的工作原理进行详细介绍。需要说明的是，图11至图14中，晶体管关闭通过“×”标记，发光二极管不发光也通过“×”标记。
在第一复位阶段和写入阶段，即图6中的t1阶段，向第一栅线Gate_P、第二第二栅线RST2_N和第二复位信号线AZ_N均输入负电压信号，向第一第二栅线RST1_N、第一发光控制信号线EM1、第一发光控制信号线EM2和第一复位信号线AZ_P均输入正电压信号。此时，参考图11所示，第一晶体管T1、第十一晶体管T11和第四晶体管T4均打开，第二晶体管T2、第三晶体管T3、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10均关闭。由于第一晶体管T1打开，数据信号线Data的数据信号可以写入第三节点N3，第三节点N3刷新。由于第四晶体管T4打开，第一初始信号线Vinit1的初始信号可以写入第一节点N1，第一节点N1复位。由于第十一晶体管T11打开，第一电压信号线VDD的电压信号可以写入第二节点N2，第二节点N2复位。
在补偿阶段，即图6中的t2阶段，向第一第二栅线RST1_N、第一复位信号线AZ_P均输入负电压信号，向第一栅线Gate_P、第二第二栅线RST2_N、第二复位信号线AZ_N、第一发光控制信号线EM1、第一发光控制信号线EM2均输入正电压信号。此时，参考图12所示，由于第七晶体管T7关闭， 第三节点N3保持数据信号线Data写入的数据信号。由于第十晶体管T10打开，第二节点N2保持第一电压信号线VDD写入的电压信号。由于第一节点N1在第一初始信号线Vinit1的初始信号的控制下打开第三晶体管，且第二晶体管打开，第一电压信号线VDD的电压信号可以写入第一节点N1，第一节点N1补偿至VDD+Vth电位。由于第六晶体管T6打开，第一复位信号线AZ_P的复位信号可以写入发光晶体管的阳极，对阳极进行复位。
在第一发光阶段，即图6中的t31阶段和t32阶段。在t31阶段，向第一第二栅线RST1_N、第一发光控制信号线EM1、第二第二栅线RST2_N、第二复位信号线AZ_N均输入负电压信号，向第一复位信号线AZ_P、第一栅线Gate_P、第一发光控制信号线EM2均输入正电压信号。此时，参考图13所示，第七晶体管T7打开，第一发光控制信号线EM1的控制信号可以写入第三节点N3，第三节点N3上的电位从Vdata跳变到Vref，使得第二节点N2上的电位变为VDD+(Vref-VData)，第一节点N1上的电位变为VDD+Vth+(Vref-VData)，第三晶体管T3打开。
在t32阶段，向第一第二栅线RST1_N、第一发光控制信号线EM1、第二第二栅线RST2_N、第二复位信号线AZ_N、第一发光控制信号线EM2均输入负电压信号，向第一复位信号线AZ_P、第一栅线Gate_P均输入正电压信号。此时，参考图14所示，第三晶体管T3和第八晶体管T8均打开，发光二极管发光，此时发光二极管上流过的电流I的计算公式为I＝k(Vgs-Vth) 2，其中，k为常数，Vgs为第三晶体管T3的栅源电压。再代入上述t31阶段中的公式得到最终发光二极管上流过的电流I的计算公式为I＝k(Vref-Vdt) 2。可以看到该电流计算公式与第一电压信号线VDD的电压信号无关，即本申请实施例提供的像素驱动电路还可以补偿第一电压信号线VDD的电压。
需要说明的是，第一，以上过程还可以适用于图16所示的时序图控制图15所示的像素驱动电路图，区别之处在于图15在图1的基础上增加了第十二晶体管T12和第十三晶体管T13。因此参考图16所示，在第一复位阶段和写入阶段，即图16中的t1阶段，第三发光控制信号线EM3输入正电压信号，第十三晶体管T13关闭；扫描信号线Scan输入负电压信号，打开第十二晶体管T12，从而对第三晶体管T3(即驱动晶体管)进行源漏复位。
在补偿阶段，即图16中的t2阶段，以及第一发光阶段，即图16中的t31和t32阶段，扫描信号线Scan输入正电压信号，第十二晶体管T12关闭；第三发光控制信号线EM3输入负电压信号，打开第十三晶体管T13，从而 使得第一电压信号线VDD的电压信号输入第三晶体管T3。这样能够对驱动晶体管进行源漏复位，保持驱动晶体管开启状态稳定，解决像素驱动电路在低刷新频率下的低灰阶闪烁问题。
当然，图15中的第六晶体管的控制极电连接的第一复位信号线可以被扫描信号线替代，此时需要改变图17中的时序，这里不再赘述。
第二，需要至少两个GOA电路实现图6中的时序图，其中，一个GOA电路控制第一复位信号线AZ_P，其它信号线由一个GOA电路控制。当然，也可以通过一个GOA电路实现对图3所示的像素驱动电路的控制，此时需要对应的信号线和时序图，例如将第六晶体管由第一栅线Gate_P控制、第二晶体管由第二第二栅线RST2_N控制，这里不再赘述。
第三，为了驱动时序简单，本申请实施例提供的第一第二栅线RST1_N、第一发光控制信号线EM1、第二第二栅线RST2_N、第二复位信号线AZ_N、第一发光控制信号线EM2、第一复位信号线AZ_P、第一栅线Gate_P的驱动时序信号只是其中的一种情况，在实际应用中，还可以是其它时序的驱动信号。
第四，图4、图6和图16中的n-1代表上一行的信号，n代表本行的信号，
第五，在上述补偿阶段向第一复位信号线AZ_P输入的负电压信号的有效脉宽与上述写入阶段向第一栅线Gate_P输入的负电压信号的有效脉宽之间的具体关系可以根据显示装置的型号、尺寸等进行确定。示例的，上述补偿阶段向第一复位信号线AZ_P输入的负电压信号的时长与上述写入阶段向第一栅线Gate_P输入的负电压信号的时长之间的比值范围包括3-32，例如写入阶段向第一栅线Gate_P输入的负电压信号的时长为1H、补偿阶段向第一复位信号线AZ_P输入的负电压信号的时长为3H，5H，6H，7H，8H，10H，12H，15H等，具体以实际应用为准。从而由于有效增加了补偿阶段中Vth检获时长，能够更进一步提高Vth检获精度，可以有效改善短期残像和Mura问题。
上述控制方法可以应用于上述实施例所述的像素驱动电路，该像素驱动电路的结构可以如图1、图2或者图3所示。
这样，通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段，一方面，可以实现像素驱动电路在不同频率下对一帧显示画面的刷新，且不同频率下的显示效果均较好；另一方面，由于将Data信号写入第三节点的Vdt 刷新过程与进行阈值电压Vth检获的过程分离，有效的解决了Vth检获时间不足的问题，从而可以实现较理想的电容充电率和Vth检获精度，并实现更好的显示效果。
本申请的实施例再提供了一种如上述像素驱动电路的控制方法，该控制方法包括：
S2、在第一刷新频率下，在一帧显示画面周期里，通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段实现所述一帧显示画面的刷新。
上述第一刷新频率可以是高刷新频率(例如：100HZ的刷新频率)，像素驱动电路在高刷新频率下工作时的时序可以参考上述实施例，即图1和图2参照图4的时序，图3参照图6的时序，这里不再赘述。
S3、在第二刷新频率下，在一帧显示画面周期里，通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段实现一帧显示画面的第一次刷新，并通过第二复位阶段和第二发光阶段实现一帧显示画面除第一次刷新以外的刷新。
上述第二刷新频率可以是低刷新频率(例如：10HZ的刷新频率)，像素驱动电路在低刷新频率下工作时可以参照图4和图5所示的时序，具体进行如下说明。
下面以第五晶体管和第九晶体管均为N型氧化物晶体管，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第六晶体管、第七晶体管和第八晶体管均为P型低温多晶硅晶体管为例，结合如图4和图5所示的各信号线的时序图，对本申请实施例提供的如图1所示的像素驱动电路在同一刷新频率(高刷新频率或低刷新频率)下的工作原理进行详细介绍。
在第一复位阶段和写入阶段，即图4中的t1阶段，向第一栅线Gate_P输入负电压信号，向第一复位信号线AZ_P、第一发光控制信号线EM1、第一发光控制信号线EM2和第二栅线Gate_N均输入正电压信号。此时，参考图7所示，第一晶体管T1、第五晶体管T5、第四晶体管T4和第九晶体管T9均打开，第二晶体管T2、第三晶体管T3、第六晶体管T6、第七晶体管T7、第八晶体管T8均关闭。由于第一晶体管T1打开，数据信号线Data的数据信号可以写入第三节点N3，第三节点N3刷新。由于第四晶体管T4和第九晶体管T9均打开，第一初始信号线Vinit1的初始信号可以写入第一节点N1，第一节点N1复位。由于第五晶体管T5打开，第一电压信号线VDD的电压信号可以写入第二节点N2，第二节点N2复位。
在补偿阶段，即图4中的t2阶段，向第一复位信号线AZ_P输入负电压信号，向第一栅线Gate_P、第一发光控制信号线EM1、第一发光控制信号线EM2和第二栅线Gate_N均输入正电压信号。此时，参考图8所示，由于第七晶体管T7关闭，第三节点N3保持数据信号线Data写入的数据信号。由于第五晶体管T5打开，第二节点N2保持第一电压信号线VDD写入的电压信号。由于第一节点N1在第一初始信号线Vinit1的初始信号的控制下打开第三晶体管，且第二晶体管打开，第一电压信号线VDD的电压信号可以写入第一节点N1，第一节点N1补偿至VDD+Vth电位。由于第六晶体管T6打开，第一复位信号线AZ_P的复位信号可以写入发光晶体管的阳极，对阳极进行复位。
在第一发光阶段，即图4中的t31阶段和t32阶段。在t31阶段，向第一发光控制信号线EM1输入负电压信号，向第一复位信号线AZ_P、第一栅线Gate_P、第一发光控制信号线EM2和第二栅线Gate_N均输入正电压信号。此时，参考图9所示，第七晶体管T7打开，第一发光控制信号线EM1的控制信号可以写入第三节点N3，第三节点N3上的电位从Vdata跳变到Vref，使得第二节点N2上的电位变为VDD+(Vref-VData)，第一节点N1上的电位变为VDD+Vth+(Vref-VData)，第三晶体管T3打开。
在t32阶段，向第一发光控制信号线EM1和第一发光控制信号线EM2均输入负电压信号，向第一复位信号线AZ_P、第一栅线Gate_P和第二栅线Gate_N均输入正电压信号。此时，参考图10所示，第三晶体管T3和第八晶体管T8均打开，发光二极管发光，此时发光二极管上流过的电流I的计算公式为I＝k(Vgs-Vth) 2，其中，k为常数，Vgs为第三晶体管T3的栅源电压。再代入上述t31阶段中的公式得到最终发光二极管上流过的电流I的计算公式为I＝k(Vref-Vdt) 2。可以看到该电流计算公式与第一电压信号线VDD的电压信号无关，即本申请实施例提供的像素驱动电路还可以补偿第一电压信号线VDD的电压。
在第二复位阶段，即图5中的t4阶段，向第一复位信号线AZ_P输入负电压信号，第一发光控制信号线EM1、第一发光控制信号线EM2、第一栅线Gate_P和第二栅线Gate_N均输入正电压信号。此时，第六晶体管T6打开，第一复位信号线AZ_P的复位信号可以写入发光晶体管的阳极，对阳极进行复位。
在第二发光阶段，即图5中的t5阶段，向第一发光控制信号线EM1输 入负电压信号，向第一发光控制信号线EM2、第一复位信号线AZ_P、第一栅线Gate_P和第二栅线Gate_N均输入正电压信号。此时，第三晶体管T3和第八晶体管T8均打开，发光二极管发光。
上述控制方法可以应用于上述实施例所述的像素驱动电路，该像素驱动电路的结构可以如图1或者图2所示。
需要说明的是，第一，以上过程还可以适用于图17所示的时序图控制图15所示的像素驱动电路图，区别之处在于图15在图1的基础上增加了第十二晶体管T12和第十三晶体管T13。因此参考图17所示，在第二复位阶段，即图17中的t4阶段，第三发光控制信号线EM3先输入正电压信号，第十三晶体管T13关闭；扫描信号线Scan先输入负电压信号，第十二晶体管T12打开，从而对第三晶体管T3(即驱动晶体管)进行源漏复位；接着在图17中的t4阶段和t5阶段，扫描信号线Scan输入高电压信号，第十二晶体管T12关闭；第三发光控制信号线EM3输入第电压信号，打开第十三晶体管T13，从而使得第一电压信号线VDD的电压信号写入第三晶体管T3。这样能够对驱动晶体管进行源漏复位，保持驱动晶体管开启状态稳定，解决像素驱动电路在低刷新频率下的低灰阶闪烁问题。
当然，图15中的第六晶体管的控制极电连接的第一复位信号线可以被扫描信号线替代，此时需要改变图17中的时序，这里不再赘述。
第二，图5和图17中的n-1代表上一行的信号，n代表本行的信号。
这样可以通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段实现高刷新频率下一帧显示画面的刷新；同时可以通过第二复位阶段和第二发光阶段按时序开启对阳极进行高帧频复位，从而通过第一复位阶段、写入阶段、补偿阶段、第一发光阶段，以及第二复位阶段和第二发光阶段实现低刷新频率下一帧显示画面的刷新，并使得像素驱动电路在发光保持阶段可以减小漏电，避免第二发光阶段完成后需要进行切换时出现Flicker现象，有效的解决了低灰阶闪烁问题。
本申请的实施例提供了一种控制方法，通过该控制方法，可以实现上述像素驱动电路驱动发光二极管发光；该控制方法驱动时序简单、易实现。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其 限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (21)

  1. 一种像素驱动电路，其中，被配置为在不同的刷新频率下驱动发光二极管发光，所述像素驱动电路包括：
    第一控制模块和第二控制模块，所述第一控制模块电连接第一栅线、第一初始信号线和第一节点，被配置为在所述第一栅线的栅极信号的控制下，将所述第一初始信号线的初始信号写入所述第一节点，并在不同刷新频率下保持所述第一节点的电位；所述第二控制模块电连接第二栅线、第一电压信号线和第二节点，被配置为在所述第二栅线的栅极信号的控制下，将所述第一电压信号线的电压信号写入所述第二节点，并在不同刷新频率下保持所述第二节点的电位；
    补偿模块，电连接复位信号线、第四节点和所述第一节点，在所述复位信号线的复位信号的控制下，将所述第四节点和所述第一节点之间的路径导通，并在不同刷新频率下保持所述第一节点的电位；
    刷新模块，电连接所述第一栅线、数据信号线和第三节点，被配置为在所述第一栅线的栅极信号的控制下，将所述数据信号线的数据信号写入所述第三节点；
    第一复位模块，电连接所述复位信号线、所述第一初始信号线和所述发光二极管的阳极，被配置为在所述复位信号线的复位信号的控制下，通过所述第一初始信号线的初始信号对所述阳极进行复位；
    第一发光控制模块，电连接第一发光控制信号线、第二电压信号线、所述第三节点和所述第一节点，被配置为在所述第一发光控制信号线的控制信号的控制下，将所述第二电压信号线的电压信号写入所述第三节点；
    驱动模块和第二发光控制模块，所述驱动模块电连接所述第一节点、所述第一电压信号线和所述第四节点，所述第二发光控制模块电连接所述第二发光控制信号线、所述第四节点和所述阳极，所述驱动模块和所述第二发光控制模块分别被配置为在所述第一节点和所述第二发光控制信号线的控制下，将用于使所述发光二极管发光的电信号传输至所述阳极。
  2. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第二复位模块，电连接扫描信号线、所述第二初始信号线和第六节 点，被配置为在所述扫描信号线的扫描信号的控制下，通过所述第二初始信号线的初始信号对所述驱动模块进行复位；
    第三发光控制模块，电连接第三发光控制信号线、所述第一电压信号线和所述第六节点，被配置为在所述第三发光控制信号线的第三发光控制信号的控制下，将所述第一电压信号线的第一电压信号写入所述驱动模块。
  3. 根据权利要求1所述的像素驱动电路，其中，所述补偿模块包括第二晶体管；
    所述第二晶体管的控制极电连接所述复位信号线、第一极电连接所述第四节点、第二极电连接所述第一节点。
  4. 根据权利要求1所述的像素驱动电路，其中，所述补偿模块包括第二晶体管和第九晶体管；
    所述第二晶体管的控制极电连接所述复位信号线、第一极电连接所述第四节点、第二极电连接所述第九晶体管的第一极；
    所述第九晶体管的控制极电连接所述第二栅线、第二极电连接所述第一节点。
  5. 根据权利要求1所述的像素驱动电路，其中，所述第二控制模块包括第五晶体管；
    所述第五晶体管的控制极电连接所述第二栅线、第一极电连接所述第一电压信号线、第二极电连接所述第二节点。
  6. 根据权利要求1所述的像素驱动电路，其中，所述第二控制模块包括第十晶体管和第十一晶体管；
    所述第十晶体管的控制极电连接第一第二栅线、第一极电连接所述第一电压信号线、第二极电连接所述第二节点；
    所述第十一晶体管的控制极电连接第二第二栅线、第一极电连接所述第一电压信号线、第二极电连接所述第二节点。
  7. 根据权利要求1所述的像素驱动电路，其中，所述第一控制模块包括第四晶体管；
    所述第四晶体管的控制极电连接所述第一栅线、第一极电连接所述第一初始信号线、第二极电连接所述第一节点。
  8. 根据权利要求1所述的像素驱动电路，其中，所述刷新模块包括第一晶体管；
    所述第一晶体管的控制极电连接所述第一栅线、第一极电连接所述数据信号线、第二极电连接所述第三节点。
  9. 根据权利要求1所述的像素驱动电路，其中，所述第一复位模块包括第六晶体管；
    所述第六晶体管的控制极电连接所述复位信号线、第一极电连接所述第一初始信号线、第二极电连接所述阳极。
  10. 根据权利要求1所述的像素驱动电路，其中，所述第一发光控制模块包括第七晶体管、第一电容和第二电容；
    所述第七晶体管的控制极电连接所述第一发光控制信号线、第一极电连接所述第二电压信号线、第二极电连接所述第三节点；
    所述第一电容的第一极电连接所述第三节点、第二极电连接所述第二节点；
    所述第二电容的第一极电连接所述第二节点、第二极电连接所述第一节点。
  11. 根据权利要求1所述的像素驱动电路，其中，所述驱动模块包括第三晶体管；
    所述第三晶体管的控制极电连接所述第一节点、第一极电连接所述第一电压信号线、第二极电连接所述第四节点。
  12. 根据权利要求1所述的像素驱动电路，其中，所述第二发光控制模块包括第八晶体管；
    所述第八晶体管的控制极电连接所述第二发光控制信号线、第一极电连接所述第四节点、第二极电连接所述阳极。
  13. 根据权利要求2所述的像素驱动电路，其中，所述第二复位模块包括十二晶体管；所述第十二晶体管的控制极电连接所述扫描信号线、第一极电连接所述第二初始信号线、第二极电连接所述第六节点；
    所述第三发光控制模块包括十三晶体管；所述第十三晶体管的控制极电连接所述第三发光控制信号线、第一极电连接所述第一电压信号线、第二极电连接所述第六节点。
  14. 根据权利要求3所述的像素驱动电路，其中，所述第二晶体管包括氧化物晶体管。
  15. 根据权利要求4所述的像素驱动电路，其中，所述第九晶体管包括氧化物晶体管，所述第二晶体管包括非氧化物晶体管。
  16. 根据权利要求5所述的像素驱动电路，其中，所述第五晶体管包括氧化物晶体管。
  17. 根据权利要求6所述的像素驱动电路，其中，所述第十晶体管和所述第十一晶体管中的至少一个包括氧化物晶体管。
  18. 根据权利要求7所述的像素驱动电路，其中，所述第四晶体管包括氧化物晶体管。
  19. 一种显示装置，其中，包括权利要求1-18任一项所述的像素驱动电路。
  20. 一种用于控制权利要求1-18任一项所述的像素驱动电路的控制方法，其中，所述方法包括：
    在不同的刷新频率下，在一帧显示画面周期里，通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段实现所述一帧显示画面的刷新。
  21. 一种用于控制权利要求1-18任一项所述的像素驱动电路的控制方法，其中，所述方法包括：
    在第一刷新频率下，在一帧显示画面周期里，通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段实现所述一帧显示画面的刷新；
    在第二刷新频率下，在一帧显示画面周期里，通过第一复位阶段、写入阶段、补偿阶段和第一发光阶段实现所述一帧显示画面的第一次刷新，并通过第二复位阶段和第二发光阶段实现所述一帧显示画面除所述第一次刷新以外的刷新。
PCT/CN2022/102760 2022-06-30 2022-06-30 一种像素驱动电路及其控制方法、显示装置 WO2024000380A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/102760 WO2024000380A1 (zh) 2022-06-30 2022-06-30 一种像素驱动电路及其控制方法、显示装置
CN202280001975.9A CN117651991A (zh) 2022-06-30 2022-06-30 一种像素驱动电路及其控制方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/102760 WO2024000380A1 (zh) 2022-06-30 2022-06-30 一种像素驱动电路及其控制方法、显示装置

Publications (1)

Publication Number Publication Date
WO2024000380A1 true WO2024000380A1 (zh) 2024-01-04

Family

ID=89383738

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/102760 WO2024000380A1 (zh) 2022-06-30 2022-06-30 一种像素驱动电路及其控制方法、显示装置

Country Status (2)

Country Link
CN (1) CN117651991A (zh)
WO (1) WO2024000380A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100045578A (ko) * 2008-10-24 2010-05-04 엘지디스플레이 주식회사 유기전계 발광 디스플레이 장치
CN103927983A (zh) * 2014-03-27 2014-07-16 京东方科技集团股份有限公司 像素电路、显示基板和显示装置
CN104157240A (zh) * 2014-07-22 2014-11-19 京东方科技集团股份有限公司 像素驱动电路、驱动方法、阵列基板及显示装置
CN112908245A (zh) * 2021-02-24 2021-06-04 昆山国显光电有限公司 像素电路及其驱动方法、显示面板
CN113838420A (zh) * 2021-08-05 2021-12-24 京东方科技集团股份有限公司 像素电路、显示装置和驱动方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100045578A (ko) * 2008-10-24 2010-05-04 엘지디스플레이 주식회사 유기전계 발광 디스플레이 장치
CN103927983A (zh) * 2014-03-27 2014-07-16 京东方科技集团股份有限公司 像素电路、显示基板和显示装置
CN104157240A (zh) * 2014-07-22 2014-11-19 京东方科技集团股份有限公司 像素驱动电路、驱动方法、阵列基板及显示装置
CN112908245A (zh) * 2021-02-24 2021-06-04 昆山国显光电有限公司 像素电路及其驱动方法、显示面板
CN113838420A (zh) * 2021-08-05 2021-12-24 京东方科技集团股份有限公司 像素电路、显示装置和驱动方法

Also Published As

Publication number Publication date
CN117651991A (zh) 2024-03-05

Similar Documents

Publication Publication Date Title
US10083658B2 (en) Pixel circuits with a compensation module and drive methods thereof, and related devices
WO2023005621A1 (zh) 像素电路及其驱动方法、显示面板
WO2021043102A1 (zh) 驱动电路及其驱动方法、显示装置
WO2021238470A1 (zh) 像素电路及其驱动方法、显示面板
WO2017031909A1 (zh) 像素电路及其驱动方法、阵列基板、显示面板及显示装置
US11132951B2 (en) Pixel circuit, pixel driving method and display device
US11335269B2 (en) Pixel circuit, display substrate and display apparatus
WO2016173124A1 (zh) 像素电路、其驱动方法及相关装置
US20200035158A1 (en) Pixel driving circuit, method for driving the same and display device
WO2016155161A1 (zh) Oeld像素电路、显示装置及控制方法
CN114586091B (zh) 像素驱动电路及显示面板
US11355060B2 (en) Pixel circuit, method of driving pixel circuit, display panel and display device
CN107369412B (zh) 一种像素电路及其驱动方法、显示装置
US10157576B2 (en) Pixel driving circuit, driving method for same, and display apparatus
CN109949739B (zh) 一种像素电路、驱动方法及显示器
EP3843071A1 (en) Pixel unit, display panel and electronic device
US20210383753A1 (en) Pixel Drive Circuit and Drive Method Thereof, and Display Device
CN113851082B (zh) 像素驱动电路及其驱动方法、显示面板
WO2024021465A1 (zh) 像素驱动电路和显示面板
CN106652910B (zh) 像素电路及其驱动方法和有机发光显示器
WO2023005597A1 (zh) 像素驱动电路及显示面板
WO2023011327A1 (zh) 像素驱动电路及其驱动方法、显示基板和显示装置
WO2024000380A1 (zh) 一种像素驱动电路及其控制方法、显示装置
WO2022226727A1 (zh) 像素电路、像素驱动方法和显示装置
CN113066439A (zh) 一种像素电路、驱动方法、电致发光显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22948489

Country of ref document: EP

Kind code of ref document: A1