WO2023284124A1 - 存储器结构 - Google Patents

存储器结构 Download PDF

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Publication number
WO2023284124A1
WO2023284124A1 PCT/CN2021/120438 CN2021120438W WO2023284124A1 WO 2023284124 A1 WO2023284124 A1 WO 2023284124A1 CN 2021120438 W CN2021120438 W CN 2021120438W WO 2023284124 A1 WO2023284124 A1 WO 2023284124A1
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WIPO (PCT)
Prior art keywords
buffer
upper electrode
column
electrode layer
conductive
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Ceased
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PCT/CN2021/120438
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English (en)
French (fr)
Inventor
杨正杰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/575,143 priority Critical patent/US12293979B2/en
Publication of WO2023284124A1 publication Critical patent/WO2023284124A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Definitions

  • Embodiments of the present application relate to but are not limited to memory structures.
  • the memory is an electronic component widely used in various electronic devices. There are conductive pillars inside the memory, and the conductive pillars are used to electrically connect the capacitor structure and the upper metal layer.
  • An embodiment of the present application provides a memory structure, including: a capacitor structure, the capacitor structure has an upper electrode layer; a conductive column, the conductive column is located on the upper electrode layer, and is electrically connected to the upper electrode layer; a metal layer, the metal layer is located on the conductive column The side away from the upper electrode layer, and the conductive column is in contact with the surface of the metal layer facing the upper electrode layer; the buffer column, the buffer column and the conductive column are arranged at intervals, the buffer column is in contact with the surface of the metal layer facing the upper electrode layer, and The metal layer extends toward the upper electrode layer.
  • the number of the buffer column is single.
  • the metal layer has a symmetry axis, and the buffer pillars and the conductive pillars are symmetrically arranged according to the symmetry axis.
  • the length of the buffer column in a direction from the metal layer to the upper electrode layer, is the same as the length of the conductive column.
  • the material of the buffer column is the same as that of the conductive column.
  • the length of the buffer column in a direction from the metal layer to the upper electrode layer, is smaller than the length of the conductive column.
  • the length of the buffer column is at least 1/2 of the length of the conductive column.
  • the material of the buffer column includes an elastic material.
  • the material of the buffer column includes polyimide.
  • a plurality of buffer columns are arranged on the same side of the conductive column, and in the direction from the metal layer to the upper electrode layer, the plurality of buffer columns of the same length.
  • a plurality of buffer columns are arranged on the same side of the conductive column, along the direction that the buffer column points to the conductive column, the plurality of buffer columns
  • the length of the metal layer in a direction pointing to the upper electrode layer increases one by one.
  • the memory structure further includes: a sense amplifier, the conductive pillar is located on the side of the metal layer close to the sense amplifier, the buffer pillar is located on the on the side of the metal layer away from the sense amplifier.
  • the memory structure further includes: a dielectric layer, the dielectric layer is located on the surface of the upper electrode layer, and the conductive column and the buffer column are located in the dielectric layer .
  • each of the metal layers extends along a first direction, and the buffer pillars and the conductive pillars are arranged along the first direction.
  • the memory structure further includes: an electrical connection layer, the electrical connection layer is in a different layer from the metal layer, and each of the electrical connection layers extends along the second direction , the second direction is different from the first direction.
  • FIG. 1 is a schematic diagram of a cross-sectional structure corresponding to a memory structure
  • FIG. 2 is an enlarged view of a partial contact between a conductive column and an upper electrode layer corresponding to a memory structure
  • FIG. 3 is a schematic diagram of a top view structure corresponding to a memory structure provided by an embodiment of the present application
  • FIG. 4 is a schematic cross-sectional structural diagram corresponding to a memory structure provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of another cross-sectional structure corresponding to a memory structure provided by an embodiment of the present application.
  • FIG. 6 is a schematic top view structural diagram corresponding to a memory structure provided by another embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional structural diagram corresponding to a memory structure provided by another embodiment of the present application.
  • FIG. 8 is a schematic diagram of another cross-sectional structure corresponding to a memory structure provided by another embodiment of the present application.
  • FIG. 1 is a schematic cross-sectional structure diagram of a memory structure in the related art.
  • the memory structure includes a capacitor structure 10, and the capacitor structure 10 includes: a capacitor unit 100 and an upper electrode layer 101, and the upper electrode layer 101 covers at least the capacitor unit 100.
  • On the top and side surfaces of the upper electrode layer 101 there are conductive columns 102, and the conductive columns 102 are electrically connected to the upper electrode layer 101.
  • the metal layer 103 is located on the surface of the conductive column 102 away from the upper electrode layer 101.
  • FIG. 2 is an enlarged view of the partial contact between the conductive pillar 102 and the upper electrode layer 101 .
  • the metal layer 103 and the upper electrode layer 101 are electrically connected only through the conductive pillar 102, and the contact area only includes the end of the conductive pillar 102.
  • the delamination of the layer 101 causes the voltage provided by the capacitive structure 10 to be unstable, and the contact resistance between the conductive pillar 102 and the upper electrode layer 101 becomes larger.
  • the main source of external stress is the external force exerted on the memory by the outside world, such as the pressure on the memory from the machine during soldering during the process of installing the memory on electronic products.
  • the internal stress mainly comes from the memory. Internally, for example, when the internal temperature of the memory changes, the internal material of the memory undergoes changes such as thermal expansion and contraction, and the material properties between the film layers, such as the lattice constant, cause stress. Layer delamination.
  • the sizes of the conductive pillars 102 and the upper electrode layer 101 are correspondingly reduced, so that the contact area between the conductive pillars 102 and the upper electrode layer 101 is correspondingly reduced; when the conductive pillars 102 When the contact area with the upper electrode layer 101 is reduced, delamination between the conductive pillar 102 and the upper electrode layer 101 is more likely to occur.
  • the present application provides a memory structure in which a buffer column is provided on the surface of the metal layer facing the upper electrode layer.
  • a buffer column is provided on the surface of the metal layer facing the upper electrode layer.
  • FIG. 3 is a schematic top view of the memory structure
  • FIG. 4 is a schematic cross-sectional structure cut along the AA1 direction in FIG. 3
  • FIG. 5 is another cross-sectional structural schematic diagram cut along the AA1 direction in FIG. 3 .
  • the memory structure includes: a capacitor structure 20, the capacitor structure 20 has an upper electrode layer 201; a conductive column 202, the conductive column 202 is located on the upper electrode layer 201, and is electrically connected to the upper electrode layer 201; a metal layer 203, the metal layer 203 is located on the side of the conductive column 202 away from the upper electrode layer 201, and the conductive column 202 is in contact with the surface of the metal layer 203 facing the upper electrode layer 201; the buffer column 204, the buffer column 204 and the conductive column 202 are arranged at intervals, The buffer column 204 is in contact with the surface of the metal layer 203 facing the upper electrode layer 201 , and extends from the metal layer 203 toward the upper electrode layer 201 .
  • the buffer column 204 can share part of the stress so as to improve the stability of the connection between the conductive column 202 and the upper electrode layer 201 .
  • the capacitor structure 20 includes: a capacitor unit 200, the capacitor unit 200 at least includes a lower electrode layer and a capacitor medium layer located on the surface of the lower electrode layer; an upper electrode layer 201, the upper electrode layer 201 covers the top surface of the capacitor unit 200 and side.
  • the capacitive unit 200 may also include an upper electrode plate, the upper electrode plate is located on the surface of the capacitor medium layer, and the upper electrode layer 201 is located on the surface of the upper electrode plate, and the capacitive unit 200 is used for storing charges.
  • the upper electrode layer 201 can be polysilicon, doped polysilicon or metal and other conductive materials.
  • the upper electrode layer 201 covers the surface and sides of the capacitor unit 200.
  • the upper electrode layer 201 is used to transfer the charges stored in the capacitor unit 200 to the outside.
  • the material of the conductive pillar 202 may be a conductive material such as copper, aluminum or tungsten.
  • the conductive column 202 penetrates the surface of the upper electrode layer 201 and is electrically connected to the inside of the upper electrode layer 201 ; in other embodiments, the conductive column 202 may only be electrically connected to the surface of the upper electrode layer 201 .
  • the width of the conductive column 202 gradually decreases from a side away from the upper electrode layer 201 to a side closer to the upper electrode layer 201 in a direction parallel to the first direction. In some other embodiments, the width of the side of the conductive column 202 away from the upper electrode layer 201 is the same as the width of the side close to the upper electrode layer 201 parallel to the first direction.
  • the material of the metal layer 203 may be a conductive material such as copper, aluminum or tungsten.
  • the memory structure may include a plurality of metal layers 203 arranged along a second direction, and each metal layer 203 extends along a first direction, and the second direction is different from the first direction.
  • the first The second direction may be perpendicular to the first direction.
  • the buffer column 204 and the conductive column 202 are arranged on the metal layer 203 along the first direction, and in the direction from the metal layer 203 to the upper electrode layer 201, the length of the buffer column 204 is the same as the length of the conductive column 202, when the buffer column
  • the through hole of the conductive pillar and the through hole of the buffer pillar can be formed in one step, thereby reducing the number of process steps.
  • the width of the buffer column 204 gradually decreases from the side away from the upper electrode layer 201 to the width of the side close to the upper electrode layer 201 in parallel to the first direction; In the first direction, the width of the side of the buffer column 204 away from the upper electrode layer 201 is the same as the width of the side close to the upper electrode layer 201 .
  • the material of the buffer pillar 204 may be the same as that of the conductive pillar 202 . Since the material of the buffer column 204 and the conductive column 202 are the same material, the buffer column 204 and the conductive column 202 can be produced simultaneously in the same production process; and the material of the buffer column 204 is also a conductive material, and the upper electrode layer 201 and the metal layer are added. The contact area between 203 can reduce the contact resistance between the metal layer 203 and the upper electrode layer 201 .
  • the material of the buffer column 204 includes elastic material, specifically, the material of the buffer column 204 may be polyimide.
  • the material of the buffer column 204 is an elastic material.
  • the buffer column 204 can absorb a part of the stress, thereby reducing the stress on the body of the conductive column 202, thereby enhancing the connection between the conductive column 202 and the upper electrode layer 201. Stability; and the polyimide material itself has excellent mechanical properties and adhesive properties, making the connection between the upper electrode layer 201 and the metal layer 203 stronger.
  • the number of the buffer column 204 is single, when the conductive column 202 is subjected to stress, the buffer column 204 can share the stress on the conductive column 202, thereby strengthening the connection between the conductive column 202 and the upper surface.
  • the stability of the electrode layer 201 connection is single, when the conductive column 202 is subjected to stress, the buffer column 204 can share the stress on the conductive column 202, thereby strengthening the connection between the conductive column 202 and the upper surface.
  • the metal layer 203 has a symmetry axis, and the symmetry axis is parallel to the second direction, the extension length of the metal layer 203 in the first direction is symmetric along the symmetry axis, and the buffer column 204 and the conductive column 202 may be symmetric along the symmetry axis.
  • the buffer column 204 and the conductive column 202 are arranged symmetrically, the buffer column 204 and the conductive column 202 can evenly share the stress from the inside or the outside, thereby reducing the stress on the conductive column 202, thereby enhancing the connection between the conductive column 202 and the upper surface.
  • the stability of the connection of the electrode layer 201 in some other embodiments, the buffer column 204 may not be arranged symmetrically with the conductive column 202 about the symmetry axis of the metal layer 203 .
  • each metal layer 203 there are multiple buffer columns 204 , and the multiple buffer columns 204 are arranged on the metal layer 203 at intervals.
  • a plurality of buffer columns 204 are arranged at intervals along the first direction on the surface of the metal layer 203 close to the upper electrode layer 201, and in the direction from the metal layer 203 to the upper electrode layer 201, each buffer column
  • the length of the column 204 and the length of the conductive column 202 can be the same; when the lengths of the plurality of buffer columns 204 and the conductive column 202 are the same, it can be formed in one step when forming the conductive column through hole and the buffer column through hole, thereby reducing Process steps in the production process.
  • the materials of the plurality of buffer columns 204 may all be conductive materials or elastic materials;
  • the material is an elastic material.
  • all the conductive materials use the same material, and all the elastic materials use the same material to reduce the types of materials and facilitate production.
  • the memory structure may further include: a sense amplifier (SA, Sensor Amplifier) 209 .
  • SA Sensor Amplifier
  • the metal layer 203 is disposed adjacent to the sense amplifier 209 .
  • the conductive post 202 is located on the side of the metal layer 203 close to the sense amplifier 209, and the buffer post 204 is located on the side of the metal layer 203 away from the sense amplifier 209, so that the conductive post 202 transmits the signal to the sense amplifier 209. It will reduce the loss in the transmission process and reduce the signal transmission time.
  • the buffer column 204 is located on the side of the metal layer 203 close to the sense amplifier 209, and the conductive column 202 is located on the side of the metal layer 203 away from the sense amplifier 209, thus improving the memory protected by the buffer column 204.
  • the area inside the structure can better improve the stability of the connection between the conductive pillar 202 and the upper electrode layer 201, thereby reducing the increase in contact resistance between the conductive pillar 202 and the upper electrode layer 201 or the instability of the power supply voltage of the capacitor structure 20 possibility of the situation occurring.
  • the memory structure includes a memory cell, and the metal layer 203 , the conductive pillar 202 and the buffer pillar 204 are located at the memory cell, and the sense amplifier 209 is located at opposite sides of the memory cell.
  • the memory structure can also include: SWC (Sub Wordline Conjunction, word line connection) area 210, SWC area 210 is located at both sides opposite to sense amplifier 209; SWD (Sub Wrodline Drive, word line drive) area 211, SWD area 211 is located at On opposite sides of the cell, and the SWD region 211 is adjacent to the corresponding SWC region 210 .
  • SWC Sub Wordline Conjunction, word line connection
  • SWC area 210 is located at both sides opposite to sense amplifier 209
  • SWD (Sub Wrodline Drive, word line drive) area 211 SWD area 211 is located at On opposite sides of the cell, and the SWD region 211 is adjacent to the corresponding SWC region 210 .
  • the memory structure may further include a first insulating layer 205 , a second insulating layer 206 , an electrical connection layer 207 and a dielectric layer 208 .
  • the first insulating layer 205 covers the surface of the metal layer 203 away from the upper electrode layer 201.
  • the extension length of the first insulating layer 205 is greater than the extension length of the metal layer 203 in parallel to the first direction.
  • the first insulating layer 205 can be made of nitrogen.
  • a material that is not easily oxidized, such as silicon oxide, is used to protect the surface of the metal layer 203 away from the upper electrode layer 201 from being oxidized.
  • the second insulating layer 206 is spaced from the first insulating layer 205 in the direction from the upper electrode layer 201 to the metal layer 203.
  • the second insulating layer 206 can be a material that is not easily oxidized, such as silicon nitride, and can be used with The materials of the first insulating layer 205 are consistent, and the second insulating layer 206 can protect the surface of the electrical connection layer 207 from being oxidized.
  • electrical connection layers 207 are in different layers from the metal layer 203, arranged along the first direction on the side of the second insulating layer 206 close to the first insulating layer 205, and each electrical connection layer 207 extends along the second direction, the second The direction is different from the first direction, and there is at least one electrical connection layer 207 passing through the first insulating layer 205 and electrically connected to the metal layer 203 .
  • the electrical connection layer 207 is used to transmit the voltage of the capacitor structure 20 .
  • the electrical connection layer 207 may extend to the area where the SWD area 211 is located besides the storage unit.
  • the dielectric layer 208 is located on the surface of the upper electrode layer 201 , and the conductive column 202 and the buffer column 204 are located in the dielectric layer 208 .
  • the dielectric layer 208 can use materials such as silicon oxide to protect the conductive pillars 202, the metal layer 203, the buffer pillars 204, and the electrical connection layer 207 from reacting with air.
  • one or more buffer pillars 204 whose extension length is the same as that of the conductive pillars 202 in the direction from the metal layer 203 to the upper electrode layer 201 are additionally provided on the metal layer 203.
  • the pressure on the conductive pillars 202 improves the stability of the connection between the conductive pillars 202 and the upper electrode layer 201 .
  • Another embodiment of the present application also provides a memory structure, the memory structure provided by this embodiment is substantially the same as the previous embodiment, the main difference includes: in the direction from the metal layer to the upper electrode layer, the length of the buffer column is shorter than that of the conductive column length.
  • the memory structure provided by another embodiment of the present application will be described below with reference to the accompanying drawings. It should be noted that for parts that are the same as or corresponding to the foregoing embodiments, reference may be made to the corresponding descriptions of the foregoing embodiments, and details will not be repeated below.
  • FIG. 6 is a schematic diagram of a top view corresponding to the memory structure provided by another embodiment of the present application
  • FIG. 7 is a schematic diagram of a cross-sectional structure cut along the AA2 direction in FIG. 6
  • FIG. 8 is another diagram of the cut along the AA2 direction in FIG.
  • the memory structure includes: a capacitor structure 30, the capacitor structure 30 includes a capacitor unit 300, an upper electrode layer 301, a conductive column 302, a metal layer 303, a buffer column 304, a first insulating layer 305, and a second insulating layer 306 , an electrical contact layer 307 , and a dielectric layer 308 .
  • the memory structure may also include: sense amplifier 309 , SWC region 310 , SWD region 311 .
  • the length of the buffer pillar 304 is smaller than the length of the conductive pillar 302 .
  • the buffer column 304 is made of an elastic material, since the material of the buffer column 304 is different from that of the upper electrode layer 301, when the memory structure is thermally expanded, the buffer column 304 will not press the upper electrode layer 301, thereby protecting the upper electrode layer 301. .
  • the length of the buffer column 304 is at least 1/2 of the length of the conductive column 302 .
  • the length of the buffer column 304 is 1/2 of the conductive column 302
  • the use of materials can be saved while ensuring the stability of the memory structure.
  • the material of the buffer column 304 is set as an elastic material.
  • the material of the buffer column 304 is an elastic material
  • the buffer column 304 will absorb part of the stress and the buffer column 304 itself will share the stress.
  • the pressure on a part of the conductive pillars 302 further reduces the stress on the conductive pillars 302 , thereby improving the stability of the connection between the conductive pillars 302 and the upper electrode layer 301 .
  • the number of buffer posts 304 may be multiple, and the plurality of buffer posts 304 are arranged at intervals on the metal layer 303, and in some embodiments, A plurality of buffer columns 304 are arranged on the same side of the conductive column 302, and along the direction of the buffer column 304 pointing to the conductive column 302, the lengths of the plurality of buffer columns 304 in the direction from the metal layer 303 to the upper electrode layer 301 are sequentially increased one by one, Therefore, when the memory structure is subjected to stress, the force on the conductive pillar 302 will be reduced through the layer-by-layer protection of the plurality of buffer pillars 304 , thereby protecting the stability of the connection between the conductive pillar 302 and the upper electrode layer 301 .
  • multiple buffer columns 304 are arranged on the same side of the conductive column 302, and in the direction from the metal layer 303 to the upper electrode layer 301, the length of each buffer column 304 is the same, and in some embodiments The lengths of the buffer posts 304 are the same and shorter than the length of the conductive posts 302 . When the lengths of the plurality of buffer posts 304 are equal, multiple buffer post through holes can also be formed in the same process.
  • the buffer columns 304 are set to the same elastic material, so that the buffer columns 304 can not be replaced during the processing process.
  • the material is easy to produce, and a plurality of buffer columns 304 of elastic material can reduce the negative impact of more stress, and further improve the stability of the connection between the conductive column 302 and the upper electrode layer 301; in other embodiments, the buffer The pillars 304 are made of different elastic materials, and the modulus of elasticity of the material of the buffer pillars 304 decreases sequentially from the direction close to the sense amplifier 309 to the direction away from the sense amplifier 309, so that through a plurality of buffer pillars 304 layer by layer For protection, the force on the conductive pillar 302 will be reduced, and the elastic modulus of the buffer pillar 304 close to the sense amplifier 309 can increase the force bearing capacity of the memory structure.
  • a plurality of buffer columns 304 shorter than the length of the conductive columns 302 are provided on the metal layer 303 , so that the phenomenon of delamination between the conductive columns 302 and the upper electrode layer 301 can be improved while saving the use of materials.

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Abstract

本申请实施例提供一种存储器结构，包括：电容结构，电容结构具有上电极层；导电柱，导电柱位于上电极层上，且与上电极层接触电连接；金属层，金属层位于导电柱远离上电极层的一侧，且导电柱与金属层朝向上电极层的表面相接触；缓冲柱，缓冲柱与导电柱间隔设置，缓冲柱与金属层朝向上电极层的表面相接触，且自金属层向上电极层方向延伸。

Description

存储器结构
相关申请的交叉引用
本申请基于申请号为202110791853.1、申请日为2021年07月13日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于存储器结构。
背景技术
存储器是一种广泛应用在各种电子设备上的电子元器件，在存储器内部存在导电柱，导电柱用来电连接电容结构与上层金属层。
然而，现有技术中存在导电柱与电容结构之间分层的问题，从而导致导电柱与电容结构之间的接触电阻增加，或导致电容结构供电电压不稳定。
发明内容
本申请实施例提供一种存储器结构，包括：电容结构，电容结构具有上电极层；导电柱，导电柱位于上电极层上，且与上电极层接触电连接；金属层，金属层位于导电柱远离上电极层的一侧，且导电柱与金属层朝向上电极层的表面相接触；缓冲柱，缓冲柱与导电柱间隔设置，缓冲柱与金属层朝向上电极层的表面相接触，且自金属层向上电极层方向延伸。
在本申请的一种可选实施例中，所述缓冲柱的数量为单个。
在本申请的一种可选实施例中，所述金属层具有对称轴，且所述缓冲柱与所述导电柱依所述对称轴对称设置。
在本申请的一种可选实施例中，在自所述金属层指向所述上电极层的方向上，所述缓冲柱的长度与所述导电柱的长度相同。
在本申请的一种可选实施例中，所述缓冲柱的材料与所述导电柱的材料相同。
在本申请的一种可选实施例中，在自所述金属层指向所述上电极层的方向上，所述缓冲柱的长度小于所述导电柱的长度。
在本申请的一种可选实施例中，在自所述金属层指向所述上电极层的方向上，所述缓冲柱的长度至少为所述导电柱的长度的1/2。
在本申请的一种可选实施例中，所述缓冲柱的材料包括弹性材料。
在本申请的一种可选实施例中，所述缓冲柱的材料包括聚酰亚胺。
在本申请的一种可选实施例中，所述缓冲柱数量为多个，且多个所述缓冲柱在所述金属层上间隔设置。
在本申请的一种可选实施例中，多个所述缓冲柱设置在所述导电柱同一侧，且在自所述金属层指向所述上电极层的方向上，多个所述缓冲柱的长度相同。
在本申请的一种可选实施例中，多个所述缓冲柱设置在所述导电柱同一侧，沿所述缓冲柱指向所述导电柱的方向上，多个所述缓冲柱在自所述金属层指向所述上电极层的方向上的长度依次逐个增加。
在本申请的一种可选实施例中，所述存储器结构还包括：感测放大器，所述导电柱位于所述金属层上靠近所述感测放大器的一侧，所述缓冲柱位于所述金属层上远离所述感测放大器的一侧。
在本申请的一种可选实施例中，所述存储器结构还包括：介质层，所述介质层位于所述上电极层表面，且所述导电柱以及所述缓冲柱位于所述介质层内。
在本申请的一种可选实施例中，每一所述金属层沿第一方向延伸，且 所述缓冲柱与所述导电柱沿所述第一方向排布。
在本申请的一种可选实施例中，所述存储器结构还包括：电连接层，所述电连接层与所述金属层处于不同层，且每一所述电连接层沿第二方向延伸，所述第二方向与所述第一方向不同。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1为一种存储器结构对应的剖面结构示意图；
图2为一种存储器结构对应的导电柱与上电极层局部接触放大图；
图3为本申请一实施例提供的存储器结构对应的一种俯视结构示意图；
图4为本申请一实施例提供的存储器结构对应的一种剖面结构示意图；
图5为本申请一实施例提供的存储器结构对应的另一种剖面结构示意图；
图6为本申请另一实施例提供的存储器结构对应的一种俯视结构示意图；
图7为本申请另一实施例提供的存储器结构对应的一种剖面结构示意图；
图8为本申请另一实施例提供的存储器结构对应的另一种剖面结构示意图。
具体实施方式
由背景技术可知，目前导电柱与上电极层之间连接的稳定性有待提高。
图1为相关技术中一种存储器结构的剖面结构示意图，参考图1，存储器结构包括电容结构10，电容结构10包括：电容单元100与上电极层101，上电极层101至少覆盖在电容单元100的顶面及侧面，在上电极层101表 面存在导电柱102，且导电柱102与上电极层101接触电连接，金属层103位于导电柱102远离上电极层101一侧的表面，金属层103远离导电柱102一侧的表面覆盖第一绝缘层104，在第一绝缘层104远离金属层103一侧的表面间隔设置一个第二绝缘层105，在第一绝缘层104和第二绝缘层105之间间隔设置若干电连接层106，且存在至少一个电连接层106穿过第一绝缘层104与金属层103接触电连接，在第一绝缘层104及第二绝缘层105表面还存在介质层107。参考图2，图2为导电柱102与上电极层101局部接触放大图。
经分析发现，金属层103与上电极层101仅通过导电柱102实现电连接，且接触面积仅包括导电柱102末端，当存储器结构工作发热，或是受到外力时，导电柱102易与上电极层101脱层导致电容结构10提供的电压不稳定，且导电柱102与上电极层101之间的接触电阻变大。
应力分为外部应力和内部应力，外部应力主要来源为外界给存储器施加的外部力量，例如将存储器安装在电子产品上的过程中焊接时机器给与存储器的压力等。当外部应力加大到一定程度时会使得导电柱与上电极层脱层进而导致上电极层与金属层之间的接触阻抗增大或者导致电容结构提供的供电电压不稳定，内部应力主要来源存储器内部，例如当存储器内部温度变化时存储器内部材料发生热胀冷缩等变化，膜层与膜层之间的材料属性如晶格常数不同导致应力内部应力挤压导电柱进而导致导电柱与上电极层脱层。
此外，随着器件朝向小型化和微型化方向发展，导电柱102和上电极层101的尺寸均相应缩小，使得导电柱102与上电极层101之间的接触面积相应的缩小；当导电柱102与上电极层101的接触面积减小时，导电柱102更易与上电极层101之间发生脱层。
为解决上述问题，本申请实施提供一种存储器结构，在金属层朝向上 电极层的表面设置缓冲柱。如此，当导电柱受到来自内部或者外部应力作用时，缓冲柱分担承受一部分应力作用，从而降低导电柱受到的应力，进而提高导电柱与上电极层连接的稳定性，从而使得电容结构提供的电压稳定。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图3为存储器结构的俯视结构示意图，图4为图3中沿AA1方向切割的一种剖面结构示意图，图5为图3沿AA1方向切割的另一种剖面结构示意图。
参考图3～图5，存储器结构包括：电容结构20，电容结构20具有上电极层201；导电柱202，导电柱202位于上电极层201上，且与上电极层201接触电连接；金属层203，金属层203位于导电柱202远离上电极层201的一侧，且导电柱202与金属层203朝向上电极层201的表面相接触；缓冲柱204，缓冲柱204与导电柱202间隔设置，缓冲柱204与金属层203朝向上电极层201的表面相接触，且自金属层203向上电极层201方向延伸。
通过在金属层203靠近上电极层201的表面额外设置缓冲柱204，当导电柱202受到应力作用时缓冲柱204可以分担一部分应力作用从而提高导电柱202与上电极层201连接的稳定性。
以下将结合附图对本实施例提供的存储器结构进行更为详细的说明。
本实施例中，电容结构20包括：电容单元200，电容单元200至少包括下电极层以及位于下电极层表面的电容介质层；上电极层201，上电极层201覆盖电容单元200的顶面以及侧面。进一步地，电容单元200还可以包 括上电极板，上电极板位于电容介质层表面，且上电极层201位于上电极板表面，电容单元200用于存储电荷。
上电极层201可以是多晶硅、掺杂多晶硅或金属等导电材料，上电极层201覆盖电容单元200的表面及侧面，上电极层201用于将电容单元200存储的电荷向外传递。
导电柱202的材料可以是如铜、铝或钨等的导电材料。本实施例中，导电柱202贯穿上电极层201的表面与上电极层201内部接触电连接；在其他实施例中，导电柱202还可以仅与上电极层201的表面接触电连接。在一些实施例中，在平行于第一方向上导电柱202的宽度自远离上电极层201一侧向靠近上电极层201一侧逐渐减小。在另一些实施例中，在平行于第一方向上导电柱202远离上电极层201一侧的宽度与靠近上电极层201一侧的宽度相同。
金属层203的材料可以是如铜、铝或钨等的导电材料。如图3所示，存储器结构可以包括多个沿第二方向排布的金属层203，且每一金属层203沿第一方向延伸，第二方向与第一方向不同，本实施例中，第二方向可以与第一方向相垂直。
缓冲柱204与导电柱202在金属层203上沿第一方向排布，且在自金属层203指向上电极层201的方向上，缓冲柱204的长度与导电柱202的长度相同，当缓冲柱204与导电柱202长度相同时，在形成导电柱通孔与缓冲柱通孔时可以一步成型，从而减少了工艺步骤。
在一些实施例中，在平行于第一方向上缓冲柱204自远离上电极层201一侧的宽度向靠近上电极层201一侧的宽度逐渐减小；在另一些实施例中，在平行与第一方向上缓冲柱204远离上电极层201一侧的宽度与靠近上电极层201一侧的宽度相同。
本实施例中，缓冲柱204的材料可以与导电柱202的材料相同。由于 缓冲柱204与导电柱202的材料为相同材料，可以在同一步生产工艺同时制作缓冲柱204以及导电柱202；且缓冲柱204的材料也为导电材料，增加了上电极层201与金属层203之间的接触面积从而可以降低金属层203与上电极层201之间的接触电阻。
此外，缓冲柱204的材料包括弹性材料，具体地，缓冲柱204的材料可以为聚酰亚胺。缓冲柱204的材料为弹性材料，当导电柱202受到应力作用，缓冲柱204可以吸收一部分应力作用，从而降低导电柱202本体受到的应力，从而增强导电柱202与上电极层201之间连接的稳定性；且聚酰亚胺材料本身具有优良的机械性能与黏合性能，使得上电极层201与金属层203之间的连接更加牢固。
在本实施例中，对于每一金属层203，缓冲柱204的数量为单个，当导电柱202受到应力作用时，缓冲柱204可以分担导电柱202上的应力，从而增强了导电柱202与上电极层201连接的稳定性。
在一些实施例中，金属层203具有对称轴，对称轴与第二方向平行，金属层203在第一方向上的延伸长度沿对称轴对称，且缓冲柱204可以与导电柱202依对称轴对称设置；由于缓冲柱204与导电柱202对称设置，缓冲柱204可以与导电柱202均匀分摊来自内部或者外部的应力，从而使得导电柱202上受到的应力作用降低，进而增强了导电柱202与上电极层201连接的稳定性；在另一些实施例中，缓冲柱204还可以不与导电柱202关于金属层203对称轴对称设置。
可以理解的是，在另一些实施例中，对于每一金属层203而言，缓冲柱204的数量为多个，且多个缓冲柱204在金属层203上间隔设置。具体地，在一些实施例中，多个缓冲柱204在金属层203靠近上电极层201的表面沿第一方向间隔设置，且在自金属层203指向上电极层201的方向上，每一缓冲柱204的长度与导电柱202的长度可以均相同；当多个缓冲柱204 与导电柱202的长度均相同时时，在形成导电柱通孔与缓冲柱通孔时可以一步成型，从而减少了在生产过程中的工艺步骤。
可以理解的是，在一些实施例中，多个缓冲柱204的材料可以均为导电材料或者均为弹性材料；在另一实施例中部分缓冲柱204的材料是导电材料，部分缓冲柱204的材料是弹性材料。在一些实施例中，当部分缓冲柱204的材料为导电材料，部分缓冲柱204的材料为弹性材料时，所有导电材料使用相同材料，所有弹性材料使用相同材料，以减少材料的种类便于生产。
进一步地，参考图3，存储器结构还可以包括：感测放大器(SA，Sensor Amplifier)209。本实施例中，金属层203邻近感测放大器209设置。导电柱202位于金属层203上靠近感测放大器209的一侧，缓冲柱204位于金属层203上远离感测放大器209的一侧，这样设置使得导电柱202将信号传递给感测放大器209的过程中会降低传输过程中的损耗，减少信号传递时间。在另一些实施例中，缓冲柱204位于金属层203上靠近感测放大器209的一侧，导电柱202位于金属层203上远离感测放大器209的一侧，如此提高了缓冲柱204保护的存储器结构内部的面积，从而更好的提高导电柱202与上电极层201之间连接的稳定性，进而降低导电柱202于上电极层201之间的接触电阻增大或者电容结构20供电电压不稳定情况出现的可能性。
具体地，存储器结构包括存储单元，且金属层203、导电柱202以及缓冲柱204均位于存储单元，感测放大器209位于存储单元相对的两侧。
存储器结构还可以包括：SWC(Sub Wordline Conjunction，字线连接)区域210，SWC区域210位于感测放大器209相对的两侧；SWD(Sub Wrodline Drive，字线驱动)区域211，SWD区域211位于存储单元相对的两侧，且SWD区域211与相应的SWC区域210相邻接。
本实施例中，存储器结构还可以包括第一绝缘层205、第二绝缘层206、电连接层207以及介质层208。
第一绝缘层205覆盖金属层203远离上电极层201一侧的表面，在平行于第一方向上第一绝缘层205的延伸长度大于金属层203的延伸长度，第一绝缘层205可以是氮化硅等不易氧化的材料，用于保护金属层203远离上电极层201一侧表面不被氧化。
第二绝缘层206在自所述上电极层201指向所述金属层203的方向上与第一绝缘层205间隔设置，第二绝缘层206可以是氮化硅等不易氧化的材料，且可以与第一绝缘层205的材料一致，第二绝缘层206可以保护电连接层207表面不被氧化。
若干电连接层207与金属层203处于不同层，在第二绝缘层206靠近第一绝缘层205的一侧沿第一方向排布，且每一电连接层207沿第二方向延伸，第二方向与第一方向不同，且至少存在一个电连接层207穿过第一绝缘层205与金属层203接触电连接。电连接层207用于传递电容结构20的电压。
具体地，电连接层207除位于存储单元外，还可延伸至SWD区域211所在的区域。
介质层208位于上电极层201表面，且导电柱202以及缓冲柱204位于介质层208内。介质层208可以使用氧化硅等材料，用于保护导电柱202、金属层203、缓冲柱204、电连接层207不与空气发生反应。
本实施例通过在金属层203上额外设置一个或者多个在自所述金属层203指向所述上电极层201的方向上的延伸长度与导电柱202的延伸长度相同的缓冲柱204，通过分担导电柱202上受到的压力来提高导电柱202与上电极层201之间连接的稳定性。
本申请另一实施例还提供一种存储器结构，该实施例提供的存储器结 构与前述实施例大致相同，主要区别包括：在自金属层指向上电极层的方向上，缓冲柱的长度小于导电柱的长度。以下将结合附图对本申请另一实施例提供的存储器结构进行说明，需要说明的是，与前述实施例相同或相应的部分，可参考前述实施例的相应说明，以下将不做赘述。
图6为本申请另一实施例提供的存储器结构对应的一种俯视结构示意图；图7为图6沿AA2方向上切割的一种剖面结构示意图；图8为图6沿AA2方向上切割的另一种剖面结构示意图。
参考图6～图8，存储器结构包括：电容结构30，电容结构30包括电容单元300，上电极层301，导电柱302，金属层303，缓冲柱304，第一绝缘层305，第二绝缘层306，电接触层307，介质层308。
存储器结构还可以包括：感测放大器309，SWC区域310，SWD区域311。
本实施例中，在自金属层303指向上电极层301的方向上，缓冲柱304的长度小于导电柱302的长度。当缓冲柱304的材料设置弹性材料时，由于缓冲柱304与上电极层301材料不同，故当存储器结构受热膨胀时，缓冲柱304不会挤压上电极层301，从而保护了上电极层301。
在一些实施例中，在自金属层303指向上电极层301的方向上，缓冲柱304的长度至少为导电柱302的长度的1/2。当缓冲柱304的长度为导电柱302的1/2时，在保证存储器结构的稳定性的同时可以节省材料的使用。
在一些实施例中，缓冲柱304的材料设置为弹性材料，当缓冲柱304的材料为弹性材料时，在导电柱302受到应力作用时缓冲柱304会吸收一部分应力作用且缓冲柱304本身会分担一部分导电柱302上的压力进而降低导电柱302所受到的应力，进而提高了导电柱302与上电极层301连接的稳定性。
可以理解的是，在一些实施例中，对于每一金属层303而言，缓冲柱 304数量可以为多个，且多个缓冲柱304在金属层303上间隔设置，且在一些实施例中，多个缓冲柱304设置在导电柱302同一侧，且沿缓冲柱304指向导电柱302的方向上，多个缓冲柱304在自金属层303指向上电极层301的方向上的长度依次逐个增加，从而当存储器结构受到应力作用时，经过多个缓冲柱304层层保护，导电柱302上受到的力会减小，进而保护了导电柱302与上电极层301之间连接的稳定性。在另一些实施例中，多个缓冲柱304设置在导电柱302同一侧，且在自金属层303指向上电极层301的方向上，每一缓冲柱304的长度相同，还在一些实施例中，缓冲柱304的长度相同且小于导电柱302的长度，当多个缓冲柱304的长度相等时，同样的可以在同一步工艺中成型多个缓冲柱通孔。
当在金属层303朝向上电极层301的表面设置多个缓冲柱304时，在一些实施例中，将缓冲柱304设置为材料相同的弹性材料，如此在加工工艺中可以不更换缓冲柱304的材料便于生产，且设置多个弹性材料的缓冲柱304可以降低更多应力带来的负面影响，进一步提高了导电柱302与上电极层301连接的稳定性；在另一些实施例中，将缓冲柱304设置为材料不同的弹性材料，且可以自靠近感测放大器309向远离感测放大器309的方向上，缓冲柱304的材料的弹性模量依次减小，如此经过多个缓冲柱304层层保护，导电柱302上受到的力会减小，且靠近感测放大器309的缓冲柱304的弹性模量最大可以增加存储器结构的受力能力。
本实施例通过在金属层303上设置多个长度小于导电柱302的缓冲柱304，从而在节约材料的使用的同时可以改善导电柱302与上电极层301脱层的现象。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精 神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (16)

  1. 一种存储器结构，包括：
    电容结构，所述电容结构具有上电极层；
    导电柱，所述导电柱位于所述上电极层上，且与所述上电极层接触电连接；
    金属层，所述金属层位于所述导电柱远离所述上电极层的一侧，且所述导电柱与所述金属层朝向所述上电极层的表面相接触；
    缓冲柱，所述缓冲柱与所述导电柱间隔设置，所述缓冲柱与所述金属层朝向所述上电极层的表面相接触，且自所述金属层向所述上电极层方向延伸。
  2. 如权利要求1所述的存储器结构，其中，所述缓冲柱的数量为单个。
  3. 如权利要求2所述的存储器结构，其中，所述金属层具有对称轴，且所述缓冲柱与所述导电柱依所述对称轴对称设置。
  4. 如权利要求1所述的存储器结构，其中，在自所述金属层指向所述上电极层的方向上，所述缓冲柱的长度与所述导电柱的长度相同。
  5. 如权利要求1或4所述的存储器结构，其中，所述缓冲柱的材料与所述导电柱的材料相同。
  6. 如权利要求1所述的存储器结构，其中，在自所述金属层指向所述上电极层的方向上，所述缓冲柱的长度小于所述导电柱的长度。
  7. 如权利要求6所述的存储器结构，其中，在自所述金属层指向所述上电极层的方向上，所述缓冲柱的长度至少为所述导电柱的长度的1/2。
  8. 如权利要求1所述的存储器结构，其中，所述缓冲柱的材料包括弹性材料。
  9. 如权利要求8所述的存储器结构，其中，所述缓冲柱的材料包括聚酰亚胺。
  10. 如权利要求1所述的存储器结构，其中，所述缓冲柱数量为多个，且多个所述缓冲柱在所述金属层上间隔设置。
  11. 如权利要求10所述的存储器结构，其中，多个所述缓冲柱设置在所述导电柱同一侧，且在自所述金属层指向所述上电极层的方向上，多个述缓冲柱的长度相同。
  12. 如权利要求10所述的存储器结构，其中，多个所述缓冲柱设置在所述导电柱同一侧，沿所述缓冲柱指向所述导电柱的方向上，多个所述缓冲柱在自所述金属层指向所述上电极层的方向上的长度依次逐个增加。
  13. 如权利要求1所述的存储器结构，还包括：感测放大器，所述导电柱位于所述金属层上靠近所述感测放大器的一侧，所述缓冲柱位于所述金属层上远离所述感测放大器的一侧。
  14. 如权利要求1所述的存储器结构，还包括：介质层，所述介质层位于所述上电极层表面，且所述导电柱以及所述缓冲柱位于所述介质层内。
  15. 如权利要求1所述的存储器结构，其中，每一所述金属层沿第一方向延伸，且所述缓冲柱与所述导电柱沿所述第一方向排布。
  16. 如权利要求15所述的存储器结构，还包括：电连接层，所述电连接层与所述金属层处于不同层，且每一所述电连接层沿第二方向延伸，所述第二方向与所述第一方向不同。
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