WO2023283774A1 - 一种扫描链设计方法、装置及芯片 - Google Patents

一种扫描链设计方法、装置及芯片 Download PDF

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Publication number
WO2023283774A1
WO2023283774A1 PCT/CN2021/105812 CN2021105812W WO2023283774A1 WO 2023283774 A1 WO2023283774 A1 WO 2023283774A1 CN 2021105812 W CN2021105812 W CN 2021105812W WO 2023283774 A1 WO2023283774 A1 WO 2023283774A1
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Prior art keywords
scan
register
chain
scan chain
registers
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PCT/CN2021/105812
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English (en)
French (fr)
Inventor
魏连志
李鹏举
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华为技术有限公司
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Priority to PCT/CN2021/105812 priority Critical patent/WO2023283774A1/zh
Priority to CN202180097844.0A priority patent/CN117280225A/zh
Publication of WO2023283774A1 publication Critical patent/WO2023283774A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning

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  • the embodiments of the present application relate to the chip field, and in particular to a scan chain design method, device and chip.
  • the Scan Chain can be used to detect faults on the shift register chain in the chip.
  • one or more scan chains can be observed through the scan chain test vector. If the observed output value of the scan chain is different from the ideal output value, it is determined that the scan chain is faulty.
  • CDR Chip Diagnosis Resolution
  • one method is to increase the logic test vector, so that the failure of the scan chain can be observed by more logic test vectors, thereby improving the CDR.
  • this method will increase the time for chip testing and increase the testing cost.
  • Another method is to add more test circuits in the chip, so that there are more propagation paths for Scan Chain faults, thereby improving CDR.
  • this method will increase the area of the chip, and the cost is high.
  • Embodiments of the present application provide a scan chain design method, device, and chip. By adjusting the structure of the scan chain, the diagnostic accuracy of the scan chain can be improved.
  • a scan chain design method includes: first, obtaining an initial scan chain structure used to indicate the connection relationship between multiple scan chains and combinational logic, and each scan chain can be Including a plurality of scan registers cascaded in series; secondly, based on the initial scan chain structure, determine the scan chain in which the first fan-in scan register corresponding to the first scan register in the first scan chain is located; the first scan chain is a plurality of For any scan chain in the scan chain, the first fan-in scan register is the scan register that fan-in to the first scan register; then, the scan chain where the first fan-in scan register is located is the same as the scan chain where the first scan register is located In some cases, the first fan-in scan register is exchanged with the second scan register in the second scan chain; the multiple scan chains include the second scan chain.
  • the first fan-in scan register and the first scan register are in the same scan chain, when there is a faulty scan register in the first scan chain, the fault value of the faulty scan register is likely to affect the first fan-in Observations of scan registers, resulting in lower diagnostic accuracy for scan chains. Therefore, in this solution, when the first scan register and its corresponding first fan-in scan register are located in the same scan chain, by exchanging the first fan-in scan register with the second scan register, the first scan register can be reduced to a certain extent. The influence of other fault scan registers in the scan chain on the first fan-in scan register helps the first fan-in scan register to produce different observation values, thereby reducing the range of fault scan registers and improving the diagnostic accuracy of the scan chain.
  • the scan chain design method provided by the embodiment of the present application improves the diagnostic accuracy of the scan chain by adjusting the scan chain structure. Compared with the prior art by adding more test circuits to the chip, this solution does not require By adding additional test circuits, the diagnostic accuracy of the scan chain can be improved, so this solution does not increase the chip area, and the cost is low. Compared with adding logic test vectors in the prior art, this solution can improve scan chain diagnosis accuracy without adding logic test vectors, thus saving test time and reducing test cost.
  • the second scan chain and the first scan chain are different scan chains.
  • the first fan-in scan register and the first scan register are in the same scan chain, when there is a faulty scan register in the first scan chain, the fault value of the faulty scan register is likely to affect the first fan-in Observations of scan registers, resulting in lower diagnostic accuracy for scan chains.
  • the influence of other faulty scan registers in the first scan chain on the first fan-in scan register can be reduced, which is helpful for the first fan-in scan
  • the registers generate different observations, thereby enabling narrowing of fault scan registers and improving scan chain diagnostic accuracy.
  • the first fan-in scan register is exchanged with the second scan register in another scan chain, so that The first scan register and its corresponding first fan-in scan register are respectively located in different scan chains, so that when a fault scan unit is detected based on the scan chain after the scan register is exchanged, the fan-in scan of the fault scan register in the first scan chain can be reduced.
  • the impact of registers improves the diagnostic accuracy of the scan chain.
  • the above-mentioned second scan chain is the same scan chain as the first scan chain; wherein, before exchanging the first fan-in scan register with the second scan register in the second scan chain, the second A scan register is closer to the shift input end of the first scan chain than the first fan-in scan register, and the second scan register is a scan register closer to the shift input end of the first scan chain than the first scan register.
  • the first fan-in scan register is farther away from the shift input end of the first scan chain, if the scan register closer to the shift input end of the first scan chain than the first fan-in scan register fails, the fault The fault value of the scan register will affect the observed value of the first fan-in scan register, resulting in low diagnostic accuracy of the scan chain.
  • the impact of other fault scan registers in the first scan chain on the first fan-in scan register can be reduced, which is helpful for the first fan-in scan register.
  • the input scan registers produce different observation values, which can narrow the range of fault scan registers and improve the diagnostic accuracy of scan chains.
  • the first scan register and its corresponding first fan-in scan register are located in the same scan chain, and the first scan register is closer to the shift input end of the first scan chain than its corresponding first fan-in scan register.
  • the first fan-in scan register is closer to the second scan register than the other scan registers.
  • the above-mentioned initial scan chain structure includes a plurality of compression channels, and logical operations are performed between the shift output ends of at least two scan chains included in each compression channel, and the above-mentioned method further includes: in the second If the compression channel where the scan chain is located is the same as the compression channel where the first scan chain is located, the second scan chain is exchanged with the third scan chain in another compression channel.
  • the coupling between the first scan register and the first fan-in scan register in the compression channel is strong, and the first fan-in scan register If the register fails, the fault value of the first fan-in scan register is likely to affect the value captured by the first scan register, and then affect the output value of the compression channel, making it impossible to distinguish the faulty scan register, resulting in scan
  • the diagnostic accuracy of the chain is low.
  • the method further includes: determining the capture probability of each scan register in the first scan chain; the capture probability of each scan register is used to indicate that the scan register captures 0 or 1 probability; in the first scan chain, the capture probabilities of two adjacent scan registers are greater than a preset threshold, or, in the first scan chain, the capture probabilities of two adjacent scan registers are both less than or equal to a preset threshold In the case of , adjust the connection relationship between multiple scan registers in the first scan chain, so that the capture probability of one scan register in two adjacent scan registers is greater than the preset threshold, and the capture probability of the other scan register is less than or equal to the preset threshold.
  • the second aspect of the embodiment of the present application provides a scan chain design method, the method includes: obtaining an initial scan chain structure used to indicate the connection relationship between multiple scan chains and combinational logic; the initial scan chain structure includes multiple Compression channels, each compression channel includes at least two scan chains, logical operations are performed between the shift outputs of at least two scan chains in each compression channel, each scan chain includes a plurality of scan registers; based on the initial scan The chain structure determines the scan chain in which the first fan-in scan register corresponding to the first scan register in the first scan chain is located; the first fan-in scan register is a scan register fan-in to the first scan register, and the first scan chain is a plurality of Any scan chain in the scan chain, the scan chain where the first fan-in scan register is located is the second scan chain, and the multiple scan chains include the second scan chain; the compression where the first scan chain and the second scan chain are located In the case of the same channel, the second scan chain is exchanged with the third scan chain in another compressed channel.
  • the above method further includes: determining the capture probability of each scan register in the first scan chain; the capture probability of each scan register is used to indicate the probability that the scan register captures 0 or 1;
  • the capture probabilities of two adjacent scan registers in a scan chain are both greater than a preset threshold, or, when the capture probabilities of two adjacent scan registers in the first scan chain are both less than or equal to a preset threshold, adjust the first
  • the connection relationship between multiple scan registers in the scan chain makes the capture probability of one scan register in two adjacent scan registers greater than a preset threshold, and the capture probability of the other scan register is less than or equal to a preset threshold.
  • the third aspect of the embodiment of the present application provides a chip, the chip includes a first scan chain and a second scan chain, the first scan chain and the second scan chain are different scan chains, the first scan chain in the first scan chain The scan registers fan into a second scan register in the second scan chain.
  • the above-mentioned first scan chain and the second scan chain are scan chains in different compression channels; wherein, the compression channel includes at least two scan chains, and the at least two scan chains in the compression channel Logical operations are performed between the shifted outputs.
  • the capture probability of one scan register is greater than a preset threshold, and the capture probability of the other scan register is less than or equal to the preset threshold.
  • a chip includes a first scan chain, the first scan register in the first scan chain is fanned into the second scan register in the first scan chain, and the first scan register It is closer to the shift input terminal of the first scan chain than the second scan register.
  • the capture probability of one scan register is greater than a preset threshold, and the capture probability of the other scan register is less than or equal to the preset threshold .
  • the fifth aspect of the embodiments of the present application provides a scan chain design device, the scan chain design device includes a processor and a memory, the memory is used to store a computer program; the processor is used to execute the computer program, so that the The electronic device executes the method described in the first aspect or the second aspect.
  • the sixth aspect of the embodiments of the present application provides a chip, the chip includes a processor and an interface circuit, the processor is used to communicate with other devices through the interface circuit, so as to implement the above-mentioned first aspect or the second aspect described method.
  • a computer-readable storage medium in which computer program code is stored, and when the computer program code is run on a processor, the processor Execute the method described in the first aspect or the second aspect above.
  • the eighth aspect of the embodiments of the present application provides a computer program product, the program product stores computer software instructions executed by the above-mentioned processor, and the computer software instructions are used to implement the solution described in the first aspect or the second aspect program of.
  • FIG. 1 is a schematic structural diagram of a general register and a scan register provided in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a scan chain provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of an initial scan chain structure provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a scan chain design method provided in an embodiment of the present application.
  • FIG. 6 is an application schematic diagram 1 of a scan chain design method provided by an embodiment of the present application.
  • FIG. 7 is a second application schematic diagram of a scan chain design method provided by the embodiment of the present application.
  • FIG. 8 is an application schematic diagram 3 of a scan chain design method provided in the embodiment of the present application.
  • FIG. 9 is an application schematic diagram 4 of a scan chain design method provided in the embodiment of the present application.
  • FIG. 10 is a schematic diagram of another initial scan chain structure provided by the embodiment of the present application.
  • FIG. 11 is a schematic flowchart of another scan chain design method provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of another initial scan chain structure provided by the embodiment of the present application.
  • FIG. 13 is a schematic diagram of the application of a scan chain design method provided in the embodiment of the present application (5);
  • FIG. 14 is a schematic flowchart of another scan chain design method provided by the embodiment of the present application.
  • FIG. 15 is a schematic diagram of another initial scan chain structure provided by the embodiment of the present application.
  • FIG. 16 is a sixth application schematic diagram of a scan chain design method provided by the embodiment of the present application.
  • FIG. 17 is a schematic composition diagram of a scan chain design device provided by an embodiment of the present application.
  • At least one item (piece) of a, b or c can represent: a, b, c, a and b, a and c, b and c, or, a and b and c, wherein a, b and c can be single or multiple.
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same function and effect, Those skilled in the art can understand that words such as “first” and “second” do not limit the quantity and execution order.
  • first in the first scan register and “second” in the second scan register in the embodiment of the present application are only used to distinguish different scan registers.
  • the first, second, etc. descriptions that appear in the embodiments of this application are only for illustration and to distinguish the description objects. Any limitations of the examples.
  • the Scan Chain can be used to detect faults on the shift register chain in the chip.
  • a scan chain can consist of serial cascading of multiple scan registers.
  • FIG. 1 is a structural schematic diagram of a common register.
  • the register includes a data input terminal D, a clock input terminal CLK, a data output terminal Q and a data output terminal QN.
  • the effective clock edge of the clock input terminal of the register can be a rising edge or a falling edge. Take the effective edge of the clock of the register as the rising edge as an example.
  • the register samples the data input terminal D and sends the sampled value to the data output terminal Q.
  • the data output terminal Q maintains the original sampling value until the clock input terminal changes from low level to high level for the second time.
  • the data output terminal QN inverts the data output terminal Q.
  • FIG. 1 is a schematic structural diagram of a scanning register.
  • a selector multiplexer, MUX
  • the scan register includes a logic data input terminal D, a scan data input terminal (scan in, SI), a scan enable terminal (scan enable, SE), a clock input terminal CLK, a data output terminal Q and data output QN.
  • the selector MUX selects the input of the scan register as the logic data input terminal D or the scan data input terminal SI through the scan enable terminal SE. Therefore, when the clock effective edge of the scan register arrives, the output value of the scan register is related to the value of the scan enable terminal SE.
  • the input of the scan register can be the value of the logic data input terminal D, and when the scan enable terminal SE is 1, the input of the scan register can be the value of the scan data input terminal SI. value.
  • the scan enable terminal SE is 1, the input of the scan register can be the value of the logic data input terminal D, and when the scan enable terminal SE is 0, the input of the scan register can be the value of the scan data input terminal SI.
  • the present application is not limited to this.
  • the scan enable terminal SE when the scan enable terminal SE is 0, the input of the scan register is the value of the logic data input terminal D, and when the scan enable terminal SE is 1, the input of the scan register is the scan
  • the value of the data input SI is used as an example for illustration.
  • the scan register performs an operation on the logic data input terminal D Sample, and send the sampled value to the data output terminal Q.
  • the scan enable terminal SE is 1
  • the scan register samples the scan data input terminal SI and sends the sampled value to the data output terminal Q.
  • the logic data input terminal D of any scan register (for example, scan register 1) in the scan chain is used to couple with the output terminal of the combinational logic, and the input terminal of the combination logic is connected to another scan register (for example, scan register 1).
  • the output terminals of the register 2 and the scanning register 3) are coupled and connected.
  • the scan register 2 and scan register 3 may be referred to as fan-in scan registers corresponding to scan register 1, and the combinatorial logic may be referred to as fan-in combinatorial logic corresponding to scan register 1.
  • the embodiment of the present application does not limit the specific number of fan-in scan registers corresponding to each scan register and the specific operation mode of the fan-in combinatorial logic.
  • Fig. 2 is a schematic structural diagram of a scan chain, taking the scan chain including three scan registers as an example, as shown in Fig. 2, the data output terminal Q of the previous scan register among two adjacent scan registers is connected The scan data input terminal SI is coupled and connected.
  • the scan enable terminal SE of each scan register is 1, the three scan registers shown in Figure 2 are connected end to end to form a scan chain.
  • the scan chain can be detected by automatic test equipment (ATE).
  • ATE automatic test equipment
  • the ATE device controls the scan enable terminal SE of each scan register in the scan chain to be 1 according to the scan chain test vector, so that multiple scan registers in the scan chain form a shift register.
  • the ATE device observes the output value of the scan chain by inputting the scan chain test vector to the scan data input terminal SI of the first scan register in the scan chain. If the observed output value of the scan chain is different from the scan chain test vector, it is determined that the scan chain is faulty.
  • the ATE device can also detect faulty scanning units (for example, scanning registers) in the scanning chain according to the logic test vector.
  • the scan chain diagnostic accuracy (Chain Diagnosis Resolution, CDR) can be used to indicate the diagnostic accuracy of the scan chain, and the smaller the CDR, the higher the diagnostic accuracy.
  • CDR Channel Diagnosis Resolution
  • the minimum value of CDR can be 1, and a CDR value of 1 means that the diagnostic accuracy of the scan chain can be as accurate as the only scan register.
  • the method for detecting faulty scanning units in the scanning chain by the ATE equipment according to the logic test vectors will be introduced in three stages below.
  • the ATE device controls the scan enable terminal SE of each scan register in the scan chain to be 1 according to the logic test vector, and multiple scan registers in the scan chain form a shift register.
  • the ATE device inputs a logic test vector to the SI end of the first scan register in the scan chain, and the value of the logic test vector can be shifted and stored in each scan register in the scan chain (that is, the load stage can be used for the scan chain Each scan register in the initial value).
  • Capture capture stage In general, in the capture stage, the scan enable terminal SE of each scan register in the scan chain is 0, and the scan register switches to a non-scan enable state (that is, a normal digital circuit), and the logic data of each scan register Input D captures the value from the fan-in combinatorial logic of the scan register.
  • the capture phase can be considered as loading the value of the fault point into the scan register, and the value captured by each scan register in the capture phase is the result of the load value of the fan-in scan register corresponding to the scan register in the load phase and the fan-in combinatorial logic operation .
  • the scan enable terminal SE of each scan register in the scan chain is 1
  • multiple scan registers in the scan chain form a shift register, and serially output the value captured by each scan register in the capture phase, ATE equipment Compare this output value with the ideal output value.
  • the observation logic of the faulty scan register may be strongly coupled with other scan registers on the faulty scan chain, resulting in low scan chain diagnosis accuracy CDR.
  • the chip includes two scan chains, namely scan chain 1 and scan chain 2, scan chain 1 is a fault-free scan chain, and the ideal values of scan registers C6 to C4 in scan chain 2 are ⁇ 1 1 1 ⁇ as an example , as shown in FIG. 3 , scan chain 1 includes scan register Ca to scan register Cg, and scan chain 2 includes scan register C0 to scan register C6.
  • the fan-in scan registers corresponding to scan register C4 in scan chain 2 are scan register C1 and scan register C2 (that is, the scan registers fanned into the scan register C4 are scan register C1 and scan register C2), and the fan-in corresponding to scan register C5
  • the scan registers are scan register C2 and scan register C3 (that is, the scan registers fanned into the scan register C5 are scan register C2 and scan register C3). If only the scan register C6 in scan chain 2 is faulty, and a fixed fault 0 (stuck at 0, SA0) occurs, the ATE device can detect the faulty scan register in three stages (load stage, capture stage, and unload stage).
  • the logic test vector input by scan chain 2 is ⁇ 1 0 1 1 1 1 1 ⁇ as an example. Since SA0 appears in scan register C6, the values of scan registers C6 to C0 in the load phase are all 0.
  • the value captured by the scan register C4 is the value of the XOR operation between the value 0 of the scan register C1 and the value 0 of the scan register C2, that is, the value captured by the scan register C4 is 0.
  • the value captured by the scanning register C5 is the value obtained by ANDing the value 0 of the scanning register C2 and the value 0 of the scanning register C3 , that is, the value captured by the scanning register C5 is 0.
  • the output values of scan registers C6, C5, and C4 are ⁇ 0 0 0 ⁇ during the unload stage.
  • the diagnosis stage by comparing the detection results of the ATE equipment with the ideal values, for example, the output values of the scan registers C6, C5, and C4 are ⁇ 0 0 0 ⁇ and the ideal values of the scan registers C6, C5, and C4 ⁇ 1 1 1 ⁇ for comparison, it can be determined that the scan registers C6, C5, and C4 may all be faulty.
  • scan registers C5 and C4 have not failed, and the output value errors of scan registers C5 and C4 are caused by the presence of SA0 in scan register C6. Therefore, the scan chain structure shown in Figure 3 will lead to the accuracy of scan chain diagnosis lower.
  • One way to improve the CDR is to increase the logic test vectors, so that the faults of the scan chain can be observed by more logic test vectors, thereby improving the CDR.
  • this method will increase the time for chip testing and increase the testing cost.
  • Another method is to add more test circuits in the chip, so that the failure of the scan chain has more propagation paths, thereby improving the CDR.
  • this method will increase the area of the chip, and the cost is high.
  • the embodiment of the present application provides a scan chain design method, and the scan chain designed based on this design method
  • the structure can effectively improve the diagnostic accuracy of the scan chain, thereby reducing the difficulty of failure analysis when performing failure analysis based on the diagnosis results, contributing to the improvement of the chip manufacturing process and improving the chip yield rate.
  • the scan chain design method provided by the embodiment of the present application improves the diagnostic accuracy of the scan chain by adjusting the structure of the scan chain. Compared with the prior art by adding more test circuits to the chip, the present application does not require additional testing.
  • the circuit can improve the diagnostic accuracy of the scan chain, so the application will not increase the chip area, and the cost is low. Compared with adding logic test vectors in the prior art, this solution can improve scan chain diagnosis accuracy without adding logic test vectors, thus saving test time and reducing test cost.
  • the scan chain design method provided in the embodiment of the present application can be executed by the electronic device shown in FIG. 4, and design tools such as electronic design automation (electronic design automation, EDA) can be run on the electronic device. Methods can be run in EDA tools.
  • the electronic device 400 includes at least one processor 401 , a memory 402 , a transceiver 403 and a communication bus 404 .
  • the processor 401 is the control center of the electronic device, and may be one processor, or may be a general term for multiple processing elements.
  • the processor 401 is a central processing unit (central processing unit, CPU), may also be a specific integrated circuit (application specific integrated circuit, ASIC), or is configured to implement one or more integrated circuits of the embodiments of the present application , for example: one or more microprocessors (digital signal processor, DSP), or, one or more field programmable gate arrays (field programmable gate array, FPGA).
  • the processor 401 can execute various functions of the electronic device by running or executing software programs stored in the memory 402 and calling data stored in the memory 402 .
  • the processor 401 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 4 .
  • the electronic device may include multiple processors, for example, the processor 401 and the processor 405 shown in FIG. 4 .
  • processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU).
  • a processor herein may refer to one or more detection devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the memory 402 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (random access memory, RAM) or other types that can store information and instructions It can also be an electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store desired program code in the form of instructions or data structures and can be programmed by a computer Any other medium accessed, but not limited to.
  • the memory 402 may exist independently, and is connected to the processor 401 through the communication bus 404 .
  • the memory 402 can also be integrated with the processor 401 .
  • the memory 402 is used to store a software program for executing the solution of the present application, and the execution is controlled by the processor 401 .
  • the transceiver 403 is used for communicating with other communication devices.
  • the transceiver 403 can also be used to communicate with a communication network, such as Ethernet, radio access network (radio access network, RAN), wireless local area network (wireless local area networks, WLAN) and so on.
  • the transceiver 403 may include a receiving unit to implement a receiving function, and a sending unit to implement a sending function.
  • the communication bus 404 may be an industry standard architecture (industry standard architecture, ISA) bus, an external detection device interconnection (peripheral component, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, etc.
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 4 , but it does not mean that there is only one bus or one type of bus.
  • the structure of the electronic device shown in FIG. 4 does not constitute a limitation on the electronic device.
  • the electronic device may include more or fewer components than shown in the figure, or combine some components, or arrange different components.
  • a scan chain design method provided in the embodiment of the present application, the method includes the following steps:
  • the initial scan chain structure is used to indicate the connection relationship between multiple scan chains and combinational logic, each scan chain includes multiple scan registers, and multiple scan registers in each scan chain are serially cascaded.
  • the number of scan registers included in different scan chains may be the same or different, which is not limited in this embodiment of the present application.
  • the initial scan chain structure may include: the identification of multiple scan registers included in each scan chain in multiple scan chains, the connection relationship of multiple scan registers in each scan chain, and the scans fanned into each scan register Register identification, and information such as the combinatorial logic fanned into each scan register.
  • the initial scan chain structure including the scan chain structure shown in FIG. 3 as an example.
  • FIG. Connection relationship between registers Ca The identification of the scan register C6 to the scan register C0 in the scan chain 2, and the connection relationship between the scan register C6 to the scan register C0.
  • the scan registers of the fan-in scan register C4 in the scan chain 2 are scan register C1 and scan register C2, and the logic operation of the fan-in scan register C4 is an exclusive OR operation, that is, the input terminals of the exclusive OR operation are respectively coupled to the scan register C1 and the scan register C2.
  • the output terminal of the scan register C2, the output terminal of the XOR operation is coupled to the D terminal of the scan register C4.
  • the scan registers of the fan-in scan register C5 in the scan chain 2 are scan register C2 and scan register C3, and the logical operation of the fan-in scan register C5 is an AND operation, that is, the input terminals of the AND operation are respectively coupled to the scan register C2 and the scan register The output terminal of C3, the output terminal of the AND operation is coupled to the D terminal of the scanning register C5.
  • the first scan chain may be any one of multiple scan chains included in the initial scan chain structure.
  • the first scan register may be any scan register among the multiple scan registers included in the first scan chain.
  • the first fan-in scan register is a scan register fan-in to the above-mentioned first scan register.
  • the scan chain where the first fan-in scan register is located and the scan chain where the first scan register is located may be the same scan chain or different scan chains.
  • the first scan chain includes the first scan register and the first fan-in scan register.
  • the scan chain where the first fan-in scan register is located and the scan chain where the first scan register is located are different scan chains, the scan chain where the first fan-in scan register is located is the scan chain other than the first scan chain among the multiple scan chains scan chain.
  • the scan registers fanned into the scan register C4 are scan register C1 and scan register C2 . Since the scan chain where scan register C1 and scan register C2 are located is scan chain 2, the scan chain where the first scan register (scan register C4) and its corresponding first fan-in scan register (scan register C1 and scan register C2) are located same.
  • the scan registers fanned into the scan register C5 are scan register C2 and scan register C3 . Since the scan chain where scan register C2 and scan register C3 are located is scan chain 2, the scan chain where the first scan register (scan register C5) and its corresponding first fan-in scan register (scan register C2 and scan register C3) are located same.
  • step S503 is to exchange the first fan-in scan register with the second scan register in the second scan chain when the first scan register and its corresponding first fan-in scan register are in the same scan chain.
  • exchanging the first fan-in scan register with the second scan register in the second scan chain may include two implementations.
  • One implementation is to exchange the first fan-in scan register in the first scan chain with another The second scan registers in the scan chain (second scan chain) are swapped, so that the first scan register and its corresponding first fan-in scan register are located in different scan chains.
  • Another implementation is to exchange the first fan-in scan register with the second scan register in the first scan chain that is closer to the shift input end of the first scan chain, so that the first fan-in scan register is closer to the first scan chain shift input.
  • the second scan chain in step S503 is a different scan chain from the first scan chain.
  • the first scan chain is scan chain 2
  • the second scan chain is scan chain 1
  • the first scan register is scan register C4 and scan register C5 in scan chain 2
  • the second scan register is Scan registers Cd, Cc, and Cb in scan chain 1 are taken as an example.
  • the scan registers of the fan-in scan register C4 are scan registers C1 and C2
  • the scan registers of the fan-in scan register C5 are scan registers C2 and C3. According to step S502, it can be determined that the scan chains where the scan registers C1, C2, and C3 are located are all scan chains 2.
  • the scanning chain of the scan register C4 and its corresponding fan-in scanning registers C1 and C2 is the same, and the scan chain of the scanning register C5 and its corresponding fan-in scanning registers C2 and C3 is the same. Therefore, the fan-in scan registers C1, C2, and C3 in scan chain 2 can be exchanged with the scan registers Cb, Cc, and Cd in scan chain 1, so that scan register C4 and its corresponding fan-in scan registers C1 and C2 are located in different positions, respectively.
  • the scan register C5 and its corresponding fan-in scan registers C2 and C3 are respectively located in different scan chains, so that the influence of the faulty scan register in scan chain 1 on the fan-in scan register can be reduced, and the diagnostic accuracy of the scan chain can be improved.
  • the SI terminal and Q terminal of the first fan-in scan register can be respectively connected to the first Disconnect in the scan chain, disconnect the SI end and Q end of the second scan register in the second scan chain respectively, and connect the SI end and Q end of the second scan register to the first scan chain respectively, and connect The SI terminal and the Q terminal of the first fan-in scan register are respectively connected to the second scan chain, so that the first scan register and its corresponding fan-in scan register are respectively located in different scan chains.
  • the fan-in scan registers C1, C2, and C3 in scan chain 2 are combined with the scan registers Cb, Cc, and scan registers in scan chain 1 (second scan chain).
  • Cd second scanning register
  • the SI terminal of the fan-in scanning register C3 can be disconnected from the Q terminal of the scanning register C4
  • the Q terminal of the fan-in scanning register C1 can be disconnected from the SI terminal of the scanning register C0
  • disconnect the SI terminal of the scanning register Cd from the Q terminal of the scanning register Ce and disconnect the Q terminal of the scanning register Cb from the SI terminal of the scanning register Ca.
  • the ideal values of scan registers C6 to C4 in scan chain 2 are Take ⁇ 1 1 1 ⁇ as an example, as shown in Figure 7, if only scan register C6 in scan chain 2 fails, and SA0 appears in scan register C6, the ATE equipment can be detected in three stages (load stage, capture stage and unload stage) Faulty scan registers, taking the logic test vector input by scan chain 1 in the load phase as ⁇ 1 0 1 1 1 1 1 ⁇ as an example, the values of fan-in scan registers C3 to C1 in the load phase are ⁇ 1 1 0 ⁇ .
  • the value captured by the scan register C4 is the value of the XOR operation between the value 0 of the scan register C1 and the value 1 of the scan register C2, that is, the value captured by the scan register C4 is 1.
  • the value captured by the scanning register C5 is the value obtained by ANDing the value 1 of the scanning register C2 and the value 1 of the scanning register C3 , that is, the value captured by the scanning register C5 is 1. Therefore, in the unload stage, the output values of the scan registers C6, C5, and C4 are ⁇ 0 1 1 ⁇ .
  • the diagnosis stage by comparing the detection results of the ATE equipment with the ideal values, for example, the output values of the scan registers C6, C5, and C4 are ⁇ 0 1 1 ⁇ and the ideal values of the scan registers C6, C5, and C4 ⁇ 1 1 1 ⁇ , it can be determined that the scan register that may be faulty is the scan register C6.
  • the fault value of the faulty scan register in the first scan chain will affect the first fan-in scan register observations, resulting in low diagnostic accuracy of the scan chain.
  • the influence of other faulty scan registers in the first scan chain on the first fan-in scan register can be reduced, which helps the first fan-in scan register Different observation values are generated, thereby being able to narrow the scope of fault scan registers and improve scan chain diagnostic accuracy.
  • the second scan chain in step S503 is the same scan chain as the first scan chain, wherein, before exchanging the first fan-in scan register with the second scan register, the first scan register The first fan-in scan register is closer to the shift input end of the first scan chain, and the second scan register is a scan register in the first scan chain closer to the shift input end than the first scan register. That is, in this implementation, the first scan register and its corresponding first fan-in scan register are located in the same scan chain, and the first scan register is closer to the first scan chain than its corresponding first fan-in scan register.
  • the first fan-in scan register in the exchanged first scan chain The scan register is closer to the shift input end of the first scan chain than the first scan register.
  • the shift input end of the first scan chain can also be referred to as the primary input (Primary Input) end of the first scan chain, and the shift input end of the first scan chain is the first scan register in the first scan chain
  • the scan input SI terminal The shift output terminal of the first scan chain may also be referred to as the primary output terminal of the first scan chain, and the shift output terminal of the first scan chain is the output terminal of the last scan register in the first scan chain.
  • the shift input terminal of scan chain 2 is the SI terminal of the first scan register C6 in scan chain 2 .
  • the first scan chain is scan chain 2
  • the first scan register is scan register C4 and scan register C5 in scan chain 2
  • the second scan register is scan register C6 in scan chain 2.
  • scan register C4 is in the same scan chain as its corresponding fan-in scan registers C1 and C2
  • scan register C5 is in the same scan chain as its corresponding fan-in scan registers C2 and C3
  • scan register C4 is more scanned than its corresponding fan-in scan registers.
  • Registers C1 and C2 are closer to the shift input of scan chain 2
  • scan register C5 is closer to the shift input of scan chain 2 than its corresponding fan-in scan registers C2 and C3.
  • the fan-in scan registers C1 to C3 in scan chain 2 can be exchanged with the scan register C6 in scan chain 2 that is closer to the shift input end of scan chain 2 than scan register C4 and scan register C5, so that scan chain 2
  • the fan-in scan registers C1 to C3 are closer to the shift input end of scan chain 2, so as to reduce the influence of faulty scan registers in scan chain 2 on the fan-in scan registers and improve the diagnostic accuracy of the scan chain.
  • the SI terminal of the first fan-in scan register, the first fan-in scan register are respectively disconnected in the first scan chain, and reconnect the first fan-in scan register and the second scan register, so that the first scan chain
  • the first fan-in scan register is closer to the shift input end of the first scan chain than the first scan register.
  • the scan chain structure after exchanging the first fan-in scan register in the first scan chain with the second scan register in the first scan chain is shown in Figure 9, the ideal output values of scan registers C6 to C4 in scan chain 2 Take ⁇ 1 1 1 ⁇ as an example, as shown in Figure 9, if only scan register C6 fails in scan chain 2, and SA0 appears in scan register C6, the ATE device inputs scan chain test vector ⁇ 1 1 1 1 1 in scan chain 2 1 0 ⁇ , the output observation value of scan chain 2 is ⁇ 0 0 0 0 0 0 0 ⁇ . ATE equipment detects faulty scan registers in three stages (load stage, capture stage, and unload stage).
  • the values of scan registers C3 to C1 are ⁇ 1 1 0 ⁇ .
  • the value captured by the scan register C4 is the value of the XOR operation between the value 0 of the scan register C1 and the value 1 of the scan register C2, that is, the value captured by the scan register C4 is 1.
  • the value captured by the scanning register C5 is the value obtained by ANDing the value 1 of the scanning register C2 and the value 1 of the scanning register C3 , that is, the value captured by the scanning register C5 is 1.
  • the output values of the scan registers C6, C5, and C4 are ⁇ 0 1 1 ⁇ .
  • the diagnosis stage by comparing the detection results of the ATE equipment with the ideal values, for example, the output values of the scan registers C6, C5, and C4 are ⁇ 0 1 1 ⁇ and the ideal values of the scan registers C6, C5, and C4 ⁇ 1 1 1 ⁇ , it can be determined that the scan register that may be faulty is the scan register C6.
  • the first scan register and its corresponding first fan-in scan register are located in the same scan chain, and the first scan register is closer to the shift input of the first scan chain than its corresponding first fan-in scan register
  • the first fan-in scan register is swapped with the first scan register, so that the first fan-in scan register in the swapped first scan chain is closer to the shift input end of the first scan chain than the first scan register.
  • the farther the first fan-in scan register is from the shift input end of the first scan chain if the scan register closer to the shift input end of the first scan chain than the first fan-in scan register fails, the fault will The fault value of the scan register will affect the observed value of the first fan-in scan register, resulting in low diagnostic accuracy of the scan chain.
  • the impact of other fault scan registers in the first scan chain on the first fan-in scan register can be reduced, which is helpful for the first fan-in scan register.
  • the input scan registers produce different observation values, which can narrow the range of fault scan registers and improve the diagnostic accuracy of scan chains.
  • the first scan register and its corresponding first fan-in scan register are located in the same scan chain, and the first scan register is closer to the first scan register than its corresponding first fan-in scan register.
  • the first fan-in scan register It is closer to the shift input end of the second scan chain than other scan registers, so that when a faulty scan unit is detected based on the scan chain after the scan register is exchanged, the influence of the faulty scan register in the first scan chain on the fan-in scan register can be reduced, improving Diagnostic accuracy of the scan chain.
  • the initial scan chain structure may include multiple compression channels, each compression channel includes at least two scan chains, and logic operations are performed between the shift output terminals of at least two scan chains in each compression channel, the present application
  • the embodiment does not limit the specific logic operations performed between the shift output terminals of at least two scan chains in each compression channel.
  • each compression channel includes two scan chains, and the two The logical operation performed between the shift output terminals of two scan chains is an exclusive OR operation as an example for illustration.
  • the compression channel shown in Figure 10 is included in the initial scan chain structure, the compression channel includes scan chain 1 and scan chain 2, and the shift output terminal of scan chain 1 and scan chain 2 in the compression channel Do XOR operation between them, the ideal value of scan register Cg, Cf, Ce in scan chain 1 is ⁇ 1 1 1 ⁇ , the ideal value of scan register C6, C5, C4 in scan chain 2 is ⁇ 1 1 1 ⁇ , scan register Take the ideal value of ⁇ 0 0 0 ⁇ after XOR operation of Cg, Cf, Ce and scan registers C6, C5, C4 as an example. Taking SA0 in scan registers C6 , C5 , and C4 as examples below, the problems that occur when the first scan register and its corresponding first fan-in scan register are in the same compression channel are described in detail.
  • the value captured by the scan register C4 is the value of the XOR operation between the value 0 of the scan register C1 and the value 1 of the scan register C2, that is, the value captured by the scan register C4 is 1.
  • the value captured by the scanning register C5 is the value obtained by ANDing the value 1 of the scanning register C2 and the value 1 of the scanning register C3 , that is, the value captured by the scanning register C5 is 1.
  • the value captured by scan register C6 is 0, the value captured by scan register Cg is 0, the value captured by scan register Cf is 0, the value captured by scan register C6 is 0, and the value captured by scan register Ce is 0.
  • the value is 0 for scan register C5.
  • the values captured by scan registers C6, C5, and C4 are ⁇ 0 1 1 ⁇ , and the values captured by scan registers Cg, Cf, and Ce are ⁇ 0 0 0 ⁇ .
  • the output values of scan registers C6, C5, and C4 are ⁇ 0 1 1 ⁇ , and the output values of scan registers Cg, Cf, and Ce are ⁇ 0 0 0 ⁇ .
  • the output value of C5, C4 and the value of scanning register Cg, Cf, Ce are XORed and the result is ⁇ 0 1 1 ⁇ .
  • the values captured by the scan registers C6, C5, and C4 are ⁇ 1 1 1 ⁇ , and the values captured by the scan registers Cg, Cf, and Ce are ⁇ 0 1 0 ⁇ .
  • the output values of scan registers C6, C5, and C4 are ⁇ 0 0 1 ⁇ , and the output values of scan registers Cg, Cf, and Ce are ⁇ 0 1 0 ⁇ .
  • the output value of C5, C4 and the output value of scanning register Cg, Cf, Ce are XORed and the result is ⁇ 0 1 1 ⁇ .
  • the values captured by the scan registers C6, C5, and C4 are ⁇ 1 1 1 ⁇ , and the values captured by the scan registers Cg, Cf, and Ce are ⁇ 0 1 1 ⁇ .
  • the output values of scan registers C6, C5, and C4 are ⁇ 0 0 0 ⁇ , and the output values of scan registers Cg, Cf, and Ce are ⁇ 0 1 1 ⁇ .
  • the output value of C5, C4 and the output value of scanning register Cg, Cf, Ce are XORed and the result is ⁇ 0 1 1 ⁇ .
  • the embodiment of the present application also provides a scan chain design method, as shown in FIG. 11 , the method may further include step S504 in addition to the above steps S501-S503.
  • the scan chain where the first scan register is located is the first scan chain
  • the scan chain where the first fan-in scan register is located is the second scan chain
  • the first scan chain and the second scan chain can be the same
  • the scan chain can also be a different scan chain.
  • the other compression channel in step S504 may be the second compression channel, and the second compression channel is a different compression channel from the first compression channel. aisle.
  • the compression channel where the first scan chain is located is the first compression channel
  • the compression channel where the second scan chain is located is also the first compression channel, and it is determined that the compression channel where the first scan chain is located is the same as the compression channel where the second scan chain is located
  • the second scan chain may be swapped with the third scan chain in the second compression pass such that the second scan chain is in a different compression pass than the first scan chain.
  • the compression channel where the first scan register is located is the same as the compression channel where the first fan-in scan register is located, by exchanging the second scan chain with the third scan chain, the compression channel where the first scan register is located It is different from the compression channel where the first fan-in scan register is located, thereby reducing the coupling between multiple scan chains in the same compression channel and improving the diagnostic accuracy of the scan chain.
  • the scan chain where the first scan register is located may be the same as or different from the scan chain where the first fan-in scan register is located. That is, the first scan chain and the second scan chain may be the same scan chain or different scan chains.
  • FIG. 10 , FIG. 12 and FIG. 13 are illustrated by taking the scan chain where the first scan register is located and the scan chain where the first fan-in scan register is located are different scan chains as an example.
  • the first compression channel includes scan chain 1 and scan chain 2
  • the second compression channel includes scan chain 3 and scan chain 4
  • the first scan register is scan register C4 in scan chain 2
  • the second compression channel includes scan chain 3 and scan chain 4.
  • One fan-in scan register is the scan registers C2 and C1 in the scan chain 1
  • the third scan chain is the scan chain 3 in the second compression channel as an example. It can be seen from FIG. 12 that the scan chain where the first scan register C4 is located is scan chain 2
  • the compression channel where scan chain 2 is located is the first compression channel
  • the scan chain where the first fan-in scan registers C2 and C1 are located is scan chain 1.
  • the compression channel where the scan chain 1 is located is also the first compression channel.
  • the compression channel where the first scan register C4 is located is the same as the compression channels where the first fan-in scan registers C2 and C1 are located.
  • the scan chain 1 where the first fan-in scan registers C2 and C1 are located can be exchanged with the scan chain 3 in the second compression channel, so that after the scan chain is exchanged, the compression channel where the scan chain 2 is located is the same as the scan chain 3 in the second compression channel.
  • Chain 1 is in a different compression channel. That is, after the scan chains are exchanged, the compression channel where the first scan register C4 is located is different from the compression channels where the corresponding first fan-in scan registers C2 and C1 are located.
  • the scan chain structure after exchanging the second scan chain with the third scan chain in the second compression channel is shown in Figure 13.
  • the ideal values of scan registers C6, C5, and C4 in scan chain 2 are ⁇ 1 1 1 ⁇
  • the ideal values of scan registers Cx, Cy, and Cz in scan chain 3 are ⁇ 1 1 1 ⁇
  • the ideal values of scan registers C6, C5, C4 and scan registers Cx, Cy, and Cz after XOR operation are ⁇ 0 0 0 ⁇
  • scan chain 3 is a normal scan chain (scan chain 3 has no fault) as an example. Taking the occurrence of SA0 in scan registers C6, C5, and C4 as an example, the reason why the diagnostic accuracy of the scan chain can be improved after the scan chain is exchanged is described below.
  • the values captured by scan registers C6, C5, and C4 are ⁇ 0 1 1 ⁇ , and the values captured by scan registers Cx, Cy, and Cz are ⁇ 1 1 1 ⁇ .
  • the output values of scan registers C6, C5, and C4 are ⁇ 0 1 1 ⁇ , the output values of scan registers Cx, Cy, and Cz are ⁇ 1 1 1 ⁇ , and the scan registers C6,
  • the output value of C5, C4 and the value of scanning register Cx, Cy and Cz carry out XOR operation and the result is ⁇ 1 0 0 ⁇ .
  • the values captured by scan registers C6, C5, and C4 are ⁇ 1 1 1 ⁇ , and the values captured by scan registers Cx, Cy, and Cz are ⁇ 1 1 1 ⁇ .
  • the output values of scan registers C6, C5, and C4 are ⁇ 0 0 1 ⁇ , and the output values of scan registers Cx, Cy, and Cz are ⁇ 1 1 1 ⁇ .
  • the output value of C5, C4 and the value of scanning register Cx, Cy and Cz carry out XOR operation and the result is ⁇ 1 1 0 ⁇ .
  • the values captured by scan registers C6, C5, and C4 are ⁇ 1 1 1 ⁇ , and the values captured by scan registers Cx, Cy, and Cz are ⁇ 1 1 1 ⁇ .
  • the output values of scan registers C6, C5, and C4 are ⁇ 0 0 0 ⁇ , and the output values of scan registers Cx, Cy, and Cz are ⁇ 1 1 1 ⁇ .
  • the output value of C5, C4 and the value of scanning register Cx, Cy and Cz are XORed and the result is ⁇ 1 1 1 ⁇ .
  • the influence of the channel output value makes the output values of the first three scan registers in the first compression channel not necessarily ⁇ 0 1 1 ⁇ , so by adjusting the value of the logic test vector, the faulty scan register can be determined more accurately in the diagnosis stage , improve scan chain diagnostic accuracy.
  • the output value of the first compression channel is no longer affected by the scan registers Cg, Cf.
  • the impact of Ce can eliminate the influence of strong coupling between scan registers C6, C5, C4 and scan registers Cg, Cf, Ce on the output value of the first compression channel, so that the first three scan registers in the first compression channel
  • the output value is not necessarily ⁇ 0 1 1 ⁇ .
  • FIG. 11 illustrates an example in which step S504 is executed after step S503.
  • the embodiment of the present application also provides a scan chain design method, as shown in FIG. 14 , in addition to the above steps S501-S504, the method may further include steps S505-S506.
  • S505. Determine the capture probability of each scan register in the first scan chain.
  • the capture probability of each scan register is used to indicate the probability that the scan register captures 0 or 1.
  • the capture probability of each scan register may be a value between 0 and 1. The closer the capture probability of the scan register is to 0, the greater the probability that the scan register captures 0. The closer the capture probability of the scan register is to 1, the greater the probability of the scan register capturing 1.
  • PC1(C) represents the probability that the scan register C captures 1
  • PC0(C) represents the probability that the scan register C captures 0
  • PC0(C) 1 ⁇ PC1(C).
  • the scan chain includes serially cascaded scan registers C1 to C5, and any two adjacent scan registers C1 to C5 In the scan registers, the output terminal Q of the previous scan register is connected to the SI terminal of the next scan register.
  • any fan-in scan register (say, Ca) has a probability of capturing a 1 of 0.5
  • the probability of a scan register C1 capturing a 1 is the product of the probabilities of its fan-in scan registers Ca to Ce capturing a 1
  • the capture probabilities of two adjacent scan registers in the first scan chain are both greater than a preset threshold, or, in the case that the capture probabilities of two adjacent scan registers in the first scan chain are both less than or equal to a preset threshold , adjusting the connection relationship between multiple scan registers in the first scan chain, so that the capture probability of one scan register in two adjacent scan registers is greater than a preset threshold, and the capture probability of the other scan register is less than or equal to a preset threshold.
  • the scan register when the capture probability of the scan register is greater than 0.5, the scan register has a higher probability of capturing 1. When the capture probability of the scan register is less than or equal to 0.5, the scan register has a higher probability of capturing 0.
  • the capture probabilities of two adjacent scan registers in the first scan chain are both greater than a preset threshold, it means that the two adjacent scan registers have a higher probability of capturing 1.
  • the capture probabilities of two adjacent scan registers in the first scan chain are both less than or equal to the preset threshold, it means that the two adjacent scan registers have a higher probability of capturing 0.
  • the capture probabilities of scan registers C1, C2 and C3 are all less than or equal to 0.5, so scan registers C1, C2 and C3 are more likely to capture the same value 0, then it will be difficult to distinguish scan register C1 , C2, and C3 have SA0, and in the scan chain diagnosis stage, it is impossible to accurately locate which scan register is faulty. That is, if multiple adjacent scan registers have a high probability of capturing the same value 0, it is difficult to distinguish which scan register has SA0.
  • the capture probabilities of scan registers C4 and C5 are both greater than 0.5, so scan registers C4 and C5 are more likely to capture 1, then it will be difficult to distinguish the situation where SA1 appears in scan registers C4 and C5.
  • the scan chain diagnosis stage It is impossible to accurately locate which scan register is faulty. That is, if multiple adjacent scan registers have a high probability of capturing the same value 1, it is difficult to distinguish which scan register has SA1.
  • the connection relationship of multiple scan registers in the scan chain can be adjusted so that among any two adjacent scan registers in the scan chain, one scan register has a higher probability of capturing 0, and one scan register captures 0.
  • the scan register has a higher probability of capturing 1, which makes it easier for two adjacent scan registers to capture different values. That is to say, in the scan chain after the connection relationship is exchanged, any two adjacent scan registers are more likely to capture different values.
  • the scan registers C1, C4, C2, C5, and C3 in the scan chain after exchanging the connection relationship are serially cascaded, and any two adjacent scan Among the registers, one scan register has a higher probability of capturing 0, and the other scan register has a higher probability of capturing 1, that is, any two adjacent scan registers are more likely to capture different values, so that SA0 or When SA1 is used, it is easier to determine the faulty scan register and improve the diagnostic accuracy of the scan chain.
  • the possibility of capturing the same value in two adjacent scan registers in the first scan chain is relatively small.
  • the connection relationship between multiple scan registers in the first scan chain it is more likely that two adjacent scan registers capture different values, so that when the faulty scan register is detected based on the scan chain after the connection relationship is adjusted , it is easier to determine the faulty scan register, and improve the diagnostic accuracy of the scan chain.
  • the embodiment of the present application also provides a chip, the chip includes a first scan chain and a second scan chain, the first scan chain and the second scan chain are different scan chains, and the second scan register in the second scan chain is fan-in The first scan register in the first scan chain.
  • the first scan chain and the second scan chain are scan chains in different compression channels.
  • the capture probability of one scan register is greater than a preset threshold, and the capture probability of the other scan register is less than or equal to a preset threshold. That is, it is more likely that two adjacent scan registers in the first scan chain capture different values.
  • the embodiment of the present application also provides a chip, the chip includes a first scan chain, the second scan register in the first scan chain is fanned into the first scan register in the first scan chain, the second scan register is larger than the The first scan register is closer to the shift input end of the first scan chain.
  • the capture probability of one scan register is greater than a preset threshold, and the capture probability of the other scan register is less than or equal to a preset threshold. That is, it is more likely that two adjacent scan registers in the first scan chain capture different values.
  • the electronic device includes hardware structures and/or software modules corresponding to each function.
  • the present application can be realized in a combined form of hardware and computer software in combination with the units and algorithm steps of each example described in the embodiments disclosed herein.
  • Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.
  • the embodiment of the present application may divide the electronic device into functional modules according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. It should be noted that the division of modules in the embodiment of the present application is schematic, and is only a logical function division, and there may be other division methods in actual implementation.
  • FIG. 17 shows a schematic structural diagram of a scan chain design device 1700.
  • the scan chain design device can be the electronic device in the above embodiment, or a chip in the electronic device.
  • the scan chain design device 1700 can be used to realize the above-mentioned The scan chain design method of any embodiment.
  • the scan chain design apparatus 1700 includes: a processing unit 1701 and a transceiver unit 1702 .
  • the transceiver unit 1702 is used to support the scan chain design apparatus 1700 to send and receive information, or to communicate with other devices.
  • the processing unit 1701 is used to control and manage the actions of the scan chain design device 1700, and to execute the processing performed by the scan chain design device 1700 in the above embodiment.
  • the scan chain design device 1700 includes a storage unit, then The processing unit 1701 may also execute programs or instructions stored in the memory, so that the scan chain design apparatus 1700 implements the methods and functions involved in any of the foregoing embodiments.
  • the above-mentioned processing unit 1701 may be used to execute, for example, steps S502-S503 in FIG. 5, or steps S502-S504 in FIG. 11, or steps S502-S506 in FIG. 14, and/or used herein Other procedures for the techniques described.
  • the transceiving unit 1702 may be used to perform, for example, step S501 in FIG. 5 , and/or other processes for the technologies described herein. Wherein, all relevant content of each step involved in the above-mentioned method embodiment can be referred to the function description of the corresponding function module, and will not be repeated here.
  • the function of the processing unit 1701 may be performed by the processor 401, and the function of the transceiver unit 1702 may be performed by the transceiver 403 (transmitter/receiver) and/or a communication interface, wherein the processing unit 1701 It can be embedded in or independent of the processor of the scan chain design device 1700 in the form of hardware, and can also be stored in the memory of the scan chain design device 1700 in the form of software, so that the processor can call and execute the operations corresponding to the above functional units.
  • the processing unit 1701 is a processor and the transceiver unit 1702 is a transceiver
  • the specific structure of the scan chain design device shown in FIG. 17 can be the electronic device shown in FIG.
  • the description of all relevant content may refer to the functional description of the corresponding components in FIG. 17 , which will not be repeated here.
  • the embodiment of the present application also provides an electronic device, the electronic device includes a processor, and may also include a transceiver and a memory, the transceiver is used to send and receive information, or to communicate with other network elements; the memory is used to store the Instructions; a processor, configured to execute the computer-executed instructions to support the detection device to implement the scan chain design method shown in any one of FIG. 5 , FIG. 11 or FIG. 14 .
  • the embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores computer program codes, and when the above-mentioned processor executes the computer program codes, the electronic device executes any of Fig. 5 , Fig. 11 or Fig. 14 .
  • the embodiment of the present application also provides a computer program product, which, when running on a computer, causes the computer to execute the scan chain design method shown in any one of FIG. 5 , FIG. 11 or FIG. 14 .
  • the embodiment of the present application also provides a scan chain design device, which can exist in the product form of a chip.
  • the structure of the device includes a processor and an interface circuit, and the processor is used to communicate with other devices through the interface circuit, so that the The device executes the scan chain design method shown in any one of FIG. 5 , FIG. 11 or FIG. 14 above.
  • the steps of the methods or algorithms described in connection with the disclosure of this application can be implemented in the form of hardware, or can be implemented in the form of a processor executing software instructions.
  • Software instructions can be composed of corresponding software modules, and software modules can be stored in random access memory (Random Access Memory, RAM), flash memory, erasable programmable read-only memory (Erasable Programmable ROM, EPROM), electrically erasable Programmable read-only memory (Electrically EPROM, EEPROM), registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
  • the storage medium may also be a component of the processor.
  • the processor and storage medium can be located in the ASIC.
  • the ASIC may be located in the core network interface device.
  • the processor and the storage medium may also exist in the core network interface device as discrete components.
  • the functions described in the present invention may be implemented by hardware, software, firmware or any combination thereof.
  • the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage media may be any available media that can be accessed by a general purpose or special purpose computer.

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Abstract

一种扫描链设计方法、装置及芯片，涉及芯片领域，通过调整扫描链结构，能够有效的提高扫描链的诊断精度。具体方案为：获取用于指示多个扫描链与组合逻辑之间的连接关系的初始扫描链结构，基于初始扫描链结构，确定第一扫描链中第一扫描寄存器对应的第一扇入扫描寄存器所在的扫描链，该第一扇入扫描寄存器为扇入第一扫描寄存器的扫描寄存器；在第一扇入扫描寄存器所在的扫描链与第一扫描寄存器所在的扫描链相同的情况下，将第一扇入扫描寄存器与第二扫描链中的第二扫描寄存器交换。

Description

一种扫描链设计方法、装置及芯片 技术领域
本申请实施例涉及芯片领域，尤其涉及一种扫描链设计方法、装置及芯片。
背景技术
随着半导体技术的发展，芯片内部的逻辑越来越复杂，为了提高芯片质量，在芯片出厂时一般要对芯片进行测试。在芯片测试领域中，可以采用扫描链Scan Chain检测芯片中移位寄存器链上的故障。
采用扫描链测试芯片时，可以通过扫描链测试向量观测一条或多条Scan Chain，如果扫描链的观测输出值与理想输出值不相同，确定扫描链发生故障。为了提高芯片测试的扫描链诊断精度(Chain Diagnosis Resolution，CDR)，一种方法是通过增加逻辑测试向量，使得扫描链的故障能够被更多的逻辑测试向量观测到，从而提高CDR。但是该方法将会导致芯片测试的时间增加，测试成本较大。另一种方法是在芯片中增加更多的测试电路，使得Scan Chain的故障有更多的传播路径，从而提高CDR。但是该方法会增加芯片的面积，成本较高。
发明内容
本申请实施例提供一种扫描链设计方法、装置及芯片，通过调整扫描链结构，能够提高扫描链的诊断精度。
为达到上述目的，本申请实施例采用如下技术方案：
本申请实施例的第一方面，提供一种扫描链设计方法，该方法包括：首先，获取用于指示多个扫描链与组合逻辑之间的连接关系的初始扫描链结构，每个扫描链可以包括串行级联的多个扫描寄存器；其次，基于初始扫描链结构，确定第一扫描链中第一扫描寄存器对应的第一扇入扫描寄存器所在的扫描链；该第一扫描链为多个扫描链中的任一个扫描链，第一扇入扫描寄存器为扇入第一扫描寄存器的扫描寄存器；然后，在第一扇入扫描寄存器所在的扫描链与第一扫描寄存器所在的扫描链相同的情况下，将第一扇入扫描寄存器与第二扫描链中的第二扫描寄存器交换；多个扫描链包括第二扫描链。
基于本方案，由于第一扇入扫描寄存器与第一扫描寄存器位于同一扫描链时，当第一扫描链中存在故障的扫描寄存器时，该故障扫描寄存器的故障值很可能会影响第一扇入扫描寄存器的观测值，导致扫描链的诊断精度较低。因此本方案在第一扫描寄存器及与其对应的第一扇入扫描寄存器位于同一扫描链的情况下，通过将第一扇入扫描寄存器与第二扫描寄存器进行交换，能够在一定程度上降低第一扫描链中其他故障扫描寄存器对该第一扇入扫描寄存器的影响，有助于第一扇入扫描寄存器产生不同的观测值，从而能够缩小故障扫描寄存器的范围，提高扫描链诊断精度。而且基于该精度较高的诊断结果进行失效分析时，能够降低失效分析的难度，有助于芯片制造工艺的改进，有利于提高芯片良率。可以理解的，本申请实施例提供的扫描链设计方法是 通过调整扫描链结构提高扫描链的诊断精度的，与现有技术中通过在芯片中增加更多的测试电路相比，本方案不需要额外增加测试电路，就可以提高扫描链诊断精度，因此本方案不会增加芯片面积，成本较低。与现有技术中通过增加逻辑测试向量相比，本方案不需要增加逻辑测试向量，就可以提高扫描链诊断精度，因此能够节省测试时间，降低测试成本。
在一种可能的实现方式中，上述第二扫描链与第一扫描链为不同的扫描链。
基于本方案，由于第一扇入扫描寄存器与第一扫描寄存器位于同一扫描链时，当第一扫描链中存在故障的扫描寄存器时，该故障扫描寄存器的故障值很可能会影响第一扇入扫描寄存器的观测值，导致扫描链的诊断精度较低。而当第一扇入扫描寄存器与第一扫描寄存器位于不同的扫描链时，能够降低第一扫描链中其他故障扫描寄存器对该第一扇入扫描寄存器的影响，有助于第一扇入扫描寄存器产生不同的观测值，从而能够缩小故障扫描寄存器的范围，提高扫描链诊断精度。因此，本方案在第一扫描寄存器及与其对应的第一扇入扫描寄存器位于同一扫描链的情况下，通过将第一扇入扫描寄存器与另一扫描链中的第二扫描寄存器进行交换，使得第一扫描寄存器及与其对应的第一扇入扫描寄存分别位于不同的扫描链，从而基于交换扫描寄存器后的扫描链检测故障扫描单元时，能够降低第一扫描链中故障扫描寄存器对扇入扫描寄存器的影响，提高扫描链的诊断精度。
在一种可能的实现方式中，上述第二扫描链与第一扫描链为同一个扫描链；其中，在将第一扇入扫描寄存器与第二扫描链中的第二扫描寄存器交换之前，第一扫描寄存器较第一扇入扫描寄存器更靠近第一扫描链的移位输入端，第二扫描寄存器为第一扫描链中较第一扫描寄存器更靠近移位输入端的扫描寄存器。
基于本方案，由于第一扇入扫描寄存器离第一扫描链的移位输入端越远，该第一扫描链中较第一扇入扫描寄存器靠近移位输入端的扫描寄存器如果发生故障，该故障扫描寄存器的故障值，会影响第一扇入扫描寄存器的观测值，导致扫描链的诊断精度较低。而当第一扇入扫描寄存器越靠近第一扫描链的移位输入端时，越能降低第一扫描链中其他故障扫描寄存器对该第一扇入扫描寄存器的影响，有助于第一扇入扫描寄存器产生不同的观测值，从而能够缩小故障扫描寄存器的范围，提高扫描链诊断精度。因此本申请在第一扫描寄存器及与其对应的第一扇入扫描寄存器位于同一扫描链，且第一扫描寄存器较其对应的第一扇入扫描寄存器更靠近第一扫描链的移位输入端的情况下，通过将第一扇入扫描寄存器与第二扫描链中靠近第二扫描链的移位输入端的第二扫描寄存器进行交换，从而使得第一扇入扫描寄存器较其他扫描寄存器更靠近第二扫描链的移位输入端，从而基于交换扫描寄存器后的扫描链检测故障扫描单元时，能够降低第一扫描链中故障扫描寄存器对扇入扫描寄存器的影响，提高扫描链的诊断精度。
在一种可能的实现方式中，上述初始扫描链结构包括多个压缩通道，每个压缩通道包括的至少两个扫描链的移位输出端之间做逻辑运算，上述方法还包括：在第二扫描链所在的压缩通道与第一扫描链所在的压缩通道相同的情况下，将第二扫描链与另一压缩通道中的第三扫描链交换。
基于本方案，由于第一扇入扫描寄存器与第一扫描寄存器位于同一压缩通道时， 该压缩通道内第一扫描寄存器与第一扇入扫描寄存器之间的耦合性较强，第一扇入扫描寄存器如果发生故障，该第一扇入扫描寄存器的故障值很可能会对第一扫描寄存器捕获的数值造成影响，进而对该压缩通道的输出值造成影响，导致无法区分故障的扫描寄存器，造成扫描链的诊断精度较低。而本方案在第二扫描链与第一扫描链所在的压缩通道相同的情况下，通过将第一扫描寄存器与第一扇入扫描寄存器设置在不同的压缩通道，从而基于交换扫描链后的压缩通道检测故障扫描单元时，能够降低同一压缩通道中的多个扫描链之间的耦合性，提升扫描链诊断精度。
在一种可能的实现方式中，所述方法还包括：确定所述第一扫描链中每个扫描寄存器的捕获概率；所述每个扫描寄存器的捕获概率用于指示该扫描寄存器捕获0或1的概率；在所述第一扫描链中相邻两个扫描寄存器的捕获概率均大于预设阈值，或者，在第一扫描链中相邻两个扫描寄存器的捕获概率均小于或等于预设阈值的情况下，调整所述第一扫描链中多个扫描寄存器之间的连接关系，使得相邻两个扫描寄存器中一个扫描寄存器的捕获概率大于预设阈值，另一个扫描寄存器的捕获概率小于或等于所述预设阈值。
基于本方案，由于扫描链中相邻扫描寄存器捕获的数值相同时，在扫描链诊断阶段，不容易定位出具体是哪个扫描寄存器故障。而本方案通过确定第一扫描链中每个扫描寄存器的捕获概率，并在第一扫描链中相邻两个扫描寄存器捕获相同数值的可能性较大时，通过调整第一扫描链中多个扫描寄存器之间的连接关系，使得相邻两个扫描寄存器捕获不同数值的可能性较大，从而基于调整连接关系后的扫描链检测故障扫描寄存器时，能够更容易确定出故障的扫描寄存器，提升扫描链的诊断精度。
本申请实施例的第二方面，提供一种扫描链设计方法，该方法包括：获取用于指示多个扫描链与组合逻辑之间的连接关系的初始扫描链结构；该初始扫描链结构包括多个压缩通道，每个压缩通道包括至少两个扫描链，每个压缩通道中的至少两个扫描链的移位输出端之间进行逻辑运算，每个扫描链包括多个扫描寄存器；基于初始扫描链结构，确定第一扫描链中第一扫描寄存器对应的第一扇入扫描寄存器所在的扫描链；第一扇入扫描寄存器为扇入第一扫描寄存器的扫描寄存器，第一扫描链为多个扫描链中的任一个扫描链，所述第一扇入扫描寄存器所在的扫描链为第二扫描链，多个扫描链包括第二扫描链；在第一扫描链和第二扫描链所在的压缩通道相同的情况下，将第二扫描链与另一压缩通道中的第三扫描链交换。
在一种可能的实现方式中，上述方法还包括：确定第一扫描链中每个扫描寄存器的捕获概率；每个扫描寄存器的捕获概率用于指示该扫描寄存器捕获0或1的概率；在第一扫描链中相邻两个扫描寄存器的捕获概率均大于预设阈值，或者，在第一扫描链中相邻两个扫描寄存器的捕获概率均小于或等于预设阈值的情况下，调整第一扫描链中多个扫描寄存器之间的连接关系，使得相邻两个扫描寄存器中一个扫描寄存器的捕获概率大于预设阈值，另一个扫描寄存器的捕获概率小于或等于预设阈值。
上述第二方面的效果描述可以参考第一方面的效果描述，在此不再赘述。
本申请实施例的第三方面，提供一种芯片，该芯片包括第一扫描链和第二扫描链，第一扫描链和第二扫描链为不同的扫描链，第一扫描链中的第一扫描寄存器扇入第二扫描链中的第二扫描寄存器。
基于本方案，通过将第二扫描寄存器及与其对应的扇入扫描寄存器(第一扫描寄存器)分别设置在不同的扫描链，能够降低第一扫描链中故障扫描寄存器对扇入扫描寄存器的影响，从而基于该扫描链结构检测故障扫描单元时，能够提高扫描链的诊断精度。
在一种可能的实现方式中，上述第一扫描链和第二扫描链为不同压缩通道中的扫描链；其中，该压缩通道包括至少两个扫描链，压缩通道中的至少两个扫描链的移位输出端之间进行逻辑运算。
基于本方案，通过将第二扫描寄存器及与其对应的扇入扫描寄存器(第一扫描寄存器)分别设置在不同的压缩通道，从而基于该扫描链结构检测故障扫描单元时，能够降低同一压缩通道中的多个扫描链之间的耦合性，提升扫描链诊断精度。
在一种可能的实现方式中，上述第一扫描链中相邻两个扫描寄存器中，一个扫描寄存器的捕获概率大于预设阈值，另一个扫描寄存器的捕获概率小于或等于预设阈值。
基于本方案，通过将捕获不同数值可能性较大的两个扫描寄存器设置为相邻的扫描寄存器，从而基于该扫描链检测故障扫描寄存器时，能够更容易确定出故障的扫描寄存器，提升扫描链的诊断精度。
本申请实施例的第四方面，提供一种芯片，该芯片包括第一扫描链，该第一扫描链中的第一扫描寄存器扇入第一扫描链中的第二扫描寄存器，第一扫描寄存器较第二扫描寄存器更靠近第一扫描链的移位输入端。
基于本方案，通过将扇入扫描寄存器(第一扫描寄存器)设置在较第二扫描寄存器更靠近第一扫描链的移位输入端，能够降低第一扫描链中故障扫描寄存器对扇入扫描寄存器的影响，从而基于该扫描链结构检测故障扫描单元时，能够提高扫描链的诊断精度。
在一种可能的实现方式中，所述第一扫描链中相邻两个扫描寄存器中，一个扫描寄存器的捕获概率大于预设阈值，另一个扫描寄存器的捕获概率小于或等于所述预设阈值。
基于本方案，通过将捕获不同数值可能性较大的两个扫描寄存器设置为相邻的扫描寄存器，从而基于该扫描链检测故障扫描寄存器时，能够更容易确定出故障的扫描寄存器，提升扫描链的诊断精度。
本申请实施例的第五方面，提供一种扫描链设计装置，该扫描链设计装置包括处理器和存储器，所述存储器用于存储计算机程序；所述处理器用于执行所述计算机程序，使得所述电子设备执行上述第一方面或第二方面所述的方法。
本申请实施例的第六方面，提供一种芯片，所述芯片包括处理器和接口电路，所述处理器用于通过所述接口电路与其它装置通信，以实现上述第一方面或第二方面所述的方法。
本申请实施例的第七方面，提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序代码，当所述计算机程序代码在处理器上运行时，使得所述处理器执行上述第一方面或第二方面所述的方法。
本申请实施例的第八方面，提供了一种计算机程序产品，该程序产品储存有上述处理器执行的计算机软件指令，该计算机软件指令包含用于执行上述第一方面或第二 方面所述方案的程序。
附图说明
图1为本申请实施例提供的一种普通寄存器及扫描寄存器的结构示意图；
图2为本申请实施例提供的一种扫描链的结构示意图；
图3为本申请实施例提供的一种初始扫描链结构的示意图；
图4为本申请实施例提供的一种电子设备的结构示意图；
图5为本申请实施例提供的一种扫描链设计方法的流程示意图；
图6为本申请实施例提供的一种扫描链设计方法的应用示意图一；
图7为本申请实施例提供的一种扫描链设计方法的应用示意图二；
图8为本申请实施例提供的一种扫描链设计方法的应用示意图三；
图9为本申请实施例提供的一种扫描链设计方法的应用示意图四；
图10为本申请实施例提供的另一种初始扫描链结构的示意图；
图11为本申请实施例提供的另一种扫描链设计方法的流程示意图；
图12为本申请实施例提供的再一种初始扫描链结构的示意图；
图13为本申请实施例提供的一种扫描链设计方法的应用示意图五；
图14为本申请实施例提供的再一种扫描链设计方法的流程示意图；
图15为本申请实施例提供的再一种初始扫描链结构的示意图；
图16为本申请实施例提供的一种扫描链设计方法的应用示意图六；
图17为本申请实施例提供的一种扫描链设计装置的组成示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c，或，a和b和c，其中a、b和c可以是单个，也可以是多个。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定。比如，本申请实施例中的第一扫描寄存器中的“第一”和第二扫描寄存器中的“第二”仅用于区分不同的扫描寄存器。本申请实施例中出现的第一、第二等描述，仅作示意与区分描述对象之用，没有次序之分，也不表示本申请实施例中对设备个数的特别限定，不能构成对本申请实施例的任何限制。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
随着半导体技术的发展，芯片内部的逻辑越来越复杂，为了提高芯片质量，在芯 片出厂时一般要对芯片进行测试。在芯片测试领域中，可以采用扫描链Scan Chain检测芯片中移位寄存器链上的故障。扫描链可以由多个扫描寄存器串行级联组成。
首先，对扫描寄存器的概念进行解释。图1中的(a)为一种普通寄存器的结构示意图，如图1中的(a)所示，该寄存器包括数据输入端D、时钟输入端CLK、数据输出端Q和数据输出端QN。寄存器的时钟输入端的时钟有效沿可以为上升沿，也可以为下降沿。以寄存器的时钟有效沿为上升沿为例，当时钟输入端由低电平变化为高电平时，寄存器对数据输入端D进行采样，并把采样值送到数据输出端Q。当时钟输入端为其它情况时数据输出端Q维持原采样值直至时钟输入端第二次由低电平变化为高电平。数据输出端QN是对数据输出端Q进行反向。
图1中的(b)为一种扫描寄存器的结构示意图，与图1中的(a)所示的普通寄存器相比，扫描寄存器中增加了选择器(multiplexer，MUX)。如图1中的(b)所示，扫描寄存器包括逻辑数据输入端D、扫描数据输入端(scan in，SI)、扫描使能端(scan enable，SE)、时钟输入端CLK、数据输出端Q和数据输出端QN。选择器MUX通过扫描使能端SE选择扫描寄存器的输入为逻辑数据输入端D或扫描数据输入端SI。故扫描寄存器的时钟有效沿到来时，扫描寄存器的输出值与扫描使能端SE的值有关。
可选的，在扫描使能端SE为0时，扫描寄存器的输入可以为逻辑数据输入端D的数值，在扫描使能端SE为1时，扫描寄存器的输入可以为扫描数据输入端SI的数值。或者，在扫描使能端SE为1时，扫描寄存器的输入可以为逻辑数据输入端D的数值，在扫描使能端SE为0时，扫描寄存器的输入可以为扫描数据输入端SI的数值。本申请对此并不限定，下述实施例以扫描使能端SE为0时，扫描寄存器的输入为逻辑数据输入端D的数值，扫描使能端SE为1时，扫描寄存器的输入为扫描数据输入端SI的数值为例进行说明。
例如，以扫描寄存器的时钟有效沿为上升沿为例，在扫描使能端SE为0的情况下，当时钟输入端由低电平变化为高电平时，扫描寄存器对逻辑数据输入端D进行采样，并把采样值送到数据输出端Q。在扫描使能端SE为1的情况下，当时钟输入端由低电平变化为高电平时，扫描寄存器对扫描数据输入端SI进行采样，并把采样值送到数据输出端Q。
可选的，扫描链中任一个扫描寄存器(比如，扫描寄存器1)的逻辑数据输入端D用于与组合逻辑的输出端耦合连接，该组合逻辑的输入端与另一扫描寄存器(比如，扫描寄存器2和扫描寄存器3)的输出端耦合连接。该扫描寄存器2和扫描寄存器3可以称为扫描寄存器1对应的扇入扫描寄存器，该组合逻辑可以称为扫描寄存器1对应的扇入组合逻辑。本申请实施例对于每个扫描寄存器对应的扇入扫描寄存器的具体数量以及扇入组合逻辑的具体运算方式并不进行限定。
接下来，对扫描链scan chain的概念进行介绍。图2为一种扫描链的结构示意图，以扫描链包括3个扫描寄存器为例，如图2所示，相邻两个扫描寄存器中前一个扫描寄存器的数据输出端Q与后一个扫描寄存器的扫描数据输入端SI耦合连接，当每个扫描寄存器的扫描使能端SE为1时，图2所示的3个扫描寄存器首尾相连可以组成一个扫描链scan chain。
在测试扫描链是否故障时，可以由自动测试设备(automatic test equipment，ATE) 对扫描链进行检测。该ATE设备根据扫描链测试向量控制扫描链中每个扫描寄存器的扫描使能端SE为1，使得扫描链中的多个扫描寄存器组成移位寄存器。ATE设备通过向扫描链中的第一个扫描寄存器的扫描数据输入端SI输入扫描链测试向量，观测该扫描链的输出值。如果扫描链的观测输出值与扫描链测试向量不相同，确定该扫描链发生故障。ATE设备还可以根据逻辑测试向量，对扫描链中故障的扫描单元(比如，扫描寄存器)进行检测。在诊断阶段，EDA工具或者工程师根据ATE设备的检测结果，诊断出故障的扫描链，以及扫描链中故障的扫描单元。通常可以使用扫描链诊断精度(Chain Diagnosis Resolution，CDR)表示扫描链的诊断精度，CDR越小表示诊断精度越高。例如，CDR的最小值可以为1，CDR值为1表示扫描链的诊断精度可以精确到唯一的扫描寄存器。
下面分三个阶段对ATE设备根据逻辑测试向量，检测扫描链中故障扫描单元的方法进行介绍。
移入load阶段：ATE设备根据逻辑测试向量控制扫描链中每个扫描寄存器的扫描使能端SE为1，扫描链中的多个扫描寄存器组成移位寄存器。ATE设备向该扫描链中的第一个扫描寄存器的SI端输入逻辑测试向量，该逻辑测试向量的值可以移位存储至扫描链中的每个扫描寄存器中(即，load阶段可以对扫描链中的每个扫描寄存器置初值)。
捕获capture阶段：一般情况下，在capture阶段扫描链中每个扫描寄存器的扫描使能端SE为0，扫描寄存器切换至非扫描使能状态(即正常数字电路)，每个扫描寄存器的逻辑数据输入端D从该扫描寄存器的扇入组合逻辑捕获数值。capture阶段可以认为是将故障点的值加载至扫描寄存器中，capture阶段每个扫描寄存器捕获的值为该扫描寄存器对应的扇入扫描寄存器在load阶段的load值和扇入组合逻辑运算后的结果。
移出unload阶段：扫描链中每个扫描寄存器的扫描使能端SE为1，扫描链中的多个扫描寄存器组成移位寄存器，将每个扫描寄存器在capture阶段捕获的值串行输出，ATE设备将该输出值与理想输出值进行比较。
但是，按照上述三个阶段测试故障扫描单元时，可能会因为故障扫描寄存器的观测逻辑与故障扫描链上其他扫描寄存器的耦合性较强，导致扫描链诊断精度CDR较低。
例如，以芯片包括两个扫描链，分别为扫描链1和扫描链2，扫描链1为无故障的扫描链，扫描链2中扫描寄存器C6至C4的理想值为{1 1 1}为例，如图3所示，扫描链1包括扫描寄存器Ca至扫描寄存器Cg，扫描链2包括扫描寄存器C0至扫描寄存器C6。扫描链2中扫描寄存器C4对应的扇入扫描寄存器为扫描寄存器C1和扫描寄存器C2(即，扇入该扫描寄存器C4的扫描寄存器为扫描寄存器C1和扫描寄存器C2)，扫描寄存器C5对应的扇入扫描寄存器为扫描寄存器C2和扫描寄存器C3(即，扇入该扫描寄存器C5的扫描寄存器为扫描寄存器C2和扫描寄存器C3)。若扫描链2中仅扫描寄存器C6故障，且出现固定故障0(stuck at 0，SA0)，ATE设备可以分三个阶段(load阶段、capture阶段和unload阶段)检测故障的扫描寄存器，以load阶段扫描链2输入的逻辑测试向量为{1 0 1 1 1 1 1}为例，由于扫描寄存器C6出现SA0， 因此load阶段扫描寄存器C6至C0的值均为0。在capture阶段，扫描寄存器C4捕获的值为扫描寄存器C1的值0与扫描寄存器C2的值0进行异或运算的值，即扫描寄存器C4捕获的值为0。扫描寄存器C5捕获的值为扫描寄存器C2的值0与扫描寄存器C3的值0进行与运算的值，即扫描寄存器C5捕获的值为0。由于扫描寄存器C6出现SA0，因此，在unload阶段，扫描寄存器C6、C5、C4的输出值为{0 0 0}。在诊断阶段，通过将ATE设备的检测结果与理想值进行比较，比如将扫描寄存器C6、C5、C4的输出值为{0 0 0}与扫描寄存器C6、C5、C4的理想值{1 1 1}进行比较，可以确定扫描寄存器C6、C5、C4均可能发生故障。但是，实际上扫描寄存器C5和C4并未发生故障，扫描寄存器C5和C4的输出值错误是因为扫描寄存器C6出现SA0引起的，因此，图3所示的扫描链结构将导致扫描链诊断的精度较低。
可以理解的，由于扫描寄存器C6出现SA0时，会对扫描寄存器C1至C3在load阶段的值造成影响，从而导致在capture阶段扫描寄存器C5和C4捕获的值错误，进而导致扫描寄存器C5和C4的输出值与理想值不同，因此扫描链2中故障的扫描寄存器C6与扫描寄存器C1至C3之间的耦合性，将导致基于图3所示的扫描链进行故障诊断时，扫描链诊断精度CDR较低。
一种提高CDR的方法是通过增加逻辑测试向量，使得扫描链的故障能够被更多的逻辑测试向量观测到，从而提高CDR。但是该方法将会导致芯片测试的时间增加，测试成本较大。另一种方法是在芯片中增加更多的测试电路，使得扫描链的故障有更多的传播路径，从而提高CDR。但是该方法会增加芯片的面积，成本较高。
为了缓解现有技术在提高扫描链诊断精度时，测试时间较长，测试成本较高，芯片面积较大等问题，本申请实施例提供一种扫描链设计方法，基于该设计方法设计的扫描链结构在进行故障诊断时，能够有效的提高扫描链诊断精度，从而基于该诊断结果进行失效分析时，能够降低失效分析的难度，有助于芯片制造工艺的改进，有利于提高芯片良率。而且本申请实施例提供的扫描链设计方法是通过调整扫描链结构提高扫描链的诊断精度的，与现有技术中通过在芯片中增加更多的测试电路相比，本申请不需要额外增加测试电路，就可以提高扫描链诊断精度，因此本申请不会增加芯片面积，成本较低。与现有技术中通过增加逻辑测试向量相比，本方案不需要增加逻辑测试向量，就可以提高扫描链诊断精度，因此能够节省测试时间，降低测试成本。
本申请实施例提供的扫描链设计方法可以由图4所示的电子设备执行，该电子设备上可以运行电子设计自动化(electronic design automation，EDA)等设计工具，下述实施例中的扫描链设计方法可以在EDA工具中运行。如图4所示，该电子设备400包括至少一个处理器401，存储器402、收发器403以及通信总线404。
下面结合图4对该电子设备的各个构成部件进行具体的介绍：
处理器401是电子设备的控制中心，可以是一个处理器，也可以是多个处理元件的统称。例如，处理器401是一个中央处理器(central processing unit，CPU)，也可以是特定集成电路(application specific integrated circuit，ASIC)，或者是被配置成实施本申请实施例的一个或多个集成电路，例如：一个或多个微处理器(digital signal processor，DSP)，或，一个或者多个现场可编程门阵列(field programmable gate array，FPGA)。
其中，处理器401可以通过运行或执行存储在存储器402内的软件程序，以及调用存储在存储器402内的数据，执行电子设备的各种功能。
在具体的实现中，作为一种实施例，处理器401可以包括一个或多个CPU，例如图4中所示的CPU0和CPU1。
在具体实现中，作为一种实施例，电子设备可以包括多个处理器，例如图4中所示的处理器401和处理器405。这些处理器中的每一个可以是一个单核处理器(single-CPU)，也可以是一个多核处理器(multi-CPU)。这里的处理器可以指一个或多个检测设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
存储器402可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器402可以是独立存在，通过通信总线404与处理器401相连接。存储器402也可以和处理器401集成在一起。
其中，所述存储器402用于存储执行本申请方案的软件程序，并由处理器401来控制执行。
收发器403，用于与其他通信装置之间进行通信。当然，收发器403还可以用于与通信网络通信，如以太网，无线接入网(radio access network，RAN)，无线局域网(wireless local area networks，WLAN)等。收发器403可以包括接收单元实现接收功能，以及发送单元实现发送功能。
通信总线404，可以是工业标准体系结构(industry standard architecture，ISA)总线、外部检测设备互连(peripheral component，PCI)总线或扩展工业标准体系结构(extended industry standard architecture，EISA)总线等。该总线可以分为地址总线、数据总线、控制总线等。为便于表示，图4中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
图4中示出的电子设备的结构并不构成对电子设备的限定，实际应用中，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
结合图4，如图5所示，为本申请实施例提供的一种扫描链设计方法，该方法包括以下步骤：
S501、获取初始扫描链结构。
该初始扫描链结构用于指示多个扫描链与组合逻辑之间的连接关系，每个扫描链包括多个扫描寄存器，每个扫描链中的多个扫描寄存器串行级联。
可选的，不同扫描链包括的扫描寄存器的数量可以相同，也可以不同，本申请实施例对此并不限定。
示例性的，初始扫描链结构可以包括：多个扫描链中每个扫描链包括的多个扫描寄存器的标识，每个扫描链中多个扫描寄存器的连接关系，扇入每个扫描寄存器的扫 描寄存器的标识，以及扇入每个扫描寄存器的组合逻辑等信息。
例如，以初始扫描链结构包括图3所示的扫描链结构为例，如图3所示，该初始扫描结构包括扫描链1中的扫描寄存器Cg至扫描寄存器Ca的标识、扫描寄存器Cg至扫描寄存器Ca之间的连接关系。扫描链2中扫描寄存器C6至扫描寄存器C0的标识、该扫描寄存器C6至扫描寄存器C0之间的连接关系。扫描链2中扇入扫描寄存器C4的扫描寄存器为扫描寄存器C1和扫描寄存器C2，扇入扫描寄存器C4的逻辑运算为异或运算，即，该异或运算的输入端分别耦合至扫描寄存器C1和扫描寄存器C2的输出端，该异或运算的输出端耦合至扫描寄存器C4的D端。扫描链2中扇入扫描寄存器C5的扫描寄存器为扫描寄存器C2和扫描寄存器C3，扇入扫描寄存器C5的逻辑运算为与运算，即，该与运算的输入端分别耦合至扫描寄存器C2和扫描寄存器C3的输出端，该与运算的输出端耦合至扫描寄存器C5的D端。
S502、基于初始扫描链结构，确定第一扫描链中第一扫描寄存器对应的第一扇入扫描寄存器所在的扫描链。
该第一扫描链可以为初始扫描链结构包括的多个扫描链中的任意一个扫描链。第一扫描寄存器可以为第一扫描链包括的多个扫描寄存器中的任意一个扫描寄存器。
第一扇入扫描寄存器为扇入上述第一扫描寄存器的扫描寄存器。可选的，扇入上述第一扫描寄存器的扫描寄存器可以为一个，也可以为多个。
第一扇入扫描寄存器所在的扫描链和第一扫描寄存器所在的扫描链可以为同一个扫描链，也可以为不同的扫描链。当第一扇入扫描寄存器所在的扫描链和第一扫描寄存器所在的扫描链为同一个扫描链时，第一扫描链包括第一扫描寄存器和第一扇入扫描寄存器。当第一扇入扫描寄存器所在的扫描链和第一扫描寄存器所在的扫描链为不同的扫描链时，第一扇入扫描寄存器所在的扫描链为多个扫描链中除第一扫描链以外的扫描链。
例如，如图3所示，以第一扫描链为扫描链2，第一扫描寄存器为扫描寄存器C4为例，扇入该扫描寄存器C4的扫描寄存器为扫描寄存器C1和扫描寄存器C2。由于扫描寄存器C1和扫描寄存器C2所在的扫描链为扫描链2，因此，第一扫描寄存器(扫描寄存器C4)与其对应的第一扇入扫描寄存器(扫描寄存器C1和扫描寄存器C2)所在的扫描链相同。
再例如，如图3所示，以第一扫描链为扫描链2，第一扫描寄存器为扫描寄存器C5为例，扇入该扫描寄存器C5的扫描寄存器为扫描寄存器C2和扫描寄存器C3。由于扫描寄存器C2和扫描寄存器C3所在的扫描链为扫描链2，因此，第一扫描寄存器(扫描寄存器C5)与其对应的第一扇入扫描寄存器(扫描寄存器C2和扫描寄存器C3)所在的扫描链相同。
S503、在第一扇入扫描寄存器所在的扫描链为第一扫描链的情况下，将第一扇入扫描寄存器与第二扫描链中的第二扫描寄存器交换。
由于第一扫描寄存器所在的扫描链为第一扫描链，因此当第一扇入扫描寄存器所在的扫描链为第一扫描链时，该第一扇入扫描寄存器所在的扫描链与第一扫描寄存器所在的扫描链相同。即上述步骤S503是在第一扫描寄存器及与其对应的第一扇入扫描寄存器在同一个扫描链的情况下，将第一扇入扫描寄存器与第二扫描链中的第二扫描 寄存器交换。
步骤S503中将第一扇入扫描寄存器与第二扫描链中的第二扫描寄存器交换可以包括两种实现方式，一种实现方式是将第一扫描链中的第一扇入扫描寄存器与另一扫描链(第二扫描链)中的第二扫描寄存器交换，使得第一扫描寄存器与其对应的第一扇入扫描寄存器位于不同的扫描链。另一种实现方式是将第一扇入扫描寄存器与第一扫描链中更靠近该第一扫描链的移位输入端的第二扫描寄存器交换，使得第一扇入扫描寄存器更靠近第一扫描链的移位输入端。下面分别对这两种实现方式进行详细说明。
在第一种实现方式中，步骤S503中的第二扫描链与第一扫描链为不同的扫描链。
例如，如图3所示，以第一扫描链为扫描链2，第二扫描链为扫描链1，第一扫描寄存器为扫描链2中的扫描寄存器C4和扫描寄存器C5，第二扫描寄存器为扫描链1中的扫描寄存器Cd、Cc和Cb为例。扇入扫描寄存器C4的扫描寄存器为扫描寄存器C1和C2，扇入扫描寄存器C5的扫描寄存器为扫描寄存器C2和C3，根据步骤S502可以确定扫描寄存器C1、C2和C3所在的扫描链均为扫描链2，即扫描寄存器C4与其对应的扇入扫描寄存器C1和C2所在的扫描链相同，扫描寄存器C5与其对应的扇入扫描寄存器C2和C3所在的扫描链相同。因此，可以将扫描链2中的扇入扫描寄存器C1、C2和C3与扫描链1中的扫描寄存器Cb、Cc和Cd交换，使得扫描寄存器C4与其对应的扇入扫描寄存器C1和C2分别位于不同的扫描链中，扫描寄存器C5与其对应的扇入扫描寄存器C2和C3分别位于不同的扫描链中，从而能够降低扫描链1中故障扫描寄存器对扇入扫描寄存器的影响，提高扫描链诊断精度。
可选的，在本实现方式中，将第一扇入扫描寄存器与第二扫描寄存器进行交换时，仅改变第一扇入扫描寄存器与第二扫描寄存器所在的扫描链的连接关系，不改变第一扇入扫描寄存器与第二扫描寄存器对应的组合逻辑的连接关系。
示例性的，将第一扫描链中的第一扇入扫描寄存器与第二扫描链中的第二扫描寄存器进行交换时，可以将第一扇入扫描寄存器的SI端和Q端分别在第一扫描链中断开连接，将第二扫描寄存器的SI端和Q端分别在第二扫描链中断开连接，并将第二扫描寄存器的SI端和Q端分别连接至第一扫描链，将第一扇入扫描寄存器的SI端和Q端分别连接至第二扫描链，从而使得第一扫描寄存器与其对应的扇入扫描寄存器分别位于不同的扫描链。
例如，结合图6和图7所示，将扫描链2(第一扫描链)中的扇入扫描寄存器C1、C2和C3与扫描链1(第二扫描链)中的扫描寄存器Cb、Cc和Cd(第二扫描寄存器)进行交换时，可以将扇入扫描寄存器C3的SI端与扫描寄存器C4的Q端断开连接，将扇入扫描寄存器C1的Q端与扫描寄存器C0的SI端断开连接，将扫描寄存器Cd的SI端与扫描寄存器Ce的Q端断开连接，将扫描寄存器Cb的Q端与扫描寄存器Ca的SI端断开连接。并将扇入扫描寄存器C3的SI端与扫描寄存器Ce的Q端连接，将扇入扫描寄存器C1的Q端与扫描寄存器Ca的SI端连接，将扫描寄存器Cd的SI端与扫描寄存器C4的Q端连接，将扫描寄存器Cb的Q端与扫描寄存器C0的SI端连接。如图7所示，交换扫描链1和扫描链2的扫描寄存器后，扫描链2中扫描寄存器C6、C5、C4、Cd、Cc、Cb、C0依次首尾相连，扫描链1中扫描寄存器Cg、Cf、Ce、C3、C2、C1、Ca依次首尾相连。结合图3、图6和图7可知，将扫描链2中的扇入扫 描寄存器C1、C2和C3与扫描链1中的扫描寄存器Cb、Cc和Cd进行交换时，仅改变了扫描链的连接关系，并未改变每个扫描寄存器对应的组合逻辑的连接关系。即，交换扫描寄存器前后，扇入每个扫描寄存器的逻辑运算以及扇入每个扫描寄存器的扫描寄存器保持不变。
接下来结合图7对改变扫描链连接关系后能够提高扫描链诊断精度的原因进行说明。
以将第一扫描链中的第一扇入扫描寄存器与第二扫描链中的第二扫描寄存器交换后的扫描链结构如图7所示，扫描链2中扫描寄存器C6至C4的理想值为{1 1 1}为例，如图7所示，若扫描链2中仅扫描寄存器C6故障，且扫描寄存器C6出现SA0，ATE设备可以分三个阶段(load阶段、capture阶段和unload阶段)检测故障的扫描寄存器，以load阶段扫描链1输入的逻辑测试向量为{1 0 1 1 1 1 1}为例，load阶段扇入扫描寄存器C3至C1的值为{1 1 0}。在capture阶段，扫描寄存器C4捕获的值为扫描寄存器C1的值0与扫描寄存器C2的值1进行异或运算的值，即扫描寄存器C4捕获的值为1。扫描寄存器C5捕获的值为扫描寄存器C2的值1与扫描寄存器C3的值1进行与运算的值，即扫描寄存器C5捕获的值为1。因此，在unload阶段，扫描寄存器C6、C5、C4的输出值为{0 1 1}。在诊断阶段，通过将ATE设备的检测结果与理想值进行比较，比如将扫描寄存器C6、C5、C4的输出值为{0 1 1}与扫描寄存器C6、C5、C4的理想值{1 1 1}进行比较，可以确定可能发生故障的扫描寄存器为扫描寄存器C6。
可以理解的，与图3所示的扫描链结构相比，由于图7所示的扫描链结构中扫描寄存器C4与其对应的扇入扫描寄存器C1和C2分别位于不同的扫描链，扫描寄存器C5与其对应的扇入扫描寄存器C2和C3分别位于不同的扫描链，因此，在load阶段，扇入扫描寄存器C2和C3的load值不会受扫描寄存器C6的SA0的影响，从而在capture阶段，扫描寄存器C4和扫描寄存器C5捕获的值不受扫描寄存器C6的SA0的影响，故通过改变扫描链1的逻辑测试向量的值，可以较为准确的确定故障的扫描寄存器为扫描寄存器C6，扫描链诊断精度较高。而图3所示的扫描链结构中，由于扫描寄存器C4与其对应的扇入扫描寄存器C1和C2位于同一扫描链，扫描寄存器C5与其对应的扇入扫描寄存器C2和C3位于同一扫描链，因此扫描寄存器C6出现的SA0会对扫描寄存器C1至C3在load阶段的值造成影响，不管load阶段输入的逻辑测试向量是什么，扫描寄存器C1至C3的值均为0，从而导致在capture阶段扫描寄存器C5和C4捕获的值始终为0，因此unload阶段扫描寄存器C6、C5和C4输出的值也始终为0。这与扫描寄存器C6、C5、C4的理想值{1 1 1}相比，只能确定出扫描寄存器C6至C4可能发生故障，不能准确的确定出故障的扫描寄存器为扫描寄存器C6，因此扫描链诊断精度较低。
需要说明的是，第一扇入扫描寄存器与第一扫描寄存器在同一条扫描链(第一扫描链)时，该第一扫描链中故障扫描寄存器的故障值，会影响第一扇入扫描寄存器的观测值，导致扫描链的诊断精度较低。而当第一扇入扫描寄存器与第一扫描寄存器在不同扫描链时，能够降低第一扫描链中其他故障扫描寄存器对该第一扇入扫描寄存器的影响，有助于第一扇入扫描寄存器产生不同的观测值，从而能够缩小故障扫描寄存 器的范围，提高扫描链诊断精度。
可以理解的，本申请实施例提供的方法，在第一扫描寄存器及与其对应的第一扇入扫描寄存器位于同一扫描链的情况下，通过将第一扇入扫描寄存器与另一扫描链中的第二扫描寄存器进行交换，使得第一扫描寄存器及与其对应的第一扇入扫描寄存分别位于不同的扫描链，从而基于交换扫描寄存器后的扫描链检测故障扫描单元时，能够降低第一扫描链中故障扫描寄存器对扇入扫描寄存器的影响，提高扫描链的诊断精度。
在第二种实现方式中，步骤S503中的第二扫描链与第一扫描链为同一个扫描链，其中，在将第一扇入扫描寄存器与第二扫描寄存器交换之前，第一扫描寄存器较第一扇入扫描寄存器更靠近第一扫描链的移位输入端，第二扫描寄存器为第一扫描链中较第一扫描寄存器更靠近移位输入端的扫描寄存器。即本实现方式是在第一扫描寄存器及其对应的第一扇入扫描寄存器位于同一个扫描链，且第一扫描寄存器较其对应的第一扇入扫描寄存器更靠近第一扫描链的移位输入端的情况下，通过将第一扇入扫描寄存器与第一扫描链中靠近该第一扫描链的移位输入端的第二扫描寄存器交换，从而使得交换后的第一扫描链中第一扇入扫描寄存器较第一扫描寄存器更靠近第一扫描链的移位输入端。
可选的，第一扫描链的移位输入端也可以称为第一扫描链的主输入(Primary Input)端，第一扫描链的移位输入端为第一扫描链中第一个扫描寄存器的扫描输入SI端。第一扫描链的移位输出端也可以称为第一扫描链的主输出(Primary Onput)端，第一扫描链的移位输出端为第一扫描链中最后一个扫描寄存器的输出端。
例如，如图3所示，以第一扫描链为扫描链2为例，扫描链2的移位输入端为扫描链2中的第一个扫描寄存器C6的SI端。
例如，如图3所示，以第一扫描链为扫描链2，第一扫描寄存器为扫描链2中的扫描寄存器C4和扫描寄存器C5，第二扫描寄存器为扫描链2中的扫描寄存器C6为例。由于扫描寄存器C4与其对应的扇入扫描寄存器C1和C2位于同一扫描链中，扫描寄存器C5与其对应的扇入扫描寄存器C2和C3位于同一扫描链中，而且扫描寄存器C4较其对应的扇入扫描寄存器C1和C2更靠近扫描链2的移位输入端，扫描寄存器C5较其对应的扇入扫描寄存器C2和C3更靠近扫描链2的移位输入端。因此可以将扫描链2中的扇入扫描寄存器C1至C3，与扫描链2中较扫描寄存器C4和扫描寄存器C5更靠近扫描链2的移位输入端的扫描寄存器C6交换，从而使得扫描链2中的扇入扫描寄存器C1至C3更靠近扫描链2的移位输入端，以降低扫描链2中故障扫描寄存器对扇入扫描寄存器的影响，提高扫描链诊断精度。
可选的，在本实现方式中，将第一扇入扫描寄存器与第二扫描寄存器进行交换时，仅改变第一扫描链中多个扫描寄存器的连接关系，不改变扇入第一扫描寄存器的逻辑门，以及扇入第一扫描寄存器的扫描寄存器。
示例性的，将第一扫描链中的第一扇入扫描寄存器与第一扫描链中的第二扫描寄存器进行交换时，可以将第一扇入扫描寄存器的SI端、第一扇入扫描寄存器的Q端、第二扫描寄存器的SI端、第二扫描寄存器的Q端分别在第一扫描链中断开连接，并重新连接第一扇入扫描寄存器和第二扫描寄存器，使得第一扫描链中第一扇入扫描寄存 器较第一扫描寄存器更靠近第一扫描链的移位输入端。
例如，结合图8和图9所示，将扫描链2中的扇入扫描寄存器C1、C2和C3与扫描链2中靠近移位输入端的扫描寄存器C6(第二扫描寄存器)进行交换时，可以将扇入扫描寄存器C3的SI端与扫描寄存器C4的Q端断开连接，将扇入扫描寄存器C1的Q端与扫描寄存器C0的SI端断开连接，将扫描寄存器C6的SI端与扫描链2的输入端口断开连接。并将扇入扫描寄存器C3的SI端与扫描链2的输入端口连接，将扇入扫描寄存器C1的Q端与扫描寄存器C6的SI端连接，将扫描寄存器C4的Q端与扫描寄存器C0的SI端连接。如图9所示，交换扫描链2中多个扫描寄存器的连接关系后，扫描链2中扫描寄存器C3、C2、C1、C6、C5、C4、C0依次首尾相连。结合图3、图8和图9可知，将扫描链2中的扇入扫描寄存器C1、C2和C3与扫描链2中的扫描寄存器C6进行交换时，仅改变了扫描链2中多个扫描寄存器之间的连接关系，并未改变每个扫描寄存器对应的组合逻辑的连接关系。即，交换扫描寄存器前后，扇入每个扫描寄存器的逻辑运算以及扇入每个扫描寄存器的扫描寄存器保持不变。
接下来结合图9对改变第一扫描链中第一扇入扫描寄存器与第二扫描寄存器的连接关系后能够提高扫描链诊断精度的原因进行说明。
以将第一扫描链中的第一扇入扫描寄存器与第一扫描链中的第二扫描寄存器交换后的扫描链结构如图9所示，扫描链2中扫描寄存器C6至C4的理想输出值为{1 1 1}为例，如图9所示，若扫描链2中仅扫描寄存器C6故障，且扫描寄存器C6出现SA0，ATE设备在扫描链2输入扫描链测试向量{1 1 1 1 1 1 0}时，扫描链2的输出观测值为{0 0 0 0 0 0 0}。ATE设备分三个阶段(load阶段、capture阶段和unload阶段)检测故障的扫描寄存器，以load阶段扫描链2输入的逻辑测试向量为{1 1 1 1 0 1 1}为例，load阶段扇入扫描寄存器C3至C1的值为{1 1 0}。在capture阶段，扫描寄存器C4捕获的值为扫描寄存器C1的值0与扫描寄存器C2的值1进行异或运算的值，即扫描寄存器C4捕获的值为1。扫描寄存器C5捕获的值为扫描寄存器C2的值1与扫描寄存器C3的值1进行与运算的值，即扫描寄存器C5捕获的值为1。因此，在unload阶段，扫描寄存器C6、C5、C4的输出值为{0 1 1}。在诊断阶段，通过将ATE设备的检测结果与理想值进行比较，比如将扫描寄存器C6、C5、C4的输出值为{0 1 1}与扫描寄存器C6、C5、C4的理想值{1 1 1}进行比较，可以确定可能发生故障的扫描寄存器为扫描寄存器C6。
可以理解的，与图3所示的扫描链结构相比，由于图9所示的扫描链结构中扇入扫描寄存器C1至C3较扫描链2中的其他扫描寄存器更靠近扫描链2的移位输入端，因此，在load阶段，扇入扫描寄存器C1至C3的load值不会受扫描寄存器C6的SA0的影响，从而在capture阶段，扫描寄存器C4和扫描寄存器C5捕获的值不受扫描寄存器C6的SA0的影响，因此通过改变扫描链2的逻辑测试向量的值，可以较为准确的确定故障的扫描寄存器为扫描寄存器C6，扫描链诊断精度较高。而图3所示的扫描链结构中，由于故障的扫描寄存器C6较扇入扫描寄存器C1至C3更靠近扫描链2的移位输入端，因此扫描寄存器C6出现的SA0会对扫描寄存器C1至C3在load阶段的值造成影响，不管load阶段输入的逻辑测试向量是什么，扫描寄存器C1至C3的值均为0，从而导致在capture阶段扫描寄存器C5和C4捕获的值始终为0，因此unload 阶段扫描寄存器C6、C5和C4输出的值也始终为0。这与扫描寄存器C6、C5、C4的理想值{1 1 1}相比，只能确定出扫描寄存器C6、C5、C4均可能发生故障，不能准确的确定出故障的扫描寄存器为扫描寄存器C6，因此扫描链诊断精度较低。
可选的，在第一扫描寄存器及其对应的第一扇入扫描寄存器位于同一个扫描链，且第一扫描寄存器较其对应的第一扇入扫描寄存器更靠近第一扫描链的移位输入端的情况下，如果第一扫描链的移位输入端与第一扫描寄存器之间不存在第二扫描寄存器(即，第一扫描链的移位输入端为第一扫描寄存器的SI端)，可以将第一扇入扫描寄存器与第一扫描寄存器交换，从而使得交换后的第一扫描链中第一扇入扫描寄存器较第一扫描寄存器更靠近第一扫描链的移位输入端。
需要说明的是，第一扇入扫描寄存器离第一扫描链的移位输入端越远，该第一扫描链中较第一扇入扫描寄存器靠近移位输入端的扫描寄存器如果发生故障，该故障扫描寄存器的故障值，会影响第一扇入扫描寄存器的观测值，导致扫描链的诊断精度较低。而当第一扇入扫描寄存器越靠近第一扫描链的移位输入端时，越能降低第一扫描链中其他故障扫描寄存器对该第一扇入扫描寄存器的影响，有助于第一扇入扫描寄存器产生不同的观测值，从而能够缩小故障扫描寄存器的范围，提高扫描链诊断精度。
可以理解的，本申请实施例提供的方法，在第一扫描寄存器及与其对应的第一扇入扫描寄存器位于同一扫描链，且第一扫描寄存器较其对应的第一扇入扫描寄存器更靠近第一扫描链的移位输入端的情况下，通过将第一扇入扫描寄存器与第二扫描链中靠近第二扫描链的移位输入端的第二扫描寄存器进行交换，从而使得第一扇入扫描寄存器较其他扫描寄存器更靠近第二扫描链的移位输入端，从而基于交换扫描寄存器后的扫描链检测故障扫描单元时，能够降低第一扫描链中故障扫描寄存器对扇入扫描寄存器的影响，提高扫描链的诊断精度。
可选的，初始扫描链结构可以包括多个压缩通道，每个压缩通道包括至少两个扫描链，每个压缩通道中的至少两个扫描链的移位输出端之间做逻辑运算，本申请实施例对于每个压缩通道中的至少两个扫描链的移位输出端之间进行的具体逻辑运算的方式并不进行限定，下述实施例以每个压缩通道包括两个扫描链，该两个扫描链的移位输出端之间进行的逻辑运算为异或运算为例进行说明。
如图10所示，以初始扫描链结构包括图10所示的压缩通道，该压缩通道包括扫描链1和扫描链2，该压缩通道中的扫描链1和扫描链2的移位输出端之间做异或运算，扫描链1中扫描寄存器Cg、Cf、Ce的理想值为{1 1 1}，扫描链2中扫描寄存器C6、C5、C4的理想值为{1 1 1}，扫描寄存器Cg、Cf、Ce与扫描寄存器C6、C5、C4进行异或运算后的理想值为{0 0 0}为例。下面分别以扫描寄存器C6、C5、C4出现SA0为例，对第一扫描寄存器及与其对应的第一扇入扫描寄存器在同一个压缩通道的情况下出现的问题进行详细说明。
结合图10所示，若扫描链2中仅扫描寄存器C6故障，且扫描寄存器C6出现SA0。ATE设备在load阶段向扫描链1输入的逻辑测试向量为{1 0 1 1 1 1 1}，向扫描链2输入的逻辑测试向量为{1 1 1 1 1 1 1}，如下表1所示，由于扫描寄存器C6出现SA0，因此load阶段扫描寄存器C6、C5和C4的值均为0，扫描寄存器C3、C2和C1的值为{1 1 0}。在capture阶段，扫描寄存器C4捕获的值为扫描寄存器C1的值0与扫 描寄存器C2的值1进行异或运算的值，即扫描寄存器C4捕获的值为1。扫描寄存器C5捕获的值为扫描寄存器C2的值1与扫描寄存器C3的值1进行与运算的值，即扫描寄存器C5捕获的值为1。扫描寄存器C6捕获的值为扫描寄存器C6的值为0，扫描寄存器Cg捕获的值为扫描寄存器C4的值为0，扫描寄存器Cf捕获的值为扫描寄存器C6的值为0，扫描寄存器Ce捕获的值为扫描寄存器C5的值为0。即扫描寄存器C6、C5、C4捕获的值为{0 1 1}，扫描寄存器Cg、Cf、Ce的捕获的值{0 0 0}。在unload阶段，由于扫描寄存器C6出现SA0，因此扫描寄存器C6、C5、C4的输出值为{0 1 1}，扫描寄存器Cg、Cf、Ce的输出值为{0 0 0}，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cg、Cf、Ce的值进行异或运算的结果为{0 1 1}。
表1
扫描寄存器 C6 C5 C4 Cg Cf Ce
Load阶段 0 0 0 1 1 1
capture阶段 0 1 1 0 0 0
Unload阶段 0 1 1 0 0 0
结合图10所示，若扫描链2中仅扫描寄存器C5故障，且扫描寄存器C5出现SA0。ATE设备在load阶段向扫描链1输入的逻辑测试向量为{1 0 1 1 1 1 1}，向扫描链2输入的逻辑测试向量为{1 1 1 1 1 1 1}，如下表2所示，由于扫描寄存器C5出现SA0，因此load阶段扫描寄存器C6、C5和C4的值为{1 0 0}，扫描寄存器C3、C2和C1的值为{1 1 0}。在capture阶段，扫描寄存器C6、C5、C4捕获的值为{1 1 1}，扫描寄存器Cg、Cf、Ce的捕获的值{0 1 0}。在unload阶段，由于扫描寄存器C5出现SA0，因此扫描寄存器C6、C5、C4的输出值为{0 0 1}，扫描寄存器Cg、Cf、Ce的输出值为{0 1 0}，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cg、Cf、Ce的输出值进行异或运算的结果为{0 1 1}。
表2
扫描寄存器 C6 C5 C4 Cg Cf Ce
Load阶段 1 0 0 1 1 1
capture阶段 1 1 1 0 1 0
Unload阶段 0 0 1 0 1 0
结合图10所示，若扫描链2中仅扫描寄存器C4故障，且扫描寄存器C4出现SA0。ATE设备在load阶段向扫描链1输入的逻辑测试向量为{1 0 1 1 1 1 1}，向扫描链2输入的逻辑测试向量为{1 1 1 1 1 1 1}，如下表3所示，由于扫描寄存器C4出现SA0，因此load阶段扫描寄存器C6、C5和C4的值为{1 1 0}，扫描寄存器C3、C2和C1的值为{1 1 0}。在capture阶段，扫描寄存器C6、C5、C4捕获的值为{1 1 1}，扫描寄存器Cg、Cf、Ce的捕获的值{0 1 1}。在unload阶段，由于扫描寄存器C4出现SA0，因此扫描寄存器C6、C5、C4的输出值为{0 0 0}，扫描寄存器Cg、Cf、Ce的输出值为{0 1 1}，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cg、Cf、Ce的输出值进行异或运算的结果为{0 1 1}。
表3
扫描寄存器 C6 C5 C4 Cg Cf Ce
Load阶段 1 1 0 1 1 1
capture阶段 1 1 1 0 1 1
Unload阶段 0 0 0 0 1 1
由上述内容可知，扫描链2中的扫描寄存器C6、C5、C4分别出现SA0时，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cg、Cf、Ce的输出值进行异或运算的结果均为{0 1 1}，与理想值{0 0 0}不同。结合图10可知，由于寄存器Cg、Cf、Ce捕获的值受其扇入寄存器C4、C6、C5的故障值影响，因此在将扫描寄存器C6、C5、C4的输出值与扫描寄存器Cg、Cf、Ce的输出值进行异或运算后，导致扫描寄存器C6、C5、C4分别出现SA0时，输出观测值始终为{0 1 1}，故在扫描链诊断阶段，根据输出观测值无法区分故障的扫描寄存器。即在扫描寄存器所在的压缩通道及与其对应的扇入扫描寄存器所在的压缩通道相同的情况下，可能导致同一压缩通道内的扫描链之间存在较强的耦合性，扫描链的诊断精度较低。
为了提升扫描链的检测精度，本申请实施例还提供一种扫描链设计方法，如图11所示，该方法除包括上述步骤S501-S503以外，还可以包括步骤S504。图11所示的实施中，第一扫描寄存器所在的扫描链为第一扫描链，第一扇入扫描寄存器所在的扫描链为第二扫描链，第一扫描链和第二扫描链可以为相同的扫描链，也可以为不同的扫描链。
S504、在第二扫描链所在的压缩通道与第一扫描链所在的压缩通道相同的情况下，将第二扫描链与另一压缩通道中的第三扫描链交换。
示例性的，以第一扫描链所在的压缩通道为第一压缩通道为例，步骤S504中的另一压缩通道可以为第二压缩通道，该第二压缩通道与第一压缩通道为不同的压缩通道。
示例性的，如果第一扫描链所在的压缩通道为第一压缩通道，第二扫描链所在的压缩通道也为第一压缩通道，确定第一扫描链与第二扫描链所在的压缩通道相同，可以将第二扫描链与第二压缩通道中的第三扫描链交换，从而使得第二扫描链与第一扫描链位于不同的压缩通道中。即，在第一扫描寄存器所在的压缩通道与第一扇入扫描寄存器所在的压缩通道相同的情况下，通过将第二扫描链与第三扫描链交换，可以使得第一扫描寄存器所在的压缩通道与第一扇入扫描寄存器所在的压缩通道不同，从而降低同一压缩通道中的多个扫描链之间的耦合性，提升扫描链诊断精度。
可选的，本实施例中，第一扫描寄存器所在的扫描链与第一扇入扫描寄存器所在的扫描链可以相同，也可以不同。即第一扫描链与第二扫描链可以为同一个扫描链，也可以为不同的扫描链。图10、图12和图13以第一扫描寄存器所在的扫描链与第一扇入扫描寄存器所在的扫描链为不同的扫描链为例进行示意。
例如，如图12所示，以第一压缩通道包括扫描链1和扫描链2，第二压缩通道包括扫描链3和扫描链4，第一扫描寄存器为扫描链2中的扫描寄存器C4，第一扇入扫描寄存器为扫描链1中的扫描寄存器C2和C1，第三扫描链为第二压缩通道中的扫描链3为例。结合图12可知，第一扫描寄存器C4所在的扫描链为扫描链2，扫描链2所在的压缩通道为第一压缩通道，第一扇入扫描寄存器C2和C1所在的扫描链为扫描链1，扫描链1所在的压缩通道也为第一压缩通道。即，第一扫描寄存器C4所在的压缩通道与第一扇入扫描寄存器C2和C1所在的压缩通道相同。如图13所示，可以将 第一扇入扫描寄存器C2和C1所在的扫描链1与第二压缩通道中的扫描链3交换，从而使得交换扫描链后，扫描链2所在的压缩通道与扫描链1所在的压缩通道不同。即，交换扫描链后，第一扫描寄存器C4所在的压缩通道与其对应的第一扇入扫描寄存器C2和C1所在的压缩通道不同。
以将第二扫描链与第二压缩通道中的第三扫描链交换后的扫描链结构如图13所示，扫描链2中扫描寄存器C6、C5、C4的理想值为{1 1 1}，扫描链3中扫描寄存器Cx、Cy、Cz的理想值为{1 1 1}，扫描寄存器C6、C5、C4与扫描寄存器Cx、Cy、Cz进行异或运算后的理想值为{0 0 0}，扫描链3为正常扫描链(扫描链3无故障)为例。下面分别以扫描寄存器C6、C5、C4出现SA0为例，对交换扫描链后能够提高扫描链诊断精度的原因进行说明。
如图13所示，若扫描链2中仅扫描寄存器C6故障，且扫描寄存器C6出现SA0。ATE设备在load阶段向扫描链3输入的逻辑测试向量为{1 1 1 1 1 1 1}，向扫描链2输入的逻辑测试向量为{1 1 1 1 1 1 1}，如下表4所示，由于扫描寄存器C6出现SA0，因此load阶段扫描寄存器C6、C5和C4的值均为0，扫描寄存器C3、C2和C1的值为{1 1 0}。在capture阶段，扫描寄存器C6、C5、C4捕获的值为{0 1 1}，扫描寄存器Cx、Cy和Cz捕获的值为{1 1 1}。在unload阶段，由于扫描寄存器C6出现SA0，因此扫描寄存器C6、C5、C4的输出值为{0 1 1}，扫描寄存器Cx、Cy和Cz的输出值为{1 1 1}，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cx、Cy和Cz的值进行异或运算的结果为{1 0 0}。
表4
扫描寄存器 C6 C5 C4 Cx Cy Cz
Load阶段 0 0 0 1 1 1
capture阶段 0 1 1 1 1 1
Unload阶段 0 1 1 1 1 1
如图13所示，若扫描链2中仅扫描寄存器C5故障，且扫描寄存器C5出现SA0。ATE设备在load阶段向扫描链3输入的逻辑测试向量为{1 1 1 1 1 1 1}，向扫描链2输入的逻辑测试向量为{1 1 1 1 1 1 1}，如下表5所示，由于扫描寄存器C5出现SA0，因此load阶段扫描寄存器C6、C5和C4的值为{1 0 0}，扫描寄存器C3、C2和C1的值为{1 1 0}。在capture阶段，扫描寄存器C6、C5、C4捕获的值为{1 1 1}，扫描寄存器Cx、Cy和Cz捕获的值为{1 1 1}。在unload阶段，由于扫描寄存器C5出现SA0，因此扫描寄存器C6、C5、C4的输出值为{0 0 1}，扫描寄存器Cx、Cy和Cz的输出值为{1 1 1}，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cx、Cy和Cz的值进行异或运算的结果为{1 1 0}。
表5
扫描寄存器 C6 C5 C4 Cx Cy Cz
Load阶段 1 0 0 1 1 1
capture阶段 1 1 1 1 1 1
Unload阶段 0 0 1 1 1 1
如图13所示，若扫描链2中仅扫描寄存器C4故障，且扫描寄存器C4出现SA0。ATE设备在load阶段向扫描链3输入的逻辑测试向量为{1 1 1 1 1 1 1}，向扫描链2输入的逻辑测试向量为{1 1 1 1 1 1 1}，如下表6所示，由于扫描寄存器C4出现SA0，因此load阶段扫描寄存器C6、C5和C4的值为{1 1 0}，扫描寄存器C3、C2和C1的值为{1 1 0}。在capture阶段，扫描寄存器C6、C5、C4捕获的值为{1 1 1}，扫描寄存器Cx、Cy和Cz捕获的值为{1 1 1}。在unload阶段，由于扫描寄存器C4出现SA0，因此扫描寄存器C6、C5、C4的输出值为{0 0 0}，扫描寄存器Cx、Cy和Cz的输出值为{1 1 1}，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cx、Cy和Cz的值进行异或运算的结果为{1 1 1}。
表6
扫描寄存器 C6 C5 C4 Cx Cy Cz
Load阶段 1 0 0 1 1 1
capture阶段 1 1 1 1 1 1
Unload阶段 0 0 0 1 1 1
由上述内容可知，扫描链2中的扫描寄存器C6出现SA0时，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cx、Cy和Cz的输出值进行异或运算的结果为{1 0 0}。扫描链2中的扫描寄存器C5出现SA0时，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cx、Cy和Cz的输出值进行异或运算的结果为{1 1 0}。扫描链2中的扫描寄存器C4出现SA0时，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cx、Cy和Cz的输出值进行异或运算的结果为{1 1 1}。即扫描链2中的扫描寄存器C6、C5、C4分别出现SA0时，扫描寄存器C6、C5、C4的输出值与扫描寄存器Cx、Cy和Cz的输出值进行异或运算的结果是不同的。结合图13可知，在将第一压缩通道中的扫描链1与第二压缩通道中的扫描链3交换后，扫描寄存器C6、C5、C4与扫描寄存器Cg、Cf、Ce位于不同的压缩通道，因此，第一压缩通道的输出值不再受扫描寄存器Cg、Cf、Ce的影响，能够消除扫描寄存器C6、C5、C4与扫描寄存器Cg、Cf、Ce之间较强的耦合性对第一压缩通道输出值的影响，使得第一压缩通道中前三个扫描寄存器的输出值不一定为{0 1 1}，因此通过调整逻辑测试向量的值，在诊断阶段可以较为准确的确定故障的扫描寄存器，提升扫描链诊断精度。
可以理解的，图12所示的扫描链结构中，由于扫描寄存器Cg、Cf、Ce捕获的值受扫描寄存器C4、C6、C5的故障值影响，因此在将扫描寄存器C6、C5、C4的输出值与扫描寄存器Cg、Cf、Ce的输出值进行异或运算后，导致扫描寄存器C6、C5、C4分别出现SA0时，输出观测值始终为{0 1 1}，故无法区分故障的扫描寄存器。而图13所示的扫描链结构中，由于扫描寄存器C6、C5、C4与扫描寄存器Cg、Cf、Ce位于不同的压缩通道，因此第一压缩通道的输出值不再受扫描寄存器Cg、Cf、Ce的影响，能够消除扫描寄存器C6、C5、C4与扫描寄存器Cg、Cf、Ce之间较强的耦合性对第一压缩通道输出值的影响，使得第一压缩通道中前三个扫描寄存器的输出值不一定为{0 1 1}。也就是说，本申请实施例通过将第一扫描寄存器与第一扇入扫描寄存 器设置在不同的压缩通道，从而基于交换扫描链后的压缩通道检测故障扫描单元时，能够降低同一压缩通道中的多个扫描链之间的耦合性，提升扫描链诊断精度。
需要说明的是，本申请实施例对于上述步骤S504与步骤S503的先后执行顺序并不限定，图11以步骤S504在步骤S503之后执行为例进行示意。
可选的，为了进一步提高扫描链的诊断精度，本申请实施例还提供一种扫描链设计方法，如图14所示，除上述步骤S501-S504以外，该方法还可以包括步骤S505-S506。
S505、确定第一扫描链中每个扫描寄存器的捕获概率。
每个扫描寄存器的捕获概率用于指示该扫描寄存器捕获0或1的概率。可选的，每个扫描寄存器的捕获概率可以为0到1之间的数值。扫描寄存器的捕获概率越接近0，表示该扫描寄存器捕获0的概率越大。扫描寄存器的捕获概率越接近1，表示该扫描寄存器捕获1的概率越大。
示例性的，PC1(C)表示扫描寄存器C捕获1的概率，PC0(C)表示扫描寄存器C捕获0的概率，PC0(C)＝1-PC1(C)。
例如，以初始扫描链结构包括图15所示的扫描链为例，如图15所示，该扫描链包括串行级联的扫描寄存器C1至C5，扫描寄存器C1至C5中任意相邻两个扫描寄存器中，前一扫描寄存器的输出端Q连接至后一个扫描寄存器的SI端。如果任意一个扇入扫描寄存器(比如，Ca)捕获1的概率为0.5，那么扫描寄存器C1捕获1的概率为其扇入扫描寄存器Ca至Ce均捕获1的概率的乘积，故PC1(C1)＝PC1(Ca)*PC1(Cb)*PC1(Cc)*PC1(Cd)*PC1(Ce)＝0.5^5＝0.03125。扫描寄存器C2捕获1的概率为其扇入的4个扫描寄存器均捕获0的概率的乘积，故PC1(C2)＝PC0(Cl)*PC0(Cm)*PC0(Cn)*PC0(Co)＝0.5^4＝0.0625。依次类推，可以确定PC1(C3)＝0.5，PC1(C4)＝0.95，PC1(C5)＝0.55。
S506、在第一扫描链中相邻两个扫描寄存器的捕获概率均大于预设阈值，或者，在第一扫描链中相邻两个扫描寄存器的捕获概率均小于或等于预设阈值的情况下，调整第一扫描链中多个扫描寄存器之间的连接关系，使得相邻两个扫描寄存器中一个扫描寄存器的捕获概率大于预设阈值，另一个扫描寄存器的捕获概率小于或等于预设阈值。
示例性的，以预设阈值为0.5为例，当扫描寄存器的捕获概率大于0.5时，该扫描寄存器捕获1的概率较大。当扫描寄存器的捕获概率小于或等于0.5时，该扫描寄存器捕获0的概率较大。
可选的，在第一扫描链中相邻两个扫描寄存器的捕获概率均大于预设阈值时，说明这两个相邻的扫描寄存器捕获1的概率较大。在第一扫描链中相邻两个扫描寄存器的捕获概率均小于或等于预设阈值时，说明这两个相邻的扫描寄存器捕获0的概率较大。
由于一条扫描链中相邻两个或相邻多个扫描寄存器捕获相同数值的概率越高，根据该扫描链的观测输出值越不容易定位出故障的扫描寄存器。例如，如图15所示，扫描寄存器C1、C2和C3的捕获概率均小于或等于0.5，故扫描寄存器C1、C2和C3捕获相同数值0的可能性较大，那么将很难区分扫描寄存器C1、C2、C3出现SA0的情况，在扫描链诊断阶段，不能准确的定位出具体是哪个扫描寄存器故障。即，如果相 邻多个扫描寄存器捕获相同数值0的概率较高，很难区分到底是哪个扫描寄存器出现SA0。再例如，扫描寄存器C4和C5的捕获概率均大于0.5，故扫描寄存器C4和C5捕获1的可能性较大，那么将很难区分扫描寄存器C4、C5出现SA1的情况，在扫描链诊断阶段，不能准确的定位出具体是哪个扫描寄存器故障。即，如果相邻多个扫描寄存器捕获相同数值1的概率较高，很难区分到底是哪个扫描寄存器出现SA1。
为了提高数据敏感性，提升扫描链检测精度，可以通过调整扫描链中多个扫描寄存器的连接关系，使得扫描链中任意相邻两个扫描寄存器中，一个扫描寄存器捕获0的概率较大，一个扫描寄存器捕获1的概率较大，从而使得相邻两个扫描寄存器更容易捕获不同的数值。也就是说，交换连接关系后的扫描链中，任意相邻两个扫描寄存器捕获不同数值的可能性较大。
例如，以交换连接关系后的扫描链结构如图16所示为例，交换连接关系后的扫描链中扫描寄存器C1、C4、C2、C5、C3串行级联，而且任意相邻两个扫描寄存器中，一个扫描寄存器捕获0的概率较大，另一个扫描寄存器捕获1的概率较大，即任意相邻两个扫描寄存器捕获不同数值的可能性较大，从而在任意一个扫描寄存器出现SA0或SA1时，能更容易确定出故障的扫描寄存器，提升扫描链的诊断精度。
可以理解的，本申请实施例提供的扫描链设计方法，通过确定第一扫描链中每个扫描寄存器的捕获概率，并在第一扫描链中相邻两个扫描寄存器捕获相同数值的可能性较大时，通过调整第一扫描链中多个扫描寄存器之间的连接关系，使得相邻两个扫描寄存器捕获不同数值的可能性较大，从而基于调整连接关系后的扫描链检测故障扫描寄存器时，能够更容易确定出故障的扫描寄存器，提升扫描链的诊断精度。
本申请实施例还提供一种芯片，该芯片包括第一扫描链和第二扫描链，第一扫描链和第二扫描链为不同的扫描链，第二扫描链中的第二扫描寄存器扇入第一扫描链中的第一扫描寄存器。
可选的，第一扫描链和第二扫描链为不同压缩通道中的扫描链。
可选的，第一扫描链中相邻两个扫描寄存器中，一个扫描寄存器的捕获概率大于预设阈值，另一个扫描寄存器的捕获概率小于或等于预设阈值。即，第一扫描链中相邻两个扫描寄存器捕获不同数值的可能性较大。
本申请实施例还提供一种芯片，该芯片包括第一扫描链，第一扫描链中的第二扫描寄存器扇入第一扫描链中的第一扫描寄存器，所述第二扫描寄存器较所述第一扫描寄存器更靠近所述第一扫描链的移位输入端。
可选的，第一扫描链中相邻两个扫描寄存器中，一个扫描寄存器的捕获概率大于预设阈值，另一个扫描寄存器的捕获概率小于或等于预设阈值。即，第一扫描链中相邻两个扫描寄存器捕获不同数值的可能性较大。
上述主要从方法步骤的角度对本申请实施例提供的方案进行了介绍。可以理解的是，电子设备为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请能够以硬件和计算机软件的结合形式来实现。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对电子设备进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
图17示出了一种扫描链设计装置1700的结构示意图，该扫描链设计装置可以为上述实施例中的电子设备，还可以为电子设备内的芯片，扫描链设计装置1700可以用于实现上述任一实施例的扫描链设计方法。
该扫描链设计装置1700包括：处理单元1701和收发单元1702。示例性的，收发单元1702用于支持扫描链设计装置1700收发信息，或者用于与其它设备之间通信。处理单元1701用于对上述扫描链设计装置1700的动作进行控制管理，用于执行上述实施例中由扫描链设计装置1700进行的处理，可选的，若扫描链设计装置1700包括存储单元，则处理单元1701还可以执行存储在存储器中的程序或指令，以使得扫描链设计装置1700实现上述任一实施例所涉及的方法和功能。
示例性的，上述处理单元1701可以用于执行例如图5中的步骤S502-S503，或，图11中的步骤S502-S504，或，图14中的步骤S502-S506，和/或用于本文所描述的技术的其它过程。收发单元1702可以用于执行例如图5中的步骤S501，和/或用于本文所描述的技术的其它过程。其中，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
示例性的，在硬件实现上，可以由处理器401执行处理单元1701的功能，可以由收发器403(发送器/接收器)和/或通信接口执行收发单元1702的功能，其中，处理单元1701可以以硬件形式内嵌于或独立于扫描链设计装置1700的处理器中，也可以以软件形式存储于扫描链设计装置1700的存储器中，以便于处理器调用执行以上各个功能单元对应的操作。
当上述处理单元1701为处理器，收发单元1702为收发器时，图17所示的扫描链设计装置的具体结构可以为上述图4所示的电子设备，其中，上述图4涉及的各部件的所有相关内容的描述均可以援引到图17对应部件的功能描述，在此不再赘述。
本申请实施例还提供一种电子设备，该电子设备包括处理器，还可以包括收发器以及存储器，收发器，用于收发信息，或者用于与其他网元通信；存储器，用于存储计算机执行指令；处理器，用于执行所计算机执行指令，以支持检测装置实现图5、图11或图14任一所示的扫描链设计方法。
本申请实施例还提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机程序代码，当上述处理器执行该计算机程序代码时，电子设备执行图5、图11或图14任一所示的扫描链设计方法。
本申请实施例还提供了一种计算机程序产品，当该计算机程序产品在计算机上运行时，使得计算机执行图5、图11或图14任一所示的扫描链设计方法。
本申请实施例还提供了一种扫描链设计装置，该装置可以以芯片的产品形态存在，该装置的结构中包括处理器和接口电路，该处理器用于通过接口电路与其它装置通信，使得该装置执行上述图5、图11或图14任一所示的扫描链设计方法。
结合本申请公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(Random Access Memory，RAM)、闪存、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、电可擦可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于核心网接口设备中。当然，处理器和存储介质也可以作为分立组件存在于核心网接口设备中。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本发明所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本发明的保护范围之内。

Claims (13)

  1. 一种扫描链设计方法，其特征在于，所述方法包括：
    获取初始扫描链结构，所述初始扫描链结构用于指示多个扫描链与组合逻辑之间的连接关系，每个扫描链包括多个扫描寄存器；
    基于所述初始扫描链结构，确定第一扫描链中第一扫描寄存器对应的第一扇入扫描寄存器所在的扫描链；所述第一扫描链为所述多个扫描链中的任一个扫描链，所述第一扇入扫描寄存器为扇入所述第一扫描寄存器的扫描寄存器；
    在所述第一扇入扫描寄存器所在的扫描链为所述第一扫描链的情况下，将所述第一扇入扫描寄存器与第二扫描链中的第二扫描寄存器交换；所述多个扫描链包括所述第二扫描链。
  2. 根据权利要求1所述的方法，其特征在于，所述第二扫描链与所述第一扫描链为不同的扫描链。
  3. 根据权利要求1所述的方法，其特征在于，所述第二扫描链与所述第一扫描链为同一个扫描链；其中，在将所述第一扇入扫描寄存器与所述第二扫描链中的第二扫描寄存器交换之前，所述第一扫描寄存器较所述第一扇入扫描寄存器更靠近所述第一扫描链的移位输入端，所述第二扫描寄存器为所述第一扫描链中较所述第一扫描寄存器更靠近所述移位输入端的扫描寄存器。
  4. 根据权利要求2或3所述的方法，其特征在于，所述初始扫描链结构包括多个压缩通道，每个压缩通道包括至少两个扫描链，每个压缩通道中的所述至少两个扫描链的移位输出端之间做逻辑运算，所述方法还包括：
    在所述第二扫描链所在的压缩通道与所述第一扫描链所在的压缩通道相同的情况下，将所述第二扫描链与另一压缩通道中的第三扫描链交换。
  5. 根据权利要求1-4中任一项所述的方法，其特征在于，所述方法还包括：
    确定所述第一扫描链中每个扫描寄存器的捕获概率；所述每个扫描寄存器的捕获概率用于指示该扫描寄存器捕获0或1的概率；
    在所述第一扫描链中相邻两个扫描寄存器的捕获概率均大于预设阈值，或者，在第一扫描链中相邻两个扫描寄存器的捕获概率均小于或等于预设阈值的情况下，调整所述第一扫描链中多个扫描寄存器之间的连接关系，使得相邻两个扫描寄存器中一个扫描寄存器的捕获概率大于预设阈值，另一个扫描寄存器的捕获概率小于或等于所述预设阈值。
  6. 一种芯片，其特征在于，所述芯片包括第一扫描链和第二扫描链，所述第一扫描链和所述第二扫描链为不同的扫描链，所述第一扫描链中的第一扫描寄存器扇入所述第二扫描链中的第二扫描寄存器。
  7. 根据权利要求6所述的芯片，其特征在于，所述第一扫描链和所述第二扫描链为不同压缩通道中的扫描链；其中，所述压缩通道包括至少两个扫描链，所述压缩通道中的所述至少两个扫描链的移位输出端之间进行逻辑运算。
  8. 根据权利要求6或7所述的芯片，其特征在于，所述第一扫描链中相邻两个扫描寄存器中，一个扫描寄存器的捕获概率大于预设阈值，另一个扫描寄存器的捕获概率小于或等于所述预设阈值。
  9. 一种芯片，其特征在于，所述芯片包括第一扫描链，所述第一扫描链中的第一扫描寄存器扇入所述第一扫描链中的第二扫描寄存器，所述第一扫描寄存器较所述第二扫描寄存器更靠近所述第一扫描链的移位输入端。
  10. 根据权利要求9所述的芯片，其特征在于，所述第一扫描链中相邻两个扫描寄存器中，一个扫描寄存器的捕获概率大于预设阈值，另一个扫描寄存器的捕获概率小于或等于所述预设阈值。
  11. 一种扫描链设计装置，其特征在于，所述扫描链设计装置包括处理器和存储器，所述存储器用于存储计算机程序；所述处理器用于执行所述计算机程序，使得所述电子设备实现如权利要求1-5中任一项所述的方法。
  12. 一种电子设备，其特征在于，所述电子设备包括处理器和接口电路，所述处理器用于通过所述接口电路与其它装置通信，以实现如权利要求1-5中任一项所述的方法。
  13. 一种计算机可读存储介质，所述计算机可读存储介质中具有计算机程序代码，其特征在于，当所述计算机程序代码在处理器上运行时，使得所述处理器执行如权利要求1-5中任一项所述的方法。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060048028A1 (en) * 2004-09-02 2006-03-02 International Business Machines Corporation Method and apparatus for selective scan chain diagnostics
CN103376405A (zh) * 2012-04-27 2013-10-30 国际商业机器公司 用于扫描链诊断的方法和装置
CN107492395A (zh) * 2016-06-12 2017-12-19 晨星半导体股份有限公司 条件式存取芯片、其内建自我测试电路及测试方法
CN108845248A (zh) * 2018-05-02 2018-11-20 清华大学 一种基于向量压缩的低功耗测试压缩方法和系统、clfsr
CN112684327A (zh) * 2020-11-30 2021-04-20 海光信息技术股份有限公司 扫描链及其设计方法和基于扫描链的串行扫描复位方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060048028A1 (en) * 2004-09-02 2006-03-02 International Business Machines Corporation Method and apparatus for selective scan chain diagnostics
CN103376405A (zh) * 2012-04-27 2013-10-30 国际商业机器公司 用于扫描链诊断的方法和装置
CN107492395A (zh) * 2016-06-12 2017-12-19 晨星半导体股份有限公司 条件式存取芯片、其内建自我测试电路及测试方法
CN108845248A (zh) * 2018-05-02 2018-11-20 清华大学 一种基于向量压缩的低功耗测试压缩方法和系统、clfsr
CN112684327A (zh) * 2020-11-30 2021-04-20 海光信息技术股份有限公司 扫描链及其设计方法和基于扫描链的串行扫描复位方法

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