WO2021007737A1 - 一种检测电路及传感器 - Google Patents

一种检测电路及传感器 Download PDF

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Publication number
WO2021007737A1
WO2021007737A1 PCT/CN2019/095949 CN2019095949W WO2021007737A1 WO 2021007737 A1 WO2021007737 A1 WO 2021007737A1 CN 2019095949 W CN2019095949 W CN 2019095949W WO 2021007737 A1 WO2021007737 A1 WO 2021007737A1
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Prior art keywords
self
input terminal
pmos
nmos
ring
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PCT/CN2019/095949
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English (en)
French (fr)
Inventor
曾秋玲
刘燕翔
陈赞锋
夏禹
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华为技术有限公司
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Priority to CN201980098408.8A priority Critical patent/CN114127915A/zh
Priority to PCT/CN2019/095949 priority patent/WO2021007737A1/zh
Publication of WO2021007737A1 publication Critical patent/WO2021007737A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8236—Combination of enhancement and depletion transistors

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  • the invention relates to the field of electricity, in particular to a detection circuit and a sensor.
  • the frequency of the CMOS inverter self-oscillation ring can be determined by the two different directions of R0 and R45.
  • the ratio obtains the influence of the stress at the place where the CMOS inverter is placed on the frequency, and then reflects the influence of the stress at the place where the CMOS inverter is placed on the electrical characteristics of the device.
  • CMOS inverters include NMOS and PMOS transistors.
  • the effect of stress on the electrical characteristics of NMOS and PMOS may be different. This solution cannot distinguish the effect of stress on the electrical characteristics of NMOS and PMOS. The impact of characteristics.
  • the embodiments of the present application provide a detection circuit and a sensor.
  • the detection circuit is used to detect the influence of stress on the current of the NMOS tube and the PMOS tube in the circuit.
  • the detection circuit includes:
  • the PMOS tube leads the self-oscillation ring
  • the NMOS tube leads the self-oscillation ring and the frequency reading module
  • the number of PMOS tubes in the signal path of the PMOS tube leads the self-oscillation ring is greater than the number of NMOS tubes
  • the NMOS tube leads the signal of the self-oscillation ring
  • the number of NMOS tubes in the path is greater than the number of PMOS tubes
  • the frequency reading module is used to read the frequency signal output by the PMOS tube leading self-oscillating ring or the NMOS tube leading self-oscillating ring.
  • the detection circuit provided by this embodiment includes a PMOS tube-dominant self-oscillation ring and an NMOS tube-dominant self-oscillation ring.
  • the frequency signal output by the NMOS tube-dominant self-oscillation ring represents the influence of stress on the electrical characteristics of the NMOS tube.
  • the frequency signal output by the PMOS tube leading the self-oscillating ring represents the influence of stress on the electrical characteristics of the PMOS tube.
  • the manufacturing process of the circuit can be improved according to the influence of stress on the NMOS tube and the influence of the PMOS tube to reduce the influence of stress on the electrical characteristics of the circuit.
  • the PMOS tube leading self-oscillating ring includes an even number of NOR gates connected in series, and the even number of NOR gates The number of PMOS tubes connected in series in the signal path in each NOR gate in the gate is greater than the number of NMOS tubes;
  • the NMOS tube leading self-oscillating ring includes an even number of NAND gates connected in series, and the even number of NAND gates The number of NMOS tubes connected in series on the signal path in each NAND gate is greater than the number of PMOS tubes.
  • the PMOS tube leading self-oscillating ring includes a first NAND gate, and the first The output of a NAND gate is coupled to the input terminals of the even number of NOR gates connected in series.
  • the first NAND gate includes a first input terminal and a second input terminal, and the first input terminal is connected to a control signal , The second input terminal is connected to the output terminals of the even number of NOR gates connected in series.
  • each of the even-numbered NOR gates includes P inputs Terminal, the P is an integer greater than or equal to 2; the third input terminal of the P input terminals is connected to the output terminal of the first NAND gate, and the P input terminals except for the third The input terminals other than the input terminal are connected to a low level, and the third input terminal is any one of the P input terminals.
  • the NMOS tube leading self-oscillating ring includes a second NAND gate, The output of the second NAND gate is coupled to the input terminals of the even number of NAND gates connected in series.
  • the second NAND gate includes a fourth input terminal and a fifth input terminal. The control signal is connected, and the fifth input terminal is connected to the output terminals of the even number of NAND gates connected in series.
  • each of the even-numbered NAND gates includes L input terminals, where L is an integer greater than or equal to 2; the sixth input terminal of the L input terminals is connected to the output of the second NAND gate, and the L input terminals except for the The input terminals other than the sixth input terminal are connected to a high level, and the sixth input terminal is any one of the L input terminals.
  • the circuit further includes an inverting The inverter is used for coupling the control signal to the first input terminal of the first NAND gate after inverting the control signal.
  • the circuit further includes a multiplexer MUX, and the MUX It is used to select to provide the output of the PMOS dominant self-oscillation ring or the NMOS dominant self-oscillation ring to the frequency reading module.
  • MUX multiplexer
  • the frequency reading module includes a frequency divider, a register, and a system clock.
  • the frequency divider is connected to the output terminals of the PMOS tube leading self-oscillating ring and the NMOS tube leading self-oscillating ring, and the frequency divider is also connected to the register and the system clock respectively.
  • a second aspect of the embodiments of the present application provides a sensor, which includes the first aspect and the detection circuit in any possible implementation of the first aspect.
  • a third aspect of the embodiments of the present application provides a chip, the chip including the first aspect and the detection circuit in any possible implementation manner of the first aspect.
  • the detection circuit includes: a PMOS tube leading self-oscillating ring, an NMOS tube leading self-oscillating ring, and a frequency reading module; the PMOS tube
  • the number of PMOS tubes in the signal path leading the self-oscillating ring is greater than the number of NMOS tubes; the number of NMOS tubes in the signal path leading the self-oscillating ring is greater than the number of PMOS tubes; the frequency reading module is used to read the
  • the PMOS tube leads the self-oscillation ring or the NMOS tube leads the frequency signal output by the self-oscillation ring.
  • the detection circuit provided by this embodiment includes a PMOS tube dominated self-oscillation ring and an NMOS tube dominated self-oscillation ring.
  • the frequency signal output from the NMOS tube dominates the self-oscillation ring represents the influence of stress on the electrical characteristics of the NMOS tube
  • the PMOS tube dominates the self-oscillation ring.
  • the output frequency signal represents the influence of stress on the electrical characteristics of the PMOS tube.
  • the manufacturing process of the circuit can be improved according to the influence of stress on the NMOS tube and the influence of the PMOS tube to reduce the influence of stress on the electrical characteristics of the circuit.
  • FIG. 1 is a schematic diagram of a circuit for detecting the influence of stress on electrical characteristics according to an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a NOR gate 1012 provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a NAND gate 1022 provided by an embodiment of the application.
  • the embodiments of the present application provide a detection circuit and a sensor.
  • the detection circuit generates a high-frequency signal through a PMOS tube-driven self-oscillating ring and an NMOS-driven self-oscillating ring. After the high-frequency signal is reduced in frequency by a frequency divider, the system clock is reduced The signal after the frequency is counted, and the counted frequency value is stored in the register.
  • the detection circuit can compare the frequency value changes before and after the circuit is packaged to detect the influence of the packaging process on the stress of the circuit to be tested.
  • the detection circuit can be placed in the integrated circuit to be detected.
  • the detection circuit is used to detect the stress on the PMOS tube in the integrated circuit. influences.
  • the detection circuit is used to detect the influence of the stress on the NMOS tube in the integrated circuit.
  • FIG. 1 is a schematic diagram of a detection circuit provided by an embodiment of the application.
  • the detection circuit includes: a PMOS dominant self-oscillation ring 101, an NMOS dominant self-oscillation ring 102, and a frequency reading module 103.
  • the PMOS dominant self-oscillating ring 101 refers to a self-oscillating ring in which the number of PMOS on the signal path is greater than the number of NMOS
  • the NMOS dominant self-oscillating ring 102 refers to a self-oscillating ring in which the number of NMOS on the signal path is greater than the number of PMOS.
  • Self-oscillating ring refers to a self-oscillating ring in which the number of NMOS on the signal path is greater than the number of PMOS.
  • the PMOS dominant self-oscillating ring 101 includes an even number of NOR gates 1012 and a first NAND gate 1011 connected in series, wherein each of the even number of NOR gates 1012 includes P input terminals , P is an integer greater than or equal to 2.
  • P is an integer greater than or equal to 2.
  • One of the P input terminals is connected to the output terminal of the first NAND gate 1011.
  • the first NAND gate 1011 includes a first input terminal and a second input terminal. The input terminal is connected with the control signal, and an inverter can be arranged between the first input terminal and the control signal.
  • the second input terminal of the first NAND gate 1011 is connected to the output terminal Z1 of an even number of NOR gates connected in series.
  • NOR gates 1012 In the PMOS dominant self-oscillating ring 101 shown in FIG. 1, only two 4-input NOR gates 1012 are illustrated. , The 4 input terminals of the NOR gate 1012 are A1, A2, A3, and A4, respectively. It should be pointed out that in practical applications, the number of NOR gates 1012 connected in series is an even number, for example, it may also be 4 NOR gates 1012 or 8 NOR gates 1012, etc., which is not specifically limited here. At the same time, the even number of NOR gates 1012 are connected in series. In the figure, only the A1 input terminal of each NOR gate 1012 is connected to the output terminal of the previous NOR gate 1012 as an example. In actual production, it can also be each The other input terminals of the NOR gate 1012 are connected to the output terminal of the previous NOR gate 1012.
  • the number of PMOSs connected in series in the signal path in each of the even number of NOR gates 1012 is greater than the number of NMOSs.
  • FIG. 2 which is provided in this embodiment A schematic diagram of one of the NOR gates 1012 of an even number of NOR gates 1012, as shown in FIG. 2, the NOR gate 1012 provided in this embodiment is composed of an NMOS tube and a PMOS tube. It is understood that in the digital cell library, There are many types of NOR gates, including different numbers of input pins and different numbers of N/P MOS. In this embodiment, only the 4-input NOR gate 1012 shown in FIG. 2 is used for illustration.
  • the NOR gate 1012 can also be an even number of inputs such as 2 inputs or 8 inputs. It should be noted that, in this embodiment, the input terminals of each NOR gate of the even number of NOR gates except for one input for connecting adjacent NOR gates are connected to low level.
  • the three input pins A2, A3, and A4 of the NOR gate 1012 shown in FIG. 2 are connected to low level 0, and the three PMOS transistors whose gates are connected to A2, A3, and A4 are in an open state. , And the three NMOSs whose gates are connected to A2, A3, and A4 are off.
  • the PMOS tube dominates the change in the electrical characteristics of the PMOS transistor reflected by the frequency signal output from the oscillation ring 101.
  • the method provided in this embodiment is used for detecting
  • the circuit for the influence of stress on electrical characteristics can determine the influence of stress on the PMOS transistor according to the frequency signal output by the PMOS tube leading the self-oscillating ring 101, so that the manufacturing process of the integrated circuit can be improved according to the influence of the stress on the PMOS transistor, and the integrated circuit can be upgraded.
  • the precision of the manufacturing process to reduce the impact of stress on the electrical characteristics of the integrated circuit s PMOS transistors.
  • the NMOS dominant self-oscillating ring 102 includes an even number of NAND gates 1022 and a second NAND gate 1021 connected in series, wherein each of the even number of NAND gates 1022 includes L input terminals. , L is an integer greater than or equal to 2, one of the L input terminals is connected to the output terminal of the second NAND gate 1021, and the second NAND gate 1021 includes a fourth input terminal and a fifth input terminal. The fourth input terminal is connected to the control signal, and the fifth input terminal is connected to the output terminal Z2 of an even number of NAND gates in series.
  • the NMOS dominant self-oscillating ring 102 shown in FIG. 1 only two 4-input NAND gates are illustrated.
  • Gate 1022 as shown in FIG. 1, the 4 inputs of NAND gate 1022 are A1, A2, A3, and A4, respectively. It should be pointed out that the number of NAND gates 1022 connected in series in practical applications is an even number, for example, it can also be 4 NAND gates 1022 or 8 NAND gates 1022, etc., which is not specifically limited here. At the same time, the even number of NAND gates 1022 are connected in series. In the figure, only the A1 input terminal of each NAND gate 1022 is connected to the output terminal of the previous NAND gate 1022 as an example. In actual production, it can also be each The other input terminals of the NOR gate 1012 are connected to the output terminal of the previous NOR gate 1012.
  • the inverter 104 the PMOS transistor dominates the first NAND gate 1011 in the oscillating ring 101, and the NMOS transistor dominates the second NAND gate 1021 in the oscillating ring 102 to control the entire detection circuit.
  • the control signal is at a high level
  • the inverter 104 sets the first input of the first NAND gate 1011 to a low level
  • the fourth input of the second NAND gate 1021 is at a high level.
  • the detection circuit only the NMOS tube leads the oscillation ring 102 to work, and the PMOS tube leads the oscillation ring 101 to not work. At this time, the detection circuit can detect the influence of stress on the NMOS tube.
  • the inverter 104 sets the first input of the first NAND gate 1011 to high level, and the fourth input of the second NAND gate 1021 is low.
  • the detection circuit only the PMOS tube leads the oscillating ring 101 to work, while the NMOS tube leads the oscillating ring 102 to not work. At this time, the detection circuit can detect the effect of stress on the PMOS tube.
  • FIG. 3 shows the AND of one of the even number of NAND gates 1022 provided in this embodiment.
  • the schematic diagram of the NOR gate 1022, as shown in FIG. 3, the NAND gate 1022 provided by this embodiment is composed of NMOS and PMOS transistors. It can be understood that there are many kinds of NOR gates in the digital cell library, including different The number of input pins and the number of different N/P MOSs. In this embodiment, only the 4-input NAND gate 1022 shown in FIG. 3 is used as an example.
  • the NAND gate 1022 can also It is 2 inputs or 8 inputs, etc. It should be noted that, in this embodiment, the input terminals of each NAND gate of the even number of NAND gates, except for one input for connecting adjacent NAND gates, are connected to a high level.
  • three of the input pins A2, A3, and A4 of the NAND gate 1022 shown in FIG. 3 are connected to high level 1, and the three PMOS transistors whose gates are connected to A2, A3, and A4 are in the off state. And the three NMOSs whose gates are connected to A2, A3, and A4 are in an open state.
  • the NMOS when the stress causes a change in the electrical characteristics of the NMOS, the NMOS dominates the change in the electrical characteristics of the NMOS tube reflected by the frequency signal output from the oscillation ring 102.
  • the method provided in this embodiment is used to detect stress effects.
  • the circuit affected by electrical characteristics can determine the impact of stress on the NMOS tube based on the frequency signal output from the self-oscillating ring 102 with the NMOS tube, so that the manufacturing process of the integrated circuit can be improved according to the influence of the stress on the PMOS tube, and the manufacturing of the integrated circuit can be improved Process accuracy to reduce the influence of stress on the electrical characteristics of the NMOS tube of the integrated circuit.
  • the PMOS leading self-oscillating ring 101 and the NMOS leading self-oscillating ring 102 provided in this embodiment are described in detail above, and the frequency reading module 103 provided in this embodiment is described below.
  • the frequency reading module 103 includes a frequency divider 1032, a register 1031, and a system clock 1033.
  • the frequency divider 1032 is connected to the PMOS dominant self-oscillation ring 101 and the NMOS dominant self-oscillation ring respectively through the multiplexer MUX105.
  • the output terminal of 102 is connected, and the frequency divider 1032 is also connected to the register 1031 and the system clock 1033 respectively.
  • the frequency divider 1032 is used to reduce the output frequency of the PMOS dominant self-oscillating ring 101 and the NMOS dominant self-oscillating ring 102
  • the frequency divider 1032 outputs a reduced frequency signal
  • the frequency signal is converted into a digital signal
  • the digital signal is stored in the register 1031 array, and can be read in real time by using the system clock 1033.
  • the MUX 105 provided in this embodiment is used to select the output of the PMOS dominant self-oscillating ring 101 and the NMOS dominant self-oscillating ring 102 to be provided to the frequency reading module. For example, when the control signal is high level 1, while the high level 1 is input to the NMOS dominant self-oscillating ring 102, the high level 1 is input to MUX105, and MUX105 can select the NMOS to dominate the output of the self-oscillating ring 102. Provided to the frequency reading module.
  • the circuit for detecting the influence of stress on electrical characteristics may also include an inverter 104.
  • the control signal is low level 0, the low level 0 passes through the inverter 104, and the inverter 104 outputs high Level 1, the high level 1 output by the inverter 104 is input to the PMOS dominant self-oscillating ring 101, and the low level 0 is input to MUX105, MUX105 thus selects the output of the PMOS dominant self-oscillating ring 101 to be provided to the frequency reading module .
  • the circuit for detecting the influence of stress on electrical characteristics can be placed in different positions of the semiconductor chip to determine the stress based on the frequency signal read by the frequency reading module 103 when the circuit is in different positions of the semiconductor chip.
  • Distribution of semiconductor chips For example, the circuit is placed in the center or around the semiconductor chip, and the stress distribution in the semiconductor chip is determined according to the frequency signal read by the frequency reading module 103 at the center of the semiconductor chip and the frequency signal read around.
  • the influence of the packaging process on the electrical characteristics can also be determined through a circuit probe (CP) test and a functional test (FT) test.
  • CP circuit probe
  • FT functional test
  • the frequency signal read by the frequency reading module 103 is obtained through the CP test
  • the frequency signal read by the frequency reading module 103 is obtained through the FT test
  • the frequency signal read by the frequency reading module 103 and the FT test are obtained by comparing the CP test.
  • the frequency signal read by the frequency reading module 103 is obtained to obtain the influence of the packaging process on the electrical characteristics of the device.
  • the CP test is completed before the semiconductor packaging
  • the FT test is completed after the semiconductor packaging.
  • the frequency reading module 103 of different packaging forms it is also possible to compare the frequency signals read by the frequency reading module 103 of different packaging forms to obtain the influence of the stress of different packaging forms on the electrical characteristics of the device, or to place the circuit directly below the Bump and near the Bump.
  • the frequency signal read by the frequency reading module 103 at the position is compared to obtain the influence of the package Bump stress on the electrical characteristics of the device, or the frequency signal read by the frequency reading module 103 before and after the drop can also be used in scenarios such as chip drop Analysis of the difference between the stress on the electrical characteristics.
  • the circuit for detecting the influence of stress on electrical characteristics can also be used in 3D integrated circuits (IC), for example, used to include through silicon vias (TSV) or insulating dielectric vias In 3D IC (through Dielectric Via, TDV), to detect the influence of the stress in TSV or TDV on the electrical characteristics of surrounding devices.
  • IC 3D integrated circuits
  • TSV through silicon vias
  • TDV through Dielectric Via
  • An embodiment of the present application also provides a sensor, which includes the circuit for detecting the influence of stress on electrical characteristics as shown in FIG. 1, wherein the function of the circuit for detecting the influence of stress on electrical characteristics is included in the sensor.
  • the structure is similar to that described in Figure 1, Figure 2 and Figure 3 above. For details, please refer to Figure 1, Figure 2 and Figure 3, which will not be repeated here.
  • An embodiment of the present application also provides a chip, which includes the circuit for detecting the influence of stress on electrical characteristics as shown in FIG. 1, wherein the function of the circuit for detecting the influence of stress on electrical characteristics is included in the chip.
  • the structure is similar to that described in Figure 1, Figure 2 and Figure 3 above. For details, please refer to Figure 1, Figure 2 and Figure 3, which will not be repeated here.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

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Abstract

一种检测电路，用于检测应力对电特性的影响，该检测电路包括：PMOS管主导自振荡环(101)、NMOS管主导自振荡环(102)和频率读取模块(103)；PMOS管主导自振荡环(101)的信号路径中的PMOS管数量大于NMOS管数量；NMOS管主导自振荡环(102)的信号路径中的NMOS管数量大于PMOS管数量；频率读取模块(103)用于读取PMOS管主导自振荡环(101)或NMOS管主导自振荡环(102)输出的频率信号。该NMOS管主导自振荡环(102)输出的频率信号表征应力对NMOS管的电特性影响，PMOS管主导自振荡环(101)输出的频率信号表征应力对PMOS管的电特性影响。可以根据应力对NMOS管的影响以及PMOS管的影响改善电路的制造工艺，以减少应力对电路的电特性的影响。

Description

一种检测电路及传感器 技术领域
本发明涉及电学领域，尤其涉及一种检测电路及传感器。
背景技术
应力在集成电路的制造及封装过程中不可避免的产生，尤其是半导体器件受到应力的影响，会对半导体器件的载流子迁移率有显著影响，进而会影响模拟和数字电路的行为，甚至导致电路失效。
在基于45°有源区方向的互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)反相器自振荡环中，可以通过R0和R45两个不同方向的CMOS反相器自振荡环的频率的比值，得到放置CMOS反相器处的应力对频率的影响，进而反应放置CMOS反相器处的应力对器件电特性的影响。
上述实施方式反应的是应力对放置CMOS反相器的电特性的影响。CMOS反相器包括NMOS管和PMOS管，应力对于NMOS管电特性的影响和PMOS管的电特性的影响可能是不同的，该方案无法区分应力对于NMOS管电特性的影响和PMOS管PMOS管电特性的影响。
发明内容
本申请实施例提供一种检测电路及传感器，该检测电路用于检测应力对电路中的NMOS管和PMOS管的电流的影响，该检测电路包括：
PMOS管主导自振荡环、NMOS管主导自振荡环和频率读取模块；所述PMOS管主导自振荡环的信号路径中的PMOS管数量大于NMOS管数量；所述NMOS管主导自振荡环的信号路径中的NMOS管数量大于PMOS管数量；所述频率读取模块用于读取所述PMOS管主导自振荡环或所述NMOS管主导自振荡环输出的频率信号。由第一方面可见，本实施例提供的检测电路包括PMOS管主导自振荡环和NMOS管主导自振荡环，其中，NMOS管主导自振荡环输出的频率信号表征应力对NMOS管的电特性影响，PMOS管主导自振荡环输出的频率信号表征应力对PMOS管的电特性影响。可以根据应力对NMOS管的影响以及PMOS管的影响改善电路的制造工艺，以减少应力对电路的电特性的影响。
基于本申请实施例的第一方面，在本申请实施例的第一方面的第一种实现方式中，所述PMOS管主导自振荡环包括串联的偶数个或非门，所述偶数个或非门中的每个或非门中串联在信号路径上的PMOS管的数量大于NMOS管的数量；所述NMOS管主导自振荡环包括串联的偶数个与非门，所述偶数个与非门中的每个与非门中串联在信号路径上的NMOS管的数量大于PMOS管的数量。
基于本申请实施例第一方面的第一种实现方式，在本申请实施例的第一方面的第二种实现方式中，所述PMOS管主导自振荡环包括第一与非门，所述第一与非门的输出被耦合至所述串联的偶数个或非门的输入端，所述第一与非门包括第一输入端和第二输入端，所述第一输入端与控制信号相连，所述第二输入端连接所述串联的偶数个或非门的输出端。
基于本申请实施例第一方面的第二种实现方式，在本申请实施例的第一方面的第三种实现方式中，所述偶数个或非门中的每个或非门包括P个输入端，所述P为大于或等于2 的整数；所述P个输入端中的第三输入端与所述第一与非门的输出端相连，所述P个输入端中除了所述第三输入端之外的其他输入端连接低电平，所述第三输入端为所述P个输入端中的任意一个输入端。
基于本申请实施例的第一方面的第一种可能的实现方式，在本申请实施例的第一方面的第四种实现方式中，所述NMOS管主导自振荡环包括第二与非门，所述第二与非门的输出被耦合至所述串联的偶数个与非门的输入端，所述第二与非门包括第四输入端和第五输入端，所述第四输入端与控制信号相连，所述第五输入端连接所述串联的偶数个与非门的输出端。
基于本申请实施例的第一方面的第四种可能的实现方式，在本申请实施例的第一方面的第五种实现方式中，所述偶数个与非门中的每个与非门包括L个输入端，所述L为大于或等于2的整数；所述L个输入端中的第六输入端与所述第二与非门的输出相连，所述L个输入端中除了所述第六输入端之外的其他输入端连接高电平，所述第六输入端为所述L个输入端中的任意一个输入端。
基于本申请实施例的第一方面第二种可能的实现方式至第一方面的第五种可能的实现方式，在第一方面的第六种可能的实现方式中，所述电路还包括反相器，所述反相器用于将所述控制信号反向之后耦合至所述第一与非门的所述第一输入端。
基于本申请实施例的第一方面至第一方面的第五种可能的实现方式，在第一方面的第七种可能的实现方式中，所述电路还包括多路选择器MUX，所述MUX用于选择将所述PMOS主导自振荡环或所述NMOS主导自振荡环的输出提供给所述频率读取模块。
基于本申请实施例第一方面的第七种可能的实现方式，在第一方面的第八种可能的实现方式中，所述频率读取模块包括分频器、寄存器和系统时钟，所述分频器与所述PMOS管主导自振荡环和所述NMOS管主导自振荡环的输出端连接，所述分频器还分别与所述寄存器和所述系统时钟连接。
本申请实施例第二方面提供一种传感器，所述传感器包括第一方面以及第一方面任一可能的实现方式中的检测电路。
本申请实施例第三方面提供一种芯片，所述芯片包括第一方面以及第一方面任一可能的实现方式中的检测电路。
本实施例提供了一种检测电路，该检测电路用于检测应力对电特性影响，该检测电路包括：PMOS管主导自振荡环、NMOS管主导自振荡环和频率读取模块；所述PMOS管主导自振荡环的信号路径中的PMOS管数量大于NMOS管数量；所述NMOS管主导自振荡环的信号路径中的NMOS管数量大于PMOS管数量；所述频率读取模块用于读取所述PMOS管主导自振荡环或所述NMOS管主导自振荡环输出的频率信号。本实施例提供的检测电路包括PMOS管主导自振荡环和NMOS管主导自振荡环，其中，NMOS管主导自振荡环输出的频率信号表征应力对NMOS管的电特性影响，PMOS管主导自振荡环输出的频率信号表征应力对PMOS管的电特性影响。可以根据应力对NMOS管的影响以及PMOS管的影响改善电路的制造工艺，以减少应力对电路的电特性的影响。
附图说明
图1为本申请实施例提供的一种用于检测应力对电特性影响的电路的示意图；
图2为本申请实施例提供的一个或非门1012的结构示意图；
图3为本申请实施例提供的一个与非门1022的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例提供一种检测电路及传感器，该检测电路通过PMOS管主导自振荡环和NMOS主导自振荡环产生高频信号，该高频信号经过分频器降低频率之后，该系统时钟对降低频率之后的信号进行计数，并将该计数得到的频率数值保存在寄存器中。该检测电路可以对比被检测的电路封装前后频率数值的变化从而检测封装工艺对于被检测电路应力的影响。
本申请实施例，可以将检测电路放置于被检测的集成电路中，当该检测电路中的PMOS管主导自振荡环处于工作状态时，该检测电路用于检测应力对集成电路中的PMOS管的影响。当该检测电路中的NMOS管主导自振荡环处于工作状态时，该检测电路用于检测应力对集成电路中的NMOS管的影响。
请参考图1，图1为本申请实施例提供的一种检测电路的示意图，如图1所示，该检测电路包括：PMOS主导自振荡环101、NMOS主导自振荡环102和频率读取模块103，在本实施例中，PMOS主导自振荡环101是指在信号路径上的PMOS数量大于NMOS数量的自振荡环,NMOS主导自振荡环102是指在信号路径上的NMOS数量大于PMOS数量的自振荡环。
下面对本申请实施例提供的PMOS主导自振荡环101和NMOS主导自振荡环102进行详细描述。
如图1所示，PMOS主导自振荡环101包括串联的偶数个或非门1012和第一与非门1011，其中，该偶数个或非门中的每个或非门1012包括P个输入端，P为大于等于2的整数，该P个输入端中的一个输入端与第一与非门1011的输出端相连，第一与非门1011包括第一输入端和第二输入端，第一输入端与控制信号的相连，在该第一输入端与该控制信号之间可以设置一个反相器。该第一与非门1011的第二输入端连接串联的偶数个或非门的输出端Z1，在图1所示的PMOS主导自振荡环101中仅示例了2个4输入端的或非门1012，或非门1012的4输入端分别为A1、A2、A3和A4。需指出，在实际应用中串联的或非门1012的数量为偶数，比如，还可以是4个或非门1012或8个或非门1012等，此处不做具体限定。同时，该偶数个或非门1012相串联，图中仅以每个或非门1012的A1输入端与上一个 或非门1012的输出端相连为例，在实际生产中，也可以是每个或非门1012的其他输入端与上一个或非门1012的输出端相连。
在本实施例中，偶数个或非门1012中的每一个或非门中串联在信号路径上的PMOS数量大于NMOS数量，具体地，请参考图2所示，图2为本实施例提供的偶数个或非门1012的其中一个或非门1012的示意图，如图2所示，本实施例提供的或非门1012由NMOS管和PMOS管组成，可以理解的是，在数字单元库中，或非门有多种，包括不同的输入引脚数量以及不同的N/P MOS的数量，其中，本实施例中，仅以图2所示4输入或非门1012进行举例说明，当然，在实际应用中，或非门1012还可以是2输入或者8输入等偶数个输入。需要说明的是，本实施例中，偶数个或非门中的每一个或非门的输入端中除了用于连接相邻的或非门的一个输入之外的其他输入接入低电平。
具体地，如图2所示的或非门1012的其中三个输入引脚A2,A3，A4接入低电平0，栅极与A2,A3，A4分别相连的3个PMOS管处于打开状态，而栅极与A2,A3，A4分别相连的3个NMOS处于关闭状态。
当A1输入低电平0时，图2所示的或非门1012中所有的PMOS管都是处于打开状态的，所有NMOS管都是处于关闭状态的。当A1输入高电平1时，栅极与A1相连的PMOS管处于关闭状态，栅极与A1相连的NMOS管处于打开状态。此时，图2所示的或非门1012中有3个PMOS管处于打开状态，1个NMOS管处于打开状态。所以，在这两种情况下，该或非门1012中处于打开状态的PMOS管的数量都多余NMOS管的数量。
因此，在本实施例中，当应力引起PMOS管电特性产生变化时，PMOS管主导自振荡环101的输出的频率信号反映的PMOS晶体管的电特性变化，显然，本实施例提供的用于检测应力对电特性影响的电路可以根据与PMOS管主导自振荡环101输出的频率信号，来确定应力对PMOS管的影响，从而可以根据应力对PMOS晶体管的影响改善集成电路的制造工艺，提升集成电路的制造工艺精确度，以减少应力对集成电路的PMOS晶体管的电特性的影响。
如图1所示，NMOS主导自振荡环102包括串联的偶数个与非门1022和第二与非门1021其中，该偶数个与非门1022中的每个与非门1022包括L个输入端，L为大于等于2的整数，该L个输入端中的一个输入端与第二与非门1021的输出端相连，第二与非门1021包括第四输入端和第五输入端。第四输入端与控制信号相连，第五输入端连接串联的偶数个与非门的输出端Z2，在图1所示的NMOS主导自振荡环102中仅示例了2个4输入段的与非门1022，如图1所示，与非门1022的4输入分别为A1、A2、A3和A4。需指出，在实际应用中串联的与非门1022的数量为偶数，比如，还可以是4个与非门1022或8个与非门1022等，此处不做具体限定。同时，该偶数个与非门1022相串联，图中仅以每个与非门1022的A1输入端与上一个与非门1022的输出端相连为例，在实际生产中，也可以是每个或非门1012的其他输入端与上一个或非门1012的输出端相连。
需要说明的是，该反相器104、PMOS管主导振荡环101中的第一与非门1011、NMOS管主导振荡环102中的第二与非门1021三者对于整个检测电路具有控制作用。当控制信号为高电平时，该反相器104将第一与非门1011的第一输入置为低电平，该第二与非门1021的第四输入为高电平。此种情况下，该检测电路中只有该NMOS管主导振荡环102工作，而 该PMOS管主导振荡环101不工作。此时，该检测电路可以检测应力对NMOS管的影响。
同理，当控制信号为低电平时，该反相器104将第一与非门1011的第一输入置为高电平，该第二与非门1021的第四输入为低电平。此种情况下，该检测电路中只有该PMOS管主导振荡环101工作，而该NMOS管主导振荡环102不工作。此时，该检测电路可以检测应力对于PMOS管的影响。
在本实施例中，偶数个与非门1022中的每一个与非门中串联在信号路径上的NMOS数量大于PMOS数量，图3为本实施例提供的偶数个与非门1022的其中一个与非门1022的示意图，如图3所示，本实施例提供的与非门1022由NMOS管和PMOS管组成，可以理解的是，在数字单元库中，或非门有多种，包括不同的输入引脚数量以及不同的N/P MOS的数量，其中，本实施例中，仅以图3所示4输入与非门1022进行举例说明，当然，在实际应用中，与非门1022还可以是2输入或者8输入等。需要说明的是，本实施例中，偶数个与非门中的每一个与非门的输入端中除了用于连接相邻的与非门的一个输入之外的其他输入接入高电平。
具体地，图3所示的与非门1022的其中三个输入引脚A2,A3，A4接入高电平1，栅极与A2,A3，A4分别相连的3个PMOS晶体管处于关闭状态，而栅极与A2,A3，A4分别相连的3个NMOS处于打开状态。
当A1输入低电平0时，图3所示的与非门1022中所有的NMOS管都是处于打开状态的，所有PMOS管都是处于关闭状态的。当A1输入高电平1时，栅极与A1相连的NMOS管处于关闭状态，栅极与A1相连的PMOS管处于打开状态。此时，图2所示的与非门1022中有3个NMOS管处于打开状态，1个PMOS管处于打开状态。所以，在这两种情况下，该或非门1012中处于打开状态的NMOS管的数量都多余PMOS管的数量。
因此，在本实施例中，当应力引起NMOS电特性产生变化时，NMOS主导自振荡环102的输出的频率信号反映的NMOS管的电特性变化，显然，本实施例提供的用于检测应力对电特性影响的电路可以根据与NMOS管主导自振荡环102输出的频率信号，来确定应力对NMOS管的影响，从而可以根据应力对PMOS管的影响改善集成电路的制造工艺，提升集成电路的制造工艺精确度，以减少应力对集成电路的NMOS管的电特性的影响。
上面对本实施例提供的PMOS主导自振荡环101和NMOS主导自振荡环102进行了详细描述，下面对本实施例提供的频率读取模块103进行描述。
如图1所示，频率读取模块103包括分频器1032、寄存器1031和系统时钟1033，其中，分频器1032通过多路选择器MUX105分别与PMOS主导自振荡环101和NMOS主导自振荡环102的输出端连接，分频器1032还分别与寄存器1031和系统时钟1033连接，在本实施例中，分频器1032用于降低PMOS主导自振荡环101和NMOS主导自振荡环102的输出频率信号的频率，分频器1032输出降低频率的频率信号，频率信号转换成数字信号，将数字信号存放在寄存器1031阵列中，并可采用系统时钟1033实时读取。
需要说明的是，本实施例提供的MUX105是用于选择将PMOS主导自振荡环101和NMOS主导自振荡环102的输出提供给所述频率读取模块。比如，当控制信号为高电平1时，该高电平1输入至NMOS主导自振荡环102的同时，将高电平1输入至MUX105，MUX105从而 可以选择将NMOS主导自振荡环102的输出提供给所述频率读取模块。
本实施例提供的用于检测应力对电特性影响的电路还可以包括反相器104，当控制信号为低电平0时，该低电平0经过反相器104，反相器104输出高电平1，反相器104输出的高电平1输入至PMOS主导自振荡环101，将低电平0输入至MUX105，MUX105从而选择将PMOS主导自振荡环101的输出提供给频率读取模块。
在实际应用中，可以将该用于检测应力对电特性影响的电路放置在半导体芯片的不同位置，以根据该电路在半导体芯片不同位置时，频率读取模块103读取的频率信号来确定应力在半导体芯片的分布。比如，将该电路放置在半导体芯片的中心或者四周，根据频率读取模块103在半导体芯片的中心位置读取的频率信号以及四周读取的频率信号来确定应力在半导体芯片的分布。
当然，本实施例还可以通过晶圆(circuit probing，CP)测试和功能(functional test，FT)测试来确定封装工艺对电特性的影响。比如，通过CP测试得到频率读取模块103读取的频率信号，以及FT测试得到频率读取模块103读取的频率信号，通过比较CP测试得到频率读取模块103读取的频率信号和FT测试得到频率读取模块103读取的频率信号来获得封装工艺对器件电特性的影响。需要说明的是，CP测试在半导体的封装前完成，FT测试在半导体的封装后完成。
本实施例中还可以通过不同的封装形式频率读取模块103读取的频率信号的比较，获得不同封装形式应力对器件电特性的影响，或者将该电路分别放置在Bump正下方处以及Bump附近位置处的频率读取模块103读取的频率信号的比较，获得封装Bump应力对器件电特性的影响，或者在芯片跌落等场景下，也可通过跌落前后频率读取模块103读取的频率信号的差异分析对应力对电特性的影响。
本实施案例提供的用于检测应力对电特性影响的电路还可以应用在3D集成电路(integrated circuit,IC)中，比如，应用于包含硅通孔(through silicon via，TSV)或者绝缘介质通孔(through Dielectric Via，TDV)的3D IC中，以检测TSV或者TDV中的应力对其周围器件电特性的影响。
上面对本申请实施例提供的用于检测应力对电特性影响的电路进行了描述，下面对本申请实施例提供的传感器进行描述。
本申请实施例还提供一种传感器，所述传感器包括图1所示的用于检测应力对电特性影响的电路，其中，该传感器所包括的用于检测应力对电特性影响的电路的功能与结构与前述的图1、图2和图3所述的类似，具体请参考图1、图2和图3，此处不再赘述。
本申请实施例还提供一种芯片，所述芯片包括图1所示的用于检测应力对电特性影响的电路，其中，该芯片所包括的用于检测应力对电特性影响的电路的功能与结构与前述的图1、图2和图3所述的类似，具体请参考图1、图2和图3，此处不再赘述。
在本申请所提供的实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示 或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (10)

  1. 一种检测电路，其特征在于，包括：
    PMOS管主导自振荡环、NMOS管主导自振荡环和频率读取模块；
    所述PMOS管主导自振荡环的信号路径中的PMOS管数量大于NMOS管数量；
    所述NMOS管主导自振荡环的信号路径中的NMOS管数量大于PMOS管数量；
    所述频率读取模块用于读取所述PMOS管主导自振荡环或所述NMOS管主导自振荡环输出的频率信号。
  2. 根据权利要求1所述的电路，其特征在于，所述PMOS管主导自振荡环包括串联的偶数个或非门，所述偶数个或非门中的每个或非门中串联在信号路径上的PMOS管的数量大于NMOS管的数量；所述NMOS管主导自振荡环包括串联的偶数个与非门，所述偶数个与非门中的每个与非门中串联在信号路径上的NMOS管的数量大于PMOS管的数量。
  3. 根据权利要求2所述的电路，其特征在于，所述PMOS管主导自振荡环包括第一与非门，所述第一与非门的输出被耦合至所述串联的偶数个或非门的输入端，所述第一与非门包括第一输入端和第二输入端，所述第一输入端与控制信号相连，所述第二输入端连接所述串联的偶数个或非门的输出端。
  4. 根据权利要求3所述的电路，其特征在于，所述偶数个或非门中的每个或非门包括P个输入端，所述P为大于或等于2的整数；
    所述P个输入端中的第三输入端与所述第一与非门的输出端相连，所述P个输入端中除了所述第三输入端之外的其他输入端连接低电平，所述第三输入端为所述P个输入端中的任意一个输入端。
  5. 根据权利要求2所述的电路，其特征在于，所述NMOS管主导自振荡环包括第二与非门，所述第二与非门的输出被耦合至所述串联的偶数个与非门的输入端，所述第二与非门包括第四输入端和第五输入端，所述第四输入端与控制信号相连，所述第五输入端连接所述串联的偶数个与非门的输出端。
  6. 根据权利要求5所述的电路，其特征在于，所述偶数个与非门中的每个与非门包括L个输入端，所述L为大于或等于2的整数；
    所述L个输入端中的第六输入端与所述第二与非门的输出相连，所述L个输入端中除了所述第六输入端之外的其他输入端连接高电平，所述第六输入端为所述L个输入端中的任意一个输入端。
  7. 根据权利要求3至6任一项所述的电路，其特征在于，所述电路还包括反相器，所述反相器用于将所述控制信号反向之后耦合至所述第一与非门的所述第一输入端。
  8. 根据权利要求1至6项任一项所述的电路，其特征在于，所述电路还包括多路选择器MUX，所述MUX用于选择将所述PMOS主导自振荡环或所述NMOS主导自振荡环的输出提供给所述频率读取模块。
  9. 根据权利要求8所述的电路，其特征在于，所述频率读取模块包括分频器、寄存器和系统时钟，所述分频器与所述PMOS管主导自振荡环和所述NMOS管主导自振荡环的输出端连接，所述分频器还分别与所述寄存器和所述系统时钟连接。
  10. 一种传感器，其特征在于，所述传感器包括如权利要求1至9项任一项所述的检测电路。
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