WO2024067035A1 - 故障定位电路、方法、芯片及计算机可读存储介质 - Google Patents

故障定位电路、方法、芯片及计算机可读存储介质 Download PDF

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WO2024067035A1
WO2024067035A1 PCT/CN2023/117939 CN2023117939W WO2024067035A1 WO 2024067035 A1 WO2024067035 A1 WO 2024067035A1 CN 2023117939 W CN2023117939 W CN 2023117939W WO 2024067035 A1 WO2024067035 A1 WO 2024067035A1
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Prior art keywords
chain
scan
unit
xor
data
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PCT/CN2023/117939
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English (en)
French (fr)
Inventor
欧阳可青
彭敏强
周国华
汪帅
王凯
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深圳市中兴微电子技术有限公司
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Publication of WO2024067035A1 publication Critical patent/WO2024067035A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of integrated circuit testing technology, and in particular, to a fault location circuit, method, chip, and computer-readable storage medium.
  • the Scan-cell and its clock path occupy about 30% of the entire chip area.
  • the scan chain like other logic, will inevitably have some faults. According to statistics, 10%-30% of Scan-cell failures may cause the failure of the entire scan chain, and 50% of chip failures are caused by the scan chain. Therefore, it can be seen that the fault diagnosis of the scan chain and the high-precision positioning of the Scan-cell are of great significance.
  • the main purpose of the present disclosure is to provide a fault location circuit, method, chip and computer-readable storage medium, aiming to efficiently and accurately locate the faulty Scan-cell and avoid technical defects such as circuit layout and wiring congestion, high computational complexity and sample imbalance.
  • the present disclosure provides a fault location circuit, including: a scan array and a dedicated debug chain.
  • the scan array includes a plurality of scan units and XOR units, each of the scan units is sequentially connected end to end along a first direction to form a multi-column scan chain, each of the scan units adjacent to each other in a second direction is a scan unit of the same level, each of the XOR units is arranged between each of the scan units of the same level, each of the XOR units adjacent to each other in the second direction is a XOR unit of the same level, each of the XOR units of the same level along the second direction is sequentially connected to form an XOR chain, wherein the first direction and the second direction are different directions;
  • the dedicated debug chain is composed of a plurality of scan units sequentially connected end to end along the first direction, each of the scan units in the dedicated debug chain is respectively connected to the output end of each of the XOR chains; the output result of the scan array is used
  • the present disclosure also provides a fault location method, which is applied to the above-mentioned fault location circuit, including: inputting a test vector into a scan array; obtaining an output result of the scan array, and comparing the output result of the scan array with the test vector to determine the column coordinates of the fault scanning unit; inputting specified data into the scan array; obtaining an output result of a dedicated debug chain, and comparing the output result of the dedicated debug chain with the specified data to determine the row coordinates of the fault scanning unit; and determining the position of the fault scanning unit in the scan array according to the column coordinates and the row coordinates.
  • the present disclosure also provides a chip, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the computer program is executed by the processor, the fault location method as described above is implemented.
  • the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the fault location method as described above is implemented.
  • FIG1 is a schematic diagram of the structure of a fault location circuit according to an embodiment of the present disclosure
  • FIG2 is a schematic diagram of the structure of a scanning unit involved in a fault location circuit according to an embodiment of the present disclosure
  • FIG3 is a schematic diagram of an application scenario of a fault location circuit according to an embodiment of the present disclosure.
  • FIG4 is a schematic diagram of another application scenario of a fault location circuit according to an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a flow chart of a fault location method according to an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a hardware structure of a chip according to an embodiment of the present disclosure.
  • references to “one embodiment” or “some embodiments” etc. described in the specification of the disclosed embodiments mean that one or more embodiments of the disclosed embodiments include specific features, structures or characteristics described in conjunction with the embodiment.
  • the statements “in one embodiment”, “in some embodiments”, “in some other embodiments”, “in some other embodiments”, etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean “one or more but not all embodiments", unless otherwise specifically emphasized in other ways.
  • the terms “including”, “comprising”, “having” and their variations all mean “including but not limited to”, unless otherwise specifically emphasized in other ways.
  • the scan chain is a structure that replaces the function register with the Scan-cell in the logic circuit and connects them in series.
  • the scan chain can effectively transfer the test data to the inside of the logic circuit, and at the same time transfer the output value of the unit under test to the output to realize the test function.
  • the scan chain Under the control of the MUX (multiplexer, data selector) selection signal of the Scan-cell, the scan chain usually has two working modes: functional mode and test mode.
  • the Scan-cell essentially performs the function of the register, mainly stores the data of the combinational logic, and works according to the original structure.
  • the test mode the test data is shifted from the scan chain to the input in sequence, and after the logic data is captured, it is shifted from the scan chain to the output for comparison.
  • the Scan-cell and its clock path occupy about 30% of the entire chip area.
  • the scan chain like other logic, will inevitably have some faults. According to statistics, 10%-30% of Scan-cell failures may cause the failure of the entire scan chain, and 50% of chip failures are caused by the scan chain. Therefore, it can be seen that the fault diagnosis of the scan chain and the high-precision positioning of the Scan-cell are of great significance.
  • a scan chain can be composed of dozens, hundreds or even more scan cells.
  • the test vector is shifted into the scan chain from one end and then shifted out from the other end.
  • it is easy to detect the faulty scan chain.
  • due to the large number of scan cells in the chain it is challenging to locate the faulty scan cell.
  • the faulty Scan-cell results can only be shifted and output from the scan chain in sequence, and the Scan-cell results at a specific position in the chain cannot be directly observed;
  • second, in a scan chain with a diagnosed fault when the test vector is shifted to a faulty Scan-cell, for example, it is a Stuck-at 1 fault, all subsequent data will be contaminated, and no matter what the subsequent vector value is, the output value after passing through this faulty Scan-cell will all be 1;
  • third, during data capture if the input of a Scan-cell is the output of another faulty Scan-cell, that is, the Scan-cell captures an erroneous value, but in the subsequent shifting process, after passing through another faulty Scan-cell in the scan chain, it will be impossible to determine in the final shifted output vector whether the data is caused by the capture of erroneous data or by the subsequent faulty Scan-cell contamination.
  • the first solution is to use a two-dimensional scan chain.
  • the specific behavior of this solution is to connect the output of any independent Scan-cell to the next Scan-cell in the horizontal and vertical directions, and finally form a two-dimensional scan chain.
  • dimensional scan chain After the scan chain is formed, the test vectors are shifted from the horizontal, vertical or diagonal paths to the inside of the circuit in sequence. Depending on whether the output of different scan paths matches the input value, the fault point can be accurately located.
  • this solution needs to increase the input port of the Scan-cell to effectively locate it.
  • the second solution is to optimize the scan chain fault diagnosis algorithm or introduce machine learning, such as ANN (Artificial Neural Network), DNN (Deep Neural Network), etc., without changing the Scan-cell design and scan chain structure, to accurately locate the faulty Scan-cell in the scan chain, but when the number of Scan-cells is huge, the computational complexity is high and there will be a sample imbalance problem.
  • ANN Artificial Neural Network
  • DNN Deep Neural Network
  • the fault location circuit includes: a scan array, the scan array includes a plurality of scan units and XOR units, each scan unit is sequentially connected end to end along a first direction to form a multi-column scan chain, each scan unit adjacent in a second direction is a same-level scan unit, each XOR unit is arranged between each same-level scan unit, each XOR unit adjacent in the second direction is a same-level XOR unit, each XOR unit of the same level along the second direction is sequentially connected to form an XOR chain, wherein the first direction and the second direction are different directions; a dedicated debugging chain, the dedicated debugging chain is composed of a plurality of scan units sequentially connected end to end along the first direction, each scan unit in the dedicated debugging chain is respectively connected to the output end of each XOR chain; the output result of the scan array is used to determine the column coordinates where the faulty scan
  • the fault location circuit with a dedicated debug chain provided in the embodiment of the present disclosure can identify the scan chain with a fault by using a conventional scan chain diagnosis method, so as to obtain the column coordinates of the faulty Scan-cell; then, a specific test vector is shifted to input, and the output values of the adjacent Scan-cells of the same level in the horizontal direction are XOR-operated in sequence, and then the output values are shifted to the corresponding Scan-cell on the dedicated debug chain, so as to obtain the row coordinates of the faulty Scan-cell, which can effectively solve the problem of pollution of subsequent data caused by the shifted data encountering the faulty Scan-cell, and finally realize high-precision positioning of the faulty Scan-cell. For the Scan-cell with multiple faults at the same time, accurate positioning can be achieved by setting it.
  • the dedicated debug chain in the fault location circuit of the embodiment of the present disclosure can reuse the ordinary vertical scan chain, except for the XOR processing of the output result of the Scan-cell, and no other hardware overhead is introduced, so there will be no congestion problem in the subsequent layout and wiring; compared with the optimized scan chain fault diagnosis algorithm or the diagnosis and location method introducing machine learning in the prior art, the fault location circuit including the dedicated debug chain provided by the embodiment of the present disclosure does not require complex logical calculations, and the fault Scan-cell is located efficiently and accurately, and there is no problem of imbalance in the number of fault Scan-cells; the embodiment of the present disclosure provides The fault location circuit can realize high-precision diagnosis of faulty Scan-cells at any location and in any number, and has strong universality.
  • the fault location circuit, method, device, and computer-readable storage medium provided by the embodiments of the present disclosure are specifically described through the following embodiments. First, the fault location circuit in the embodiments of the present disclosure is described.
  • Figure 1 is a schematic diagram of the structure of a fault location circuit provided in an embodiment of the present disclosure.
  • the fault location circuit according to this embodiment includes a scan array 10 and a dedicated debug chain 20.
  • the scanning array 10 includes a plurality of scanning units 101 and XOR units 102, wherein the scanning units 101 are sequentially connected end to end along a first direction to form a plurality of scanning chains 103, wherein the scanning units 101 adjacent to each other in a second direction are scanning units of the same level, and the XOR units 102 are arranged between the scanning units of the same level, and the XOR units 102 adjacent to each other in the second direction are XOR units of the same level, and the XOR units of the same level along the second direction are sequentially connected to form an XOR chain 104, wherein the first direction and the second direction are not in the same direction;
  • the dedicated debug chain 20 is composed of a plurality of scanning units 101 connected end to end in sequence along a first direction, and each scanning unit 101 in the dedicated debug chain 20 is connected to an output end of each XOR chain 104 respectively;
  • the output result of the scan array 10 is used to determine the column coordinates where the fault scan unit 101 is located, and the output result of the dedicated debug chain 20 is used to determine the row coordinates where the fault scan unit 101 is located.
  • the scanning units 101 constituting the dedicated debug chain 20 are all known fault-free scanning units, and their number is consistent with the number of scanning units 101 constituting a scan chain 103. Therefore, each scanning unit 101 in the dedicated debug chain 20 adjacent in the second direction (i.e., Cell in FIG. 1 ) and each scanning unit 101 in the scan array 10 can also be regarded as a scanning unit of the same level, the difference being that no XOR unit 102 is required between each scanning unit of the dedicated debug chain 20 and the scan array 10 of the same level.
  • FIG. 1 the structural diagram of the fault location circuit shown in FIG.
  • the first direction is regarded as a vertical direction
  • the second direction is regarded as a horizontal direction
  • the first direction and the second direction are orthogonal to each other, and this embodiment is only an example, as long as the first direction is not parallel to the second direction, they all belong to the protection scope summarized by the different directions mentioned in this embodiment).
  • the scanning units 101 adjacent in the vertical direction are connected end to end in sequence to form a plurality of scan chains 103, and the input signal of each scan chain 103 is Scan in, and the output signal is Scan out.
  • An XOR unit 102 i.e., XOR in FIG1 ) is provided between each adjacent scanning unit 101 in the horizontal direction.
  • the XOR units 102 are not connected in the vertical direction, but the XOR units 102 adjacent in the horizontal direction are sequentially connected to form a plurality of XOR chains 104.
  • the output end of each XOR chain 104 is respectively connected to the scanning unit of the same level in the dedicated debugging chain 20.
  • the test vector shifted to each vertical scan chain 103 is a 001100110011 sequence, which can detect all four different signal transitions of any Scan-cell, namely 0-0, 0-1, 1-0, and 1-1. Since the test vector is shifted from the input end to the output end of the scan chain 103, each Scan-cell in the scan chain will be diagnosed. If the vector sequence obtained from the shifted output end of the vertical scan chain is also 001100110011, that is, it is consistent with the input diagnostic vector, it means that the scan chain is normal.
  • the fault location circuit can identify the faulty scan chain using a conventional scan chain diagnosis method, that is, by comparing the input vector and the output vector of each scan chain in the scan array, it can be known which scan chain has a fault, and then the column coordinates of the faulty scan unit are obtained; then a specific test vector is shifted and input, and the output values of each adjacent same-level scan unit in the horizontal direction are sequentially XORed based on the XOR chain, and then the output values are shifted to the corresponding same-level scan unit on the dedicated debug chain, and then according to the output value of the dedicated debug chain, it can be known which row of scan units in the horizontal direction has a fault, and then the row coordinates of the faulty unit are obtained. After obtaining the column coordinates and row coordinates of the faulty scan unit, the position of the faulty scan unit in the scan array can be accurately determined.
  • FIG. 2 is a schematic diagram of the structure of a scanning unit involved in a fault location circuit provided in an embodiment of the present disclosure.
  • the scanning unit 101 includes:
  • a first data input terminal Data_in1 the first data input terminal Data_in1 is used to receive a test vector
  • a second data input terminal Data_in2 the second data input terminal Data_in2 is used to receive set data;
  • Data selection terminal Data_sel the data selection terminal Data_sel is used to select receiving test vectors or setting data
  • Data output terminal Data_out the data output terminal Data_out is used to output the detection result.
  • the upper port of the scanning unit 101 in Figure 2 namely the first data input terminal Data_in1
  • the right port namely the second data input terminal Data_in2
  • the set data can be 0 or 1.
  • the left port namely the data selection terminal Data_sel
  • the lower port namely the data output terminal Data_out, can be used to output the detection result.
  • the head-to-tail connection of each adjacent scanning unit 101 in the vertical direction is that the data output terminal Data_out of the previous scanning unit is connected to the first data input terminal Data_in1 of the next scanning unit.
  • the first data input terminal Data_in1 of the scanning unit 101 at the top of the scan chain 103 is used to receive the test vector input by the input scan line Scan in.
  • the data output terminal Data_out of the scanning unit 101 at the bottom of the scan chain 103 is used to output the detection result of the current scan chain 103 to the output scan line Scan out;
  • the second data input terminal Data_in2 of each scanning unit 101 on the rightmost side of the scan array 10 can be used to receive the set data, and the second data input terminal Data_in2 of each other scanning unit 101 is connected to the XOR unit 102;
  • the data selection terminal Data_sel of each scanning unit 101 in the scan array 10 is connected to the output terminal of an AND gate, and the two input terminals of the AND gate are respectively connected to the Data_sel signal and the Config_in signal.
  • the scanning unit 101 selects to receive the setting data through the second data input terminal Data_in2. In other cases, the scanning unit 101 receives the test data through the first data input terminal Data_in1 by default.
  • each scan unit 101 in the scan array 10 will only receive a test vector from one input terminal, and the data selection terminal Data_sel of each scan unit 101 in the dedicated debug chain 20 is unconnected.
  • Each scan unit 101 in the dedicated debug chain 20 can receive test vectors from two input terminals at the same time (the first data input terminal Data_in1 of the top scan unit in the dedicated debug chain 20 is unconnected). This is because each scan unit 101 in the dedicated debug chain 20 is a non-fault scan unit, and after receiving the test vector, they will only shift the connected test vector to the next scan unit with the clock signal, and will not affect the value and order of the test vector.
  • the XOR unit 102 includes: a first logic input terminal, a second logic input terminal, a first logic output terminal, and a second logic output terminal.
  • the scan chain 103 includes a boundary chain and an intermediate chain
  • the XOR unit 102 includes a head XOR unit disposed between the boundary chain and the middle chain, a middle XOR unit disposed between two middle chains, and a tail XOR unit closest to the dedicated debugging chain 20;
  • the head XOR unit, the middle XOR unit and the tail XOR unit are sequentially connected to form an XOR chain 104 .
  • each XOR unit 102 is referred to as the first logic input terminal
  • the left port is referred to as the second logic input terminal
  • the upper port is referred to as the first logic output terminal
  • the lower port is referred to as the second logic output terminal.
  • This embodiment is also based on the different connection relationships of the ports of each scanning unit 101 in the scan chain 103, and the rightmost scan chain 103 in the scan array 10 of FIG. 1 is referred to as a boundary chain, and the remaining scan chains 103 in the scan array 10 are referred to as intermediate chains. As shown in FIG.
  • the difference between the boundary chain and the intermediate chain mainly lies in the connection method of the second data input terminal Data_in2 of each scanning unit 103.
  • the second data input terminal Data_in2 of each scanning unit 103 of the boundary chain can be used to receive the set data from the data line, while the second data input terminal Data_in2 of each scanning unit 101 of the middle chain is connected to the first logic output terminal of the XOR unit 102.
  • the head XOR unit is a column of XOR units adjacent to the boundary chain, which is also the rightmost column of XOR units in Figure 1
  • the tail XOR unit is a column of XOR units closest to the dedicated debug chain 20, which is also the leftmost column of XOR units in Figure 1.
  • the middle XOR unit is an XOR unit located between the head XOR unit and the tail XOR unit.
  • the second logic output terminal of the head XOR unit is connected to the first logic input terminal of the middle XOR unit, and the second logic output terminal of the middle XOR unit is connected to the first logic input terminal of the tail XOR unit, that is, an XOR chain 104 is formed.
  • the output end of the XOR chain 104 i.e., the second logic output end of the tail XOR unit, is connected to the same-level scanning unit in the dedicated debug chain 20, and the output values of the same-level scanning units 101 in the horizontally adjacent scanning array 10 are subjected to multiple XOR processing and transmitted to the dedicated debug chain 20, and then the position of the faulty scanning unit can be deduced through the output of the dedicated debug chain 20.
  • the first logic input terminal of the head XOR unit is connected to the data output terminal of the same-level scanning unit in the boundary chain
  • the second logic input terminal of the head XOR unit is connected to the data output terminal of the same-level scanning unit in the middle chain
  • the first logic output terminal of the head XOR unit is connected to the second data input terminal of the same-level scanning unit in the middle chain
  • the second logic output terminal of the head XOR unit is connected to the first logic input terminal of the same-level XOR unit in the middle XOR unit.
  • the first logic input terminal of the intermediate XOR unit is connected to the second logic output terminal of the same-level XOR unit on the side of the intermediate chain close to the boundary chain
  • the second logic input terminal of the intermediate XOR unit is connected to the data output terminal of the same-level scanning unit in the intermediate chain away from the boundary chain
  • the first logic output terminal of the intermediate XOR unit is connected to the second data input terminal of the same-level scanning unit in the intermediate chain away from the boundary chain
  • the second logic output terminal of the intermediate XOR unit is connected to the first logic input terminal of the same-level XOR unit on the side of the intermediate chain away from the boundary chain.
  • the first logic input terminal of the tail XOR unit is connected to the second logic output terminal of the same-level XOR unit on the side of the middle chain close to the boundary chain
  • the second logic input terminal of the tail XOR unit is connected to the data output terminal of the same-level scan unit in the middle chain away from the boundary chain
  • the first logic output terminal of the tail XOR unit is connected to the second data input terminal of the same-level scan unit in the middle chain away from the boundary chain
  • the second logic output terminal of the tail XOR unit is connected to the second data input terminal of the scan unit 101 in the dedicated debug chain 20.
  • the fault location circuit provided in this embodiment is universal for high-precision location diagnosis of fault scanning units, the following detailed explanation is given for two different fault scenarios occurring in the vertical scan chain in this embodiment.
  • the analysis principles for other fault scenarios are the same. There are two major categories, namely, Stuck-at type faults and delayed type faults.
  • the stuck-at faults include SA1 (Stuck-At-1, fixed 1) faults and SA0 (Stuck-At-0, fixed 0) faults, that is, in the internal circuit, mainly due to the problem of the manufacturing process, some Scan-cells in the scan chain always have their outputs fixed to 1 or 0 regardless of the value of the stimulus; and the delayed type faults mainly include FTR (Fast-To-Rise, over-speed rise), FTF (Fast-To-Fall, over-speed fall), STR (Slow-To-Rise, slow rise), STF (Slow-To-Fall, slow fall), etc.
  • the STF fault is used as an example for explanation, and the other fault types can be deduced in the same way.
  • the data should change from 1 to 0 when the next clock is triggered.
  • the output data of the current faulty Scan-cell has the problem of slow decline, the output of the Scan-cell still remains 1 when the next clock arrives. It can be seen that this type of fault will cause the output data of the Scan-cell to advance or lag by one clock cycle.
  • the final output result of the delay type fault can also be attributed to a fixed type fault, so this embodiment mainly explains the fixed type faults SA0 and SA1.
  • FIG3 is a schematic diagram of an application scenario of a fault location circuit provided by an embodiment of the present disclosure. As shown in FIG3, assuming that the second Scan-cell of the second vertical scan chain 303 from the right has an SA0 fault, the location flow of the fault location circuit provided by the present embodiment is as follows:
  • test vector 001100110011 is simultaneously input 301 to the first data input terminals of all vertical scan chains;
  • test vector is shifted and output from the data output end of the scan chain, and the output vector sequence 304 is detected;
  • the fault type of the second scan chain is SA0.
  • a single vector 1 is shifted and input from the first data input terminal to the second faulty scan chain and a scan chain immediately adjacent to the right thereof, and a single vector 0 is shifted and input to the first data input terminal of each of the remaining vertical scan chains at the same time;
  • the present embodiment identifies the fault based on the position where data 1 first appears in the output vector sequence of the dedicated debug chain 302, in order to exclude the possibility that other Scan-cells of the same faulty scan chain also have SA0 fault, for the remaining Scan-cells, their input data input terminals are selected as the second data input terminals. Even if they receive the XOR result with the Scan-cell immediately to the right, the input of the Scan-cell with SA0 fault will be set to 1. Since its output is still 0, the fault can be determined by observing the XOR result finally transmitted to the Scan-cell corresponding to the Dedicated debug chain at this stage.
  • FIG4 is a schematic diagram of another application scenario of a fault location circuit provided by an embodiment of the present disclosure. As shown in FIG4, assuming that the second Scan-cell of the second vertical scan chain 404 from the right has an SA0 fault, and the fifth Scan-cell of the seventh vertical scan chain 403 from the right has an SA1 fault, the location flow of the fault location circuit provided by the present embodiment is as follows:
  • test vector 001100110011 is simultaneously input 401 to the first data input terminals of all vertical scan chains;
  • test vector is shifted and output from the data output end of the scan chain, and the output vector sequence is detected 405;
  • the output vector sequence of the second vertical scan chain is 000000000000
  • the output vector sequence of the seventh vertical scan chain is 1111111111111
  • the other output vectors 405 remain 001100110011. It can be located that the second scan chain has an SA0 fault and the seventh scan chain has an SA1 fault, that is, the column coordinates of the faulty scan unit are obtained;
  • the 0 vector is shifted to all vertical scan chains. It can be seen that the Scan-cell output of the level with SA1 fault is XOR-processed in sequence and transmitted to the Scan-cell corresponding to the dedicated debug chain 402. Its value is 1. Then, the position where data 1 first appears in the vector shifted output from the dedicated debug chain 402 is the exact position of the SA1 fault Scan-cell. Then, the same method as scenario 1 can be used to determine the positions of the remaining SA0 fault Scan-cells.
  • FIG. 5 is a flow chart of a fault location method provided in an embodiment of the present disclosure. As shown in Figure 5, the fault location method provided in this embodiment includes steps S10 to S50.
  • Step S10 inputting a test vector into the scan array
  • Step S20 obtaining the output result of the scan array, and comparing the output result of the scan array with the test vector to determine the column coordinates where the faulty scan unit is located;
  • Step S30 inputting designated data into the scan array
  • Step S40 obtaining the output result of the dedicated debug chain, and comparing the output result of the dedicated debug chain with the specified data to determine the row coordinates where the fault scanning unit is located;
  • Step S50 determining the position of the fault scanning unit in the scanning array according to the column coordinates and the row coordinates.
  • a test vector is generated for inputting into each vertical scan chain in the scan array. Then, the same test vector is shifted along each vertical ordinary scan chain to the internal circuit. Driven by the shift clock, the vector value is detected at the output end of the scan array (i.e., the output result is obtained). Then, the input and output vector values are compared. If the two are the same, and the dedicated debug chain outputs an all-0 vector, it means that the scan chain has no defects. If the output vector changes, the vertical scan chain with a fault can be diagnosed, i.e., the column coordinates are obtained.
  • a specific diagnostic vector i.e., specified data
  • the specific diagnostic vector is repeatedly input to the first data input terminal of each scan chain, so that the diagnostic vector can be shifted into the circuit.
  • the output value along the horizontal direction will pass through the XOR logic in turn, and finally be transmitted to the corresponding Scan-cell of the Dedicated debug chain, and then shifted and output along the dedicated debug chain; by determining the position where 1 first appears in the output vector of the dedicated debug chain, the row coordinates of the faulty scan cell can be obtained; finally, the position of the faulty scan cell can be determined according to the column coordinates and row coordinates.
  • the Scan-cell in the faulty scan chain can be set through the second data input terminal, so that the faulty Scan-cell can be accurately located.
  • the step of the set processing may be repeated for multiple times until the position of the faulty scan cell is determined.
  • the fault location method provided in this embodiment is applied to the above fault location circuit.
  • the scan chain with fault can be identified through the conventional scan chain diagnosis method, that is, the column coordinates of the faulty Scan-cell are obtained; then a specific test vector is shifted and input, and after the XOR processing of the output of the Scan-cell at the same level, its value is
  • the Scan-cell corresponding to the dedicated debug chain is captured, thereby obtaining the row coordinates of the faulty Scan-cell.
  • the faulty Scan-cell can also be accurately located by setting the Scan-cell in the faulty scan chain.
  • This embodiment can effectively solve the problem of contamination of subsequent data caused by the faulty Scan-cell when the shifted data encounters the faulty Scan-cell, and finally achieves high-precision positioning of the faulty Scan-cell.
  • the dedicated debug chain in this embodiment can reuse the ordinary vertical scan chain without introducing other hardware overhead, so there will be no congestion problem in the subsequent layout and wiring.
  • the fault positioning method implemented in this embodiment based on the fault positioning circuit including the dedicated debug chain does not require complex logical calculations, can efficiently and accurately locate the faulty Scan-cell, and there is no problem of imbalance in the number of faulty Scan-cells.
  • the fault location method provided in this embodiment and the fault location circuit provided in the above embodiment belong to the same inventive concept.
  • the technical details not fully described in this embodiment can be referred to any of the above embodiments, and this embodiment has the same beneficial effects as the fault location circuit.
  • an embodiment of the present disclosure further provides a chip, including the above-mentioned fault location circuit, which can execute the above-mentioned fault location method applied to the fault location circuit.
  • the fault location circuit can be implemented by software and/or hardware and integrated in the chip.
  • FIG. 6 is a schematic diagram of the hardware structure of a chip provided in an embodiment of the present disclosure.
  • the chip may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005.
  • the communication bus 1002 is used to realize the connection and communication between these components.
  • the user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface.
  • the network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (WIreless-FIdelity, WI-FI) interface).
  • the memory 1005 may be a high-speed random access memory (Random Access Memory, RAM) or a stable non-volatile memory (Non-Volatile Memory, NVM), such as a disk storage.
  • RAM Random Access Memory
  • NVM Non-Volatile Memory
  • the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
  • the structure shown in FIG6 does not limit the chip, and may include more or fewer components than shown, or combine certain components, or arrange components differently.
  • the memory 1005 as a storage medium may include an operating system, a data storage module, a network communication module, a user interface module, and a computer program.
  • the network interface 1004 is mainly used for data communication with other devices;
  • the user interface 1003 is mainly used for data interaction with the user;
  • the processor 1001 and the memory 1005 in this embodiment can be set in the chip, and the chip calls the computer program stored in the memory 1005 through the processor 1001, and executes the fault location method applied to the chip provided in any of the above embodiments.
  • the chip proposed in this embodiment and the fault location method applied to the fault location circuit proposed in the above embodiment belong to the same inventive concept.
  • the technical details not fully described in this embodiment can be referred to any of the above embodiments, and this embodiment has the same beneficial effects as executing the fault location method.
  • an embodiment of the present disclosure further provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the fault location method provided in any of the above embodiments is implemented.
  • computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data).
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

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Abstract

本申请公开了一种故障定位电路、方法、芯片及计算机可读存储介质。该故障定位电路包括扫描阵列和专用调试链。扫描阵列包括多个扫描单元和异或单元，各所述扫描单元沿第一方向依次首尾相连以组成多列扫描链，在第二方向上相邻的各所述扫描单元互为同级扫描单元，各异或单元设置于各所述同级扫描单元之间，在第二方向上相邻的各所述异或单元互为同级异或单元，各沿着第二方向上的所述同级异或单元依次相连以组成异或链。专用调试链由多个沿第一方向依次首尾相连的扫描单元组成，专用调试链中各扫描单元分别与各异或链的输出端相连。扫描阵列的输出结果用于确定故障扫描单元所在的列坐标，专用调试链的输出结果用于确定故障扫描单元所在的行坐标。

Description

故障定位电路、方法、芯片及计算机可读存储介质
相关公开的交叉引用
本公开要求在2022年9月28日提交国家知识产权局、公开号为CN202211196928.2、发明名称为“故障定位电路、方法、芯片及计算机可读存储介质”的中国专利申请的优先权，该申请的全部内容通过引用结合在本公开中。
技术领域
本公开的实施例涉及但不限于集成电路测试技术领域，尤其涉及故障定位电路、方法、芯片及计算机可读存储介质。
背景技术
随着芯片加工先进制程的不断提高，芯片上集成的晶体管数量也在同步大幅增加，良率的提升成为芯片制造环节中的关键要素，集成电路故障诊断的重要性也愈发凸显。
在实际芯片中，Scan-cell(扫描单元)及其时钟通路大约占据了整个芯片面积的30％。扫描链作为内部测试电路，和其它逻辑一样，不可避免的会存在一些故障。据统计，10％-30％的Scan-cell故障就可能会导致整条扫描链的失效，而50％的芯片故障是由扫描链所致。由此可知，扫描链的故障诊断与Scan-cell的高精度定位具有重要意义。
目前，要实现扫描链的故障诊断与Scan-cell的高精度定位，就需要改变增加Scan-cell的输入端口，或需要引入复杂的故障诊断算法。但是前者会导致电路布局布线拥塞的问题，后者存在计算复杂性高和样本不平衡的问题。
发明内容
本公开的主要目的在于提供一种故障定位电路、方法、芯片及计算机可读存储介质，旨在高效且精准地定位到故障Scan-cell，避免电路布局布线拥塞、计算复杂性高和样本不平衡等技术缺陷。
为实现上述目的，本公开提供一种故障定位电路，包括：扫描阵列和专用调试链。所述扫描阵列包括多个扫描单元和异或单元，各所述扫描单元沿第一方向依次首尾相连以组成多列扫描链，在第二方向上相邻的各所述扫描单元互为同级扫描单元，各所述异或单元设置于各所述同级扫描单元之间，在所述第二方向上相邻的各所述异或单元互为同级异或单元，各沿着第二方向上的所述同级异或单元依次相连以组成异或链，其中，所述第一方向和所述第二方向不同向；所述专用调试链由多个沿所述第一方向依次首尾相连的扫描单元组成，所述专用调试链中各所述扫描单元分别与各所述异或链的输出端相连；所述扫描阵列的输出结果用于确定故障扫描单元所在的列坐标，所述专用调试链的输出结果用于确定所述故障扫描单元所在的行坐标。
此外，为实现上述目的，本公开还提供一种故障定位方法，应用于上述故障定位电路，包括：向扫描阵列输入测试向量；获取所述扫描阵列的输出结果，将所述扫描阵列的输出结果与所述测试向量进行对比以确定所述故障扫描单元所在的列坐标；向所述扫描阵列中输入指定数据；获取专用调试链的输出结果，将所述专用调试链的输出结果与所述指定数据进行对比以确定所述故障扫描单元所在的行坐标；根据所述列坐标和所述行坐标确定所述故障扫描单元在所述扫描阵列中的位置。
此外，为实现上述目的，本公开还提供一种芯片，所述芯片包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述计算机程序被所述处理器执行时实现如上所述的故障定位方法。
此外，为实现上述目的，本公开还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如上所述的故障定位方法。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一部分，对于本领域普通技术人员来讲，在不付出创造性劳 动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本公开一实施例的一种故障定位电路的结构示意图；
图2为根据本公开一实施例的一种故障定位电路涉及的扫描单元的结构示意图；
图3为根据本公开一实施例的一种故障定位电路的应用场景示意图；
图4为根据本公开一实施例的一种故障定位电路的另一应用场景示意图；
图5为根据本公开一实施例的一种故障定位方法的流程示意图；
图6为根据本公开一实施例的一种芯片的硬件结构示意图。
具体实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本公开实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本公开实施例。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本公开实施例的描述。
需要说明的是，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于流程图中的顺序执行所示出或描述的步骤。说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
还应当理解，在本公开实施例说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本公开实施例的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
随着芯片加工先进制程的不断提高，芯片上集成的晶体管数量也在同步大幅增加，良率的提升成为芯片制造环节中的关键要素，集成电路故障诊断的重要性也愈发凸显。
在测试过程中，由于芯片内部拥有庞大数量的组合逻辑和时序逻辑，电路中的寄存器数据难以被直接测量与控制，导致其可观测性和可控制性低，整个芯片的可测试性因此难以满足要求。传统依赖于电子扫描显微镜等物理手段，已无法在如今先进制程下的芯片中进行故障的有效定位，基于扫描链的DFT(Design For Test，可测性设计)应运而生。
扫描链是在逻辑电路中将功能寄存器替换为Scan-cell并串接成链的结构。通过扫描链可以有效地将测试数据传递到逻辑电路内部，同时将被测试单元的输出值传递输出，实现测试功能。在Scan-cell的MUX(multiplexer，数据选择器)选择信号控制下，扫描链通常存在两种工作模式：功能模式和测试模式。功能模式下，Scan-cell本质是执行寄存器的功能，主要存储组合逻辑的数据，按照原来的结构工作。测试模式下，将测试数据从扫描链依次移位输入，经过对逻辑数据的捕获，再从扫描链移位输出比较。
在实际芯片中，Scan-cell及其时钟通路大约占据了整个芯片面积的30％。扫描链作为内部测试电路，和其它逻辑一样，不可避免的会存在一些故障。据统计，10％-30％的Scan-cell故障就可能会导致整条扫描链的失效，而50％的芯片故障是由扫描链所致，由此可知，扫描链的故障诊断与Scan-cell的高精度定位具有重要意义。
一般情况下，一条扫描链可以由几十、上百甚至更多的Scan-cell组成。采用传统的方法，将测试向量从一端依次移位进入扫描链，再从另一端移位输出。通过与输入向量比较，很容易检测到故障扫描链。但由于链中的Scan-cell数目较多，具体定位到故障的Scan-cell具有一定的挑战性。主要原因有几下几点：第一，故障的Scan-cell结果只能从扫描链依次移位输出，无法直接观测链中特定位置的Scan-cell结果；第二，在一条诊断存在故障的扫描链中，当测试向量移位至某个故障Scan-cell，例如其为Stuck-at 1故障，则其后的所有数据均会被污染，无论后续的向量为何值，经此故障Scan-cell后输出值将全为1；第三，在数据捕获期间，如果某一Scan-cell的输入为另一个故障Scan-cell的输出，即该Scan-cell捕获的是一个错误数值，但在后续的移位过程中，经过扫描链中的另一故障Scan-cell，在最终的移位输出向量中将无法判别该数据是由捕获错误数据所致还是后续的故障Scan-cell污染所致。
为了精确定位扫描链中的故障Scan-cell，目前主要有以下两种可行方案。第一种方案是采取二维扫描串链，该方案采取的具体行为是对任意一个独立的Scan-cell，将其输出分别在水平和垂直方向与下一个Scan-cell相连，最终形成二 维的扫描链。在扫描链形成后，依次从水平、垂直或者对角线路径移位测试向量到电路内部。根据不同扫描路径的输出与输入值匹配与否，可以精确定位到故障点。然而，当电路中出现故障的Scan-cell数量增加或故障点的位置集中时，该方案就需要增加Scan-cell的输入端口，才能进行有效的定位。但是这会带来布局布线拥塞的问题。第二种方案是在不改变Scan-cell设计和扫描链结构的前提下，通过优化扫描链故障诊断算法或者引入机器学习，如：ANN(Artificial Neural Network，人工神经网络)、DNN(Deep Neural Network，深度神经网络)等，进行对扫描链中故障Scan-cell的准确定位，但是当Scan-cell的数量巨大时，其计算复杂性高，并且会存在样本不平衡问题。
基于此，本公开实施例提供了一种故障定位电路、方法、设备及计算机可读存储介质。该故障定位电路包括：扫描阵列，扫描阵列包括多个扫描单元和异或单元，各扫描单元沿第一方向依次首尾相连以组成多列扫描链，在第二方向上相邻的各扫描单元互为同级扫描单元，各异或单元设置于各同级扫描单元之间，在第二方向上相邻的各异或单元互为同级异或单元，各沿着第二方向上的同级异或单元依次相连以组成异或链，其中，第一方向和第二方向不同向；专用调试链，专用调试链由多个沿第一方向依次首尾相连的扫描单元组成，专用调试链中各扫描单元分别与各异或链的输出端相连；扫描阵列的输出结果用于确定故障扫描单元所在的列坐标，专用调试链的输出结果用于确定故障扫描单元所在的行坐标。
本公开实施例提供的具备Dedicated debug chain(专用调试链)的故障定位电路，利用常规的扫描链诊断方法可以识别到存在故障的扫描链，即可获得故障Scan-cell的列坐标；再移位输入特定的测试向量，经过水平方向同级相邻的Scan-cell输出值依次做异或操作，然后将输出值移位至Dedicated debug chain上相应的Scan-cell，从而获取到故障Scan-cell的行坐标，可以有效解决移位数据遇到故障Scan-cell对后续数据造成的污染问题，最终实现对故障Scan-cell的高精度定位，对于同时出现多种故障的Scan-cell，还可以通过对其进行置位处理，实现精准定位。
相比于现有技术中的二维串链，本公开实施例故障定位电路中的专用调试链可以复用普通的垂直扫描链，除去对Scan-cell的输出结果做异或处理，并未引入其他的硬件开销，因此在后续的布局布线中不会发生拥塞问题；相比于现有技术中的优化扫描链故障诊断算法或者引入机器学习的诊断定位方法，本公开实施例提供的包括专用调试链的故障定位电路无需复杂的逻辑计算，定位故障Scan-cell高效精准，不存在故障Scan-cell数量不平衡问题；本公开实施例提供 的故障定位电路可以实现对任意位置和任意数量的故障Scan-cell进行高精度诊断，具有很强的普适性。
本公开实施例提供的故障定位电路、方法、设备及计算机可读存储介质，具体通过如下实施例进行说明，首先描述本公开实施例中的故障定位电路。
本公开实施例提供了一种故障定位电路。参照图1，图1为本公开实施例一实施例提供的一种故障定位电路的结构示意图。如图1所示，根据本实施例的故障定位电路包括扫描阵列10和专用调试链20。
扫描阵列10包括多个扫描单元101和异或单元102，各扫描单元101沿第一方向依次首尾相连以组成多列扫描链103，在第二方向上相邻的各扫描单元101互为同级扫描单元，各异或单元102设置于各同级扫描单元之间，在第二方向上相邻的各异或单元102互为同级异或单元，各沿着第二方向上的同级异或单元依次相连以组成异或链104，其中，第一方向和第二方向不同向；
专用调试链20由多个沿第一方向依次首尾相连的扫描单元101组成，专用调试链20中各扫描单元101分别与各异或链104的输出端相连；
扫描阵列10的输出结果用于确定故障扫描单元101所在的列坐标，专用调试链20的输出结果用于确定故障扫描单元101所在的行坐标。
需要说明的是，本实施例中，组成专用调试链20的扫描单元101均为已知无故障的扫描单元，其数量与组成一条扫描链103的扫描单元101的数量一致。因此，在第二方向上相邻的专用调试链20中的各扫描单元101(即图1中的Cell)与扫描阵列10中的各扫描单元101亦可视为同级扫描单元，区别在于专用调试链20与扫描阵列10的各同级扫描单元之间无需设置异或单元102。为便于描述，在如图1所示故障定位电路的结构图中，将第一方向视为垂直方向，将第二方向视为水平方向(此时第一方向和第二方向相互正交，本实施例仅为举例，只要第一方向不与第二方向平行，均属于本实施例提及的不同向所概括的保护范围)。在垂直方向上相邻的各扫描单元101首尾依次相连组成了多条扫描链103，各扫描链103的输入信号为Scan in，输出信号为Scan out。在水平方向上相邻的各扫描单元101两两之间设置有一个异或单元102(即图1中的XOR)，各异或单元102在垂直方向上无连接关系，但在水平方向上相邻的各异或单元102依次连接组成了多条异或链104。各异或链104的输出端分别与专用调试链20中的同级扫描单元相连。各扫描单元101在正常工作的情况下，经过扫描单元的输入向量 与输出向量数值相同，在出现故障的情况下，会将经过该扫描单元的向量值强制转换为0或1；各异或单元102用于进行异或逻辑运算，遵循同0异1的运算规则，即两个输入值相同，则输出值为0，两个输入值不同，则输出值为1。
本实施例中，为了便于检测扫描链中最常见的几种Scan-cell故障类型，向每条垂直扫描链103移位输入的测试向量为001100110011序列，该序列能够检测任一Scan-cell所有的四种不同信号跳变，即0-0、0-1、1-0、1-1。由于该测试向量从扫描链103的输入端一直移位到输出端，因此扫描链中的每个Scan-cell都会被诊断。如果从垂直扫描链的移位输出端得到的向量序列也为001100110011，即和输入的诊断向量保持一致，则说明该扫描链正常。
本实施例提供的故障定位电路，利用常规的扫描链诊断方法可以识别到出现故障的扫描链，即通过对比扫描阵列中各扫描链的输入向量和输出向量，可以获知哪条扫描链出现了故障，进而获得故障扫描单元所在的列坐标；再移位输入特定的测试向量，基于异或链对水平方向相邻的各同级扫描单元的输出值依次做异或操作，然后将输出值移位至专用调试链上相应的同级扫描单元，之后根据专用调试链的输出值即可得知水平方向上是哪一行扫描单元出现了故障，进而获取到故障单元的行坐标，在获取到故障扫描单元的列坐标和行坐标后，即可准确地在扫描阵列中确定故障扫描单元所在的位置。
在一些可行的实施例中，参照图2，图2为本公开实施例提供的一种故障定位电路涉及的扫描单元的结构示意图。如图2所示，扫描单元101包括：
第一数据输入端Data_in1，第一数据输入端Data_in1用于接收测试向量；
第二数据输入端Data_in2，第二数据输入端Data_in2用于接收置位数据；
数据选择端Data_sel，数据选择端Data_sel用于选择接收测试向量或置位数据；
数据输出端Data_out，数据输出端Data_out用于输出检测结果。
本实施例中，图2中扫描单元101的上侧端口即第一数据输入端Data_in1可以用于接收测试向量，右侧端口即第二数据输入端Data_in2可以用于接收置位数据，置位数据可以是0或1，左侧端口即数据选择端Data_sel用于选择扫描单元101是通过第一数据输入端Data_in1接收测试向量还是通过第二数据输入端Data_in2接收置位数据，下侧端口即数据输出端Data_out可以用于输出检测结果。
结合图1可知，在垂直方向上相邻的各扫描单元101的首尾连接方式即前一扫描单元的数据输出端Data_out与后一扫描单元的第一数据输入端Data_in1相连。而在组成扫描链103后，位于扫描链103顶部的扫描单元101的第一数据输入端Data_in1用于接收输入扫描线Scan in输入的测试向量。位于扫描链103底部的扫描单元101的数据输出端Data_out用于将当前扫描链103的检测结果输出至输出扫描线Scan out；扫描阵列10中最右侧的各扫描单元101的第二数据输入端Data_in2可以用于接收置位数据，而其他的各扫描单元101的第二数据输入端Data_in2与异或单元102相连；扫描阵列10中各扫描单元101的数据选择端Data_sel和一与门的输出端相连，该与门的两个输入端分别接入Data_sel信号和Config_in信号。本实施例中，仅在Data_sel信号为1且Config_in信号为1时，扫描单元101才选择通过第二数据输入端Data_in2接收置位数据，其余情况均默认扫描单元101通过第一数据输入端Data_in1接收测试数据。
需要说明的是，在同一时刻，扫描阵列10中的各扫描单元101只会接收来自一个输入端的测试向量，而专用调试链20中的各扫描单元101的数据选择端Data_sel空接。专用调试链20中的各扫描单元101可以同时接收来自两个输入端的测试向量(专用调试链20中的顶部扫描单元的第一数据输入端Data_in1空接)。这是因为专用调试链20中的各扫描单元101均为非故障扫描单元，它们在接收到测试向量之后只会随时钟信号将接入的测试向量移位输出至下一扫描单元，不会对测试向量的值和排序产生影响。
在一些可行的实施例中，异或单元102包括：第一逻辑输入端、第二逻辑输入端、第一逻辑输出端和第二逻辑输出端。
在一些可行的实施例中，扫描链103包括边界链和中间链；
异或单元102包括设置于边界链与中间链之间的头部异或单元、设置于两个中间链之间的中间异或单元以及与专用调试链20距离最近的尾部异或单元；
头部异或单元、中间异或单元以及尾部异或单元依次相连以组成异或链104。
需要说明的是，本实施例同样可结合图1进行理解，将各异或单元102的右侧端口称为第一逻辑输入端、左侧端口称为第二逻辑输入端、上侧端口称为第一逻辑输出端、下侧端口称为第二逻辑输出端。本实施例还基于扫描链103中各扫描单元101的各端口连接关系的不同，将图1扫描阵列10中最右侧的扫描链103称为边界链，扫描阵列10中的其余扫描链103称为中间链。如图1所示，边界链与中间链的区别主要在于各扫描单元103的第二数据输入端Data_in2连接方 式不同，边界链的各扫描单元103的第二数据输入端Data_in2可以用于接收来自数据线的置位数据，而中间链的各扫描单元101的第二数据输入端Data_in2是与异或单元102的第一逻辑输出端相连。头部异或单元即与边界链相邻的一列异或单元，亦为图1中最右侧的一列异或单元，尾部异或单元即最靠近专用调试链20的一列异或单元，亦为图1中最左侧的一列异或单元。中间异或单元即位于头部异或单元和尾部异或单元之间的异或单元。头部异或单元的第二逻辑输出端与中间异或单元的第一逻辑输入端相连，中间异或单元的第二逻辑输出端与尾部异或单元的第一逻辑输入端相连，即组成了异或链104。而异或链104的输出端即尾部异或单元的第二逻辑输出端，其与专用调试链20中的同级扫描单元相连，将在水平方向上相邻的扫描阵列10中的各同级扫描单元101的输出值进行多次异或处理后传输至专用调试链20，进而可以通过专用调试链20的输出推导出故障扫描单元所在的位置。
在一些可行的实施例中，头部异或单元的第一逻辑输入端与边界链中的同级扫描单元的数据输出端相连，头部异或单元的第二逻辑输入端与中间链中的同级扫描单元的数据输出端相连，头部异或单元的第一逻辑输出端与中间链中的同级扫描单元的第二数据输入端相连，头部异或单元的第二逻辑输出端与中间异或单元中的同级异或单元的第一逻辑输入端相连。
在一些可行的实施例中，中间异或单元的第一逻辑输入端与靠近边界链的中间链一侧的同级异或单元的第二逻辑输出端相连，中间异或单元的第二逻辑输入端与远离边界链的中间链中的同级扫描单元的数据输出端相连，中间异或单元的第一逻辑输出端与远离边界链的中间链中的同级扫描单元的第二数据输入端相连，中间异或单元的第二逻辑输出端与远离边界链的中间链一侧的同级异或单元的第一逻辑输入端相连。
在一些可行的实施例中，尾部异或单元的第一逻辑输入端与靠近边界链的中间链一侧的同级异或单元的第二逻辑输出端相连，尾部异或单元的第二逻辑输入端与远离边界链的中间链中的同级扫描单元的数据输出端相连，尾部异或单元的第一逻辑输出端与远离边界链的中间链中的同级扫描单元的第二数据输入端相连，尾部异或单元的第二逻辑输出端与专用调试链20中的扫描单元101的第二数据输入端相连。
示例性地，由于基于本实施例提供的故障定位电路对故障扫描单元进行高精度定位诊断具有普适性，因此本公开实施例针对垂直扫描链中出现的两种不同故障场景，作如下详细讲解，其它故障情况分析原理一致。扫描链的故障类型主要 包括两大类，分别是Stuck-at(固定)型故障和延时型故障。其中，固定型故障包括SA1(Stuck-At-1，固定1)故障和SA0(Stuck-At-0，固定0)故障，即在内部电路中，主要由于制备工艺的问题，扫描链中的某些Scan-cell无论激励为何值，其输出始终固定为1或0；而延时型故障主要包括FTR(Fast-To-Rise，过速上升)、FTF(Fast-To-Fall，过速下降)、STR(Slow-To-Rise，慢速上升)、STF(Slow-To-Fall，慢速下降)等。本实施例中仅以STF故障为例进行说明，其余故障类型可同理推导得知。经过STF故障类型的Scan-cell，在下一个时钟触发时，数据本应该从1变为0。但是由于当前故障Scan-cell存在输出数据下降过缓的问题，在下一个时钟到来时，该Scan-cell的输出仍然保持为1。由此可知，该类型的故障会使Scan-cell的输出数据超前或滞后一个时钟周期。而延时型故障最终的输出结果也可以归结为固定型故障，故而本实施例主要对于固定型故障SA0和SA1进行讲解。
场景一：
对于单种故障类型的情况，可参照图3。图3为本公开实施例提供的一种故障定位电路的应用场景示意图。如图3所示，假设右起第2条垂直扫描链303的第2个Scan-cell出现SA0故障，则本实施例提供的故障定位电路的定位流程如下：
3.1)除了Dedicated debug chain专用调试链302之外，对所有垂直扫描链的第一数据输入端同时输入301测试向量001100110011；
3.2)经过若干时钟周期，将测试向量从扫描链的数据输出端移位输出，并检测输出向量序列304；
3.3)与输入的301测试向量对比，可以发现右起第2条垂直扫描链的输出向量序列为000000000000，其它扫描链的输出向量均保持为001100110011，由此可以定位出第2条扫描链存在故障，相当于获得了故障列坐标；
3.4)根据输出测试向量全为0，可以反推出第2条扫描链的故障类型为SA0，则此时向第2条故障扫描链和其右边紧邻的一条扫描链，同时从第一数据输入端移位输入单个向量1，同时向剩余的每条垂直扫描链的第一数据输入端同时移位输入单个向量0；
3.5)检测Dedicated debug chain专用调试链302的输出向量序列，由于故障扫描链中功能正常的Scan-cell输出值为1，它与右边紧邻Scan-cell输出值相同，经异或逻辑，结果为0，而其它同级的Scan-cell输出值均为0，经过逐个异或， 其值始终保持为0，最后传递到同级的Dedicated debug chain的Scan-cell上。但当遇到SA0故障的Scan-cell时，由于其输出为0，而其输出0与右边紧邻Scan-cell的输出值1相反，两者异或的结果为1，而剩余同级的Scan-cell的输出值保持为0，当从右往左依次做异或处理时，可以发现输出值始终保持为1，最终传递到Dedicated debug chain专用调试链302对应的Scan-cell上；所以可以根据专用调试链302的输出向量序列中首次出现数据1的位置，即可获得故障Scan-cell的行坐标，进而精确定位到故障垂直扫描链的具体Scan-cell位置；
3.6)由于本实施例是根据首次出现专用调试链302的输出向量序列中首次出现数据1的位置认定故障，故而为了排除同一条故障扫描链的其它Scan-cell也存在SA0故障，对剩余的Scan-cell，将其输入数据输入端选择为第二数据输入端，即使其接收与右边紧邻Scan-cell异或的结果，则此时带有SA0故障的Scan-cell输入会被置为1，由于其输出仍然为0，观察该级最终传递至Dedicated debug chain对应的Scan-cell上的异或结果，即可实现故障确定。
场景二：
对于多种故障类型的情况，可参照图4。图4为本公开实施例提供的一种故障定位电路的另一应用场景示意图。如图4所示，假设右起第2条垂直扫描链404的第2个Scan-cell出现SA0故障，右起第7条垂直扫描链403的第5个Scan-cell出现SA1故障，则本实施例提供的故障定位电路的定位流程如下：
4.1)除了Dedicated debug chain专用调试链402之外，对所有垂直扫描链的第一数据输入端同时输入401测试向量001100110011；
4.2)经过若干时钟周期，将测试向量从扫描链的数据输出端移位输出，并检测输出向量序列405；
4.3)与输入测试向量401对比，可以发现第2条垂直扫描链的输出向量序列为000000000000，第7条垂直扫描链的输出向量序列为111111111111，而其它输出向量405保持为001100110011，至此可以定位出第2条扫描链存在SA0故障，第7条扫描链存在SA1故障，即获得故障扫描单元的列坐标；
4.4)同时向所有的垂直扫描链移位输入0向量，可知存在SA1故障的那级Scan-cell输出经过依次异或处理，传递至Dedicated debug chain专用调试链402对应的Scan-cell上，其值为1，则从Dedicated debug chain专用调试链402上移位输出的向量中，首次出现数据1的位置即SA1故障Scan-cell的准确位置，然后可以采取与场景一相同的方式来确定剩余的SA0故障Scan-cell位置。
此外，本公开实施例还提供一种故障定位方法，该故障定位方法可以应用于上述故障定位电路。参照图5，图5为本公开实施例一实施例提供的一种故障定位方法的流程示意图。如图5所示，本实施例提供的故障定位方法包括步骤S10至S50。
步骤S10，向扫描阵列输入测试向量；
步骤S20，获取扫描阵列的输出结果，将扫描阵列的输出结果与测试向量进行对比以确定故障扫描单元所在的列坐标；
步骤S30，向扫描阵列中输入指定数据；
步骤S40，获取专用调试链的输出结果，将专用调试链的输出结果与指定数据进行对比以确定故障扫描单元所在的行坐标；
步骤S50，根据列坐标和行坐标确定故障扫描单元在扫描阵列中的位置。
本实施例可结合上述故障定位电路的各实施例和附图进行理解，首先生成用于输入到扫描阵列中各垂直方向的扫描链的测试向量；之后沿每条垂直方向的普通扫描链移位相同的测试向量到内部电路，在移位时钟的驱动下，在扫描阵列的输出端检测向量值(即获取输出结果)；再对比输入、输出的向量值，如果两者相同，并且Dedicated debug chain专用调试链输出为全0向量，说明该扫描链没有缺陷，如果输出向量有变化，则可以诊断到存在故障的垂直扫描链，即获取到列坐标；对存在故障的垂直扫描链，重新生成特定的诊断向量(即指定数据)，重复向各扫描链的第一数据输入端输入该特定的诊断向量，使诊断向量能够移位到电路内部，此时每经过一个Scan-cell，沿水平方向的输出值就会依次经过异或逻辑，最终传递到Dedicated debug chain相应的Scan-cell，再沿该专用调试链移位输出；通过判断专用调试链的输出向量中首次出现1的位置，即可获得故障扫描单元的行坐标；最后即可根据列坐标和行坐标确定故障扫描单元的位置。此外，为了避免漏检同一扫描链中的后续故障扫描单元，还可以通过第二数据输入端对故障扫描链中的Scan-cell做置位处理，就可以准确定位到故障Scan-cell，根据实际故障类型的不同，该置位处理的步骤可能会重复迭代多次，直至得到确定的故障扫描单元位置。
本实施例提供的故障定位方法应用于上述故障定位电路，通过常规的扫描链诊断方法可以识别到存在故障的扫描链，即获得故障Scan-cell的列坐标；再移位输入特定的测试向量，经过同一级Scan-cell输出的异或处理，其数值被 Dedicated debug chain对应的Scan-cell捕获到，从而获取到故障Scan-cell的行坐标。对复杂情况，还可以利用对故障扫描链中的Scan-cell置位处理，进行故障Scan-cell精确定位。本实施例可以有效解决移位数据遇到故障Scan-cell对后续数据造成的污染问题，最终实现对故障Scan-cell的高精度定位。相对于二维串链，本实施例中的Dedicated debug chain可以复用普通的垂直扫描链，并未引入其他的硬件开销，因此在后续的布局布线中不会发生拥塞问题。相对于优化扫描链故障诊断算法或者引入机器学习的诊断定位方法，本实施例基于包括Dedicated debug chain的故障定位电路实现的故障定位方法无需复杂的逻辑计算，能够高效精准地定位故障Scan-cell，不存在故障Scan-cell数量不平衡的问题。
本实施例提供的故障定位方法与上述实施例提供的故障定位电路属于同一发明构思，未在本实施例中详尽描述的技术细节可参见上述任意实施例，并且本实施例具备与故障定位电路相同的有益效果。
此外，本公开实施例还提供一种芯片，包括上述故障定位电路，可以执行上述应用于故障定位电路的故障定位方法，该故障定位电路可以通过软件和/或硬件的方式实现，并集成在芯片中。
参照图6，图6为本公开实施例一实施例提供的一种芯片的硬件结构示意图。如图6所示，芯片可以包括：处理器1001，例如中央处理器(Central Processing Unit，CPU)，通信总线1002、用户接口1003，网络接口1004，存储器1005。其中，通信总线1002用于实现这些组件之间的连接通信。用户接口1003可以包括显示屏(Display)、输入单元比如键盘(Keyboard)，可选用户接口1003还可以包括标准的有线接口、无线接口。网络接口1004可选的可以包括标准的有线接口、无线接口(如无线保真(WIreless-FIdelity，WI-FI)接口)。存储器1005可以是高速的随机存取存储器(Random Access Memory，RAM)，也可以是稳定的非易失性存储器(Non-Volatile Memory，NVM)，例如磁盘存储器。存储器1005可选的还可以是独立于前述处理器1001的存储设备。
本领域技术人员可以理解，图6中示出的结构并不构成对芯片的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。如图6所示，作为一种存储介质的存储器1005中可以包括操作系统、数据存储模块、网络通信模块、用户接口模块以及计算机程序。
在图6所示的芯片中，网络接口1004主要用于与其他设备进行数据通信； 用户接口1003主要用于与用户进行数据交互；本实施例中的处理器1001、存储器1005可以设置在芯片中，芯片通过处理器1001调用存储器1005中存储的计算机程序，并执行上述任一实施例提供的应用于芯片的故障定位方法。
本实施例提出的芯片与上述实施例提出的应用于故障定位电路的故障定位方法属于同一发明构思，未在本实施例中详尽描述的技术细节可参见上述任意实施例，并且本实施例具备与执行故障定位方法相同的有益效果。
此外，本公开实施例还提供一种计算机可读存储介质，该计算机可读存储介质可以为非易失性计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器执行时实现上述任一实施例提供的故障定位方法。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统可以被实施为软件、固件、硬件及其适当的组合。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
以上是对本公开实施例的较佳实施进行了具体说明，但本公开实施例并不局限于上述实施方式，熟悉本领域的技术人员在不违背本公开实施例精神的前提下还可作出种种的等同变形或替换，这些等同的变形或替换均包含在本公开实施例权利要求所限定的范围内。

Claims (10)

  1. 一种故障定位电路，包括：扫描阵列和专用调试链，
    所述扫描阵列包括多个扫描单元和异或单元，各所述扫描单元沿第一方向依次首尾相连以组成多列扫描链，在第二方向上相邻的各所述扫描单元互为同级扫描单元，各所述异或单元设置于各所述同级扫描单元之间，在所述第二方向上相邻的各所述异或单元互为同级异或单元，各沿着第二方向上的所述同级异或单元依次相连以组成异或链，其中，所述第一方向和所述第二方向不同向；
    所述专用调试链由多个沿所述第一方向依次首尾相连的扫描单元组成，所述专用调试链中各所述扫描单元分别与各所述异或链的输出端相连；
    所述扫描阵列的输出结果用于确定故障扫描单元所在的列坐标，所述专用调试链的输出结果用于确定所述故障扫描单元所在的行坐标。
  2. 如权利要求1所述的故障定位电路，其中，所述扫描单元包括：
    第一数据输入端，所述第一数据输入端用于接收测试向量；
    第二数据输入端，所述第二数据输入端用于接收置位数据；
    数据选择端，所述数据选择端用于选择接收所述测试向量或所述置位数据；
    数据输出端，所述数据输出端用于输出检测结果。
  3. 如权利要求2所述的故障定位电路，其中，所述异或单元包括：第一逻辑输入端、第二逻辑输入端、第一逻辑输出端和第二逻辑输出端。
  4. 如权利要求3所述的故障定位电路，其中，所述扫描链包括边界链和中间链；
    所述异或单元包括设置于所述边界链与所述中间链之间的头部异或单元、设置于两个所述中间链之间的中间异或单元以及与所述专用调试链距离最近的尾部异或单元；
    所述头部异或单元、所述中间异或单元以及所述尾部异或单元依次相连以组 成所述异或链。
  5. 如权利要求4所述的故障定位电路，其中，所述头部异或单元的第一逻辑输入端与所述边界链中的同级扫描单元的数据输出端相连，所述头部异或单元的第二逻辑输入端与所述中间链中的同级扫描单元的数据输出端相连，所述头部异或单元的第一逻辑输出端与所述中间链中的同级扫描单元的第二数据输入端相连，所述头部异或单元的第二逻辑输出端与所述中间异或单元中的同级异或单元的第一逻辑输入端相连。
  6. 如权利要求4所述的故障定位电路，其中，所述中间异或单元的第一逻辑输入端与靠近所述边界链的所述中间链一侧的同级异或单元的第二逻辑输出端相连，所述中间异或单元的第二逻辑输入端与远离所述边界链的所述中间链中的同级扫描单元的数据输出端相连，所述中间异或单元的第一逻辑输出端与远离所述边界链的所述中间链中的同级扫描单元的第二数据输入端相连，所述中间异或单元的第二逻辑输出端与远离所述边界链的所述中间链一侧的同级异或单元的第一逻辑输入端相连。
  7. 如权利要求4所述的故障定位电路，其中，所述尾部异或单元的第一逻辑输入端与靠近所述边界链的所述中间链一侧的同级异或单元的第二逻辑输出端相连，所述尾部异或单元的第二逻辑输入端与远离所述边界链的所述中间链中的同级扫描单元的数据输出端相连，所述尾部异或单元的第一逻辑输出端与远离所述边界链的所述中间链中的同级扫描单元的第二数据输入端相连，所述尾部异或单元的第二逻辑输出端与所述专用调试链中的扫描单元的第二数据输入端相连。
  8. 一种故障定位方法，其中，应用于权利要求1至7中任一项所述的故障定位电路，包括：
    向扫描阵列输入测试向量；
    获取所述扫描阵列的输出结果，将所述扫描阵列的输出结果与所述测试向量进行对比以确定所述故障扫描单元所在的列坐标；
    向所述扫描阵列中输入指定数据；
    获取专用调试链的输出结果，将所述专用调试链的输出结果与所述指定数据进行对比以确定所述故障扫描单元所在的行坐标；
    根据所述列坐标和所述行坐标确定所述故障扫描单元在所述扫描阵列中的位置。
  9. 一种芯片，其中，所述芯片包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述计算机程序被所述处理器执行时实现如权利要求8所述的故障定位方法。
  10. 一种计算机可读存储介质，其中，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求8所述的故障定位方法。
PCT/CN2023/117939 2022-09-28 2023-09-11 故障定位电路、方法、芯片及计算机可读存储介质 WO2024067035A1 (zh)

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