WO2023281795A1 - 保護回路及び半導体装置 - Google Patents

保護回路及び半導体装置 Download PDF

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Publication number
WO2023281795A1
WO2023281795A1 PCT/JP2022/005953 JP2022005953W WO2023281795A1 WO 2023281795 A1 WO2023281795 A1 WO 2023281795A1 JP 2022005953 W JP2022005953 W JP 2022005953W WO 2023281795 A1 WO2023281795 A1 WO 2023281795A1
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Prior art keywords
semiconductor device
misfet
protection circuit
external terminal
main electrode
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PCT/JP2022/005953
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English (en)
French (fr)
Japanese (ja)
Inventor
知矢 西田
理一 本山
英昭 二井
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Priority to JP2023533057A priority Critical patent/JP7853299B2/ja
Priority to CN202280046646.6A priority patent/CN117581380A/zh
Priority to US18/574,986 priority patent/US20240347529A1/en
Publication of WO2023281795A1 publication Critical patent/WO2023281795A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H03F1/523—Circuit arrangements for protecting such amplifiers for amplifiers using field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/84—Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present disclosure relates to protection circuits and semiconductor devices.
  • Patent Document 1 discloses a high-frequency integrated circuit with an electrostatic protection element.
  • the static electricity protection element has a depletion field effect transistor and an enhancement field effect transistor electrically connected in series, and further has a capacitor electrically connected in parallel with the enhancement field effect transistor.
  • a field effect transistor is composed of a MESFET, a gate junction type FET, a HEMT, or the like.
  • Patent Document 2 discloses a surge protection element and a semiconductor device.
  • the surge protection element is composed of a pnp bipolar transistor.
  • This bipolar transistor has a p-type GaN layer as a collector region, an AlGaN layer and a GaN layer as a base region, and a p-type GaN layer as an emitter region.
  • a surge protection device absorbs a surge as a punch-through current.
  • Patent Document 3 discloses a semiconductor integrated circuit equipped with an electrostatic discharge protection circuit.
  • the electrostatic breakdown protection circuit is composed of a diode-connected transistor. Bipolar transistors or MOSFETs are used for the transistors.
  • High-frequency power amplifiers operating in the millimeter wave band have been developed for next-generation mobile terminals.
  • Insulated gate field effect transistors using GaN-based wide bandgap materials are used to construct high frequency power amplifiers.
  • a metal-insulator-semiconductor field-effect transistor (hereinafter referred to simply as "MISFET") is used.
  • MISFET metal-insulator-semiconductor field-effect transistor
  • a p-type layer is used in each of the electrostatic protection element disclosed in Patent Document 1, the surge protection element disclosed in Patent Document 2, and the electrostatic discharge protection circuit disclosed in Patent Document 3. .
  • the activation rate of p-type impurities is very low, so it is difficult to manufacture p-type GaN, and the process affinity (mass productivity) in the manufacturing process is poor.
  • ESD Electro Static Discharge
  • This technology provides a protection circuit and a semiconductor device with excellent ESD resistance or avalanche resistance.
  • a protection circuit has a first main electrode connected between an external terminal and an internal circuit, a second main electrode and a gate electrode connected to a reference power supply, and accumulates hot carriers. It comprises a first insulated gate field effect transistor with a possible charge storage disposed in the gate insulator.
  • a semiconductor device comprises: an external terminal provided on a substrate; an internal circuit provided on the substrate and connected to the external terminal; A first insulating gate having a first main electrode connected between and, a second main electrode and a gate electrode connected to a reference power supply, and a charge accumulating portion capable of accumulating hot carriers disposed in a gate insulating film.
  • a protection circuit comprising a field effect transistor.
  • FIG. 1 is a layout diagram (plan view) of a high frequency power amplifier module in which a semiconductor device having a protection circuit and an internal circuit according to a first embodiment of the present disclosure is mounted;
  • FIG. 2 is a circuit block diagram of a protection circuit and an internal circuit of the semiconductor device shown in FIG. 1;
  • FIG. A cross-sectional view of a main part of a semiconductor device (a cross-sectional view cut along line AA shown in FIG. 4) for explaining a cross-sectional structure of a MISFET constructing a protection circuit and an internal circuit shown in FIGS. be.
  • FIG. 3 is a plan view of a main part of a semiconductor device for explaining a planar structure of a MISFET constructing a protection circuit and an internal circuit shown in FIGS.
  • FIG. 1 and 2; 4 is a cross-sectional view of a first process corresponding to FIG. 3 for explaining the manufacturing method of the semiconductor device on which the protection circuit and the internal circuit are mounted according to the first embodiment;
  • FIG. It is a 2nd process sectional drawing explaining the manufacturing method of a semiconductor device. It is a 3rd process sectional drawing explaining the manufacturing method of a semiconductor device. It is a 4th process sectional drawing explaining the manufacturing method of a semiconductor device. It is a 5th process sectional drawing explaining the manufacturing method of a semiconductor device. It is a 6th process sectional drawing explaining the manufacturing method of a semiconductor device. It is a 7th process sectional drawing explaining the manufacturing method of a semiconductor device. It is the 8th process sectional drawing explaining the manufacturing method of a semiconductor device.
  • FIG. 5 is a flow chart illustrating a method for adjusting the threshold voltage of the protection circuit shown in FIGS. 2 to 4;
  • FIG. 14 is a timing chart illustrating a method of adjusting the threshold voltage of the protection circuit based on the flowchart shown in FIG. 13;
  • 4 is a cross-sectional view of main parts of a semiconductor device corresponding to FIG. 3, illustrating a cross-sectional structure of a MISFET constructing a protection circuit and an internal circuit according to a second embodiment of the present disclosure;
  • FIG. 3 is a circuit block diagram of a protection circuit and an internal circuit, corresponding to FIG. 2, of a semiconductor device according to a third embodiment of the present disclosure;
  • FIG. 3 is a circuit block diagram of a protection circuit and an internal circuit, corresponding to FIG.
  • FIG. 3 is a circuit block diagram of a protection circuit and an internal circuit, corresponding to FIG. 2, of a semiconductor device according to a fourth embodiment of the present disclosure
  • FIG. 3 is a circuit block diagram of a protection circuit and an internal circuit, corresponding to FIG. 2, of a semiconductor device according to a fifth embodiment of the present disclosure
  • FIG. 3 is a circuit block diagram of a protection circuit and an internal circuit corresponding to FIG. 2 of a semiconductor device according to a sixth embodiment of the present disclosure
  • FIG. FIG. 11 is a circuit block diagram of a protection circuit and an internal circuit, corresponding to FIG. 2, of a semiconductor device according to a seventh embodiment of the present disclosure
  • FIG. 13 is a circuit block diagram of a protection circuit and an internal circuit, corresponding to FIG. 2, of a semiconductor device according to an eighth embodiment of the present disclosure
  • FIG. 12 is a circuit block diagram of a protection circuit and an internal circuit, corresponding to FIG. 2, of a semiconductor device according to a ninth embodiment of the present disclosure
  • FIG. 20 is a circuit block diagram of a protection circuit and an internal circuit, corresponding to FIG. 2, of a semiconductor device according to a tenth embodiment of the present disclosure
  • FIG. 13 is a circuit block diagram of a protection circuit and an internal circuit, corresponding to FIG. 2, of a semiconductor device according to an eleventh embodiment of the present disclosure
  • FIG. 20 is a circuit block diagram of a protection circuit and an internal circuit, corresponding to FIG. 2, of a semiconductor device according to a twelfth embodiment of the present disclosure
  • the first embodiment is a radio frequency (hereinafter simply referred to as "RF") power amplifier module mounted with a semiconductor device equipped with a protection circuit and an internal circuit.
  • RF radio frequency
  • One example is explained.
  • the configuration of the RF power amplifier module, the layout of the semiconductor device, the configuration of the circuit blocks of the protection circuit and the internal circuit, the vertical cross-sectional structure, the planar structure, the manufacturing method, and the adjustment method of the threshold voltage of the protection circuit will be described.
  • Second Embodiment A second embodiment will explain a second example in which the configuration of the protection circuit is changed in the semiconductor device according to the first embodiment. 3.
  • Third Embodiment A third embodiment will explain a third example in which the configuration of the protection circuit is changed in the semiconductor device according to the first embodiment. 4. Fourth Embodiment A fourth embodiment will explain a fourth example in which the configuration of the protection circuit in the semiconductor device according to the first embodiment is changed. 5. Fifth Embodiment A fifth embodiment will explain a fifth example in which the semiconductor device according to the third embodiment and the semiconductor device according to the fourth embodiment are combined. 6. Sixth Embodiment A sixth embodiment will explain a sixth example in which the configuration of the protection circuit is changed in the semiconductor device according to the fourth embodiment. 7. Seventh Embodiment A seventh embodiment describes a seventh example in which the semiconductor device according to the fifth embodiment and the semiconductor device according to the sixth embodiment are combined. 8.
  • the eighth embodiment describes an eighth example in which the configuration of the protection circuit is changed in the semiconductor device according to the sixth embodiment.
  • Ninth Embodiment A ninth embodiment describes a ninth example in which the semiconductor device according to the seventh embodiment and the semiconductor device according to the eighth embodiment are combined.
  • Tenth Embodiment A tenth embodiment will explain a tenth example in which the configuration of the protection circuit is changed in the semiconductor device according to the eighth embodiment.
  • the eleventh embodiment describes an eleventh example in which the semiconductor device according to the ninth embodiment and the semiconductor device according to the tenth embodiment are combined.
  • Twelfth Embodiment A twelfth embodiment will explain a twelfth example in which the configuration of the protection circuit in the semiconductor device according to the first embodiment is changed.
  • FIG. 1 A protection circuit 22, a protection circuit 23, and a semiconductor device 2 according to the first embodiment of the present disclosure will be described with reference to FIGS. 1 to 14.
  • FIG. the arrow X direction shown as appropriate indicates one plane direction of the semiconductor device 2 placed on the plane for the sake of convenience.
  • the arrow Y direction indicates another planar direction perpendicular to the arrow X direction.
  • the arrow Z direction indicates an upward direction orthogonal to the arrow X direction and the arrow Y direction. That is, the arrow X direction, the arrow Y direction, and the arrow Z direction exactly match the X-axis direction, the Y-axis direction, and the Z-axis direction of the three-dimensional coordinate system, respectively. It should be noted that each of these directions is shown to aid understanding of the description and is not intended to limit the direction of the present technology.
  • FIG. 1 shows a plan layout of the RF power amplifier module 1 .
  • the RF power amplifier module 1 includes an input matching circuit 3 , a semiconductor device 2 , an output matching circuit 4 , and a direct current (hereinafter simply referred to as “DC”) bias circuit 5 .
  • DC direct current
  • the substrate 10 is formed as a module substrate.
  • the substrate 10 is formed in, for example, a rectangular shape when viewed from the direction of the arrow Z (hereinafter simply referred to as "plan view").
  • the input matching circuit 3 is mounted on the upper left side of the substrate 10 here.
  • An RF signal is input to the input unit matching circuit 3 from the outside of the RF power amplifier module 1 .
  • the semiconductor device 2 is mounted in the center of the substrate 10 .
  • the semiconductor device 2 includes a protection circuit 22 , an internal circuit 24 and a protection circuit 23 .
  • the protection circuit 22 is configured as an input side protection circuit.
  • the protection circuit 22 is connected to each of the input matching circuit 3 and the internal circuit 24 .
  • the internal circuit 24 has an RF power amplifier in the first embodiment.
  • the internal circuitry 24 includes an RF power amplifier operating in the millimeter wave band for fifth generation or later generation mobile terminals.
  • the protection circuit 23 is configured as an output side protection circuit.
  • the protection circuit 23 is connected to each of the internal circuit 24 and the output matching circuit 4 . Since the configuration of the protection circuit 23 is the same as that of the protection circuit 22, the description thereof will be omitted.
  • the output matching circuit 4 is mounted on the lower right side of the substrate 10 .
  • the output matching circuit 4 outputs an RF signal to the outside of the RF power amplifier module 1 .
  • the DC bias circuit 5 is mounted below the substrate 10 .
  • a DC bias circuit 5 is connected to the semiconductor device 2 .
  • DC power is supplied to the DC bias circuit 5 from the outside of the RF power amplifier module 1 .
  • a reference power supply GND is supplied to a power supply wiring (not shown) arranged on the substrate 10 .
  • the reference power supply GND is, for example, 0V.
  • the semiconductor device 2 includes an external terminal 201 as an input-side external terminal and an internal circuit 24 connected to the external terminal 201 .
  • the external terminals 201 and the internal circuit 24 are formed on the semiconductor substrate 21 .
  • the external terminal 201 is connected to the input matching circuit 3 .
  • the internal circuit 24 is here an RF power amplifier.
  • a coupling capacitor 202 is electrically connected in series between the external terminal 201 and the internal circuit 24 .
  • One end of a DC bias resistor 203 is connected between the coupling capacitor 202 and the internal circuit 24 , and the other end of the DC bias resistor 203 is connected to an external power supply terminal 208 .
  • the DC bias circuit 5 is connected to the external power supply terminal 208, and a DC negative bias power supply is supplied from the DC bias circuit 5, for example.
  • one electrode of a decoupling capacitor 207 is connected between the other end of the DC bias resistor 203 and the external power supply terminal 208 .
  • the other electrode of decoupling capacitor 207 is connected to reference
  • the semiconductor device 2 further includes a protection circuit 22 as an input side protection circuit.
  • the protection circuit 22 is provided with one MISFET221.
  • the MISFET 221 corresponds to the "first insulated gate field effect transistor" according to the present technology.
  • the MISFET 221 is provided with a charge storage section (see reference numeral 219 in FIG. 3) capable of storing hot carriers in the gate insulating film. When hot carriers are not accumulated in the charge accumulation section, the MISFET 221 is adjusted to a depletion-type threshold voltage. On the other hand, when hot carriers are accumulated in the charge accumulation portion, the MISFET 221 is adjusted to an enhancement-type threshold voltage. When operated as the protection circuit 22, the MISFET 221 is adjusted to an enhancement-type threshold voltage.
  • One first main electrode (for example, drain electrode) of the MISFET 221 is connected between the external terminal 201 and the internal circuit 24 with the DC bias resistor 203 interposed. Specifically, the first main electrode is connected between the coupling capacitor 202 and the internal circuit 24 .
  • the other second main electrode (for example, source electrode) and gate electrode of the MISFET 221 are connected to the reference power supply GND.
  • Protection circuit 22 further comprises resistor 222 .
  • the resistor 222 is electrically connected in series between the second main electrode and gate electrode of the MISFET 221 .
  • the resistor 222 corresponds to a "resistor" according to the present technology.
  • the resistor 222 is set to a resistance value of, for example, 100 ⁇ or more and 10M ⁇ or less.
  • the DC bias resistor 203 is set to have a resistance value of, for example, 10 ⁇ or more and 10M ⁇ or less, like the resistor 222 .
  • the protection circuit 22 is provided with a first external terminal 204 , a second external terminal 205 and a third external terminal 206 for injecting hot carriers into the charge storage portion of the MISFET 221 .
  • Hot carriers are hot electrons here.
  • the first external terminal 204 , the second external terminal 205 and the third external terminal 206 are arranged on the semiconductor substrate 21 .
  • a first external terminal 204 is connected to the first main electrode of the MISFET 221 .
  • the first external terminal 204 corresponds to the "first external terminal" according to the present technology.
  • a second external terminal 205 is connected to the second main electrode.
  • the second external terminal 205 corresponds to a "second external terminal” according to the present technology.
  • a third external terminal 206 is connected to the gate electrode.
  • the third external terminal 206 corresponds to a "third external terminal” according to the present technology.
  • FIG. 4 shows the planar structure of the protection circuit 22 and the internal circuit 24. As shown in FIG. The internal circuit 24 has a MISFET 241 that builds it.
  • the MISFET 221 constructing the protection circuit 22 and the MISFET 241 constructing the internal circuit 24 are formed on the semiconductor substrate 21 with the buffer layer 211 interposed therebetween.
  • a Si substrate for example, is used as the semiconductor substrate 21 .
  • the Si substrate is formed with a thickness of 600 ⁇ m or more and 700 ⁇ m or less.
  • AlGaN for example, is used for the buffer layer 211 .
  • AlGaN is formed to a thickness of 0.3 ⁇ m or more and 1.0 ⁇ m or less by using an epitaxial growth method, for example.
  • a ceramic substrate such as a sapphire substrate can be used instead of the semiconductor substrate 21 .
  • the MISFET 241 constructing the internal circuit 24 is arranged on the buffer layer 211 in a region surrounded by the element isolation portion 212 .
  • the MISFET 241 includes a semiconductor layer 213 , a two dimensional electron gas (hereinafter simply referred to as “2DEG”) 214 , a gate insulating film 215 , a gate electrode 216 and a pair of main electrodes 217 .
  • 2DEG two dimensional electron gas
  • the MISFET 241 corresponds to the "second insulated gate field effect transistor" according to the present technology.
  • the element isolation part 212 amorphizes the semiconductor layer 213 between the adjacent MISFETs 241 to eliminate the conductivity of the 2DEG 214 .
  • the element isolation part 212 is formed using, for example, an ion implantation method.
  • B ions for example, are used as ions to be implanted. More specifically, B ions are implanted under the conditions of, for example, an acceleration energy of 50 keV and a dose of about 1 ⁇ 10 15 ions/cm 2 .
  • the semiconductor layer 213 here includes a GaN layer 213A, a GaN channel layer 213B, an AlN layer 213C, and an InAlN layer 213D.
  • a GaN layer 213 A is laminated on the buffer layer 211 .
  • the GaN layer 213A is formed with a thickness of, for example, 0.8 ⁇ m or more and 1.5 ⁇ m or less.
  • a GaN channel layer 213B is laminated on the GaN layer 213A.
  • the GaN channel layer 213B is formed with a thickness of, for example, 100 nm or more and 500 nm or less.
  • the AlN layer 213C is laminated on the GaN channel layer 213B.
  • the AlN layer 213C is formed with a thickness of 0.5 nm or more and 1.5 nm or less, for example.
  • the InAlN layer 213D is stacked on the AlN layer 213C.
  • the InAlN layer 213D is formed with a thickness of, for example, 5 nm or more and 15 nm or less.
  • the 2DEG 214 is generated in the GaN channel layer 213B from one main electrode 217 to the other main electrode 217 in the vicinity of the interface between the GaN channel layer 213B and the InAlN layer 213D.
  • MISFET 214 is conductive because 2DEG 214 is constantly generated. That is, the MISFET 214 is of depletion type.
  • the MISFET 241 is configured with a high electron mobility transistor (hereinafter simply referred to as “HEMT”) structure using a compound semiconductor material.
  • HEMT high electron mobility transistor
  • the InAlN layer 213D is laminated to generate the 2DEG 214 and the spontaneous polarization of the InAlN layer 213D is used, the carrier concentration of the 2DEG 214 can be increased. Therefore, since the HEMT structure is adopted for the MISFET 241, the RF output of the internal circuit 24, that is, the RF power amplifier can be enhanced.
  • a gate insulating film 215 is formed on the semiconductor layer 213 .
  • the gate insulating film 215 here includes a first oxide film 215A and a second oxide film 215B laminated on the first oxide film 215A.
  • the oxide film is formed containing at least one selected from Al 2 O 3 , HfO 2 , Ta 2 O 5 , ZrO 2 , Y 2 O 3 and SiO 2 .
  • Al 2 O 3 is used for the first oxide film 215A.
  • the first oxide film 215A is formed with a thickness of, for example, 1 nm or more and 10 nm or less.
  • HfO 2 is used for the second oxide film 215B.
  • the second oxide film 215B is formed with a thickness of, for example, 1 nm or more and 10 nm or less.
  • a gate electrode 216 is laminated on the gate insulating film 215 .
  • the gate electrode 216 is formed of a laminated film of, for example, Ni and Au laminated on Ni.
  • Ni is formed with a thickness of, for example, 30 nm or more and 50 nm or less.
  • Au is formed with a thickness of, for example, 400 nm or more and 500 nm or less.
  • the gate length dimension of the MISFET 241 is set to, for example, 0.1 ⁇ m or more and 0.3 ⁇ m or less.
  • the gate length dimension is the length of the gate electrode 216 in the direction (arrow X direction) that matches the direction in which the pair of main electrodes 217 are arranged.
  • a pair of main electrodes 217 are stacked on the GaN channel layer 213B in contact with or on the 2DEG 214 .
  • one main electrode 217 is used as a first main electrode, eg, a drain electrode.
  • the other main electrode 217 is used as a second main electrode, for example a source electrode.
  • the main electrode 217 is formed by thermal diffusion of a laminated film containing, for example, Ti, Al laminated on Ti, Ni laminated on Al, and Au laminated on Ni.
  • the main electrode 217 is an ohmic electrode.
  • Ti is formed with a thickness of, for example, 5 nm or more and 15 nm or less.
  • Al is formed with a thickness of, for example, 50 nm or more and 150 nm or less.
  • Ni is formed with a thickness of, for example, 15 nm or more and 25 nm or less.
  • Au is formed with a thickness of, for example, 5 nm or more and 15 nm or less.
  • An insulator 218 is provided between the gate insulating film 215 and the gate electrode 216 and the main electrode 217 .
  • the insulator 218 is also provided on the element isolation portion 212 .
  • the insulator 218 is made of Al 2 O 3 , for example.
  • the MISFET 221 constructing the protection circuit 22 is arranged on the buffer layer 211 in a region surrounded by the element isolation portion 212 , similarly to the MISFET 241 .
  • the MISFET 221 includes a semiconductor layer 213 , a 2DEG 214 , a gate insulating film 215 , a charge storage section 219 , a gate electrode 216 and a pair of main electrodes 217 .
  • an InAlN layer 213E is arranged instead of the InAlN layer 213D.
  • Hot carriers can be accumulated in the charge accumulation unit 219 .
  • hot carriers are injected from the 2DEG 214 into the charge accumulation section 219 in the vicinity of the main electrode 217 serving as the drain electrode, and the injected hot carriers are accumulated in the charge accumulation section 219 .
  • a 2DEG 214 is generated in the GaN channel layer 213B in the vicinity of the interface between the GaN channel layer 213B and the InAlN layer 213E from one main electrode 217 to the other main electrode 217. . That is, the MISFET 221 is manufactured as a depletion type.
  • the MISFET 221 is adjusted to an enhancement-type threshold voltage.
  • the InAlN layer 213E of the MISFET 221 is formed thinner than the InAlN layer 213D of the MISFET 241 .
  • the InAlN layer 213E of the MISFET 221 is formed to have a thickness of 1 nm or more and 9 nm or less, and is formed to be 1/5 or more and 3/5 or less of the thickness of the InAlN layer 213D of the MISFET 241.
  • the InAlN layer 213E is formed thin, the injection efficiency of hot carriers into the charge storage section 219 can be improved.
  • the gate insulating film 215 of the MISFET 221 includes a first oxide film 215A, a second oxide film 215B laminated on the first oxide film 215A, a nitride film 215C laminated on the second oxide film 215B, and a nitride film 215C. and a third oxide film 215D laminated thereon.
  • SiN for example, is used for the nitride film 215C.
  • the nitride film 215C is formed with a thickness of, for example, 1 nm or more and 10 nm or less.
  • SiO 2 is used for the third oxide film 215D.
  • the third oxide film 215D is formed with a thickness of, for example, 1 nm or more and 10 nm or less. That is, the gate insulating film 215 employs an ONO (Oxide-Nitride-Oxide) structure in which an oxide film, a nitride film, and an oxide film are sequentially laminated.
  • ONO Oxide-Nitride-Oxide
  • a MONOS Metal-Oxide-Nitride-Oxide-Semiconductor
  • the charge storage portion 219 includes a nitride film 215C having a hot carrier trap level.
  • the charge storage portion 219 may further include an interface between the nitride film 215C and the second oxide film 215B.
  • the gate length dimension of the MISFET 221 is set to, for example, 0.05 ⁇ m or more and 0.3 ⁇ m or less. Also, the gate width dimension of the MISFET 221 is set to, for example, 10 ⁇ m or more and 10000 ⁇ m or less. Here, the gate width dimension is the length of the gate electrode 216 in the gate width direction (arrow Y direction) perpendicular to the gate length direction.
  • first external terminal 204 Configuration of first external terminal 204, second external terminal 205 and third external terminal 206 As shown in FIG. and the wiring of the same layer disposed on the MISFET 221 .
  • the first external terminals 204 , the second external terminals 205 and the third external terminals 206 are arranged in a line in the arrow Y direction on the surface of the semiconductor substrate 21 .
  • These first external terminals 204 and the like are formed in the same layer as the external terminals 201 (not shown) shown in FIG.
  • the first external terminal 204 is integrally connected to wiring (not numbered) connected to the main electrode (first main electrode) 217 of the MISFET 221 of the protection circuit 22, the DC bias resistor 203, and the external power supply terminal 208 (see FIG. 2). formed.
  • the second external terminal 205 is formed integrally with wiring (not labeled) connected to the resistor 222 and the main electrode (second main electrode) 217 of the MISFET 221 .
  • the third external terminal 206 is formed integrally with wiring (not labeled) connected to the resistor 222 and the gate electrode 216 of the MISFET 221 .
  • the MISFET 221 and the MISFET 241 are arranged with their gate length directions aligned with the arrow X direction in plan view.
  • the MISFET 221 and the MISFET 241 may be arranged without matching the gate length directions.
  • the resistor 222 and the DC bias resistor 203 are made of Ta cermet resistors, for example.
  • a semiconductor substrate 21 is prepared (see FIG. 5).
  • a buffer layer 211 is formed on the semiconductor substrate 21 (see FIG. 5).
  • a semiconductor layer 213 is formed on the entire surface of the buffer layer 211 .
  • the semiconductor layer 213 is formed by laminating a GaN layer 213A, a GaN channel layer 213B, an AlN layer 213C, and an InAlN layer 213D in sequence. Once the semiconductor layer 213 is formed, a 2DEG 214 is created.
  • An insulator 218 is formed on the entire surface of the semiconductor layer 213 (see FIG. 6).
  • a pair of main electrodes 217 are formed in respective formation regions of the MISFET 241 and the MISFET 221 .
  • the main electrode 217 is formed by forming an opening in the insulator 218 through which the surface of the semiconductor layer 213 is exposed, and filling the opening with an electrode material.
  • the electrode material is deposited using, for example, a vacuum deposition method. Further, the film-formed electrode material is subjected to heat treatment at a temperature of 500° C. or more and 700° C. or less by, for example, a thermal diffusion method. This allows the main electrode 217 to have ohmic characteristics.
  • element isolation portions 212 are formed in the semiconductor layer 213 between the MISFETs 221 and 241 and between the MISFETs 241 .
  • the element isolation portion 212 is formed by implanting ions into the semiconductor layer 213 using the ion implantation method, as described above.
  • An opening 218A is formed in the insulator 218 in the formation region of the gate insulating film 215 of the MISFET 221 (see FIG. 8).
  • the opening 218A is formed using photolithography technology and etching technology, for example.
  • a portion in the thickness direction of the InAlN layer 213D of the semiconductor layer 213 exposed from the opening 218A is etched.
  • an InAlN layer 213E having a thickness smaller than that of the InAlN layer 213D is formed.
  • Opening 218A is filled with insulator 218, as shown in FIG.
  • An opening 218B is formed in the insulator 218 in the formation region of the gate insulation film 215 of the MISFET 221 and the formation region of the gate insulation film 215 of the MISFET 241 (see FIG. 10).
  • the opening 218B is formed using photolithographic technology and etching technology.
  • a gate insulating film 215 is formed on the InAlN layer 213E in the formation region of the MISFET 221 within the opening 218B. Furthermore, the gate insulating film 215 is formed on the InAlN layer 213D in the formation region of the MISFET 241 within the opening 218B by the same manufacturing process.
  • the gate insulating film 215 is formed by sequentially stacking a first oxide film 215A, a second oxide film 215B, a nitride film 215C, and a third oxide film 215D.
  • the gate insulating film 215 is formed using, for example, an atomic layer deposition method.
  • the MISFET 221 since the gate insulating film 215 has an ONO structure, a charge storage portion 219 is formed. Also, at this time point, hot carriers are not accumulated in the charge accumulation unit 219, so the MISFET 221 is formed to have a depletion-type threshold voltage.
  • the third oxide film 215D and the nitride film 215C of the gate insulating film 215 are selectively removed in the MISFET 241 formation region. Photolithographic technology and etching technology are used for this removal. In other words, the charge storage section 219 is not formed in the MISFET 241 .
  • the MISFET 241 is formed to have a depletion type threshold voltage.
  • a gate electrode 216 is formed on the gate insulating film 215 in each of the MISFET 221 formation region and the MISFET 241 formation region.
  • the gate electrode 216 is formed, each of the MISFETs 221 and 241 is completed.
  • a resistor 222 and a DC bias resistor 203 are formed on the MISFET 221 and MISFET 241, and the external terminal 201, the first external terminal 204 to the third external terminal 206, and wiring are further formed on the upper layer (see FIGS. 2 and 4). After completing these series of steps, the semiconductor device 2 including the protection circuit 22 and the internal circuit 24 is completed.
  • FIG. 13 represents a flow chart describing the charge accumulation method.
  • FIG. 14 represents a timing chart showing the relationship between the injection voltage and the injection time for explaining the charge accumulation method.
  • the horizontal axis is time [ms] and the vertical axis is voltage [V].
  • a second power supply is supplied from the second external terminal 205 to the main electrode 217 of the MISFET 221 .
  • This main electrode 217 is the second main electrode and corresponds to the source electrode.
  • the second power supply is the source power supply.
  • a third power supply is supplied from the third external terminal 206 to the gate electrode 216 of the MISFET 221 .
  • the third power supply is the gate power supply.
  • Vdsw is the voltage between the drain electrode and the source electrode
  • BVpth is the punch through voltage
  • Vt is the threshold voltage
  • Vgsw is the voltage between the gate electrode and the source electrode
  • BVg is the gate breakdown voltage
  • BVj is the junction breakdown voltage.
  • hot carriers are injected while satisfying the conditions of the following formulas ⁇ 1> to ⁇ 3>.
  • BVpth ⁇ BVj is calculated as the following formula ⁇ 4>. 3.25[V] ⁇ 5.5[V] ⁇ 6.0[V] ⁇ 6.5[V] ⁇ 15[V]... ⁇ 4>
  • step S1 based on the above formula ⁇ 4>, for example, 3.25 [V] is supplied to the first external terminal 204, 0 [V] is supplied to the second external terminal 205, and 0 [V] is supplied to the third external terminal 206. 6.5 [V] is supplied (see FIG. 14).
  • the power supply is performed 50 times with a pulse width of 1 [ms], for example.
  • the hot carrier injection time is set to, for example, 100 [ms] in consideration of reproducibility.
  • Voltage conditions such as the voltage Vdsw between the drain electrode and the source electrode are, for example, as follows.
  • Vdsw 1 [V] to 5 [V]
  • BVpth 3.5 [V] to 7.5 [V]
  • Vt (after hot carrier injection): 4 [V] to 8 [V]
  • Vgsw 4.5 [V] to 8.5 [V]
  • BVg 13 [V] to 17 [V]
  • BVj 8 [V] to 12 [V]
  • step S2 the threshold voltage Vt of the MISFET 221 is measured (step S2). Based on the measurement result, it is determined whether or not the threshold voltage Vt is equal to or higher than the predetermined value (here, 6.0 [V]) set in the above formula ⁇ 1> (step S3).
  • the threshold voltage Vt is equal to or higher than a predetermined value
  • injection of hot carriers ends.
  • the threshold voltage Vt is less than the predetermined value in step S3
  • the number of times of power supply is added (step S4).
  • the number of times of additional power supply is n, and n is set to 10 times, for example. In accordance with this added number of times of power supply, the process returns to step S1 to continue injection of hot carriers.
  • the MISFET 221 is formed to have a threshold voltage Vt from the depletion type to the enhancement type.
  • an external DC bias circuit 5 is connected to an external power supply terminal 208 of semiconductor device 2 .
  • a “positive” surge current Iesd flows from the DC bias circuit 5 through the external power supply terminal 208 to the semiconductor device 2 .
  • a surge current Iesd flows through DC bias resistor 203 and main electrode 217 which is used as the drain electrode of MISFET 221 .
  • the surge voltage is equal to or higher than the protection voltage Vesd, the resistance of the drain electrode side of the MISFET 221 is low. Therefore, the surge current Iesd flows through the drain electrode and source electrode of the MISFET 221 to the reference power supply GND.
  • the pair of main electrodes 217 of the MISFET 221 is adjusted to a constant punch-through voltage BVpth by adjusting the gate length dimension. Therefore, the surge voltage is reduced to the protection voltage Vesd, and the ESD protection function is obtained.
  • the protection circuit 22 includes a MISFET 221, as shown in FIGS.
  • the MISFET 221 has a main electrode (first main electrode) 217 connected between the external terminal 201 and the internal circuit 24, and has a main electrode (second main electrode) 217 connected to the reference power supply GND.
  • a charge accumulating portion 219 capable of accumulating hot carriers is provided in the gate insulating film 215 .
  • the MISFET 221 is formed as a depletion type and can be formed to have an enhancement type threshold voltage by accumulating hot carriers in the charge storage section 219 . Therefore, the protection circuit 22 excellent in ESD resistance or avalanche resistance can be constructed by using the MISFET 221 with high process affinity without using a pn junction.
  • the MISFET 211 does not use a pn junction or a Schottky junction. Therefore, it is possible to realize the protection circuit 22 that is free from surge damage at the junction.
  • the protection circuit 22 is electrically connected in series between the gate electrode 216 of the MISFET 22 and the main electrode (second main electrode) 217 used as the source electrode.
  • a resistor 222 is provided. Therefore, it is not necessary to separate the main electrodes 217 when injecting hot carriers into the charge storage section 219 .
  • the protection circuit 22 can be operated immediately after injection of hot carriers into the charge storage section 219 .
  • the gate potential of the MISFET 221 does not immediately rise due to the CR delay operation, and punch-through occurs between the pair of main electrodes 217 during this period. Therefore, the MISFET 221 alone can protect against positive and negative surges without destroying the gate insulating film 215 .
  • the protection circuit 22 also includes a first external terminal 204, a second external terminal 205 and a third external terminal 206, as shown in FIGS.
  • the first external terminal 204 is connected between the external terminal 201 and a main electrode (first main electrode) 217 of the MISFET 221, and is supplied with a first power source for generating hot carriers.
  • the second external terminal 205 is connected to the main electrode (second main electrode) 217 of the MISFET 221, and is supplied with a second power source for generating hot carriers.
  • the third external terminal 206 is connected to the gate electrode 216 of the MISFET 221, and is supplied with a third power source that generates hot carriers.
  • the first external terminal 204 , the second external terminal 205 and the third external terminal 206 are dedicated external terminals for injecting hot carriers into the MISFET 221 . Therefore, immediately after the protection circuit 22 is manufactured or thereafter, hot carriers can be injected into the charge storage section 219 as necessary to start the protection function of the protection circuit 22 .
  • the semiconductor device 2 includes an external terminal 201, an internal circuit 24, and a protection circuit 22, as shown in FIGS.
  • the protection circuit 22 is arranged on the semiconductor substrate 21 and includes a MISFET 221 .
  • a main electrode (first main electrode) 217 is connected between the external terminal 201 and the internal circuit 24, a main electrode (second main electrode) 217 and a gate electrode 216 are connected to the reference power supply GND, and hot carrier A charge storage unit 219 capable of storing is provided. Therefore, it is possible to obtain the same effects as those obtained by the protection circuit 22 described above.
  • the MISFET 221 of the protection circuit 22 can be easily constructed with substantially the same structure as the MISFET 241 constructing the internal circuit 24 or with substantially the same manufacturing process.
  • the MISFET 221 of the protection circuit 22 further includes a resistor 222 electrically connected in series between the gate electrode 216 and the main electrode (second main electrode) 217 . Therefore, according to the semiconductor device 2, it is possible to obtain the same effects as those obtained by the protection circuit 22 described above.
  • the semiconductor device 2 also includes a first external terminal 204, a second external terminal 205, and a third external terminal 206, as shown in FIGS. Therefore, according to the semiconductor device 2, it is possible to obtain the same effects as those obtained by the protection circuit 22 described above.
  • the charge storage section 219 of the MISFET 221 of the protection circuit 22 is configured by sequentially stacking an oxide film, a nitride film, and an oxide film. More specifically, the charge storage section 219 has an ONO structure in which a first oxide film 215A, a second oxide film 215B, a nitride film 215C, and a third oxide film 215D are sequentially laminated.
  • the nitride film contains SiN.
  • the oxide film contains at least one selected from Al 2 O 3 , HfO 2 , Ta 2 O 5 , ZrO 2 , Y 2 O 3 and SiO 2 .
  • the charge storage unit 219 includes Al 2 O 3 , HfO 2 laminated on Al 2 O 3 , SiN laminated on HfO 2 , and SiO 2 laminated on SiN. . Therefore, by adopting the ONO structure for the gate insulating film 215, the charge storage section 219 can be easily constructed.
  • the MISFET 221 is made of a compound semiconductor.
  • the compound semiconductor includes GaN or GaAs.
  • MISFET 221 contains InAlN. Therefore, the protection circuit 22 can be constructed with the MISFET 221 having the HEMT structure. In particular, the protection circuit 22 can be easily constructed with substantially the same structure as the MISFET 241 that constructs the internal circuit 24 .
  • the MISFET 221 of the protection circuit 22 stores hot carriers in the charge storage section 219, and shifts the threshold voltage from the depletion type to the positive direction to form the enhancement type. Therefore, since the MISFET 221 of the protection circuit 22 is formed by substantially the same structure or manufacturing process as the MISFET 241 of the internal circuit 24, the protection circuit 22 can be constructed easily.
  • the gate length of the MISFET 221 of the protection circuit 22 shown in FIGS. 3 and 4 is formed to be 0.05 ⁇ m or more and 0.3 ⁇ m or less.
  • the gate width of the MISFET 221 is formed to be 10 ⁇ m or more and 10000 ⁇ m or less.
  • the resistance 222 of the protection circuit 22 is formed at 100 ⁇ or more and 10M ⁇ or less. Therefore, when a surge is input, the MISFET 221 can appropriately generate punch-through.
  • the internal circuit 24 includes an RF power amplifier including a MISFET 241 formed in a depletion type. Therefore, the protection circuit 22 can be easily manufactured by using the structure and manufacturing process of the depression type MISFET 241 .
  • the thickness of the InAlN 213E of the MISFET 221 of the protection circuit 22 is thinner than the thickness of the InAlN 213D of the MISFET 241 of the internal circuit 24, as shown in FIG. Therefore, the injection efficiency of hot carriers into the charge storage section 219 of the MISFET 221 can be improved.
  • Second Embodiment> A protection circuit 22 and a semiconductor device 2 according to a second embodiment of the present disclosure will be described. In the second embodiment and subsequent embodiments, the same or substantially the same components as those of the protection circuit 22 and the semiconductor device 2 according to the first embodiment , and duplicate descriptions are omitted.
  • FIG. 15 shows vertical cross-sectional structures of the protection circuit 22 and the internal circuit 24 .
  • the MISFET 221 of the protection circuit 22 has the InAlN layer 213E thinner than the InAlN layer 213D in a part of the InAlN layer 213D of the semiconductor layer 213. are doing. More specifically, the InAlN layer 213E is arranged in the gate length direction near the main electrode (first main electrode) 217 used as the drain electrode. Hot carriers injected into the charge storage section 219 are generated in the vicinity of the drain electrode where the electric field strength increases.
  • the protection circuit 22 and the semiconductor device 2 according to the second embodiment it is possible to obtain the same effects as those obtained by the protection circuit 22 and the semiconductor device 2 according to the first embodiment. Furthermore, as shown in FIG. 15, in the protection circuit 22 and the semiconductor device 2, in the semiconductor layer 213 of the MISFET 221, a thin InAlN layer 213E is provided as part of the InAlN layer 213D. Therefore, the MISFET 221 including the charge storage section 219 can be constructed with minimal processing.
  • a protection circuit 22 and a semiconductor device 2 according to a third embodiment of the present disclosure will be described.
  • the third embodiment is a modification of the protection circuit 22 and the internal circuit 24 according to the first embodiment.
  • FIG. 16 shows a circuit block configuration of a protection circuit 22 and an internal circuit 24 as an input-side protection circuit of the semiconductor device 2.
  • the main electrode (first main electrode) of the MISFET 221 is connected between the external terminal 201 and the coupling capacitor 202 with the surge induction resistor 223 interposed. It is One end of the DC bias resistor 203 is connected between the coupling capacitor 202 and the internal circuit 24 , and the other end of the DC bias resistor 203 is connected to the decoupling capacitor 207 and the DC bias circuit 25 .
  • the DC bias circuit 25 is built in the semiconductor device 2 instead of the external DC bias circuit 5 .
  • the surge current Iesd flows through the surge induction resistor 223 and the pair of main electrodes of the MISFET 221 of the protection circuit 22 to the reference power supply GND side. flow.
  • a constant punch-through voltage BVpth is applied between the pair of main electrodes of the MISFET 221 by adjusting the gate length dimension. Therefore, the surge voltage is reduced to the protection voltage Vesd, and the ESD protection function is obtained.
  • the surge current Iesd flows from the reference power supply GND side to the external terminal 201 through the pair of main electrodes of the MISFET 221 and the surge induction resistor 223 .
  • a resistor 222 is arranged between the gate electrode of the MISFET 221 and the main electrode used as the source electrode. Therefore, the gate potential of the gate electrode increases while the gate capacitance of the gate electrode is charged through the resistor 222 .
  • a constant punch-through voltage BVpth is applied between the pair of main electrodes of the MISFET 221 by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd. In other words, since the gate potential does not rise above the protective voltage Vesd, it is possible to effectively suppress or prevent breakdown of the gate insulating film. Therefore, an ESD protection function is obtained.
  • the protection circuit 22 and the semiconductor device 2 according to the third embodiment it is possible to obtain the same effects as those obtained by the protection circuit 22 and the semiconductor device 2 according to the first embodiment. Furthermore, in the protection circuit 22 and the semiconductor device 2, the single MISFET 221 can protect against positive and negative surges.
  • a protection circuit 22 and a semiconductor device 2 according to a fourth embodiment of the present disclosure will be described.
  • the fourth embodiment is a modification of the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
  • FIG. 17 shows a circuit block configuration of a protection circuit 22 and an internal circuit 24 as an input-side protection circuit of the semiconductor device 2. As shown in FIG. In the protection circuit 22 and the semiconductor device 2 according to the fourth embodiment, the protection circuit 22 is connected between the coupling capacitor 202 and the internal circuit 24 with the DC bias resistor 203 interposed.
  • the protection circuit 22 includes two MISFETs 221A and 221B electrically connected in series that share a main electrode (here, a second main electrode) used as a drain electrode.
  • the second main electrodes of the MISFET 221A and MISFET 221B are connected to the first external terminal 204.
  • FIG. A main electrode (here, the first main electrode) used as the source electrode of the MISFET 221B is connected to the DC bias resistor 203 .
  • a resistor 222A is electrically connected in series between the first main electrode and the gate electrode of the MISFET 221A.
  • a first main electrode of the MISFET 221A is connected to the second external terminal 205A and the reference power supply GND.
  • the gate electrode is connected to the third external terminal 206A.
  • a resistor 222B is electrically connected in series between the first main electrode and gate electrode of the MISFET 221B.
  • a first main electrode of the MISFET 221B is connected to the second external terminal 205B.
  • the gate electrode is connected to the third external terminal 206B. That is, the MISFET 221A and the MISFET 221B are arranged symmetrically with the second main electrode as a boundary.
  • An external DC bias circuit 5 is connected to the external power supply terminal 208 .
  • hot carriers are injected into the charge storage section 219 in the order of the MISFET 221A and the MISFET 221B, or in the reverse order, or both at the same time.
  • the second main electrodes of MISFET 221A and MISFET 221B are shared.
  • a first main electrode of the MISFET 221B is connected to the external power supply terminal 208 .
  • a first main electrode of the MISFET 221A is connected to the reference power supply GND.
  • the protection voltage Vesd of the protection circuit 22 according to the fourth embodiment is approximately double that of the protection circuit 22 according to the first embodiment.
  • the MISFET 221A and the MISFET 221B are arranged symmetrically, so the protection response characteristics are substantially the same.
  • an external DC bias circuit 5 is connected to an external power supply terminal 208 of the semiconductor device 2 .
  • a “positive” surge current Iesd flows from the DC bias circuit 5 through the external power supply terminal 208 to the semiconductor device 2 .
  • the surge current Iesd flows through the MISFET 221B and MISFET 221A of the protection circuit 22 to the reference power supply GND.
  • a resistor 222A is arranged between the gate electrode of the MISFET 221A and the first main electrode used as the source electrode.
  • a resistor 222B is arranged between the gate electrode of the MISFET 221B and the main electrode used as the source electrode. Therefore, the surge current flowing from the source electrode side increases the gate potential of the gate electrode while charging the gate capacitance of the gate electrode through the resistor 222A or the resistor 222B.
  • a constant punch-through voltage BVpth is obtained between the pair of main electrodes of the MISFET 221A and the MISFET 221B by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd.
  • the gate potential does not rise above the protective voltage Vesd, it is possible to effectively suppress or prevent breakdown of the gate insulating film. Therefore, an ESD protection function is obtained.
  • the protection circuit 22 and the semiconductor device 2 according to the fourth embodiment it is possible to obtain the same effects as those obtained by the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
  • the protection circuit 22 since the protection circuit 22 has the MISFET 221A and the MISFET 221B arranged symmetrically, it can cope with positive and negative surge voltages.
  • the protection voltage Vesd is approximately double that of the protection circuit 22 according to the first embodiment, variations in the polarity of the punch-through voltage BVpth are suppressed, and the transient response characteristics are the same for positive and negative surge voltages.
  • the protection voltage Vesd since the protection voltage Vesd is approximately double that of a single device, the withstand voltage of the RF signal is doubled, and the RF output can be increased.
  • a protection circuit 22 and a semiconductor device 2 according to a fifth embodiment of the present disclosure will be described.
  • the fifth embodiment is a modification obtained by combining the third embodiment and the fourth embodiment.
  • FIG. 18 shows circuit block configurations of a protection circuit 22 and an internal circuit 24 as an input side protection circuit of the semiconductor device 2 .
  • the protection circuit 22 is connected between the external terminal 201 and the coupling capacitor 202 with the surge induction resistor 223 interposed.
  • the protection circuit 22 is composed of MISFETs 221A and 221B arranged symmetrically, like the protection circuit 22 according to the fourth embodiment.
  • One end of the DC bias resistor 203 is connected between the coupling capacitor 202 and the internal circuit 24 , and the other end of the DC bias resistor 203 is connected to the decoupling capacitor 207 and the DC bias circuit 25 .
  • the DC bias circuit 25 is built in the semiconductor device 2 instead of the external DC bias circuit 5 .
  • the second main electrodes of MISFET 221A and MISFET 221B are shared.
  • a first main electrode of MISFET 221B is connected to external terminal 201 through surge induction resistor 223 .
  • a first main electrode of the MISFET 221A is connected to the reference power supply GND.
  • the protection voltage Vesd of the protection circuit 22 according to the fifth embodiment is approximately double that of the protection circuit 22 according to the first embodiment.
  • the MISFET 221A and the MISFET 221B are arranged symmetrically, so the protection response characteristics are substantially the same.
  • the surge current Iesd flows through the surge induction resistance 223, the MISFETs 221B and 221A of the protection circuit 22 to the reference power supply GND side.
  • a constant punch-through voltage BVpth is obtained between the pair of main electrodes of the MISFET 221A and the MISFET 221B by adjusting the gate length dimension. Therefore, the surge voltage is reduced to the protection voltage Vesd, and the ESD protection function is obtained.
  • the surge current Iesd flows from the reference power supply GND side to the external terminal 201 through the MISFET 221A, MISFET 221B and surge induction resistor 223.
  • a resistor 222A is arranged between the gate electrode of the MISFET 221A and the main electrode used as the source electrode.
  • a resistor 222B is arranged between the gate electrode of the MISFET 221B and the main electrode used as the source electrode. Therefore, the surge current flowing from the source electrode side increases the gate potential of the gate electrode while charging the gate capacitance of the gate electrode through the resistor 222A or the resistor 222B.
  • a constant punch-through voltage BVpth is obtained between the pair of main electrodes of the MISFET 221A and the MISFET 221B by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd.
  • the gate potential does not rise above the protective voltage Vesd, it is possible to effectively suppress or prevent breakdown of the gate insulating film. Therefore, an ESD protection function is obtained.
  • Sixth Embodiment> A protection circuit 22 and a semiconductor device 2 according to a sixth embodiment of the present disclosure will be described.
  • the sixth embodiment is a modification of the protection circuit 22 and the semiconductor device 2 according to the fourth embodiment.
  • FIG. 19 shows circuit block configurations of a protection circuit 22 and an internal circuit 24 as an input-side protection circuit of the semiconductor device 2 .
  • the protection circuit 22 includes two electrically connected in series sharing a main electrode (here, the second main electrode) used as a source electrode. It has MISFETs 221A and MISFETs 221B. The second main electrodes of the MISFET 221A and MISFET 221B are connected to the second external terminal 205.
  • FIG. A main electrode (here, a first main electrode) used as a drain electrode of the MISFET 221B is connected to the DC bias resistor 203 .
  • a common resistor 222 is electrically connected in series between the second main electrode and the gate electrode of the MISFET 221A and between the MISFET 221B and the second main electrode.
  • a first main electrode of the MISFET 221A is connected to the first external terminal 204A and the reference power supply GND.
  • a gate electrode is connected to a third external terminal 206 common to the gate electrode of the MISFET 221B.
  • the first main electrode of MISFET 221B is connected to first external terminal 204B.
  • the MISFET 221A and the MISFET 221B are arranged symmetrically with the second main electrode as a boundary.
  • An external DC bias circuit 5 is connected to the external power supply terminal 208 .
  • the second main electrodes of MISFET 221A and MISFET 221B are shared.
  • a first main electrode of the MISFET 221B is connected to the external power supply terminal 208 .
  • a first main electrode of the MISFET 221A is connected to the reference power supply GND. Therefore, the protection voltage Vesd of the protection circuit 22 according to the sixth embodiment is approximately double that of the protection circuit 22 according to the first embodiment. Also, in the protection circuit 22 according to the first embodiment, there is a slight difference in the response characteristics to the protection of the "positive" surge and the "negative" surge. On the other hand, in the protection circuit 22 according to the sixth embodiment, the MISFET 221A and the MISFET 221B are arranged symmetrically, so the protection response characteristics are substantially the same.
  • an external DC bias circuit 5 is connected to an external power supply terminal 208 of the semiconductor device 2 .
  • a “positive” surge current Iesd flows from the DC bias circuit 5 through the external power supply terminal 208 to the semiconductor device 2 .
  • the surge current Iesd flows through the MISFET 221B and MISFET 221A of the protection circuit 22 to the reference power supply GND.
  • a resistor 222 is arranged between the gate electrode of the MISFET 221A and the MISFET 221B and the second main electrode used as the source electrode. Therefore, the surge current flowing from the source electrode side increases the gate potential of the gate electrode while charging the gate capacitance of the gate electrode through the resistor 222 .
  • a constant punch-through voltage BVpth is obtained between the pair of main electrodes of the MISFET 221A and the MISFET 221B by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd.
  • the gate potential does not rise above the protective voltage Vesd, it is possible to effectively suppress or prevent breakdown of the gate insulating film. Therefore, an ESD protection function is obtained.
  • Seventh Embodiment> A protection circuit 22 and a semiconductor device 2 according to a seventh embodiment of the present disclosure will be described.
  • the seventh embodiment is an example in which the protection circuit 22 and the semiconductor device 2 according to the fifth embodiment and the protection circuit 22 and the semiconductor device 2 according to the sixth embodiment are combined.
  • FIG. 20 shows circuit block configurations of a protection circuit 22 and an internal circuit 24 as an input-side protection circuit of the semiconductor device 2 .
  • the protection circuit 22 is connected between the external terminal 201 and the coupling capacitor 202 with the surge induction resistor 223 interposed.
  • the protection circuit 22 is composed of MISFETs 221A and 221B arranged symmetrically, like the protection circuit 22 according to the sixth embodiment.
  • One end of the DC bias resistor 203 is connected between the coupling capacitor 202 and the internal circuit 24 , and the other end of the DC bias resistor 203 is connected to the decoupling capacitor 207 and the DC bias circuit 25 .
  • the DC bias circuit 25 is built in the semiconductor device 2 instead of the external DC bias circuit 5 .
  • the second main electrodes of MISFET 221A and MISFET 221B are shared.
  • a first main electrode of MISFET 221B is connected to external terminal 201 through surge induction resistor 223 .
  • a first main electrode of the MISFET 221A is connected to the reference power supply GND. Therefore, the protection voltage Vesd of the protection circuit 22 according to the seventh embodiment is approximately double that of the protection circuit 22 according to the first embodiment. Also, in the protection circuit 22 according to the first embodiment, there is a slight difference in the response characteristics for protection of "positive" surges and "negative" surges. On the other hand, in the protection circuit 22 according to the seventh embodiment, the MISFET 221A and the MISFET 221B are arranged symmetrically, so the protection response characteristics are substantially the same.
  • the surge current Iesd flows through the surge induction resistance 223, the MISFETs 221B and 221A of the protection circuit 22 to the reference power supply GND side.
  • a constant punch-through voltage BVpth is obtained between the pair of main electrodes of the MISFET 221A and the MISFET 221B by adjusting the gate length dimension. Therefore, the surge voltage is reduced to the protection voltage Vesd, and the ESD protection function is obtained.
  • the surge current Iesd flows from the reference power supply GND side to the external terminal 201 through the MISFET 221A, MISFET 221B and surge induction resistor 223.
  • a resistor 222 is arranged between the gate electrode of the MISFET 221A and the MISFET 221B and the main electrode used as the source electrode. Therefore, the surge current flowing from the source electrode side increases the gate potential of the gate electrode while charging the gate capacitance of the gate electrode through the resistor 222 . At this time, a constant punch-through voltage BVpth is obtained between the pair of main electrodes of the MISFET 221A and the MISFET 221B by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd. In other words, since the gate potential does not rise above the protective voltage Vesd, it is possible to effectively suppress or prevent breakdown of the gate insulating film. Therefore, an ESD protection function is obtained.
  • Eighth Embodiment> A protection circuit 22 and a semiconductor device 2 according to an eighth embodiment of the present disclosure will be described.
  • the eighth embodiment is a modification of the protection circuit 22 and the semiconductor device 2 according to the sixth embodiment.
  • FIG. 21 shows circuit block configurations of a protection circuit 22 and an internal circuit 24 as an input-side protection circuit of the semiconductor device 2 .
  • the protection circuit 22 is connected between the coupling capacitor 202 and the internal circuit 24 with the DC bias resistor 203 interposed.
  • the protection circuit 22 includes two MISFETs 221A and 221B electrically connected in parallel.
  • the first main electrode used as the drain region of the MISFET 221A is connected to the first external terminal 204A and also to the DC bias resistor 203 via the current relaxation resistor 224A.
  • the second main electrode used as the source electrode is connected to the second external terminal 205A and to the reference power supply GND via the current relaxation resistor 224B.
  • the gate electrode is connected to the third external terminal 206A.
  • a resistor 222A is electrically connected in series between the second main electrode and the gate electrode.
  • Each of the current relaxation resistors 224A and 224B relaxes current flow during injection of hot carriers.
  • a first main electrode used as a drain region of the MISFET 221B is connected to the first external terminal 204B and also connected to the reference power supply GND via a current relaxation resistor 224C.
  • a second main electrode used as a source electrode is connected to the second external terminal 205B and to the DC bias resistor 203 via a current relaxation resistor 224D.
  • the gate electrode is connected to the third external terminal 206B.
  • a resistor 222B is electrically connected in series between the second main electrode and the gate electrode.
  • Each of the current relaxation resistors 224C and 224D relaxes current flow during injection of hot carriers.
  • the MISFET 221A and the MISFET 221B are configured such that the polarities of the first main electrode and the second main electrode are opposite to each other.
  • An external DC bias circuit 5 is connected to the external power supply terminal 208 .
  • the protection voltage Vesd of the protection circuit 22 is equivalent to the protection voltage Vesd of the protection circuit 22 according to the first embodiment.
  • the protection circuit 22 according to the first embodiment there is a slight difference in the response characteristics for protection of "positive" surges and "negative” surges.
  • the polarities of the MISFET 221A and the MISFET 221B are opposite to each other, so the protection response characteristics are substantially the same.
  • an external DC bias circuit 5 is connected to an external power supply terminal 208 of the semiconductor device 2 .
  • a “positive” surge current Iesd flows from the DC bias circuit 5 through the external power supply terminal 208 to the semiconductor device 2 .
  • the surge current Iesd flows through the MISFET 221A of the protection circuit 22 to the reference power supply GND.
  • a resistor 222A is arranged between the gate electrode of the MISFET 221A and the second main electrode.
  • a resistor 222B is arranged between the gate electrode of the MISFET 221B and the second main electrode. Therefore, the surge current flowing from the source electrode side increases the gate potential of the gate electrode while charging the gate capacitance of the gate electrode through the resistor 222A or the resistor 222B.
  • a constant punch-through voltage BVpth is obtained between the pair of main electrodes of the MISFET 221A and the MISFET 221B by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd.
  • the gate potential does not rise above the protective voltage Vesd, it is possible to effectively suppress or prevent breakdown of the gate insulating film. Therefore, an ESD protection function is obtained.
  • the protection circuit 22 and the semiconductor device 2 according to the eighth embodiment it is possible to obtain the same effects as those obtained by the protection circuit 22 and the semiconductor device 2 according to the first embodiment. Furthermore, since the protection circuit 22 includes the MISFET 221A and the MISFET 221B arranged with opposite polarities, it is possible to effectively suppress variations in surge polarities. Also, the transient response characteristics can be made equal to positive and negative surges.
  • a protection circuit 22 and a semiconductor device 2 according to a ninth embodiment of the present disclosure will be described.
  • the ninth embodiment is an example in which the protection circuit 22 and the semiconductor device 2 according to the seventh embodiment and the protection circuit 22 and the semiconductor device 2 according to the eighth embodiment are combined.
  • FIG. 22 shows a circuit block configuration of a protection circuit 22 and an internal circuit 24 as an input-side protection circuit of the semiconductor device 2. As shown in FIG. In the protection circuit 22 and the semiconductor device 2 according to the ninth embodiment, the protection circuit 22 is connected between the external terminal 201 and the coupling capacitor 202 with the surge induction resistor 223 interposed.
  • the protection circuit 22 includes two MISFETs 221A and 221B electrically connected in parallel, like the protection circuit 22 according to the eighth embodiment.
  • the configuration and circuit operation other than the above are substantially the same as the configuration and circuit operation of the protection circuit 22 according to the seventh embodiment and the protection circuit 22 according to the eighth embodiment, so descriptions thereof are omitted here. do.
  • Tenth Embodiment> A protection circuit 22 and a semiconductor device 2 according to the tenth embodiment of the present disclosure will be described.
  • the tenth embodiment is a modification of the protection circuit 22 and the semiconductor device 2 according to the eighth embodiment.
  • FIG. 23 shows a circuit block configuration of a protection circuit 22 and an internal circuit 24 as an input-side protection circuit of the semiconductor device 2. As shown in FIG. In the protection circuit 22 and the semiconductor device 2 according to the tenth embodiment, the protection circuit 22 is connected between the coupling capacitor 202 and the internal circuit 24 with the DC bias resistor 203 interposed.
  • the protection circuit 22 includes two MISFETs 221A and 221B electrically connected in parallel.
  • a first main electrode used as a drain region of the MISFET 221A is connected to the first external terminal 204A and to the DC bias resistor 203.
  • a second main electrode used as a source electrode is connected to the first external terminal 204B and to the reference power supply GND.
  • the gate electrode is connected to the third external terminal 206A.
  • a resistor 222A is electrically connected in series between the second main electrode and the gate electrode.
  • a first main electrode used as a drain region of the MISFET 221B is connected to the first external terminal 204B and to the reference power supply GND.
  • the first external terminal 204B is also connected to the second main electrode of the MISFET 221A.
  • a second main electrode used as a source electrode is connected to the first external terminal 204A and to the DC bias resistor 203 .
  • the first external terminal 204A is also connected to the first main electrode of the MISFET 221A.
  • the gate electrode is connected to the third external terminal 206B.
  • a resistor 222B is electrically connected in series between the second main electrode and the gate electrode.
  • the MISFET 221A and the MISFET 221B are configured such that the polarities of the first main electrode and the second main electrode are opposite to each other.
  • An external DC bias circuit 5 is connected to the external power supply terminal 208 .
  • the protection voltage Vesd of the protection circuit 22 is equivalent to the protection voltage Vesd of the protection circuit 22 according to the first embodiment.
  • the protection circuit 22 according to the first embodiment there is a slight difference in the response characteristics for protection of "positive" surges and "negative” surges.
  • the protection circuit 22 according to the tenth embodiment since the polarities of the MISFET 221A and the MISFET 221B are opposite to each other, the response characteristics to protection are substantially the same.
  • an external DC bias circuit 5 is connected to an external power supply terminal 208 of the semiconductor device 2 .
  • a “positive” surge current Iesd flows from the DC bias circuit 5 through the external power supply terminal 208 to the semiconductor device 2 .
  • the surge current Iesd flows through the MISFET 221A of the protection circuit 22 to the reference power supply GND.
  • a resistor 222A is arranged between the gate electrode of the MISFET 221A and the second main electrode.
  • a resistor 222B is arranged between the gate electrode of the MISFET 221B and the second main electrode. Therefore, the surge current flowing from the source electrode side increases the gate potential of the gate electrode while charging the gate capacitance of the gate electrode through the resistor 222A or the resistor 222B.
  • a constant punch-through voltage BVpth is obtained between the pair of main electrodes of the MISFET 221A and the MISFET 221B by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd.
  • the gate potential does not rise above the protective voltage Vesd, it is possible to effectively suppress or prevent breakdown of the gate insulating film. Therefore, an ESD protection function is obtained.
  • the protection circuit 22 and the semiconductor device 2 according to the tenth embodiment it is possible to obtain the same effects as those obtained by the protection circuit 22 and the semiconductor device 2 according to the eighth embodiment.
  • the first external terminal 204A is also used as an external terminal that connects the first main electrode of the MISFET 221A and the second main electrode of the MISFET 221B.
  • the second external terminal 204B is also used as an external terminal connecting the second main electrode of the MISFET 221A and the first main electrode of the MISFET 221B. Therefore, the number of external terminals into which hot carriers are injected can be reduced.
  • a protection circuit 22 and a semiconductor device 2 according to the eleventh embodiment of the present disclosure will be described.
  • the eleventh embodiment is an example in which the protection circuit 22 and the semiconductor device 2 according to the ninth embodiment and the protection circuit 22 and the semiconductor device 2 according to the tenth embodiment are combined.
  • FIG. 24 shows circuit block configurations of a protection circuit 22 and an internal circuit 24 as an input side protection circuit of the semiconductor device 2 .
  • the protection circuit 22 is connected between the external terminal 201 and the coupling capacitor 202 with the surge induction resistor 223 interposed therebetween.
  • the protection circuit 22 includes two MISFETs 221A and 221B electrically connected in parallel, like the protection circuit 22 according to the tenth embodiment.
  • the configuration and circuit operation other than the above are substantially the same as the configuration and circuit operation of the protection circuit 22 according to the ninth embodiment and the protection circuit 22 according to the tenth embodiment, so descriptions thereof are omitted here. do.
  • a protection circuit 22 and a semiconductor device 2 according to a twelfth embodiment of the present disclosure will be described.
  • the twelfth embodiment is a modification of the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
  • FIG. 25 shows circuit block configurations of a protection circuit 22 and an internal circuit 24 as an input-side protection circuit of the semiconductor device 2 .
  • the external protection element 6 is electrically connected in parallel with the DC bias circuit 5 to the external power supply terminal 208 .
  • the external protection element 6 has an ESD protection tolerance higher than that of the protection circuit 22 .
  • a GGnMOS-Tr Gate Grounded n-type MOSFET
  • a pn diode or the like can be practically used for the external protection element 6 .
  • the present technology is not limited to the above-described embodiments, and can be modified in various ways without departing from the scope of the present technology.
  • the protection circuits and semiconductor devices according to the first to twelfth embodiments may be combined.
  • the present technology has been described using the input-side protection circuit as an example, it may be applied to an output-side protection circuit.
  • the present technology is not limited to insulated gate field effect transistors formed of compound semiconductor materials, and may be applied to protection circuits and semiconductor devices including insulated gate field effect transistors formed of Si semiconductor materials.
  • a protection circuit includes a MISFET.
  • a MISFET has a first main electrode connected between an external terminal and an internal circuit, and a second main electrode connected to a reference power supply.
  • a charge accumulating portion capable of accumulating hot carriers is provided in the gate insulating film.
  • the MISFET is formed as a depletion type, and can be formed to have an enhancement-type threshold voltage by accumulating hot carriers in the charge storage section. Therefore, it is possible to construct a protection circuit excellent in ESD tolerance or avalanche tolerance without using a pn junction and using a MISFET with high process affinity.
  • the semiconductor device includes an external terminal, an internal circuit, and a protection circuit.
  • the protection circuit is arranged on the semiconductor substrate and has a MISFET.
  • a MISFET has a first main electrode connected between an external terminal and an internal circuit, a second main electrode and a gate electrode connected to a reference power supply, and a charge storage section capable of storing hot carriers. Therefore, it is possible to obtain the same effects as those obtained by the protection circuit described above.
  • the present technology has the following configuration. According to the present technology having the following configuration, it is possible to construct a protection circuit and a semiconductor device excellent in ESD tolerance or avalanche tolerance using MISFETs with high process affinity.
  • a first main electrode is connected between an external terminal and an internal circuit, a second main electrode and a gate electrode are connected to a reference power source, and a charge storage portion capable of storing hot carriers is provided on the gate insulating film.
  • a protection circuit comprising: a disposed first insulated gate field effect transistor.
  • the protection circuit according to (1) further comprising a resistor electrically connected in series between the gate electrode and the second main electrode.
  • a semiconductor device comprising (5) The semiconductor device according to (4), wherein the protection circuit further includes a resistor electrically connected in series between the gate electrode and the second main electrode. (6) a first external terminal connected between the external terminal and the first main electrode and supplied with a first power source for generating hot carriers; a second external terminal connected to the second main electrode and supplied with a second power supply for generating hot carriers; The semiconductor device according to (4) or (5), further comprising a third external terminal connected to the gate electrode and supplied with a third power supply that generates hot carriers.
  • the charge storage section has a structure in which an oxide film, a nitride film, and an oxide film are sequentially laminated.
  • the nitride film contains SiN;
  • the oxide film contains at least one selected from Al 2 O 3 , HfO 2 , Ta 2 O 5 , ZrO 2 , Y 2 O 3 and SiO 2 .
  • the charge storage section includes Al 2 O 3 , HfO 2 laminated on the Al 2 O 3 , SiN laminated on the HfO 2 , and SiO 2 laminated on the SiN.
  • the compound semiconductor contains GaN or GaAs.
  • the first insulated gate field effect transistor contains InAlN.
  • the first insulated gate field effect transistor accumulates hot carriers in the charge storage section and shifts the threshold voltage from the depletion type to the positive direction to form the enhancement type from (4) to (12). ).
  • the gate length of the first insulated gate field effect transistor in the direction coinciding with the direction in which the first main electrode and the second main electrode are arranged is 0.05 ⁇ m or more and 0.3 ⁇ m or less;
  • the resistor has a resistance of 100 ⁇ to 10M ⁇ .
  • each of the first insulated gate field effect transistor and the second insulated gate field effect transistor contains InAlN;

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PCT/JP2022/005953 2021-07-09 2022-02-15 保護回路及び半導体装置 Ceased WO2023281795A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007189204A (ja) * 2005-12-13 2007-07-26 Matsushita Electric Ind Co Ltd 半導体記憶装置及びその製造方法
WO2010082498A1 (ja) * 2009-01-19 2010-07-22 株式会社日立製作所 半導体装置
JP2013247143A (ja) * 2012-05-23 2013-12-09 Semiconductor Energy Lab Co Ltd 半導体装置
JP2015073093A (ja) * 2013-09-04 2015-04-16 株式会社半導体エネルギー研究所 半導体装置および半導体装置の作製方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007189204A (ja) * 2005-12-13 2007-07-26 Matsushita Electric Ind Co Ltd 半導体記憶装置及びその製造方法
WO2010082498A1 (ja) * 2009-01-19 2010-07-22 株式会社日立製作所 半導体装置
JP2013247143A (ja) * 2012-05-23 2013-12-09 Semiconductor Energy Lab Co Ltd 半導体装置
JP2015073093A (ja) * 2013-09-04 2015-04-16 株式会社半導体エネルギー研究所 半導体装置および半導体装置の作製方法

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