WO2023280142A1 - 直流失调电流的消除电路、方法、相关设备及系统 - Google Patents

直流失调电流的消除电路、方法、相关设备及系统 Download PDF

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Publication number
WO2023280142A1
WO2023280142A1 PCT/CN2022/103815 CN2022103815W WO2023280142A1 WO 2023280142 A1 WO2023280142 A1 WO 2023280142A1 CN 2022103815 W CN2022103815 W CN 2022103815W WO 2023280142 A1 WO2023280142 A1 WO 2023280142A1
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WIPO (PCT)
Prior art keywords
module
voltage
current
elimination
offset
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PCT/CN2022/103815
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English (en)
French (fr)
Inventor
景磊
黄伟
李丹
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP22836893.2A priority Critical patent/EP4354764A1/en
Publication of WO2023280142A1 publication Critical patent/WO2023280142A1/zh
Priority to US18/405,607 priority patent/US20240146270A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
    • H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/66—Non-coherent receivers, e.g. using direct detection
    • H04B10/69—Electrical arrangements in the receiver
    • H04B10/693—Arrangements for optimizing the preamplifier in the receiver
    • H04B10/6933—Offset control of the differential preamplifier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/40—Transceivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/261—Amplifier which being suitable for instrumentation applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45212—Indexing scheme relating to differential amplifiers the differential amplifier being designed to have a reduced offset

Definitions

  • the embodiments of the present application relate to the communication field, and in particular to a DC offset current elimination circuit, method, related equipment and system.
  • a photodetector converts an optical signal into an electrical current signal.
  • Amplifiers convert current signals into voltage signals and amplify them.
  • the current signal output by the photodetector includes DC offset current and AC current. If there is a DC offset current in the current input to the amplifier, it will cause the output voltage signal of the amplifier to be distorted. Therefore, it is necessary to eliminate the DC offset current in the current signal to make the voltage signal output by the amplifier stable and accurate.
  • the offset voltage is extracted from the voltage signal output by the amplifier, the offset voltage is applied to the gate of the field effect transistor, and the field effect transistor is turned on to extract the DC offset current from the input terminal of the amplifier, so as to eliminate the DC offset current. Purpose.
  • the DC offset voltage applied to the gate of the field effect transistor has a process of slowly increasing from zero to the offset voltage, resulting in a slow speed of the conduction of the field effect transistor and the extraction of the DC offset current.
  • Embodiments of the present application provide a DC offset current elimination circuit, method, related equipment and system, which are used to quickly and accurately eliminate the DC offset voltage output by the photodetection module.
  • the first aspect of the embodiments of the present application provides a circuit for eliminating DC offset current.
  • the elimination circuit includes a light detection module, a first amplification module, a first filter module, an acceleration module, a charging module and a DC current elimination module.
  • the light detection module is respectively connected with the first end of the direct current elimination module and the first amplification module.
  • the first filter module is connected with the first amplification module and the charging module.
  • the second end of the DC current elimination module is respectively connected with the acceleration module and the charging module.
  • the third end of the direct current elimination module is grounded.
  • the light detection module is used for receiving the light signal and converting the light signal into a current signal.
  • the first amplifying module is used for receiving the current signal and converting and amplifying the current signal into a voltage signal.
  • the first filter module is used to filter out the DC offset voltage from the voltage signal.
  • the acceleration module is used to provide the charging module with a target voltage, and provides the target voltage.
  • the charging module is used for outputting the elimination voltage to the direct current elimination module based on the target voltage and the offset DC voltage, wherein the elimination voltage is positively correlated with the target voltage and the DC offset voltage.
  • the direct current elimination module is used to conduct the first end and the third end of the elimination module based on the elimination voltage direct current, so that the DC offset current in the current signal is grounded through the first end and the third end of the direct current elimination module.
  • Sharing the charge with the charging module through the acceleration module is equivalent to outputting an initial voltage for the charging module, so that the voltage of the charging module can increase rapidly, so as to improve the charging efficiency of the charging module, thereby speeding up the speed of eliminating the voltage to reach the DC offset voltage.
  • the elimination voltage is positively correlated with the target voltage and DC offset voltage.
  • the DC offset current in the current signal is larger, the corresponding DC offset voltage is larger, and the cancellation voltage is also larger, so the DC offset current flowing to the ground through the DC current cancellation module is also larger.
  • the DC offset current flowing to the ground through the DC current elimination module is eliminated, realizing accurate elimination of the DC offset current.
  • the elimination circuit in this embodiment further includes an acceleration module.
  • the acceleration module is used to provide a target voltage to the charging module in a target state.
  • the acceleration module has multiple states, the target state is one of the multiple states, and different states correspond to different voltages. Different states of the acceleration module can provide different voltages for the charging module, thereby increasing the charging rate of the charging module.
  • the value of the target voltage is positively related to the value of the DC offset voltage.
  • the charging time of the charging module is longer. Then providing different target voltages for different DC offset voltages can increase the charging rate of the charging module under various conditions.
  • the capacitance of the charging module is negatively correlated with the value of the target voltage. In this way, the time constants of the charging module and the accelerating module are kept constant, and the charging rate of the charging module by the DC offset voltage is not reduced due to the increase of the capacitance in the charging module.
  • the elimination circuit of this embodiment further includes a deceleration module.
  • the deceleration module is connected with the first filter module, and the deceleration module is used to control the filtering time of the voltage signal filtered by the first filter module.
  • the filtering time for filtering the voltage signal by the first filtering module is shortened, the elimination voltage can quickly reach the DC offset voltage.
  • the filtering time for filtering the voltage signal by the first filtering module is increased, the elimination circuit is made more stable and baseline drift is suppressed.
  • the elimination circuit of this embodiment further includes a start module and a switch module.
  • the start-up module is respectively connected with the first filter module and the switch module
  • the switch module is connected between the first filter module and the second terminal of the DC current elimination module
  • the start-up module is used for determining that the DC offset voltage is greater than or equal to the first reference
  • the switch module is turned on to connect the first filter module and the direct current elimination module.
  • the starting module can make the canceling circuit not start the DC current canceling module when the DC offset voltage is not greater than the first reference voltage, thereby reducing the interference to the light detecting module and improving the signal-to-noise ratio of the signal output by the light detecting module.
  • the elimination circuit of this embodiment further includes a second amplification module.
  • the second amplifying module is connected between the first filtering module and the DC current eliminating module, and the second amplifying module is used for amplifying the DC offset voltage and outputting the amplified DC offset voltage to the charging module.
  • the second amplifying module increases the gain of the DC offset voltage, thereby improving the accuracy of eliminating the DC offset current.
  • the elimination circuit in this embodiment further includes a second filtering module.
  • the second filtering module is connected between the second amplifying module and the DC current elimination module, and the second filtering module is used for filtering the amplified DC offset voltage output by the second amplifying module, and for converting the filtered DC offset voltage to The voltage is output to the charging module.
  • the second filtering module makes the voltage delivered to the charging module more stable, thereby stably eliminating the DC offset current, so that the voltage signal output by the first amplifying module is accurate and stable.
  • the second aspect of the embodiments of the present application provides a method for eliminating a DC offset current.
  • the method is applied to a DC offset current elimination circuit, and the elimination circuit includes a light detection module, a first amplification module, a first filter module, an acceleration module, a charging module and a DC current elimination module.
  • the light detection module is respectively connected with the first end of the direct current elimination module and the first amplification module.
  • the first filter module is connected with the first amplification module and the charging module.
  • the second end of the DC current elimination module is respectively connected with the acceleration module and the charging module.
  • the third end of the direct current elimination module is grounded.
  • the method includes: the optical detection module receives the optical signal and converts the optical signal into a current signal; the first amplification module receives the current signal and converts the current signal into a voltage signal; the first filter module filters out the DC offset voltage from the voltage signal; The module provides the target voltage to the charging module; the charging module outputs the elimination voltage to the DC current elimination module based on the target voltage and the offset DC voltage, wherein the elimination voltage is positively correlated with the target voltage and the DC offset voltage; the DC current elimination module will output the elimination voltage based on the elimination voltage The DC offset current in the current signal is conducted to the ground through the first terminal and the third terminal of the DC current elimination module.
  • providing the target voltage to the charging module by the acceleration module specifically includes: providing the target voltage to the charging module by the acceleration module in a target state.
  • the acceleration module has multiple states.
  • the target state is one of multiple states, and different states correspond to different voltages.
  • the target state is a preset state of the acceleration module, and the target voltage is a minimum value among multiple voltages corresponding to multiple states.
  • the value of the target voltage is positively related to the value of the DC offset voltage.
  • the elimination circuit further includes a deceleration module.
  • the method further includes: the deceleration module controls the filtering time of the voltage signal filtered by the first filtering module.
  • a second aspect of the embodiments of the present application provides an optical receiver.
  • the optical receiver includes a post-amplification circuit and a DC offset current elimination circuit described in the first aspect or any specific design thereof.
  • the post-amplification circuit is connected to the output terminal of the elimination circuit of the DC offset current, and is used for amplifying the voltage signal output by the elimination circuit of the DC offset current.
  • a third aspect of the embodiments of the present application provides a passive optical network system.
  • the passive optical network system includes an optical transmitter and the optical receiver described in the second aspect above.
  • the optical transmitter is used to send optical signals to the optical receiver.
  • the optical receiver is used to eliminate the DC offset current corresponding to the optical signal.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a DC offset current elimination circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of the acceleration module and the charging module in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a second embodiment of the DC offset current elimination circuit provided by the embodiment of the present application.
  • Fig. 4 is a schematic structural diagram of the deceleration module in Fig. 2;
  • FIG. 5 is a schematic structural diagram of a third embodiment of the DC offset current elimination circuit provided by the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a specific embodiment of a DC offset current elimination circuit provided in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a fourth embodiment of the DC offset current elimination circuit provided by the embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of the second amplification module in Fig. 7;
  • FIG. 9 is a schematic structural diagram of a fifth embodiment of the DC offset current elimination circuit provided by the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an automatic gain adjustment module provided in an embodiment of the present application.
  • FIG. 11 is a simulation diagram of the fifth embodiment of the elimination circuit based on DC offset current provided by the present application.
  • FIG. 12 is another simulation diagram of the fifth embodiment of the elimination circuit based on DC offset current provided by the present application.
  • FIG. 13 is a schematic flowchart of an embodiment of a method for eliminating a direct current provided by an embodiment of the present application.
  • Embodiments of the present application provide a DC offset current elimination circuit, method, related equipment and system. Used to accurately and quickly cancel the DC offset current of the photodetector output.
  • a passive optical network includes an optical distribution network (ODN), an optical line terminal (OLT) on the office (central office) side, and an optical network unit (optical network unit) on the user side. unit, ONU) or optical network terminal (optical network terminal, ONT), etc.
  • OLT provides a network-side interface for the PON system
  • the ONU provides a user-side interface for the PON system.
  • ODN is a network composed of optical fibers and passive optical splitting devices, used to connect OLT and ONU, and distribute or multiplex data signals between OLT and ONU.
  • a communication signal of each ONU is called a burst optical signal (hereinafter referred to as an optical signal).
  • the optical receiver on the OLT side should have the ability to quickly capture optical signals within a certain dynamic range.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a DC offset current elimination circuit provided by the present application.
  • the DC offset current elimination circuit 100 includes a light detection module 101 , a first amplification module 102 , a first filter module 103 , an acceleration module 104 , a charging module 105 and a DC current elimination module 106 .
  • the light detection module 101 is respectively connected to the first end of the direct current elimination module 106 and the first amplification module 102 .
  • the first filtering module 103 is connected with the first amplification module 102 and the charging module 105 .
  • the second end of the direct current elimination module 106 is respectively connected to the acceleration module 104 and the charging module 105 .
  • the third end of the direct current elimination module 106 is grounded.
  • the output terminal of the light detection module 101 is respectively connected to the first terminal of the direct current elimination module 106 and the input terminal of the first amplification module 102 .
  • the output end of the first amplification module 102 is connected to the input end of the first filter module 103, and the output end of the first filter module 103 is respectively connected to the second end of the DC current elimination module 106, the first end of the charging module 105 and the acceleration module 104 the first end of .
  • the third end of the direct current elimination module 106, the second end of the charging module 105 and the second end of the acceleration module 104 are grounded.
  • the first amplifying module 102, the first filtering module 103, the accelerating module 104, the charging module 105 and the DC current canceling module 106 constitute an automatic offset cancellation (AOC) loop. Each device included in the AOC loop is described below.
  • the light detection module 101 may be a photodiode (photo diode, PD).
  • PD is a PN diode working in reverse bias state.
  • APD avalanche photo diode
  • PIN PIN type diode.
  • the light detection module 101 is used for receiving light signals and converting the light signals into current signals. It should be noted that the current signal output by the light detection module 101 includes an AC current and a DC offset current.
  • the first amplification module 102 converts and amplifies the current signal output by the light detection module 101 into a voltage signal, and outputs the voltage signal.
  • the voltage signal includes AC voltage and DC offset voltage.
  • the AC voltage is output after the AC current is converted and amplified by the first amplifying module 102 .
  • the DC offset voltage is output after the DC offset current is converted and amplified by the first amplification module 102 .
  • the first amplification module 102 may be a trans-impedance amplifier (trans-impedance amplifier, TIA), a low-impedance amplifier, or a high-impedance amplifier. In this regard, this application does not make a limitation.
  • the first filter module 103 filters out the AC voltage in the voltage signal output by the first amplification module 102, and outputs a DC offset voltage.
  • the first filtering module 103 includes a first filter 1031 .
  • the first filter 1031 may be a resistor-capacitor filter or an inductor-capacitor filter (not shown).
  • the filter in this application may be a low-pass filter such as a resistor-capacitor filter, an inductor-capacitor filter, or a resistor-inductor-capacitor filter. In this regard, this application does not make a limitation.
  • FIG. 6 is a schematic structural diagram of a specific embodiment of a DC offset current elimination circuit provided by an embodiment of the present application. It should be noted that the elimination circuit of the DC offset current in FIG. 6 is only used as an example, and is not a limitation of the technical solution of the present application.
  • the first filter 1031 when the first filter 1031 is a resistor-capacitor filter, it may specifically include a first resistor R1 and a first capacitor C1. A first end of the first resistor R1 is connected to an output end of the first amplification module 102 .
  • the second end of the first resistor R1 is respectively connected to the first end of the first capacitor C1 , the second end of the DC current elimination module 106 , the first end of the charging module 105 and the first end of the acceleration module 104 .
  • the second terminal of the first capacitor C1 is grounded.
  • the first filter 1031 may be a filter with a small time constant, so as to improve the filtering rate of the voltage signal.
  • the size of the first resistor R1 can be any value between 3000 ohms and 8000 ohms, for example, it can be 5000 ohms.
  • the size of the first capacitor C1 can be any value between 200 Farads and 300 Farads, for example, it can be 250 Farads.
  • the DC offset voltage output by the first filtering module 103 is used for charging the charging module 105 .
  • the charging module 105 can provide the elimination voltage to the second terminal of the direct current elimination module 106 .
  • Fig. 2 is a schematic structural diagram of an acceleration module and a charging module provided by the present application.
  • the number of capacitors of the acceleration module 104 and the charging module 105 in FIG. 2 is only an example, and the number of capacitors may be 1, 2, 4 or more, which is not limited.
  • the charging module 105 includes, for example, a second capacitor C2.
  • the first end of the second capacitor C2 is respectively connected to the output end of the first filter module 103 , the second end of the direct current elimination module 106 and the first end of the acceleration module 104 .
  • the second end of the second capacitor C2 is grounded.
  • the second capacitor C2 uses the DC offset voltage output by the first filter module 103 to charge itself, and the second capacitor C2 is equivalent to a power supply, which can provide voltage for the second terminal of the DC current elimination module 106 .
  • the voltage of the second capacitor C2 is the same as the voltage (elimination voltage) of the second terminal of the direct current elimination module 106 .
  • the DC offset voltage begins to charge the charging module 105 from 0 volts (V), to the final voltage of the charging module 105 and the DC offset voltage
  • V volts
  • the voltage of the charging module 105 does not instantly reach the voltage value of the DC offset voltage from 0V, but slowly increases from 0V to the voltage value of the DC offset voltage. It takes a long time for the voltage of the charging module 105 to charge to the DC offset voltage. Therefore, the application uses the acceleration module 104 to speed up the charging rate of the charging module 105 .
  • the acceleration module 104 includes a third capacitor C3 , a first switch S1 and a second switch S2 .
  • the first end of the third capacitor C3 is respectively connected to the first end of the second capacitor C2 and the second end of the direct current elimination module 106 through the first switch S1.
  • the first end of the third capacitor C3 is also connected to the first power supply through the second switch S2, and the second end of the third capacitor C3 is grounded.
  • the first switch S1 When the first switch S1 is closed and the second switch S2 is opened, the first end of the second capacitor C2 is connected to the first end of the third capacitor C3.
  • the third capacitor C3 charges the second capacitor C2 to provide the target voltage.
  • the process of the third capacitor C3 charging the second capacitor C2 can actually be interpreted as a process of the third capacitor C3 sharing charges for the second capacitor C2.
  • the first end of the second capacitor C2 is connected to the first end of the third capacitor C3, it is equivalent to connecting the second capacitor C2 and the third capacitor C3 in parallel.
  • the amount of charge at the first end of the third capacitor C3 is greater than the amount of charge at the first end of the second capacitor C2, and the charge at the first end of the third capacitor C3
  • the charge moves to the first end of the second capacitor C2, and the charge can quickly reach a balance between the second capacitor C2 and the third capacitor C3.
  • the first terminal of the second capacitor C2 stores charges, so that the voltage of the second capacitor C2 rapidly changes from 0V to the target voltage.
  • the DC offset voltage is also charging the second capacitor C2, but because the third capacitor C3 charges the second capacitor C2 for a short period of time, the DC offset voltage during this period
  • the charge provided to the second capacitor C2 is negligible compared with the charge provided to the second capacitor C2 by the third capacitor C3.
  • U is the target voltage.
  • U 2 is the initial voltage of C2, regarded as 0V.
  • C2 is the capacitance of C2.
  • U 3 is the first preset voltage of C3.
  • C3 is the capacitance of C3.
  • Q is the total charge of C2 and C3.
  • C is the total capacitance of C2 and C3. Since C2 and C3 are connected in parallel, Q is the sum of the charges of C2 and C3, and C is the sum of the capacitance of C2 and C3.
  • the charging module 105 is charged by the accelerating module 104 , so that the voltage of the charging module 105 can instantly reach the target voltage, which is equivalent to providing an initial voltage for the charging module 105 .
  • the time required for the charging module 105 to charge from 0V to the target voltage from the DC offset voltage is saved, the charging rate of the charging module 105 is accelerated, and the voltage value of the charging module 105 can reach the value of the DC offset voltage faster.
  • the target voltage provided by the acceleration module 104 is not greater than the DC offset voltage.
  • the DC offset voltage is positively correlated with the DC offset current output by the light detection module 101 , and the DC offset current is positively correlated with the intensity of the optical signal.
  • Optical signals have different strengths, so the DC offset voltage also has different values. If the target voltage provided by the acceleration module 104 is too large, the target voltage may be greater than the DC offset voltage if the DC offset voltage is small. If the target voltage provided by the acceleration module 104 is too small, the degree of acceleration of the acceleration module 104 is limited when the DC offset voltage is relatively large.
  • the acceleration module 104 in the embodiment of the present application may further have multiple states to provide corresponding voltages for the charging module 105 .
  • the target state is determined from various states of the acceleration module 104 , and then a corresponding target voltage is provided for the charging module 105 .
  • Each state corresponds to the connection of capacitors carrying different amounts of charge in the acceleration module 104 to the charging module 105 , for example, the acceleration module 104 has different numbers of capacitors connected to the charging module in different states.
  • the target state of the acceleration module 104 may be a preset state.
  • the default state is the default initial state.
  • the target voltage corresponding to the preset state is the minimum value among multiple voltages.
  • the preset state is, for example, a state where C3 is connected to C2 when the first switch S1 is closed and the second switch S2 is open.
  • the value of the voltage corresponding to the state is positively correlated with the value of the DC offset voltage. That is, the greater the DC offset voltage, the greater the target voltage provided by the acceleration module 104 .
  • the acceleration module 104 may be switched based on preset states.
  • the acceleration module 104 includes a plurality of capacitors carrying charges. When switching from the preset state to other states, on the basis of the preset state, one or more capacitors carrying charges are added to be connected to the charging module 105 .
  • the acceleration module 104 includes three states: a preset state, a first dynamic state, and a second dynamic state. As shown in FIG. 2, the acceleration module 104 includes a third capacitor C3, a first switch S1, a second switch S2, a fourth capacitor C4, a third switch S3, a fourth switch S4, a fifth capacitor C5, a fifth switch S5 and Sixth switch.
  • the connection manners of the third capacitor C3, the first switch S1 and the second switch S2 are the same as those described above, so details will not be repeated here.
  • the first end of the fourth capacitor C4 is respectively connected to the first end of the second capacitor C2, the first end of the third capacitor C3 and the second end of the DC current elimination module 106 through the third switch S3, and the first end of the fourth capacitor C4 The end is also connected to the second power supply through the fourth switch S4, and the second end of the fourth capacitor C4 is grounded.
  • the first terminal of the fifth capacitor C5 is respectively connected to the first terminal of the second capacitor C2, the first terminal of the third capacitor C3, the first terminal of the fourth capacitor C4 and the second terminal of the direct current elimination module 106 through the fifth switch S5. terminal, the first terminal of the fifth capacitor C5 is also connected to the third power supply through the sixth switch, and the second terminal of the fifth capacitor C5 is grounded.
  • the first switch S1 , the third switch S3 and the fifth switch S5 are turned off, and the second switch S2 , the fourth switch S4 and the sixth switch S6 are turned on.
  • the first power supply provides a first preset voltage for the fourth capacitor C4, so that the first terminal of the third capacitor C3 stores charges;
  • the second power supply provides a second preset voltage for the fourth capacitor C4, so that the first The first terminal of the fourth capacitor C4 stores charges;
  • the third power supply provides a third preset voltage for the fifth capacitor C5, so that the first terminal of the fifth capacitor C5 stores charges.
  • the first preset voltage, the second preset voltage and the third preset voltage may be all the same, partially the same or completely different.
  • the first preset voltage, the second preset voltage and the third preset voltage Both can be greater than the DC offset voltage.
  • the first to third preset voltages may also be no greater than the DC offset voltage, as long as the initial voltage of the acceleration module 104 is greater than the voltage of the charging module 105 when the acceleration module 104 is in the target state.
  • the first switch S1, the fourth switch S4 and the sixth switch are closed, the second switch S2, the third switch S3 and the fifth switch S5 are opened, and the first terminal of the third capacitor C3 and the second capacitor C2 The first terminal of is connected, and the third capacitor C3 charges the second capacitor C2 to provide the target voltage.
  • the first switch S1, the third switch S3, and the sixth switch are closed, the second switch S2, the fourth switch S4, and the fifth switch S5 are open, and the first terminal of the fourth capacitor C4 and the second capacitor
  • the first terminal of C2 is connected with the first terminal of the third capacitor C3, and the fourth capacitor C4 charges the second capacitor C2 to provide the target voltage.
  • the first switch S1, the third switch S3, and the fifth switch S5 are closed, the second switch S2, the fourth switch S4, and the sixth switch are open, and the first end of the fifth capacitor C5 and the second capacitor
  • the first terminal of C2 the first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 are connected, and the fifth capacitor C5 charges the second capacitor C2 to provide the target voltage.
  • the target voltage mentioned in the embodiment of the present application refers to the amount of charge provided by the acceleration module 104 to the charging module 105 as a whole during the whole process of accelerating the charging module 105 by the accelerating module 104. increasing voltage.
  • C3 has charged C2 first and reached a balance.
  • C4 continues to charge C2.
  • the target voltage in the first dynamic state refers to the difference between the charges provided by C3 and C4 to C2. and the voltage that makes C2 grow.
  • the target voltage under the second dynamic refers to the voltage that C2 increases due to the sum of charges provided by C3, C4 and C5 to C2.
  • the acceleration module 104 connects the charged capacitor to the charging module 105 to charge the charging module 105 , it is equivalent to connecting one or more capacitors in parallel in the charging module 105 . In this way, the capacitance of the charging module 105 is increased, so that the time constant of the AOC loop and the charging module 105 becomes larger, which will slow down the rate at which the DC offset voltage charges the charging module 105 to a certain extent. Therefore, in the embodiment of the present application, when the acceleration module 104 is connected to the capacitor of the target capacity to charge the charging module 105 , the target capacity is reduced from the total capacity of the charging module 105 .
  • the charging module 105 also includes one or more parallel capacitors other than the second capacitor C2. A first end of each parallel capacitor is connected to a first end of the second capacitor C2 through a switch, and a second end of each parallel capacitor is grounded. In an initial state, the switch at the first end of each parallel capacitor is closed, and the second capacitor C2 is connected in parallel with the parallel capacitor.
  • the charging module 105 disconnects one or more switches connected with the parallel capacitors to reduce the electric capacity of the charging module 105, so that The reduced capacitance of the charging module 105 is the same as the capacitance of the capacitor newly connected to the charging module 105 by the acceleration module 104 .
  • the charging module 105 further includes, for example, a sixth capacitor C6, a seventh switch S7, a seventh capacitor, and an eighth switch S8.
  • the first end of the sixth capacitor C6 is connected to the first end of the second capacitor C2 through the seventh switch S7.
  • the first terminal of the seventh capacitor is connected to the first terminal of the second capacitor C2 through the eighth switch S8, and the second terminals of the sixth capacitor C6 and the seventh capacitor are grounded.
  • the capacitances of the fourth capacitor C4 , the fifth capacitor C5 , the sixth capacitor C6 and the seventh capacitor are all 1.5 picofarads, for example.
  • the acceleration module 104 In the initial state, the acceleration module 104 is in a preset state, the first switch S1, the seventh switch S7 and the eighth switch S8 are closed, the second switch S2 is open, and the first end of the third capacitor C3 is connected to the first end of the second capacitor C2.
  • One terminal, the first terminal of the sixth capacitor C6 and the first terminal of the seventh capacitor, the third capacitor C3 charges the second capacitor C2, the sixth capacitor C6 and the seventh capacitor.
  • the acceleration module 104 switches from the preset state to the first dynamic state, the third switch S3 is closed, the fourth switch S4 is opened, and the first end of the fourth capacitor C4 is connected to the first end of the charging module 105 to charge the charging module 105 , the charging module 105 turns off the seventh switch S7, the capacitance of the acceleration module 104 increases by 1.5 picofarads, and the capacitance of the charging module 105 decreases by 1.5 picofarads. The same goes for switching the acceleration module 104 from the first dynamic to the second dynamic.
  • the second capacitor C2 is a variable capacitor. As the capacitance of the capacitor connected to the charging module 105 in the acceleration module 104 increases, the second capacitor C2 decreases correspondingly by an equal capacitance. In this case, the second capacitor C2 in the charging module 105 does not need a parallel capacitor.
  • the capacitance of the charging module 105 may not be changed, and the time constant of the AOC loop is realized by keeping the capacitance of the capacitor connected to the charging module 105 in the acceleration module 104 unchanged. , to ensure the charging rate of the charging module by the DC offset voltage.
  • the capacitances of C3 , C4 and C5 are all 1.5 picofarads.
  • the acceleration module 104 is in a preset state, the first switch S1 is closed, the second switch S2 is open, the first end of the third capacitor C3 is connected to the first end of the second capacitor C2, and the third capacitor C3 is the second Capacitor C2 charges, and the charge quickly balances between the two. If the acceleration module 104 switches from the preset state to the second state, the third switch S3 is closed, the fourth switch S4 is opened, and the first end of the fourth capacitor C4 is connected to the first end of the charging module 105 to charge the charging module 105 .
  • the acceleration module 104 also disconnects the first switch S1 to disconnect the connection between the third capacitor C3 and the charging module 105.
  • the acceleration module 104 adds a fourth capacitor C4, and the capacitance increases by 1.5 picofarads. Three capacitors C3, the capacitance is reduced by 1.5 picofarads.
  • the capacitance of the acceleration module 104 remains unchanged, and the capacitance of the charging module 105 and the AOC loop remain unchanged.
  • the target state of the acceleration module 104 can also be directly determined without switching based on the previous state (for example, the first dynamic state is switched based on the preset state, and the second dynamic state is switched based on the first dynamic state).
  • the magnitude of the DC offset voltage is positively correlated with the DC offset current
  • the DC offset current is positively correlated with the optical signal intensity. That is to say, the greater the optical power of the optical signal, the greater the DC offset voltage, and the greater the voltage that the acceleration module 104 needs to provide for the charging module 105 .
  • the target state of the acceleration module 104 can be determined based on the optical power of the optical signal. That is to say, the acceleration module 104 provides the charging module 105 with a corresponding amount of charge at one time, without charging the charging module 105 in batches.
  • the integrated chip of the AOC generates a reset signal according to the optical power.
  • the magnitude of the optical power is positively correlated with the magnitude of the pulse width of the reset signal, or is positively correlated with the magnitude of the level of the reset signal.
  • the target state of the acceleration module 104 is determined according to the width and level of the reset signal. For example, when the level of the reset signal is 0.1-0.3 decibel (dB), it corresponds to the first state of the acceleration module 104 . When the level of the reset signal is 0.4-0.6dB, it corresponds to the second state of the acceleration module 104 . When the level of the reset signal is 0.7-1.0 dB, it corresponds to the third state of the acceleration module 104 .
  • the level of the reset signal was 0.8dB, it was determined that the target state of the acceleration module 104 was the third state, and then the acceleration module 104 was directly controlled to be in the third state without switching from the first state to the second state, and then by the second The state switches to the third state.
  • the acceleration module 104 can provide the target voltage for the charging module 105 .
  • different states of the acceleration module 104 correspond to different quantities of capacitors connected to the charging module 105 in the acceleration module 104. By controlling the number of capacitors connected to the charging module 105 in the acceleration module, a corresponding target voltage is provided to the charging module 105 .
  • the acceleration module 104 includes a plurality of capacitors carrying different charges, and each state corresponds to one of the capacitors being connected to the charging module 105 to provide a corresponding target voltage to the charging module 105 .
  • the elimination voltage of the second terminal of the direct current elimination module 106 is the same as the voltage of the charging module 105 .
  • the voltage of the charging module 105 during the charging process is jointly determined by the target voltage and the DC offset voltage.
  • the magnitude of the cancellation voltage is positively related to the target voltage and the DC offset voltage.
  • the direct current elimination module 106 may be a voltage-controlled current source. When the voltage at the second end of the direct current elimination module 106 reaches a threshold, the first end and the third end of the direct current elimination module 106 are turned on, so that the output of the light detection module 101 At least part of the DC offset current in the current signal flows to the ground through the first terminal and the third terminal of the DC current elimination module 106, thereby eliminating at least part of the DC offset current in the current signal and reducing the DC flowing into the first amplification module 102 offset current.
  • the DC current canceling module 106 may include field effect transistors. The field effect transistor can be P-type or N-type, which is not limited in this application. The relationship between the DC offset current eliminated by the DC current elimination module 106 and the elimination voltage is as follows:
  • I dc is the DC offset current eliminated by the DC current elimination module 106
  • gm is the transconductance of the FET
  • U VG is the elimination voltage
  • the gate of the field effect transistor is the second terminal of the DC current elimination module 106, and the source and drain are respectively the third terminal and the first terminal of the DC current elimination module 106.
  • the source and drain of the field effect tube have the characteristics of conducting direct current and blocking alternating current, so the direct current in the current signal output by the photodetection module 101 can flow to the ground through the field effect tube, and the alternating current in the current signal is input to the first An amplification module 102 .
  • the direct current elimination module 106 can also be a current control current source.
  • the direct current elimination module 106 includes, for example, a triode (not shown in the figure) and a voltage-to-current converter (not shown in the figure).
  • the triode can be NPN or PNP, which is not limited in this application.
  • the conduction of its first terminal and third terminal is controlled by the elimination voltage, and the magnitude of the DC offset current flowing to the ground through the first terminal and the third terminal of the DC current elimination module 106 .
  • the greater the elimination voltage the greater the DC offset current flowing through the first end and the third end of the current elimination module.
  • the embodiment of the present application uses the acceleration module 104 to increase the charging rate of the charging module 105, so that the elimination voltage can quickly reach the DC offset voltage, so that the DC current elimination module can extract the DC offset current from the current signal more quickly and stably, and achieve fast , Accurately eliminate the target of DC offset current.
  • the data frame corresponding to the optical signal received by the optical detection module 101 includes a preamble and a data code.
  • the preamble is encapsulated before the data code, and the preamble is used to indicate clock synchronization timing, and the data code carries the data to be transmitted. Therefore, the optical detection module 101 receives the optical signal corresponding to the preamble earlier than the optical signal corresponding to the data code, and the current signal corresponding to the preamble is input to the AOC loop earlier than the current signal corresponding to the data code. The time of input to the AOC loop. Moreover, compared with the voltage signal corresponding to the preamble output by the first amplification module 102, the accuracy and stability of the voltage signal corresponding to the data code have higher requirements.
  • FIG. 3 is a schematic structural diagram of a second embodiment of a circuit for eliminating direct current in the present application.
  • the elimination circuit 100 of this embodiment further includes a deceleration module 107 .
  • the deceleration module 107 is connected to the first filter module 103 and is used to control the time constant of the first filter module 103 , so as to control the filter time of the filtered voltage signal.
  • the deceleration module 107 controls the first filter module 103 to be in a state of a small time constant, so as to reduce the filter time of the voltage signal, so that the direct current elimination module 106
  • the elimination voltage of the second terminal can quickly reach the DC offset voltage, so that the AOC loop can be quickly stabilized.
  • the DC current elimination module 106 can accurately extract the DC offset current from the current signal, so that the current signal input to the first amplification module 102 is more accurate, and the first amplification The voltage signal output by the module 102 is also more stable and accurate.
  • time constants of other modules in the AOC loop remain unchanged, and changing the time constant of the first filtering module 103 is equivalent to changing the time constant of the AOC loop. It should be noted that the large time constant and the small time constant are relative terms between the two, and do not correspond to a specific time constant value.
  • the deceleration module 107 controls the first filter module 103 to be in a state with a large time constant. Compared with the state with a small time constant, the state with a large time constant increases the filtering time of the voltage signal and slows down the filtering speed of the voltage signal, thereby improving the stability of the AOC loop and making the voltage signal output by the first amplification module 102 stable. , to suppress baseline drift.
  • the deceleration module 107 controls the first filter module 103 to switch between the large time constant and the small time constant by generating and outputting the first control signal to the first filter module 103 .
  • the deceleration module 107 uses the reset signal generated by the chip before the arrival of the preamble to generate the first control signal.
  • the chip refers to a chip integrated with the deceleration module 107 and the AOC loop.
  • the time corresponding to the falling edge of the reset signal is the same as the time corresponding to the rising edge of the first bit current signal output by the light detection module 101 of the preamble.
  • the deceleration module 107 reshapes the reset signal, and delays the falling edge of the reset signal to obtain the first control signal.
  • the time corresponding to the falling edge of the first control signal is earlier than the time corresponding to the rising edge of the data code current signal output by the light detection module 101 .
  • FIG. 4 is a schematic structural diagram of the deceleration module in FIG. 2 .
  • the deceleration module 107 includes a second filter 1701 , a shaper 1702 , a first flip-flop 1703 , a first inverter 1704 , a third filter 1705 , a first comparator 1076 and a ninth switch S9 .
  • the input end of the second filter 1701 is used to receive the reset signal, and the output end is connected to the input end of the shaper 1702 .
  • the output terminal of the shaper 1702 is connected to the clock control terminal of the first flip-flop 1703, the first input terminal is connected to the fourth power supply, the second input terminal is used to receive the reset signal, and the output terminal is connected to the input terminal of the first inverter 1704 and the first inverter 1704.
  • the fourth power supply is used to maintain the first input terminal in a high level state.
  • the output terminal of the first inverter 1704 is connected to the input terminal of the third filter 1705 .
  • the output end of the third filter 1705 is connected to the first input end of the first comparator 1076 .
  • the second input terminal of the first comparator 1076 is used to receive the second reference voltage, and the output terminal is connected to the first filtering module 103 .
  • One end of the ninth switch S9 is connected to the input end of the third filter 1705, and the other end is connected to the output end of the third controller.
  • the first flip-flop 1703 is a falling edge flip-flop.
  • the time constant of the second filter 1701 is smaller than the time constant of the third filter 1705 .
  • the main function of the second filter 1701 is to make the falling edge of the reset signal arrive at the clock control end of the first flip-flop later than the falling edge of the reset signal arrive at the second input end of the first flip-flop. Therefore, when the falling edge of the reset signal reaches the clock control terminal of the first flip-flop, the second input terminal of the first flip-flop recovers to a low level.
  • the generation process of the first control signal is as follows.
  • the rising edge of the reset signal is input to the second input terminal of the first flip-flop 1703
  • the output terminal of the first flip-flop 1703 is triggered to output the first falling edge signal.
  • the first falling edge signal triggers the ninth switch S9 to be closed and short-circuits the third filter 1705 .
  • the first inverter 1704 inverts the first falling edge signal into a first rising edge signal, and inputs the first rising edge signal to the first input end of the first comparator 1076 through the ninth switch S9.
  • the first comparator 1076 compares the first rising edge signal with the second reference voltage, and outputs the rising edge of the first control signal when the voltage value of the first rising edge signal is greater than the voltage value of the second reference voltage.
  • the second input terminal of the first flip-flop 1703 returns to low level; the second filter 1701 delays the falling edge of the reset signal for the first time, because the The falling edge of the input reset signal is slowed down, and the waveform of the reset signal is no longer a square wave. Therefore, the delayed and slowed falling edge of the reset signal is shaped by the shaper 1702 and output as a falling edge of a square wave.
  • the falling edge of the reset signal after shaping is input to the clock control terminal of the first flip-flop 1703.
  • the shaped The falling edge of the reset signal triggers the first flip-flop 1703 to output the second rising edge signal.
  • the second rising edge signal triggers the ninth switch S9 to turn off, and the third filter 1705 is connected to the output terminal of the first inverter 1704 .
  • the first inverter 1704 inverts the second rising edge signal into a second falling edge signal, and inputs the second falling edge signal to the third filter 1705 .
  • the third filter 1705 delays the second falling edge signal, and outputs the delayed second falling edge signal to the first input terminal of the first comparator 1076 .
  • the first comparator 1076 compares the second falling edge signal with the second reference voltage, and outputs the falling edge of the first control signal when the voltage value of the second falling edge signal is smaller than the voltage value of the second reference voltage.
  • the first control signal can control the switching of the time constant of the first filter module 103 by changing the resistance of the first filter module 103 .
  • This embodiment is described by taking the first filter module 103 as a resistor-capacitor filter as an example.
  • the resistance of the first filter module 103 can be changed by increasing or decreasing the number of resistors connected to the AOC loop in the first filter module 103 .
  • the first filter module 103 includes, for example, a first resistor R1 , a second resistor R2 , a tenth switch S10 and a first capacitor C1 .
  • the input terminal of the first resistor R1 is connected to the output terminal of the first amplification module 102
  • the output terminal of the first resistor R1 is connected to the input terminal of the second resistor R2 .
  • the output end of the second resistor R2 is respectively connected to the first end of the first capacitor C1 , the first end of the charging module 105 , the first end of the acceleration module 104 and the second end of the DC current elimination module 106 .
  • the second terminal of the first capacitor C1 is grounded.
  • One end of the tenth switch S10 is connected to the input end of the first resistor R1, and the other end is connected to the output end of the first resistor R1.
  • the control end of the tenth switch S10 is connected to the deceleration module 107 .
  • the control terminal of the tenth switch S10 After the control terminal of the tenth switch S10 receives the first control signal sent by the deceleration module 107, the control terminal of the tenth switch S10 is in a high level state, which triggers the closing of the tenth switch S10 and short-circuits the first resistor R1. At this time, the resistance of the first filter module 103 becomes smaller, and the time constant becomes smaller, so that the first filter module and the AOC loop are in a state of a small time constant.
  • the control terminal of the tenth switch S10 After the first control signal disappears, the control terminal of the tenth switch S10 returns to a low level state, triggering the opening of the tenth switch S10, and the first resistor R1 is connected to the AOC loop. At this time, the resistance of the first filter module 103 becomes larger, and the time constant becomes larger, so that the first filter module and the AOC loop are in a state of a large time constant.
  • the resistance of the first filtering module 103 can be changed by changing the resistance of a certain resistance in the first filtering module 103 .
  • the first filtering module 103 includes, for example, a first resistor R1 and a first capacitor C1.
  • a first end of the first resistor R1 is connected to an output end of the first amplification module 102 .
  • the second terminal of the first resistor R1 is respectively connected to the first terminal of the first capacitor C1, the second terminal of the DC current elimination module 106, the first terminal of the charging module 105 and the first terminal of the acceleration module 104, and the first terminal of the first capacitor C1 The second end is grounded.
  • the first resistor R1 is a variable resistor, and the first resistor R1 is also connected to the output end of the deceleration module 107 .
  • the resistance value of the first resistor R1 is reduced, so that the first filter module 103 is in a small time constant state.
  • the resistance value of the first resistor R1 is increased, so that the first filter module 103 is in a state with a large time constant.
  • FIG. 5 is a schematic structural diagram of a third embodiment of a circuit for eliminating DC offset current provided by an embodiment of the present application.
  • the canceling circuit 100 further includes a starting module 108 and a switching module 109 .
  • the starting module 108 is used to control the opening and closing of the switch module 109 to control whether the AOC loop works. Since the light detection module 101 is very sensitive to noise in the circuit when it starts to receive light signals, if the AOC loop works at this time, the light detection module 101 will receive unnecessary noise.
  • the embodiment shown in FIG. 5 can improve the signal-to-noise ratio of the current signal output by the light detection module 101 .
  • the input end of the startup module 108 is connected to the output end of the first filtering module 103 .
  • the output terminal of the start module 108 is connected to the control terminal of the switch module 109 , and the switch module 109 is connected between the first filter module 103 and the second terminal of the direct current elimination module 106 .
  • the starting module 108 obtains the DC offset voltage from the first filtering module 103, and compares the DC offset voltage with the first reference voltage. When the DC offset voltage is greater than the first reference voltage, the second control signal is output.
  • the second control signal is used to control the switch module 109 to turn on the second terminal of the first filter module 103 and the DC current elimination module 106 to start the AOC loop and make the AOC loop work.
  • the switch module 109 is turned off, the connection between the first filter module 103 and the second terminal of the DC current elimination module 106 is disconnected, and the AOC loop does not work.
  • the starting module 108 may include a second comparator 1081 , an AND gate unit 1082 and a second flip-flop 1083 .
  • the switch module 109 may include an eleventh switch S11 and a twelfth switch S12.
  • the first input end of the second comparator 1081 is connected to the output end of the first filtering module 103 .
  • the second input terminal of the second comparator 1081 is used for receiving a preset voltage.
  • the output end of the second comparator 1081 is connected to the first input end of the AND gate unit 1082 .
  • the second input end of the AND gate unit 1082 is connected to the output end of the deceleration module 107 for receiving the first control signal.
  • the output end of the AND gate unit 1082 is connected to the clock control end of the second comparator 1081 .
  • the first input terminal of the second comparator 1081 is connected to the fifth power supply
  • the second input terminal of the second comparator 1081 is used to receive the reset signal
  • the output terminal of the second comparator 1081 is connected to the eleventh switch S11 and the twelfth switch
  • the second flip-flop 1083 is a rising edge flip-flop.
  • the fifth power supply is used to keep the first input terminal of the second flip-flop 1083 at a high level.
  • One end of the eleventh switch S11 is connected to the first end of the charging module 105, the first end of the acceleration module 104 and the first end of the first filtering module 103, and the other end of the eleventh switch S11 is connected to one end of the twelfth switch S12 and the second terminal of the DC current elimination module 106 .
  • the other end of the twelfth switch S12 is grounded.
  • the second comparator 1081 compares the DC offset voltage with the first reference voltage. When the DC offset voltage is greater than the first reference voltage, the second comparator 1081 outputs a first high level signal to the AND gate unit 1082 . When the first input terminal of the AND gate unit 1082 receives the first high level signal and is at high level, and its second input terminal receives the first control signal is also at high level, it outputs the third rising edge signal to the second trigger The clock control terminal of device 1083. Since the first input terminal of the second flip-flop 1083 is at a high level, the third rising edge signal triggers the second flip-flop 1083 to output a second high-level signal.
  • the second high-level signal is used to control the eleventh switch S11 to close, and the twelfth switch S12 to open, so that the second end of the DC current elimination module 106 is connected to the first end of the charging module 105 and the first end of the acceleration module 104 It communicates with the first end of the first filter module 103 to start the AOC loop.
  • the AND gate unit 1082 only outputs the third rising edge signal when both the first high level signal and the first control signal are valid, which can prevent the light detection module 101 from outputting the current signal incorrectly when receiving noise without receiving the burst signal.
  • the first control signal is generated when the light detection module 101 receives the burst signal, so the starting module 108 takes the first control signal as a necessary condition to ensure that the AOC loop will not be started at a wrong time.
  • the second comparator 1081 outputs the first high-level signal.
  • the DC offset voltage that is, the DC offset current is relatively large, and it is necessary to start the AOC loop to eliminate the DC offset current; on the other hand, it indicates the strength of the current signal output by the optical detection module 101. is larger, at this time the noise caused by starting the AOC loop has little impact on the light detection module 101, and the AOC loop can be started.
  • the second control signal can also be used to control the acceleration module 104 to be in a preset state.
  • the output end of the starting module 108 is also connected to the control ends of the first switch S1 and the second switch S2.
  • the first switch S1 and the second switch S2 receive the second control signal, the first switch S1 is closed, the second switch S2 is opened, and the second capacitor C2 is connected to the charging module 105 to provide the charging module 105 with a target voltage.
  • the twelfth switch S12 is closed under the control of the reset signal coming after the optical signal ends, so as to release the charge in the charging module 105 to the ground, so that the voltage of the charging module 105 returns to the initial state before the next optical signal arrives, that is, 0V .
  • FIG. 7 is a schematic structural diagram of a fourth embodiment of a circuit for eliminating DC offset current provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of the second amplification module in FIG. 7 .
  • the DC offset current elimination circuit 100 of this embodiment further includes a second amplification module 110 .
  • the second amplification module 110 is connected between the first filter module 103 and the first end of the charging module 105 .
  • the input terminal of the second amplification module 110 is connected to the output terminal of the first filtering module 103
  • the output terminal of the second amplification module 110 is connected to the first terminal of the charging module 105 .
  • the second amplification module 110 is used to amplify the DC offset voltage output by the first filter module 103 , and output the amplified DC offset voltage to the charging module 105 .
  • the second amplifying module 110 can increase the range of the DC offset voltage, so that the magnitude of the DC current drawn by the DC current canceling module 106 can be more precisely controlled.
  • the second amplification module 110 may be a high-speed amplifier.
  • the second amplifying module 110 may include a plurality of inverters, and each inverter is formed by connecting a P-type field effect transistor and an N-type field effect transistor in parallel.
  • the input terminal of the inverter is the gate of the two inverters, and the output terminal of the inverter is the drain of the two inverters.
  • the first source of the N-type field effect transistor in the inverter is connected to the working voltage, and the second source of the P-type field effect transistor is grounded.
  • the amplification function can be realized when both FETs in the inverter work in the saturation region.
  • the second amplifying module 110 can increase the gain of the AOC loop by cascading three stages of inverters, so that the loop eliminates the DC current accurately enough.
  • the input end of the first-stage inverter 1101 is connected to the output end of the first filtering module 103, the output end of the first-stage inverter 1101 is connected to the input end of the second-stage inverter 1102, and the output end of the second-stage inverter 1102
  • the output end is connected to the input end of the third-stage inverter 1103 , and the output end of the third-stage inverter 1103 is connected to the first end of the charging module 105 .
  • each stage of inverter may include one inverter and at least one load. At least one load of the inverters of each stage is respectively connected in parallel with the inverters of the stage to amplify the DC offset voltage.
  • the first-stage inverter 1101 and the second-stage inverter 1102 are used to stabilize the common mode point, and the third-stage inverter 1103 can adopt a larger size to ensure high amplification speed.
  • the first-stage inverter 1101 includes a first inverter 11011, a first load 11012, a second load 11013 and a third load 11014, and the second-stage inverter 1102 includes a second inverter 11021 and two loads,
  • the third-stage inverter 1103 includes a third inverter 11031 for illustration.
  • the number of loads in the first-stage inverter 1101 can also be 2, 4 or more.
  • the number of loads in the second-stage inverter 1102 may also be 2, 3 or more, which is not limited in this application.
  • the third-stage inverter 1103 may also include one or more loads.
  • the optical detection module 101 When the optical detection module 101 is switched from 10G mode to 2.5G mode or in the case of slow-slow process corner (slow-slow corner, SS corner), because the gain of the first amplification module 102 becomes larger, in order to maintain the AOC loop The overall gain of the AOC remains unchanged, and the gain of the second amplifying module 110 can be reduced to ensure the stability of the AOC loop.
  • the second amplification module 110 may support at least two gain modes. Specifically, the gain of the second amplification module 110 can be adjusted by adjusting the gain of the first-stage inverter 1101 .
  • the first-stage inverter 1101 supports three gain modes as an example. Of course, the first-stage inverter 1101 can also support 2, 4 or more gain modes. The number of loads in the converter 1101 and the actual gain requirements are determined, which is not limited in the present application.
  • the first stage inverter 1101 further includes a thirteenth switch S13 , a fourteenth switch S14 , a fifteenth switch S15 and a sixteenth switch S16 .
  • the first source of the second load 11013 is connected to the sixth power supply through the thirteenth switch S13, and the second source of the second load 11013 is grounded through the fourteenth switch S14.
  • the first source of the third load 11014 is connected to the seventh power supply through the fifteenth switch S15, and the second source of the third load 11014 is grounded through the sixteenth switch S16.
  • the sixth power supply is used to provide the working voltage for the second load 11013
  • the seventh power supply is used to provide the working voltage for the third load 11014 .
  • the thirteenth switch S13 , the fourteenth switch S14 , the fifteenth switch S15 and the sixteenth switch S16 are all closed.
  • the thirteenth switch S13 and the fourteenth switch S14 are turned off so that the second load 11013 does not work, and the fifteenth switch S15 and the sixteenth switch S16 are turned on.
  • the thirteenth switch S13 , the fourteenth switch S14 , the fifteenth switch S15 and the sixteenth switch S16 are all turned off so that neither the second load 11013 nor the third load 11014 works.
  • the gain of the second amplifying module 110 can also be adjusted by adjusting the number of loads working in the second-stage inverter and the third-stage inverter, which is not limited in the present application.
  • the DC offset current elimination circuit 100 further includes a second filtering module 111 .
  • the second filtering module 111 is connected between the second amplifying module 110 and the first end of the charging module 105, and is used for stabilizing the amplified DC offset voltage output by the second amplifying module 110, so as to stabilize the second DC current elimination module 106. terminal voltage.
  • the second filtering module 111 may specifically be a filter.
  • the second filtering module 111 includes a capacitor.
  • the second filtering module 111 shares a capacitor with the charging module 105 , that is, the second filtering module 111 includes the second capacitor C2 in the charging module 105 . In this way, it is possible to avoid excessive capacitance at the second terminal of the DC current elimination module 106 and cause the elimination voltage to grow slowly, so as to speed up the rate at which the elimination voltage reaches the DC offset voltage.
  • the first control signal can also be used to control switching of the time constant of the second filtering module 111 , the control principle is like switching the time constant of the first filtering module 103 , so details will not be repeated here.
  • FIG. 9 is a schematic structural diagram of a fifth embodiment of a circuit for eliminating DC offset current provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an automatic gain adjustment module provided by an embodiment of the present application.
  • the DC offset current elimination circuit 100 of this embodiment further includes an automatic gain adjustment module 112 .
  • the input end of the automatic gain adjustment module 112 is connected to the second end of the DC current elimination module 106 to obtain the elimination voltage.
  • the output end of the automatic gain adjustment module 112 is connected to the first amplifying module 102 to control the gain of the first amplifying module 102 .
  • the automatic gain module 112 uses the DC offset current eliminated by the AOC loop as an input signal, uses the extinction ratio of the input signal to determine the proportional relationship between the DC offset current and the AC current, and replicates the AC current value through the current mirror.
  • the extinction ratio of the known input signal is ER (unit: decibel (dB))
  • the DC offset current eliminated by the AOC loop is Idc
  • the alternating current Iac input to the first amplifying module 102 at this time can be converted as :
  • the automatic gain adjustment module 112 of this embodiment includes a first branch 1121 and a second branch 1122, and controls the two branches of the first amplification module 102 respectively. gain gear.
  • the output of this branch is high level (that is, output digital "1"), the first The gain of the amplification module 102 is shifted.
  • the first branch 1121 includes a first current mirror 11211 , a third comparator 11212 and a third flip-flop 11213 .
  • the second branch 1122 includes a second current mirror 11221 , a fourth comparator 11222 and a fourth flip-flop 11223 .
  • the first current mirror 11211 replicates the DC offset current eliminated by the AOC loop at a first preset ratio by using the cancellation voltage, and then uses the copied DC offset current to mirror a corresponding AC current at a second preset ratio.
  • the AC circuit outputs a first mirror image voltage through the first load resistor.
  • the second current mirror 11221 outputs the second mirror voltage in the same way.
  • the third comparator 11212 compares the first mirror voltage with the third reference voltage, and outputs a fourth rising edge signal to the clock control terminal of the third flip-flop 11213 when the first mirror voltage is greater than the third reference voltage. After the third flip-flop 11213 is triggered by the fourth rising edge signal, it outputs a third high level signal (digital "1") and performs latching.
  • the fourth comparator 11222 compares the second mirror voltage with the third reference voltage, and outputs a fifth rising edge signal to the clock control terminal of the fourth flip-flop 11223 when the second mirror voltage is greater than the third reference voltage.
  • the third high-level signal output by the third flip-flop 11213 is used as the input of the fourth flip-flop 11223, that is, the first input terminal of the fourth flip-flop 11223 is used to receive the first Three high-level signals, the second input terminal of the fourth flip-flop 11223 is used to receive the reset signal.
  • the third flip-flop 11213 outputs the third high-level signal
  • the first input terminal of the fourth flip-flop 11223 is still at low level.
  • the fourth flip-flop 11223 outputs a low-level signal (outputs a digital "0").
  • the digital "1" output by the third flip-flop 11213 and the digital "0" output by the fourth flip-flop 11223 serve as the third control signal.
  • the fourth flip-flop 11223 After the fourth flip-flop 11223 is triggered by the fifth rising edge signal, and the first input terminal of the fourth flip-flop 11223 receives the third high level signal and is at high level, the output terminal of the fourth flip-flop 11223 outputs the fourth high level Level signal (digital "1") and latched. At this time, the digital "1" output by the third flip-flop 11213 and the digital "1" output by the fourth flip-flop 11223 serve as the fourth control signal.
  • the third control signal and the fourth control signal are used to control the gain level of the first amplifying module 102 . If the first mirror voltage and the second mirror voltage are greater than the third reference voltage, it means that the current signal output by the light detection module 101 is stronger, so the gain of the first amplification module 102 can be reduced to prevent its oversaturation from causing distortion of the output voltage signal. Therefore, the third control signal is used to control the gain of the first amplifying module 102 to switch from high gain to medium gain, and the fourth control signal is used to control the gain of the first amplifying module 102 to switch from medium gain to low gain. The third flip-flop is reset until the next reset signal arrives, and the first amplifying module returns to the highest gain.
  • the fourth control signal is also used to control the acceleration module 104 to switch states. Since the generation of the fourth signal can indicate that the current signal output by the photodetection module 101 is relatively strong, the DC offset voltage therein is also relatively large, so the DC offset voltage is also large. In order to speed up the charging efficiency of the charging module 105, it is necessary to improve the acceleration module. 104 is the target voltage provided by the charging module 105 .
  • the fourth control signal is specifically used to control the third switch S3 to be closed and the fourth switch S4 to be opened, so that the fourth capacitor C4 charges the charging module 105 .
  • the automatic gain adjustment module 112 When it is detected that the DC offset current eliminated by the AOC loop is greater than the current threshold, the automatic gain adjustment module 112 also outputs a fifth control signal.
  • the fifth control signal is used to control the acceleration module 104 to switch from the second state to the third state.
  • the current threshold can be any value in 1.2-1.8 milliamps (mA).
  • the gain of the first amplification module 101 and the state of the acceleration module 104 may also be controlled by a signal identification module (not shown).
  • the signal identification module is connected to the first amplification module 101 and the acceleration module 104 respectively.
  • the signal recognition module receives external input signals.
  • the external input signal can be a signal specially introduced, or a signal multiplexed on the reset signal.
  • the signal identification module can generate a corresponding control signal through the pulse width of the external input signal, and can also generate a corresponding control signal through the level, which is not limited here.
  • the pulse width of the external input signal is proportional to the intensity of the optical signal.
  • the level of the external input signal is proportional to the intensity of the optical signal.
  • the gain level of the first amplification module 101 has a mapping relationship with the level or pulse width of the external input signal.
  • the state of the acceleration module 104 has a mapping relationship with the level or pulse width of the external input signal.
  • the signal recognition module can generate a corresponding control signal according to the pulse width and level of the external input signal to switch the gain of the first amplification module 101 or determine the target state of the acceleration module 104 .
  • FIGS. 11 and 12 a simulation diagram of a fifth embodiment of the elimination circuit based on the DC offset current is provided, as shown in FIGS. 11 and 12 .
  • the abscissa is time
  • the ordinate is voltage or current.
  • Figure 11 shows the working process of the AOC loop when the burst mode signal (3mApp-3uApp-3mApp) is input, and the reset signal is active high.
  • the AC current in the current signal is 3mA
  • the second control signal output by the starting module 108 is high, and the AOC loop is turned on to eliminate the DC offset current.
  • the output gear signal of the automatic gain control module 112 is "11" (the fourth control signal, the lowest gain gear).
  • the time required for the AOC loop to draw the DC offset current stably that is, the elimination voltage is the same as the DC offset voltage
  • ns nanoseconds
  • Figure 12 shows the working process of the AOC loop when the burst mode signal (3mApp-300uApp-3mApp) is input.
  • the AOC loop When the input AC current is 300uApp, the AOC loop is in the open state.
  • the output gear signal of the automatic gain control module 112 is "10" (the third control signal, middle gain gear).
  • the AOC loop can draw a stable DC offset current of 14ns.
  • FIG. 13 is a schematic flowchart of the first embodiment of the method for eliminating the DC offset current provided by the present application. This embodiment is realized based on the above-mentioned first embodiment of the circuit for eliminating DC offset current. This embodiment includes the following steps:
  • the light detection module receives the light signal and converts the light signal into a current signal.
  • the first amplifying module receives the current signal and converts the current signal into a voltage signal.
  • the first filter module filters the DC offset voltage from the voltage signal.
  • the acceleration module provides the target voltage to the charging module.
  • the charging module outputs a elimination voltage to the DC current elimination module based on the target voltage and the offset DC voltage, wherein the elimination voltage is positively correlated with the target voltage and the DC offset voltage.
  • the direct current elimination module guides the direct current offset current in the current signal to ground through the first end and the third end of the direct current elimination module based on the elimination voltage.
  • S101-S106 in this embodiment can refer to the corresponding content of the first embodiment of the DC offset current elimination circuit, so it will not be repeated here.
  • the present application also provides a second embodiment of the method for eliminating the DC offset current.
  • This embodiment is realized based on the above-mentioned second embodiment of the circuit for eliminating DC offset current. Compared with the first embodiment of the method for eliminating DC offset current, this embodiment also includes before S103:
  • the deceleration module switches the time constant of the first filtering module to change the filtering time for filtering the DC offset voltage.
  • the present application also provides a third embodiment of the method for eliminating the DC offset current.
  • This embodiment is realized based on the above-mentioned third embodiment of the circuit for eliminating DC offset current. Compared with the first embodiment of the method for eliminating the DC offset current, this embodiment also includes before S104:
  • the present application also provides a fourth embodiment of the method for eliminating the DC offset current.
  • This embodiment is realized based on the above-mentioned fourth embodiment of the circuit for eliminating DC offset current. Compared with the first embodiment of the method for eliminating the DC offset current, this embodiment also includes before S104:
  • S404 the second amplifying module amplifies the DC offset voltage, and outputs the amplified DC offset voltage to the charging module.
  • the present application also provides a fifth embodiment of the method for eliminating the DC offset current.
  • This embodiment is realized based on the above-mentioned fifth embodiment of the circuit for eliminating DC offset current. Compared with the first embodiment of the method for eliminating DC offset current, this embodiment further includes:
  • the automatic gain control module controls switching the gain of the first amplifying module according to the magnitude of the DC offset current conducted by the DC current canceling module, and controls switching the state of the accelerating module.
  • An embodiment of the present application provides an optical receiver, and the optical receiver includes the DC offset current elimination circuit and the post-amplification circuit in any of the above embodiments.
  • the post-stage amplifying circuit is connected to the output terminal of the first amplifying module in the elimination circuit of the post-stage amplifying circuit DC offset current, so as to further amplify the voltage signal.
  • the post-amplification circuit is connected to the output end of the first amplification module in the DC offset current elimination circuit, and has further amplified the voltage signal to drive the data corresponding to the voltage signal to output from the optical receiver.
  • An embodiment of the present application provides an optical switch.
  • the optical switch includes the elimination circuit of the DC offset current in any of the above embodiments.
  • the post-stage amplifying circuit is connected to the output end of the DC offset current eliminating circuit, and the post-stage amplifying circuit is used to amplify the voltage signal output by the DC offset current eliminating circuit.
  • An embodiment of the present application provides a passive optical network system.
  • the passive optical network system includes an optical transmitter and the above-mentioned optical receiver.
  • the optical transmitter is used to send optical signals to the optical receiver.
  • the optical receiver receives the optical signal and converts the optical signal into a current signal.
  • the current signal includes the DC offset current.
  • the optical receiver includes the DC offset current elimination circuit in any of the above embodiments, and the optical receiver eliminates the DC offset current corresponding to the optical signal based on the elimination circuit.

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Abstract

本申请实施例公开了一种直流失调电流的消除电路、方法及相关设备，用于提高消除直流失调电流的精确度和速度。本申请消除电路包括的光检测模块用于输出电流信号；第一放大模块用于将电流信号转换并放大为电压信号；第一滤波模块用于从电压信号中过滤出直流失调电压；加速模块用于向充电模块提供目标电压；充电模块用于基于目标电压和失直流调电压输出消除电压；直流电流消除模块用于基于消除电压消除电流信号中的直流失调电流。

Description

直流失调电流的消除电路、方法、相关设备及系统
本申请要求于2021年7月6日提交中国国家知识产权局、申请号202110764123.2、申请名称为“直流失调电流的消除电路、方法、相关设备及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信领域，特别涉及一种直流失调电流的消除电路、方法、相关设备及系统。
背景技术
光纤通信的快速发展有力地推动了光通信产品的广泛应用。这对光通信产品的性能提出了苛刻的要求。光接收机中，光检测器将光信号转换为电流信号。放大器将电流信号转换为电压信号并放大。光检测器输出的电流信号中包括直流失调电流和交流电流。如果输入到放大器中的电流中有直流失调电流，会导致放大器输出的电压信号失真。因此，需要消除电流信号中的直流失调电流以使放大器输出的电压信号稳定和准确。
现有技术通过在放大器输出的电压信号中提取出失调电压，将失调电压施加到场效应管的栅极，导通场效应管以从放大器的输入端抽取直流失调电流，从而达到消除直流失调电流的目的。这么做，施加到场效应管的栅极的直流失调电压有个由零缓慢增长到失调电压的过程，导致场效应管的导通和抽取直流失调电流的速度慢。
发明内容
本申请实施例提供了一种直流失调电流的消除电路、方法、相关设备及系统，用于快速准确地消除光检测模块输出的直流失调电压。
本申请实施例第一方面提供一种直流失调电流的消除电路。该消除电路包括光检测模块、第一放大模块、第一滤波模块、加速模块、充电模块和直流电流消除模块。光检测模块分别与直流电流消除模块的第一端和第一放大模块连接。第一滤波模块与第一放大模块和充电模块连接。直流电流消除模块的第二端分别与加速模块和充电模块连接。直流电流消除模块的第三端接地。其中，光检测模块用于接收光信号并将光信号转换为电流信号。第一放大模块用于接收电流信号并将电流信号转换并放大为电压信号。第一滤波模块用于从电压信号中过滤出直流失调电压。加速模块用于向充电模块提供目标电压，提供目标电压。充电模块用于基于目标电压和失直流调电压向直流电流消除模块输出消除电压，其中，消除电压与目标电压和直流失调电压呈正相关关系。直流电流消除模块用于基于消除电压直流电流导通消除模块的第一端和第三端，从而电流信号中的直流失调电流经由直流电流消除模块的第一端和第三端导地。通过加速模块向充电模块分享电荷，相当于为充电模块输出了一个初始电压，以使充电模块电压得以迅速增长，以提高充电模块的充电效率，从而加快消除电压达到直流失调电压的速度。并且，由于消除电压与目标电压和直流失调电压呈正相关关系。当电流信号中的直流失调电流越大，对应的直流失调电压越大，消除电压也就越大，从而通过直流电流 消除模块流向地的直流失调电流也越大。通过直流电流消除模块流向地的直流失调电流被消除，实现了直流失调电流的准确消除。
在一种可能的设计中，本实施例的消除电路还包括加速模块。加速模块用于在目标状态下向充电模块提供目标电压。其中，加速模块具有多个状态，目标状态为多个状态中的一个，不同的状态对应不同的电压。加速模块不同的状态可以为充电模块提供不同的电压，从而提高充电模块的充电速率。
在一种可能的设计中，目标电压的值与直流失调电压的值正相关。在直流失调电压越大时，充电模块充电所需的时间就越长。那么为不同大小的直流失调电压提供不同的目标电压，能够提高各种情况下的充电模块的充电速率。
在一种可能的设计中，充电模块的电容量与目标电压的值负相关。如此保证充电模块和加速模块的时间常数不变，不因充电模块中电容量的增加而降低直流失调电压对充电模块的充电速率。
在一种可能的设计中，本实施例的消除电路还包括减速模块。其中，减速模块与第一滤波模块连接，减速模块用于控制第一滤波模块过滤电压信号的滤波时间。在减小第一滤波模块过滤电压信号的过滤时间时，能够快速使消除电压达到直流失调电压。在增加第一滤波模块过滤电压信号的过滤时间时，使消除电路更加稳定，抑制基线漂移。
在一种可能的设计中，本实施例的消除电路还包括启动模块和开关模块。其中，启动模块分别与第一滤波模块和开关模块连接，开关模块连接于第一滤波模块和直流电流消除模块的第二端之间，启动模块用于在确定直流失调电压大于或等于第一参考电压时，导通开关模块以使第一滤波模块和直流电流消除模块连接。启动模块能够使消除电路在直流失调电压不大于第一参考电压时，不启动直流电流消除模块，从而减小对光检测模块的干扰，提高光检测模块输出的信号的信噪比。
在一种可能的设计中，本实施例的消除电路还包括第二放大模块。其中，第二放大模块连接于第一滤波模块和直流电流消除模块之间，第二放大模块用于对直流失调电压进行放大，并用于将放大后的直流失调电压输出至充电模块。第二放大模块提高直流失调电压的增益，从而能够提高消除直流失调电流的精度。
在一种可能的设计中，本实施例的消除电路还包括第二滤波模块。其中，第二滤波模块连接于第二放大模块和直流电流消除模块之间，第二滤波模块用于对第二放大模块输出的放大后的直流失调电压进行过滤，并用于将过滤后的直流失调电压输出至充电模块。第二滤波模块使得输送至充电模块的电压更加稳定，从而稳定地消除直流失调电流，使得第一放大模块输出的电压信号准确和稳定。
本申请实施例第二方面提供一种直流失调电流的消除方法。该方法应用于直流失调电流的消除电路，消除电路包括光检测模块、第一放大模块、第一滤波模块、加速模块、充电模块和直流电流消除模块。其中，光检测模块分别与直流电流消除模块的第一端和第一放大模块连接。第一滤波模块与第一放大模块和充电模块连接。直流电流消除模块的第二端分别与加速模块和充电模块连接。直流电流消除模块的第三端接地。该方法包括：光检测模块接收光信号并将光信号转换为电流信号；第一放大模块接收电流信号并将电流信号转换为电压信号；第一滤波模块从电压信号中过滤出直流失调电压；加速模块向充电模块提供目标电压； 充电模块基于目标电压和失直流调电压向直流电流消除模块输出消除电压，其中，消除电压与目标电压和直流失调电压呈正相关关系；直流电流消除模块基于消除电压将电流信号中的直流失调电流经由直流电流消除模块的第一端和第三端导地。
在一种可能的设计中，加速模块向充电模块提供目标电压具体包括：加速模块目标状态下向充电模块提供目标电压。其中，加速模块具有多个状态。目标状态为多个状态中的一个，不同的状态对应不同的电压。
在一种可能的设计中，目标状态为加速模块的预设状态，且目标电压为多个状态对应的多个电压中的最小值。
在一种可能的设计中，目标电压的值与直流失调电压的值正相关。
在一种可能的设计中，消除电路还包括减速模块。该方法还包括：减速模块控制第一滤波模块过滤电压信号的滤波时间。
本申请实施例第二方面提供一种光接收机。该光接收机包括后级放大电路和上述第一方面或其任意一种具体设计所描述的直流失调电流的消除电路。后级放大电路连接于直流失调电流的消除电路的输出端，用于放大直流失调电流的消除电路输出的电压信号。
本申请实施例第三方面提供一种无源光网络系统。该无源光网络系统包括光发射机和上述第二方面所描述的光接收机。光发射机用于向光接收机发送光信号。光接收机用于消除光信号对应的直流失调电流。
附图说明
图1为本申请实施例提供的直流失调电流的消除电路的第一实施例的结构示意图；
图2为图1中的加速模块和充电模块的一种结构示意图；
图3为本申请实施例提供的直流失调电流的消除电路的第二实施例的结构示意图；
图4为图2中的减速模块的一种结构示意图；
图5为本申请实施例提供的直流失调电流的消除电路的第三实施例的结构示意图；
图6为本申请实施例提供的直流失调电流的消除电路的一具体实施方式的结构示意图；
图7为本申请实施例提供的直流失调电流的消除电路的第四实施例的结构示意图；
图8为图7中第二放大模块的一种结构示意图；
图9为本申请实施例提供的直流失调电流的消除电路的第五实施例的结构示意图；
图10为本申请实施例提供的自动增益调节模块的一种结构示意图；
图11为本申请提供的基于直流失调电流的消除电路的第五实施例的一仿真图；
图12为本申请提供的基于直流失调电流的消除电路的第五实施例的另一仿真图；
图13为本申请实施例提供的直流电流消除方法的一实施例的流程示意图。
具体实施方式
本申请实施例提供了一种直流失调电流的消除电路、方法、相关设备及系统。用于准确且快速地消除光检测器输出的直流失调电流。
无源光网(passive optical network，PON)包括光分配网络(optical distribution network，ODN)、局(中心局)侧的光线路终端(optical line terminal，OLT)和用户侧的光网络单元(optical  network unit，ONU)或者光网络终端(optical network terminal，ONT)等。OLT为PON系统提供网络侧接口，ONU为PON系统提供用户侧接口。ODN是由光纤和无源分光器件组成的网络，用于连接OLT和ONU，以及分发或复用OLT和ONU之间的数据信号。
每一个ONU的一次通讯信号称为一次突发光信号(以下简称光信号)。OLT侧的光接收机应当具有快速捕获一定动态范围内光信号的能力。
图1为本申请提供的直流失调电流的消除电路的第一实施例的结构示意图。如图1所示，直流失调电流的消除电路100包括光检测模块101、第一放大模块102、第一滤波模块103、加速模块104、充电模块105和直流电流消除模块106。光检测模块101分别与直流电流消除模块106的第一端和第一放大模块102连接。第一滤波模块103与第一放大模块102和充电模块105连接。直流电流消除模块106的第二端分别与加速模块104和充电模块105连接。直流电流消除模块106的第三端接地。
具体地，光检测模块101的输出端分别与直流电流消除模块106的第一端和第一放大模块102的输入端连接。第一放大模块102的输出端与第一滤波模块103的输入端连接，第一滤波模块103的输出端分别连接直流电流消除模块106的第二端、充电模块105的第一端和加速模块104的第一端。直流电流消除模块106的第三端、充电模块105的第二端和加速模块104的第二端接地。第一放大模块102、第一滤波模块103、加速模块104、充电模块105和直流电流消除模块106构成了自动失调消除(adaptive offset cancellation，AOC)环路。以下对AOC环路所包括的各个器件进行说明。
光检测模块101可以是光电二极管(photo diode，PD)。PD是一个工作在反偏状态下的PN二极管。例如，雪崩二极管(avalanche photo diode，APD)或PIN型二极管。对此，本申请不做限制。光检测模块101用于接收光信号并将光信号转换为电流信号。需要说明的是，光检测模块101输出的电流信号中，包括交流电流和直流失调电流。
第一放大模块102将光检测模块101输出的电流信号转换并放大为电压信号，并将该电压信号输出。电压信号中包括交流电压和直流失调电压。交流电压为交流电流经第一放大模块102转换和放大后输出的。直流失调电压为直流失调电流经第一放大模块102转换和放大后输出的。第一放大模块102可以是跨阻放大器(trans-impedance amplifier，TIA)、低阻放大器或高阻放大器等。对此，本申请不做限制。
第一滤波模块103将第一放大模块102输出的电压信号中的交流电压过滤掉，输出直流失调电压。第一滤波模块103包括第一滤波器1031。第一滤波器1031可以为电阻-电容滤波器或电感-电容滤波器(图未示)。如无特殊说明，本申请中的滤波器可以是电阻-电容滤波器、电感-电容滤波器或电阻-电感-电容滤波器等低通滤波器。对此，本申请不做限制。
图6是本申请实施例提供的直流失调电流的消除电路的一具体实施方式的结构示意图。需要说明的是，图6中的直流失调电流的消除电路仅作为一个示例，不作为本申请技术方案的限制。如图6所示，第一滤波器1031为电阻-电容滤波器时，具体可以包括第一电阻R1和第一电容C1。第一电阻R1的第一端连接第一放大模块102的输出端。第一电阻R1的第二端分别连接第一电容C1的第一端、直流电流消除模块106的第二端、充电模块105的第一端和加速模块104的第一端。第一电容C1的第二端接地。其中，第一滤波器1031可以为一个时间常数较小的滤波器，以提高对电压信号的过滤速率。具体地，第一电阻R1大小可以 为3000欧姆-8000欧姆之间的任一值，例如可以为5000欧姆。第一电容C1大小可以为200法拉-300法拉之间的任一值，例如可以为250法拉。
第一滤波模块103输出的直流失调电压用于为充电模块105充电。充电模块105能够为直流电流消除模块106的第二端提供消除电压。
图2是本申请提供的加速模块和充电模块的一种结构示意图。图2中加速模块104和充电模块105的电容数量仅作为示例，电容还可以是1个，2个、4个或者更多，对此不做限制。如图2所示，充电模块105例如包括第二电容C2。第二电容C2的第一端分别与第一滤波模块103的输出端、直流电流消除模块106的第二端和加速模块104的第一端连接。第二电容C2的第二端接地。第二电容C2利用第一滤波模块103输出的直流失调电压为自身充电，第二电容C2则相当于成为了一个电源，能够为直流电流消除模块106的第二端提供电压。第二电容C2的电压与直流电流消除模块106的第二端的电压(消除电压)相同。
在直流失调电压产生的初始阶段，由于充电模块105中第二电容C2的电容特性，直流失调电压从对充电模块105由0伏(V)开始充电，到最终充电模块105的电压与直流失调电压达到一致存在过渡过程。也即，充电模块105的电压不会由0V瞬间到达直流失调电压的电压值，而是由0V缓慢增长到直流失调电压的电压值。充电模块105的电压充到直流失调电压所需时间较长，因此，本申请利用加速模块104加快充电模块105的充电速率。
具体而言，如图2所示，加速模块104包括第三电容C3、第一开关S1和第二开关S2。第三电容C3的第一端通过第一开关S1分别连接第二电容C2的第一端和直流电流消除模块106的第二端。第三电容C3的第一端还通过第二开关S2连接第一电源，第三电容C3的第二端接地。当第一开关S1断开，第二开关S2闭合时，第一电源为第三电容C3提供第一预设电压，以使第三电容C3的第一端存储有电荷。
当第一开关S1闭合，第二开关S2断开时，第二电容C2的第一端和第三电容C3的第一端连通。第三电容C3为第二电容C2充电以提供目标电压。第三电容C3为第二电容C2充电的过程实际可解释为第三电容C3为第二电容C2分享电荷的过程。具体地，当第二电容C2的第一端和第三电容C3的第一端连通，相当于第二电容C2与第三电容C3并联。由于第二电容C2的第一端在初始阶段电荷为0，第三电容C3的第一端的电荷量大于第二电容C2第一端的电荷量，则第三电容C3的第一端的电荷向第二电容C2的第一端移动，并且电荷在第二电容C2和第三电容C3之间能够迅速达到平衡。第二电容C2的第一端存储电荷，从而第二电容C2的电压由0V迅速变为目标电压。当然，在第三电容C3为第二电容C2充电期间，直流失调电压也在为第二电容C2充电，但由于第三电容C3为第二电容C2充电的时间较短，在此期间直流失调电压为第二电容C2提供的电荷相较于第三电容C3为第二电容C2提供的电荷可以忽略不计。
初始阶段目标电压的计算公式如下：
Figure PCTCN2022103815-appb-000001
其中，U为目标电压。U 2为C2的初始电压，视为0V。C 2为C2的电容量。U 3为C3的第一预设电压。C 3为C3的电容量。Q为C2和C3的总电荷量。C为C2和C3的总电容量。 由于C2和C3并联，所以Q为C2的电荷量和C3的电荷量之和，C为C2的电容量和C3的电容量之和。
本申请实施例通过加速模块104为充电模块105充电，能够使充电模块105的电压瞬间达到目标电压，相当于为充电模块105提供了初始电压。节省了充电模块105由直流失调电压从0V充到目标电压所需的时间，加快了充电模块105的充电速率，使充电模块105的电压的值能够更快地达到直流失调电压的值。
为使充电模块105的电压在稳定后能够与直流失调电压相同，加速模块104提供的目标电压不大于直流失调电压。直流失调电压与光检测模块101输出的直流失调电流正相关，直流失调电流与光信号的强度正相关。光信号有不同的强度，因而直流失调电压也有不同大小的值。若加速模块104提供的目标电压过大，在直流失调电压较小的情况下则目标电压有可能大于直流失调电压。若加速模块104提供的目标电压过小，在直流失调电压较大的情况下则加速模块104的加速程度有限。
因此，本申请实施例中的加速模块104进一步可以具有多种状态，以为充电模块105提供相应的电压。从加速模块104的多种状态中确定目标状态，进而为充电模块105提供对应的目标电压。每一状态对应于加速模块104中携带不同电荷量的电容连接充电模块105，具体例如加速模块104在不同状态下有不同数量的电容与充电模块连接。
加速模块104的目标状态可以为预设状态。预设状态为默认的初始状态。为确保目标电压不大于直流失调电压，预设的状态对应的目标电压为多个电压中的最小值。请参阅图2，预设的状态例如为第一开关S1闭合、第二开关S2断开情况下C3与C2连接的状态。
加速模块104的多个状态中除预设状态以外的其他状态下，状态对应的电压的值与直流失调电压的值正相关。即，直流失调电压越大，加速模块104提供的目标电压也越大。
加速模块104的其他状态可以是在预设状态的基础上切换的。具体而言，加速模块104包括多个携带电荷的电容。由预设状态切换至其他状态时，在预设状态的基础上，增加一个或多个携带电荷的电容连接到充电模块105。
本实施例以加速模块104包括预设状态、第一动态状态和第二动态状态这3种状态举例说明。如图2所示，加速模块104包括第三电容C3、第一开关S1、第二开关S2、第四电容C4、第三开关S3、第四开关S4、第五电容C5、第五开关S5和第六开关。第三电容C3、第一开关S1和第二开关S2的连接方式与上述的相同，故在此不再赘述。第四电容C4的第一端通过第三开关S3分别连接第二电容C2的第一端、第三电容C3的第一端和直流电流消除模块106的第二端，第四电容C4的第一端还通过第四开关S4连接第二电源，第四电容C4的第二端接地。第五电容C5的第一端通过第五开关S5分别连接第二电容C2的第一端、第三电容C3的第一端、第四电容C4的第一端和直流电流消除模块106的第二端，第五电容C5的第一端还通过第六开关连接第三电源，第五电容C5的第二端接地。
当直流失调电流的消除电路100未接收光信号时，第一开关S1、第三开关S3和第五开关S5断开，第二开关S2、第四开关S4和第六开关S6闭合。该情况下，第一电源为第四电容C4提供第一预设电压，以使第三电容C3的第一端存储电荷；第二电源为第四电容C4提供第二预设电压，以使第四电容C4的第一端存储电荷；第三电源为第五电容C5提供第三预设电压，以使第五电容C5的第一端存储电荷。第一预设电压、第二预设电压和第三预设电 压之间可以均相同、部分相同或者完全不同。当直流失调电流的消除电路100接收光信号时，根据目标状态确定第一开关S1至第六开关S6的闭合或断开。
可选地，为使加速模块104与充电模块105之间存在电势差，使加速模块104能够为充电模块105提供更多的电荷，第一预设电压、第二预设电压和第三预设电压可以均大于直流失调电压。当然，第一至第三预设电压也可以不大于直流失调电压，加速模块104在目标状态下，加速模块104的初始电压大于充电模块105的电压即可。
预设状态下，第一开关S1、第四开关S4和第六开关闭合，第二开关S2、第三开关S3和第五开关S5断开，第三电容C3的第一端和第二电容C2的第一端连通，第三电容C3为第二电容C2充电以提供目标电压。
第一动态状态下，第一开关S1、第三开关S3和第六开关闭合，第二开关S2、第四开关S4和第五开关S5断开，第四电容C4的第一端和第二电容C2的第一端、第三电容C3的第一端连通，第四电容C4为第二电容C2充电以提供目标电压。
第二动态状态下，第一开关S1、第三开关S3和第五开关S5闭合，第二开关S2、第四开关S4和第六开关断开，第五电容C5的第一端和第二电容C2的第一端、第三电容C3的第一端和第四电容C4的第一端连通，第五电容C5为第二电容C2充电以提供目标电压。
需要说明的是，本申请实施例所述的目标电压是指加速模块104为充电模块105加速的整个过程中，加速模块104整体为充电模块105提供的电荷量，充电模块105基于该电荷量所增长的电压。例如，预设状态下C3已在先为C2充电并达到平衡，后续切换第二状态时，C4继续为C2充电，那么第一动态下的目标电压是指C3和C4为C2提供的电荷量之和使C2增长的电压。同理，第二动态下的目标电压是指C3、C4和C5为C2提供的电荷量之和使C2所增长的电压。
由于加速模块104将带电荷的电容与充电模块105连接从而为充电模块105充电，相当于在充电模块105中并联了一个或多个电容。如此增大了充电模块105的电容量，使得AOC环路和充电模块105的时间常数变大，会在一定程度上减缓直流失调电压为充电模块105充电的速率。因而，本申请实施例在加速模块104连接目标电容量的电容为充电模块105充电的过程中，充电模块105的总电容量中减少目标电容量。一般地，加速模块104中每一电容的预设电压固定的情况下，加速模块104连接到充电模块105的电容的电容量越大，能够为充电模块105提供的电荷量越大，为充电模块105提供的目标电压也就越大，充电模块105需要减少的目标电容量越大，充电模块105的剩余的电容量也就越小。
减小充电模块105的电容量的方式有多种。
例如，可以减少充电模块105中接入的电容的数量。充电模块105还包括一个或多个除第二电容C2以外的并联电容。每一并联电容的第一端通过开关与第二电容C2的第一端连接，每一并联电容的第二端接地。在初始状态下，每一并联电容的第一端的开关闭合，第二电容C2与并联电容并联连接。当加速模块104切换状态，新增加速模块104中一个或多个电容连接到充电模块105时，充电模块105断开一个或多个与并联电容连接的开关以减少充电模块105的电容量，使得充电模块105减少的电容量与加速模块104新连接到充电模块105的电容的电容量相同。
举例说明，如图2所示，充电模块105例如还包括第六电容C6、第七开关S7、第七电容 和第八开关S8。第六电容C6的第一端通过第七开关S7连接第二电容C2的第一端。第七电容的第一端通过第八开关S8连接第二电容C2的第一端，第六电容C6和第七电容的第二端接地。第四电容C4、第五电容C5、第六电容C6和第七电容的电容量例如均为1.5皮法。初始状态下，加速模块104处于预设状态，第一开关S1、第七开关S7和第八开关S8闭合，第二开关S2断开，第三电容C3的第一端连接第二电容C2的第一端、第六电容C6的第一端和第七电容的第一端，第三电容C3为第二电容C2、第六电容C6和第七电容充电。若加速模块104由预设状态切换到第一动态状态，第三开关S3闭合、第四开关S4断开，第四电容C4的第一端与充电模块105的第一端连接以为充电模块105充电，充电模块105则断开第七开关S7，加速模块104的电容量增加1.5皮法，充电模块105的电容量减少1.5皮法。加速模块104由第一动态切换到第二动态同理。
还例如，第二电容C2为可变电容。随着加速模块104中与充电模块105连接的电容的电容量的增加，第二电容C2随之相应减小相等的电容量。该情况下，充电模块105中第二电容C2不需要并联电容。
当然，加速模块104切换状态的过程中，还可以不改变充电模块105的电容量大小，通过保持加速模块104中与充电模块105连接的电容的电容量不变实现AOC环路的时间常数不变，以保证直流失调电压对充电模块的充电速率。
如图2所示，示例地，C3、C4和C5的电容量均为1.5皮法。初始状态下，加速模块104处于预设状态，第一开关S1闭合，第二开关S2断开，第三电容C3的第一端连接第二电容C2的第一端，第三电容C3为第二电容C2充电，电荷并且迅速在两者间达到平衡。若加速模块104由预设状态切换到第二状态，第三开关S3闭合、第四开关S4断开，第四电容C4的第一端与充电模块105的第一端连接以为充电模块105充电。加速模块104此过程中还断开第一开关S1以断开第三电容C3与充电模块105的连接，加速模块104新增第四电容C4、电容量增加1.5皮法，加速模块104断开第三电容C3、电容量减小1.5皮法。加速模块104的电容量保持不变，充电模块105及AOC环路的电容量不变。
加速模块104的目标状态也可以是直接确定的，而无需基于上一状态进行切换(如上述的第一动态状态基于预设状态切换，第二动态状态基于第一动态状态切换)。具体而言，直流失调电压的大小与直流失调电流正相关，而直流失调电流与光信号强度正相关。也就是说，光信号的光功率越大，直流失调电压也就越大，加速模块104需要为充电模块105提供的电压也就越大。因而，可以基于光信号的光功率确定加速模块104的目标状态。也即，加速模块104一次性为充电模块105提供相应的电荷量，无需分次向充电模块105充电。
例如，AOC所集成的芯片根据光功率生成复位(reset)信号。光功率的大小与复位信号的脉冲宽度大小正相关，或者与复位信号的电平大小正相关。进而，根据复位信号的宽度和电平确定加速模块104的目标状态。例如，复位信号的电平为0.1-0.3分贝(dB)时对应于加速模块104的的第一状态。复位信号的电平为0.4-0.6dB时对应于加速模块104的第二状态。复位信号的电平为0.7-1.0dB时对应于加速模块104的第三状态。当复位信号的电平为0.8dB时，确定加速模块104的目标状态为第三状态，则直接控制加速模块104处于第三状态，而无需由第一状态切换到第二状态，再由第二状态切换为第三状态。
加速模块104为充电模块105提供目标电压的方式有多种。例如，加速模块104不同状 态对应加速模块104中与充电模块105连接的电容的不同数量。通过控制加速模块中连接充电模块105的电容的数量，以向充电模块105提供相应的目标电压。或者，加速模块104包括多个携带不同电荷量的电容，每一状态对应其中一个电容与充电模块105接通，以向充电模块105提供相应的目标电压。
直流电流消除模块106的第二端的消除电压与充电模块105的电压相同。充电模块105在充电过程中的电压由目标电压和直流失调电压共同决定。消除电压的大小与目标电压和直流失调电压正相关。
直流电流消除模块106可以是压控电流源，当直流电流消除模块106的第二端的电压达到阈值时，直流电流消除模块106的第一端和第三端导通，使得光检测模块101输出的电流信号中的至少部分直流失调电流通过直流电流消除模块106的第一端和第三端流向地，从而消除电流信号中的至少部分直流失调电流，减小流入到第一放大模块102中的直流失调电流。直流电流消除模块106可以包括场效应管。场效应管可以是P型或N型，本申请对此不做限制。直流电流消除模块106消除的直流失调电流与消除电压的关系如下：
I dc＝gm·U VG
其中，I dc为直流电流消除模块106消除的直流失调电流，gm为场效应管的跨导，U VG为消除电压。
如图6所示，以P型场效应管为例说明，场效应管的栅极为直流电流消除模块106的第二端，源极和漏极分别为直流电流消除模块106的第三端和第一端。场效应管的源极和漏极之间具有通直流电阻隔交流电的特性，因而光检测模块101输出的电流信号中的直流电流能够通过场效应管流向地，电流信号中的交流电流则输入到第一放大模块102。
当然，直流电流消除模块106还可以是电流控制电流源。直流电流消除模块106例如包括三极管(图未示)和电压电流转换器(图未示)。三极管可以是NPN型或PNP，本申请对此不做限制。
无论是哪种类型的直流电流消除模块106，均由消除电压控制其第一端和第三端的导通，以及经过直流电流消除模块106第一端和第三端流向地的直流失调电流的大小。在一定的电压范围内，消除电压越大，经过电流消除模块第一端和第三端流出的直流失调电流也越大。消除电压达到直流失调电压时，理论上光检测模块101输出的电流信号中的直流失调电流几乎被消除。消除电压与直流失调电压相等后，直流电流消除模块106第二端的电压不再增长，稳定在直流失调电压对应的值，直流电流消除模块106从电流信号中抽取的直流失调电流的趋于稳定，第一放大模块102输出的电压信号也更加准确和稳定。因而，本申请实施例利用加速模块104提高充电模块105的充电速率，使消除电压快速地达到直流失调电压，从而直流电电流消除模块能够更加快速、稳定地从电流信号中抽取直流失调电流，达到快速、准确地消除直流失调电流的目标。
光检测模块101接收到的光信号对应的数据帧中包括前导码和数据码。前导码封装于数据码之前，前导码用于指示时钟同步计时，数据码中携带有需要传输的数据。因此，光检测模块101接收到前导码对应的光信号的时间早于接收数据码对应的光信号的时间，前导码对应的电流信号输入到AOC环路的时间也早于数据码对应的电流信号输入到AOC环路的时间。 并且，相较于第一放大模块102输出的前导码对应的电压信号，数据码对应的电压信号的准确性和稳定性具有更高的要求。
图3为本申请提供直流电流的消除电路的第二实施例的结构示意图。与直流失调电流的消除电路100的第一实施例不同的是，本实施例的消除电路100还包括减速模块107。如图3所示，减速模块107与第一滤波模块103连接，用于控制第一滤波模块103的时间常数大小，从而控制过滤电压信号的滤波时间。
具体地，在数据码对应的电流信号输入到AOC环路之前，减速模块107控制第一滤波模块103处于小时间常数的状态，以减小电压信号的滤波时间，从而使直流电流消除模块106的第二端的消除电压能够快速达到直流失调电压，使AOC环路快速稳定。待光检测模块101输出数据码对应的电流信号时，直流电流消除模块106能够准确地从电流信号中抽取出直流失调电流，从而使输入到第一放大模块102的电流信号更加准确，第一放大模块102输出的电压信号也更加稳定和准确。AOC环路中其他模块的时间常数不变，改变第一滤波模块103的时间常数，即相当于改变AOC环路的时间常数。需要说明的是，大时间常数和小时间常数是两者间相对而言的，并非对应于某一具体时间常数值。
在数据码对应的电流信号输入到AOC环路时，减速模块107控制第一滤波模块103处于大时间常数状态。相较于小时间常数的状态，大时间常数的状态增加了电压信号的过滤时间，减缓了电压信号的过滤速度，从而提高AOC环路的稳定性，使第一放大模块102输出的电压信号稳定，抑制基线漂移。
减速模块107通过生成并向第一滤波模块103输出的第一控制信号来控制第一滤波模块103大时间常数和小时间常数之间的切换。减速模块107利用前导码到来前芯片产生的复位信号生成第一控制信号。其中，芯片是指减速模块107和AOC环路所集成的芯片。复位信号的下降沿对应的时刻，与光检测模块101输出前导码的第一比特电流信号的上升沿对应的时刻相同。
具体而言，减速模块107对复位信号重新整形，将复位信号的下降沿进行延时得到第一控制信号。第一控制信号的下降沿对应的时刻，早于光检测模块101输出数据码电流信号的上升沿对应的时刻。第一控制信号处于高电平时，第一滤波模块103处于小时间常数状态；第一控制信号处于低电平时，第一滤波模块103处于大时间常数状态。
图4为图2中的减速模块的一种结构示意图。如图4所示，减速模块107包括第二滤波器1701、整形器1702、第一触发器1703、第一反相器1704、第三滤波器1705、第一比较器1076和第九开关S9。第二滤波器1701的输入端用于接收复位信号，输出端连接整形器1702的输入端。整形器1702的输出端连接第一触发器1703的时钟控制端，第一输入端连接第四电源，第二输入端用于接收复位信号，输出端连接第一反相器1704的输入端和第九开关S9的控制端。第四电源用于维持第一输入端处于高电平状态。第一反相器1704的输出端连接第三滤波器1705的输入端。第三滤波器1705的输出端连接第一比较器1076的第一输入端。第一比较器1076的第二输入端用于接收第二参考电压，输出端连接第一滤波模块103。第九开关S9的一端连接第三滤波器1705的输入端，另一端连接第三控制器的输出端。其中，第一触发器1703器为下降沿触发器。
第二滤波器1701的时间常数小于第三滤波器1705的时间常数。第二滤波器1701的主要 作用为，使复位信号的下降沿到达第一触发器的时钟控制端晚于复位信号的下降沿到达第一触发器第二输入端。从而复位信号的下降沿到达第一触发器的时钟控制端时，第一触发器第二输入端恢复为低电平。
第一控制信号的生成过程如下。当复位信号的上升沿输入到第一触发器1703的第二输入端时，触发第一触发器1703的输出端输出第一下降沿信号。第一下降沿信号触发第九开关S9闭合，将第三滤波器1705短路。第一反相器1704的将第一下降沿信号反转为第一上升沿信号，并且将第一上升沿信号经过第九开关S9输入到第一比较器1076的第一输入端。第一比较器1076比较第一上升沿信号和第二参考电压，并在第一上升沿信号电压值大于第二参考电压的电压值时输出第一控制信号的上升沿。当复位信号的下降沿到来时，第一触发器1703的第二输入端恢复为低电平；第二滤波器1701对复位信号的下降沿进行第一次延时，由于经过第二滤波器1701输入的复位信号下降沿变缓，复位信号的波形不再表现为方波，因而将延时、变缓后的复位信号的下降沿经过整形器1702整形输出为方波的下降沿。整形后的复位信号的下降沿输入到第一触发器1703的时钟控制端，由于此时第一触发器1703的第一输入端为高电平，第二输入端为低电平，整形后的复位信号的下降沿触发第一触发器1703输出第二上升沿信号。第二上升沿信号触发第九开关S9断开，第三滤波器1705接入第一反相器1704的输出端。第一反相器1704将第二上升沿信号反转为第二下降沿信号，并且将第二下降沿信号输入到第三滤波器1705。第三滤波器1705对第二下降沿信号进行延时，并将延时后的第二下降沿信号输出至第一比较器1076的第一输入端。第一比较器1076比较第二下降沿信号和第二参考电压，并在第二下降沿信号电压值小于第二参考电压的电压值时输出第一控制信号的下降沿。
第一控制信号可以通过改变第一滤波模块103的电阻大小控制第一滤波模块103的大小时间常数的切换。本实施例以第一滤波模块103为电阻-电容滤波器进行举例说明。
例如，可以通过增加或减小第一滤波模块103中的接入AOC环路的电阻数量，来改变第一滤波模块103的电阻大小。如图6所示，第一滤波模块103例如包括第一电阻R1、第二电阻R2、第十开关S10和第一电容C1。第一电阻R1的输入端连接第一放大模块102的输出端，第一电阻R1的输出端连接第二电阻R2的输入端。第二电阻R2的输出端分别连接第一电容C1的第一端、充电模块105的第一端、加速模块104的第一端和直流电流消除模块106的第二端。第一电容C1的第二端接地。第十开关S10一端连接第一电阻R1的输入端、另一端连接第一电阻R1的输出端。第十开关S10的控制端连接减速模块107。
第十开关S10的控制端接收到减速模块107发出的第一控制信号后，第十开关S10的控制端处于高电平状态，触发闭合第十开关S10，将第一电阻R1短路。此时第一滤波模块103电阻变小，时间常数变小，使得第一滤波模块和AOC环路处于小时间常数状态。
第一控制信号消失后，第十开关S10的控制端恢复为低电平状态，触发断开第十开关S10，第一电阻R1接入AOC环路。此时第一滤波模块103电阻变大，时间常数变大，使得第一滤波模块和AOC环路处于大时间常数状态。
还例如，可以通过改变第一滤波模块103中某一电阻的大小来改变第一滤波模块103的电阻大小。第一滤波模块103例如包括第一电阻R1和第一电容C1。第一电阻R1的第一端连接第一放大模块102的输出端。第一电阻R1的第二端分别连接第一电容C1的第一端、直 流电流消除模块106的第二端、充电模块105的第一端和加速模块104的第一端，第一电容C1的第二端接地。其中，第一电阻R1为可变电阻，第一电阻R1还连接减速模块107的输出端。当第一电阻R1接收到第一控制信号时，减小第一电阻R1的电阻值，以使第一滤波模块103处于小时间常数状态。当第一控制信号消失时，增大第一电阻R1的电阻值，以使第一滤波模块103处于大时间常数状态。
图5为本申请实施例提供的直流失调电流的消除电路的第三实施例的结构示意图。如图5所示，消除电路100还包括启动模块108和开关模块109。启动模块108用于控制开关模块109的开合，以控制AOC环路是否工作。由于光检测模块101开始接收光信号时，对电路中的噪声十分敏感，若此时AOC环路工作会使光检测模块101接收到不必要的噪声。图5所示的实施例能够提高光检测模块101输出的电流信号的信噪比。
具体地，如图5所示，启动模块108的输入端连接第一滤波模块103的输出端。启动模块108的输出端连接开关模块109的控制端，并且开关模块109连接于第一滤波模块103和直流电流消除模块106的第二端之间。启动模块108从第一滤波模块103获取直流失调电压，并比较直流失调电压和第一参考电压。在直流失调电压大于第一参考电压时，输出第二控制信号。第二控制信号用于控制开关模块109导通第一滤波模块103和直流电流消除模块106的第二端，以启动AOC环路，使AOC环路工作。在直流失调电压不大于第一参考电压时，开关模块109为断开状态，第一滤波模块103和直流电流消除模块106的第二端之间的连接断开，AOC环路不工作。
如图6所示，启动模块108可以包括第二比较器1081、与门单元1082和第二触发器1083。开关模块109可以包括第十一开关S11和第十二开关S12。第二比较器1081的第一输入端连接第一滤波模块103的输出端。第二比较器1081的第二输入端用于接收预设电压。第二比较器1081的输出端连接与门单元1082的第一输入端。与门单元1082的第二输入端连接减速模块107的输出端，用于接收第一控制信号。与门单元1082的输出端连接第二比较器1081的时钟控制端。第二比较器1081的第一输入端连接第五电源，第二比较器1081的第二输入端用于接收复位信号，第二比较器1081的输出端连接第十一开关S11和第十二开关S12的控制端。第二触发器1083为上升沿触发器。第五电源用于使第二触发器1083的第一输入端保持高电平。第十一开关S11的一端连接充电模块105的第一端、加速模块104的第一端和第一滤波模块103的第一端，第十一开关S11的另一端连接第十二开关S12的一端和直流电流消除模块106的第二端。第十二开关S12的另一端接地。
第二比较器1081比较直流失调电压与第一参考电压的大小，在直流失调电压大于第一参考电压时，第二比较器1081向与门单元1082输出第一高电平信号。与门单元1082的第一输入端接收到第一高电平信号处于高电平，且其第二输入端接收到第一控制信号也处于高电平时，输出第三上升沿信号到第二触发器1083的时钟控制端。由于第二触发器1083的第一输入端处于高电平，第三上升沿信号触发第二触发器1083输出第二高电平信号。第二高电平信号用于控制第十一开关S11闭合，第十二开关S12断开，使得直流电流消除模块106的第二端与充电模块105的第一端、加速模块104的第一端和第一滤波模块103的第一端连通，以启动AOC环路。
与门单元1082在第一高电平信号和第一控制信号均有效时才输出第三上升沿信号，可以 防止光检测模块101在未接收到突发信号而接收噪声时，输出电流信号错误地导致AOC环路启动。第一控制信号是在光检测模块101接收突发信号时产生的，因而启动模块108将第一控制信号作为必要条件能够保证AOC环路不会在错误的时间启动。第二比较器1081输出第一高电平信号，一方面说明直流失调电压也就是直流失调电流较大，需要启动AOC环路消除直流失调电流；另一方面说明光检测模块101输出的电流信号强度较大，此时启动AOC环路所造成的噪声对光检测模块101影响较小，可以启动AOC环路。
第二控制信号还可以用于控制加速模块104处于预设状态。启动模块108的输出端还连接第一开关S1和第二开关S2的控制端。当第一开关S1和第二开关S2接收到第二控制信号时，闭合第一开关S1，断开第二开关S2，使第二电容C2与充电模块105连接从而为充电模块105提供目标电压。
第十二开关S12在光信号结束后到来的复位信号的控制下闭合，以将充电模块105中的电荷释放到地，使充电模块105的电压在下一个光信号到来前恢复到初始状态，即0V。
图7为本申请实施例提供的直流失调电流的消除电路的第四实施例的结构示意图。图8为图7中第二放大模块的一种结构示意图。如图7所示，本实施例的直流失调电流的消除电路100还包括第二放大模块110。第二放大模块110连接于第一滤波模块103和充电模块105的第一端之间。具体地，第二放大模块110的输入端连接第一滤波模块103的输出端，第二放大模块110输出端连接充电模块105的第一端。
第二放大模块110用于对第一滤波模块103输出的直流失调电压进行放大，将放大后的直流失调电压输出至充电模块105。第二放大模块110能够提高直流失调电压的范围，如此能够更加精确地控制直流电流消除模块106抽取的直流电流的大小。
为了提高AOC环路稳定的速率，第二放大模块110可以为高速放大器。如图8所示，第二放大模块110可以包括多个反相器，每一反相器由一个P型场效应管和一个N型场效应管并联而成。反相器的输入端为两个反相器的栅极，反相器的输出端为两个反相器的漏极。反相器中的N型场效应管的第一源极接工作电压，P型场效应管的第二源极接地。当反相器中的两个场效应管都工作在饱和区时就能实现放大功能。
第二放大模块110可以由三级反相器级联的方式增加AOC环路的增益，使得环路消除直流电流足够精确。第一级反相器1101的输入端连接第一滤波模块103的输出端，第一级反相器1101的输出端连接第二级反相器1102的输入端，第二级反相器1102的输出端连接第三级反相器1103的输入端，第三级反相器1103的输出端连接充电模块105的第一端。
其中，每一级反相器均可以包括1个反相器和至少1个负载。各级反相器中的至少1个负载分别与该级的反相器并联，以放大直流失调电压。第一级反相器1101和第二级反相器1102用于稳住共模点，第三级反相器1103可以采用较大的尺寸保证高的放大速度。
以第一级反相器1101包括第一反相器11011、第一负载11012、第二负载11013和第三负载11014，第二级反相器1102包括第二反相器11021和2个负载，第三级反相器1103包括第三反相器11031进行举例说明。当然，第一级反相器1101中负载的数量还可以是2个、4个或者更多。第二级反相器1102中负载的数量还可以是2个、3个或更多，本申请对此不做限制。第三级反相器1103也可以包括1个或多个负载。
在光检测模块101由10G模式切换至2.5G模式或处于慢速-慢速工艺角(slow-slow  corner,SScorner)的情况下，因为第一放大模块102的增益变大，为了保持AOC环路的整体增益不变，可以降低第二放大模块110的增益，保证AOC环路的稳定性。
第二放大模块110可以支持至少两个增益模式。具体可以通过调整第一级反相器1101的增益来调整第二放大模块110的增益。本实施例以第一级反相器1101支持三个增益模式举例说明，当然第一级反相器1101还可以支持2个、4个或更多的增益模式，具体可根据第一级反相器1101中的负载的数量以及实际的增益需求确定，本申请对此不做限制。
如图8所示，第一级反相器1101还包括第十三开关S13、第十四开关S14、第十五开关S15和第十六开关S16。第二负载11013的第一源极通过第十三开关S13连接第六电源，第二负载11013的第二源极通过第十四开关S14接地。第三负载11014的第一源极通过第十五开关S15连接第七电源，第三负载11014的第二源极通过第十六开关S16接地。第六电源用于为第二负载11013提供工作电压，第七电源用于为第三负载11014提供工作电压。
第二放大模块110处于高增益模式时，第十三开关S13、第十四开关S14、第十五开关S15和第十六开关S16均闭合。第二放大模块110处于中增益模式时，第十三开关S13和第十四开关S14断开使第二负载11013不工作，第十五开关S15和第十六开关S16闭合。第二放大模块110处于低增益时，第十三开关S13、第十四开关S14、第十五开关S15和第十六开关S16均断开使第二负载11013和第三负载11014均不工作。
当然，也可以通过调控第二级反相器和第三级反相器中工作的负载的数量，来调控第二放大模块110的增益，本申请对此不做限制。
可选地，如图6-7所示，直流失调电流的消除电路100还包括第二滤波模块111。第二滤波模块111连接于第二放大模块110和充电模块105的第一端之间，用于稳定第二放大模块110输出的放大后的直流失调电压，以稳定直流电流消除模块106的第二端的电压。
第二滤波模块111具体可以为滤波器。第二滤波模块111包括电容。第二滤波模块111与充电模块105共享电容，即第二滤波模块111包括充电模块105中的第二电容C2。如此，能够避免直流电流消除模块106的第二端存在过多电容而造成消除电压增长慢，以加快消除电压达到直流失调电压的速率。
第一控制信号还可以用于控制切换第二滤波模块111的时间常数，控制原理如切换第一滤波模块103的时间常数，故在此不再赘述。
图9为本申请实施例提供的直流失调电流的消除电路的第五实施例的结构示意图。图10为本申请实施例提供的自动增益调节模块的一种结构示意图。如图9所示，本实施例的直流失调电流的消除电路100还包括自动增益调整模块112。自动增益调整模块112的输入端连接直流电流消除模块106的第二端，以获取消除电压。自动增益调整模块112的输出端连接第一放大模块102，以控制第一放大模块102的增益。
自动增益模块112采用AOC环路消除的直流失调电流作为输入信号，利用输入信号的消光比确定直流失调电流和交流电流之间的比例关系，通过电流镜复制镜像出交流电流的值。当已知输入信号的消光比为ER(单位：分贝(dB))，AOC环路消除的直流失调电流为I dc时，可换算出此时输入到第一放大模块102的交流电流I ac为：
Figure PCTCN2022103815-appb-000002
Figure PCTCN2022103815-appb-000003
因为电流信号的强度的动态范围大，为了提高电流镜像的准确性，本实施例的自动增益调整模块112包括第一支路1121和第二支路1122，并且分别控制第一放大模块102的两个增益档位。当第一支路1121或第二支路1122镜像的交流电流流经电阻产生的电压高于第三参考电压值时，该支路输出为高电平(即输出数字“1”)，第一放大模块102的增益换档。
如图10所示，第一支路1121包括第一电流镜11211、第三比较器11212和第三触发器11213。第二支路1122包括第二电流镜11221、第四比较器11222和第四触发器11223。其中，第一电流镜11211利用消除电压以第一预设比例复制出AOC环路消除的直流失调电流，然后利用复制出的直流失调电流以第二预设比例镜像出对应的交流电流。交流电路经过第一负载电阻，输出第一镜像电压。第二电流镜11221按照同样的方式输出第二镜像电压。第三比较器11212比较第一镜像电压和第三参考电压，在第一镜像电压大于第三参考电压时，输出第四上升沿信号到第三触发器11213的时钟控制端。第三触发器11213被第四上升沿信号触发后，输出第三高电平信号(数字“1”)并进行锁存。
第四比较器11222比较第二镜像电压和第三参考电压，在第二镜像电压大于第三参考电压时，输出第五上升沿信号到第四触发器11223的时钟控制端。为了避免第一放大模块102的增益越档触发，第三触发器11213输出的第三高电平信号作为第四触发器11223的输入，即第四触发器11223的第一输入端用于接收第三高电平信号，第四触发器11223的第二输入端用于接收复位信号。
因此，在第三触发器11213输出第三高电平信号时，第四触发器11223的第一输入端尚处于低电平。第四触发器11223输出低电平信号(输出数字“0”)。此时，第三触发器11213输出的数字“1”和第四触发器11223输出的数字“0”作为第三控制信号。
第四触发器11223被第五上升沿信号触发后，并且第四触发器11223的第一输入端接收到第三高电平信号处于高电平时，第四触发器11223的输出端输出第四高电平信号(数字“1”)并进行锁存。此时，第三触发器11213输出的数字“1”和第四触发器11223输出的数字“1”作为第四控制信号。
第三控制信号和第四控制信号用于控制第一放大模块102的增益档次。第一镜像电压、第二镜像电压大于第三参考电压说明光检测模块101输出的电流信号较强，因此可以降低第一放大模块102的增益防止其过饱和导致输出的电压信号失真。因而，第三控制信号用于控制第一放大模块102的增益由高增益切换到中增益，第四控制信号用于控制第一放大模块102的增益由中增益切换到低增益。直到下个复位信号到来时第三触发器进行复位，第一放大模块恢复为最高增益。
第四控制信号还用于控制加速模块104切换状态。由于第四信号的产生能够说明光检测模块101输出的电流信号较强，其中的直流失调电压也相应较大，因此直流失调电压也就大，为了加快充电模块105的充电效率，需要提高加速模块104为充电模块105提供的目标电压。第四控制信号具体用于控制第三开关S3闭合、第四开关S4断开，使第四电容C4为充电模块105充电。
当检测到AOC环路消除的直流失调电流大于电流阈值时，自动增益调整模块112还输出第五控制信号。第五控制信号用于控制加速模块104从第二状态切换到第三状态。其中，电流阈值可以为1.2-1.8毫安(mA)中的任意值。
在另一些实施方式中，第一放大模块101的增益和加速模块104的状态还可以是由信号识别模块(图未示)控制的。信号识别模块分别与第一放大模块101和加速模块104连接。信号识别模块接收外部输入信号。外部输入信号可以是专门引入的信号，也可以复用在复位信号上的信号。信号识别模块可以通过外部输入信号的脉冲宽度生成相应的控制信号，也可以通过电平生成相应的控制信号，此处不限。
具体地，外部输入信号的脉冲宽度与光信号的强度成正比。或者外部输入信号的电平与光信号的强度成正比信号。第一放大模块101的增益等级与外部输入信号的电平或脉冲宽度具有映射关系。加速模块104的状态与外部输入信号的电平或脉冲宽度具有映射关系。信号识别模块根据外部输入信号的脉冲宽度和电平即可生成相应的控制信号，以切换第一放大模块101的增益，或确定加速模块104的目标状态。
为了更直观地说明本申请实施例的有益效果，提供基于直流失调电流的消除电路的第五实施例的仿真图，如图11和12所示。其中，横坐标为时间，纵坐标为电压或电流。
图11展示了突发模式信号(3mApp-3uApp-3mApp)输入时AOC环路的工作过程，其中复位信号为高有效。当电流信号中的交流电流为3mA时，启动模块108输出的第二控制信号为高，开启AOC环路进行直流失调电流的消除。自动增益控制模块112输出档位信号为“11”(第四控制信号，最低增益档)。当输入交流电流为3mA时，AOC环路稳定抽取直流失调电流(即消除电压与直流失调电压相同)所需的时间为17纳秒(ns)。当交流电流为3uApp时，启动模块108输出的第二控制信号为低，AOC环路不工作，AGC输出档位信号为“00”(最高增益档)。
图12展示了突发模式信号(3mApp-300uApp-3mApp)输入时AOC环路的工作过程，当输入交流电流为300uApp时，AOC环路为开启状态。自动增益控制模块112输出档位信号为“10”(第三控制信号，中增益档)。当输入AC电流为300uApp时，AOC环路稳定抽取直流失调电流为14ns。
图13是本申请提供的直流失调电流的消除方法的第一实施例的流程示意图。本实施例是基于上述的直流失调电流的消除电路第一实施例实现的。本实施例包括如下步骤：
S101：光检测模块接收光信号并将光信号转换为电流信号。
S102：第一放大模块接收电流信号并将电流信号转换为电压信号。
S103：第一滤波模块从电压信号中过滤出直流失调电压。
S104：加速模块向充电模块提供目标电压。
S105：充电模块基于目标电压和失直流调电压向直流电流消除模块输出消除电压，其中，消除电压与目标电压和直流失调电压呈正相关关系。
S106：直流电流消除模块基于消除电压将电流信号中的直流失调电流经由直流电流消除模块的第一端和第三端导地。
本实施例S101-S106的具体内容可以参阅直流失调电流的消除电路第一实施例对应内容，故在此不再赘述。
本申请还提供直流失调电流的消除方法的第二实施例。本实施例是基于上述的直流失调电流的消除电路第二实施例实现的。本实施例相较于直流失调电流的消除方法的第一实施例，在S103之前，还包括：
S203：减速模块切换第一滤波模块的时间常数，以改变过滤直流失调电压的过滤时间。
具体内容可以参阅直流失调电流的消除电路第二实施例对应内容，故在此不再赘述。
本申请还提供直流失调电流的消除方法的第三实施例。本实施例是基于上述的直流失调电流的消除电路第三实施例实现的。本实施例相较于直流失调电流的消除方法的第一实施例，在S104之前，还包括：
S304：启动模块在确定直流失调电压大于或等于预设电压时，导通开关模块以使第一滤波模块和直流电流消除模块连接。具体内容可以参阅直流失调电流的消除电路第三实施例对应内容，故在此不再赘述。
本申请还提供直流失调电流的消除方法的第四实施例。本实施例是基于上述的直流失调电流的消除电路第四实施例实现的。本实施例相较于直流失调电流的消除方法的第一实施例，在S104之前，还包括：
S404：第二放大模块放大直流失调电压，并用于将放大后的直流失调电压输出至充电模块。
具体内容可以参阅直流失调电流的消除电路第四实施例对应内容，故在此不再赘述。
本申请还提供直流失调电流的消除方法的第五实施例。本实施例是基于上述的直流失调电流的消除电路第五实施例实现的。本实施例相较于直流失调电流的消除方法的第一实施例，本实施例还包括：
S507：自动增益控制模块根据直流电流消除模块导地的直流失调流的大小控制切换第一放大模块的增益，以及控制切换加速模块的状态。
具体内容可以参阅直流失调电流的消除电路第五实施例对应内容，故在此不再赘述。
本申请实施例提供一种光接收机，该光接收机包括上述任意实施例中的直流失调电流的消除电路和后级放大电路。后级放大电路连接于后级放大电路直流失调电流的消除电路中第一放大模块的输出端，以对电压信号进行进一步放大。
具体地，后级放大电路连接于直流失调电流的消除电路中的第一放大模块的输出端，已对电压信号进行进一步放大，以驱动电压信号对应的数据从光接收机输出。
本申请实施例提供一种光交换机。该光交换机包括上述任意实施例中的直流失调电流的消除电路。后级放大电路连接于直流失调电流的消除电路的输出端，后级放大电路用于放大直流失调电流的消除电路输出的电压信号。
本申请实施例提供一种无源光网络系统。该无源光网络系统包括光发射机和上述的光接收机。光发射机用于向光接收机发送光信号。光接收机接收光信号，并将光信号转换为电流信号。电流信号中包括直流失调电流。光接收机包括上述任意实施例中的直流失调电流的消除电路，光接收机基于该消除电路消除光信号对应的直流失调电流。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只 是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (16)

  1. 一种直流失调电流的消除电路，其特征在于，所述消除电路包括光检测模块、第一放大模块、第一滤波模块、加速模块、充电模块和直流电流消除模块，其中：
    所述光检测模块分别与所述直流电流消除模块的第一端和所述第一放大模块连接，所述第一滤波模块与所述第一放大模块和所述充电模块连接，所述直流电流消除模块的第二端分别与所述加速模块和所述充电模块连接，所述直流电流消除模块的第三端接地；
    所述光检测模块，用于接收光信号并将所述光信号转换为电流信号；
    所述第一放大模块，用于接收所述电流信号并将所述电流信号转换并放大为电压信号；
    所述第一滤波模块，用于从所述电压信号中过滤出直流失调电压；
    所述加速模块，用于向所述充电模块提供目标电压；
    所述充电模块，用于基于所述目标电压和所述失直流调电压向所述直流电流消除模块输出消除电压，其中，所述消除电压与所述目标电压和所述直流失调电压呈正相关关系；
    所述直流电流消除模块，用于基于所述消除电压将所述电流信号中的直流失调电流经由所述直流电流消除模块的所述第一端和所述第三端导地。
  2. 根据权利要求1所述的电路，其特征在于，所述加速模块，用于在目标状态下向所述充电模块提供所述目标电压，其中，所述加速模块具有多个状态，所述目标状态为所述多个状态中的一个，不同的所述状态对应不同的电压。
  3. 根据权利要求2所述的电路，其特征在于，所述目标状态为所述加速模块的预设状态，且所述目标电压的值为所述多个状态对应的多个电压中的最小值。
  4. 根据权利要求1或2所述的电路，其特征在于，所述目标电压的值与所述直流失调电压的值正相关。
  5. 根据权利要求4所述的电路，其特征在于，所述充电模块的电容量与所述目标电压的值负相关。
  6. 根据权利要求1至5任一项所述的电路，其特征在于，所述消除电路还包括减速模块，所述减速模块与所述第一滤波模块连接，所述减速模块用于控制所述第一滤波模块过滤所述电压信号的滤波时间。
  7. 根据权利要求1至6任一项所述的电路，其特征在于，所述消除电路还包括启动模块和开关模块，所述启动模块分别与所述第一滤波模块和所述开关模块连接，所述开关模块连接于所述第一滤波模块和所述直流电流消除模块的第二端之间，所述启动模块用于在确定所述直流失调电压大于或等于第一参考电压时，导通所述开关模块以使所述第一滤波模块和所述直流电流消除模块连接。
  8. 根据权利要求1至7任一项所述的电路，其特征在于，所述消除电路还包括第二放大模块，所述第二放大模块连接于所述第一滤波模块和所述直流电流消除模块之间，所述第二放大模块用于放大所述直流失调电压，并用于将放大后的所述直流失调电压输出至所述充电模块。
  9. 根据权利要求8所述的电路，其特征在于，所述消除电路还包括第二滤波模块，所述第二滤波模块连接于所述第二放大模块和所述直流电流消除模块之间，所述第二滤波模块用于对所述第二放大模块输出的放大后的所述直流失调电压进行过滤，并用于将过滤后的所述 直流失调电压输出至所述充电模块。
  10. 一种直流失调电流的消除方法，其特征在于，应用于直流失调电流的消除电路，所述消除电路包括光检测模块、第一放大模块、第一滤波模块、加速模块、充电模块和直流电流消除模块,所述光检测模块分别与所述直流电流消除模块的第一端和所述第一放大模块连接，所述第一滤波模块与所述第一放大模块和所述充电模块连接，所述直流电流消除模块的第二端分别与所述加速模块和所述充电模块连接，所述直流电流消除模块的第三端接地；
    所述光检测模块接收光信号并将所述光信号转换为电流信号；
    所述第一放大模块接收所述电流信号并将所述电流信号转换为电压信号；
    所述第一滤波模块从所述电压信号中过滤出直流失调电压；
    所述加速模块向所述充电模块提供目标电压；
    所述充电模块基于所述目标电压和所述失直流调电压向所述直流电流消除模块输出消除电压，其中，所述消除电压与所述目标电压和所述直流失调电压呈正相关关系；
    所述直流电流消除模块基于所述消除电压将所述电流信号中的直流失调电流经由所述直流电流消除模块的所述第一端和所述第三端导地。
  11. 根据权利要求10所述的方法，其特征在于，所述加速模块向所述充电模块提供目标电压包括：
    处于目标状态下的所述加速模块向所述充电模块提供所述目标电压，其中，所述加速模块具有多个状态，所述目标状态为所述多个状态中的一个，不同的所述状态对应不同的电压。
  12. 根据权利要求11所述的方法，其特征在于，所述目标状态为所述加速模块的预设状态，且所述目标电压的值为所述多个状态对应的多个电压中的最小值。
  13. 根据权利要求11所述的方法，其特征在于，所述目标电压的值与所述直流失调电压的值正相关。
  14. 根据权利要求10至13中任一项所述的方法，其特征在于，所述消除电路还包括减速模块，所述方法还包括：
    所述减速模块控制所述第一滤波模块过滤所述电压信号的滤波时间。
  15. 一种光接收机，其特征在于，包括后级放大电路和如权利要求1至9任一所述的直流失调电流的消除电路，所述后级放大电路连接于所述直流失调电流的消除电路的输出端，所述后级放大电路用于放大所述直流失调电流的消除电路输出的电压信号。
  16. 一种无源光网络系统，其特征在于，包括光发射机和如权利要求15所述的光接收机，所述光发射机用于向所述光接收机发送光信号，所述光接收机用于消除所述光信号对应的直流失调电流。
PCT/CN2022/103815 2021-07-06 2022-07-05 直流失调电流的消除电路、方法、相关设备及系统 WO2023280142A1 (zh)

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