WO2023279838A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023279838A1
WO2023279838A1 PCT/CN2022/091989 CN2022091989W WO2023279838A1 WO 2023279838 A1 WO2023279838 A1 WO 2023279838A1 CN 2022091989 W CN2022091989 W CN 2022091989W WO 2023279838 A1 WO2023279838 A1 WO 2023279838A1
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WIPO (PCT)
Prior art keywords
contact
layer
contact hole
substrate
region
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PCT/CN2022/091989
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English (en)
French (fr)
Inventor
张书浩
李宁
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长鑫存储技术有限公司
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Publication of WO2023279838A1 publication Critical patent/WO2023279838A1/zh
Priority to US18/166,022 priority Critical patent/US20230187522A1/en

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Definitions

  • the present disclosure relates to the technical field of integrated circuits, in particular to a semiconductor structure and a manufacturing method thereof.
  • MOSFETs Metal-oxide-semiconductor field-effect transistors
  • other components are commonly used in semiconductor manufacturing processes. They are usually heavily doped in the active region to form source and drain regions, and deep source regions are formed. And the conductive contact structure of the drain region, so as to realize the connection of the current (conduction current) between the source region and the drain region with the outside.
  • a semiconductor structure and fabrication method thereof are provided.
  • a semiconductor structure including a substrate, a contact hole, a barrier layer, and a conductive contact structure,
  • the substrate includes an active region, and a drain region and a source region are formed in the active region;
  • the contact hole extends from the surface of the substrate to at least one of the source region and the drain region;
  • the barrier layer is located on the bottom surface of the conductive contact structure
  • the conductive contact structure fills the contact hole and includes a contact layer contacting at least one of the source region and the drain region.
  • the base includes a substrate and a dielectric layer
  • the substrate includes the active region
  • the dielectric layer is located on the substrate
  • the contact hole extends from the surface of the dielectric layer to the At least one of the source region and the drain region extends.
  • the barrier layer is located inside the contact hole.
  • the contact hole extends from the surface of the substrate to the active region below at least one of the source region and the drain region, and the barrier layer covers the contact hole and extends to the active region. A portion within the active region outside at least one of the source region and the drain region.
  • the contact layer is located between the contact hole and at least one of the source region and the drain region.
  • the conductive contact structure further includes a conductive metal structure, the conductive metal structure fills the contact hole, and the contact layer is located between the conductive metal structure and the source region and the drain region. At least one of the barrier layers is between the conductive metal structure and the active region below the contact hole.
  • the material of the conductive metal structure is at least one of tungsten, molybdenum and aluminum.
  • the material of the contact layer is metal silicide.
  • a method for fabricating a semiconductor structure including:
  • the substrate includes an active region, and a drain region and a source region are formed in the active region;
  • the contact hole extending from a surface of the substrate to at least one of the source region and the drain region;
  • the barrier layer is located on the bottom surface of the conductive contact structure, the conductive contact structure fills the contact hole, and includes a contact layer, and the contact layer contacts at least one of the source region and the drain region.
  • the base includes a substrate and a dielectric layer
  • the substrate includes the active region
  • the dielectric layer is located on the substrate
  • the contact hole extends from the surface of the dielectric layer to the At least one of the source region and the drain region extends.
  • the barrier layer is located inside the contact hole.
  • the formation of the barrier layer includes:
  • a barrier material layer is formed on the inner wall of the contact hole based on a first mask, the first mask has a first opening, and the first opening exposes the contact hole;
  • At least part of the barrier material layer located on the sidewall of the contact hole is removed, and the remaining barrier material layer constitutes the barrier layer.
  • the forming the barrier material layer on the inner wall of the contact hole based on the first mask includes:
  • a barrier material layer is deposited on the inner wall of the contact hole by atomic layer deposition.
  • the removing at least part of the barrier material layer located on the sidewall of the contact hole includes:
  • the barrier material layer is etched by isotropic etching.
  • the forming the conductive contact structure includes:
  • a contact material layer is formed on the sidewall of the contact hole and the barrier layer, the second mask has a second opening, and the second opening exposes the contact hole;
  • the contact material layer is diffused to at least one of the source region and the drain region to react and crystallize with it, so as to form a contact layer.
  • the material of the contact layer is metal silicide.
  • the conductive contact structure further includes a conductive metal structure, and the contact material layer is diffused to at least one of the source region and the drain region and reacted with it to form a contact layer. Afterwards, said forming the conductive contact structure also includes:
  • the conductive metal structure is filled in the contact hole.
  • the material of the conductive metal structure is at least one of tungsten, molybdenum and aluminum.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the barrier layer is located on the bottom surface of the conductive contact structure. At this time, the contact layer can form a good ohmic contact with the source region and/or the drain region through the side surface, so as to perform good current transmission, thereby effectively reducing the lateral on-resistance, thereby effectively increasing the on-current.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure provided in an embodiment
  • FIGS. 2-7 are structural schematic diagrams during the manufacturing process of the semiconductor structure provided in an embodiment
  • FIG. 8 is a schematic structural diagram of a semiconductor structure provided in an embodiment
  • FIG. 9 is a schematic structural diagram of a semiconductor structure provided in another embodiment.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure such that variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
  • the fabrication process of the conductive contact structure is generally as follows: first, contact holes extending to the source region and the drain region are formed, and then a layer of cobalt (Co) is deposited in the contact holes. Subsequently, heat treatment is carried out to make Co diffuse into the source region and the drain region (the material is usually heavily doped silicon), and react with it to form a cobalt silicide (CoSi) contact layer, so that the conductive contact structure can communicate with the surrounding through CoSi. A good ohmic contact is formed between the source region and the drain region, thereby effectively reducing the contact resistance between the conductive contact structure and the source region and the drain region.
  • Co cobalt
  • the conductive contact structure may exceed the source and drain doped regions and be connected to the substrate, thereby increasing the leakage current.
  • the present disclosure provides an improved conductive contact structure, a semiconductor structure with improved device performance and a manufacturing method thereof.
  • a method for manufacturing a semiconductor structure including:
  • Step S100 providing a substrate 100, the substrate 100 includes an active region 111, a drain region 1112 and a source region 1111 are formed in the active region 111, please refer to FIG. 2;
  • Step S200 forming a contact hole 100a in the substrate 100, the contact hole 100a extending from the surface of the substrate 100 to at least one of the source region 1111 and the drain region 1112, please refer to FIG. 3;
  • Step S300 forming a barrier layer 200, please refer to FIG. 5;
  • Step S400 forming a conductive contact structure 300, please refer to FIG. 8;
  • the barrier layer 200 is located on the bottom surface of the conductive contact structure 300 , the conductive contact structure 300 fills the contact hole 100 a, and includes a contact layer 310 , and the contact layer 310 contacts at least one of the source region 1111 and the drain region 1112 .
  • the active region 111 may be a P-type active region, or an N-type active region.
  • the P-type active region can form an NMOS device, and the N-type active region can form a PMOS device.
  • base 100 may include substrate 110 .
  • the substrate 110 may include, but is not limited to, a silicon substrate.
  • a P-type well region or an N-type well region may be formed in the substrate 110 , and a shallow trench isolation structure may be formed.
  • the shallow trench isolation structure isolates the P-type well region or the N-type well region into a plurality of P-type active regions or N-type active regions arranged at intervals.
  • the two sides of the active region 111 can be heavily doped by means of ion implantation, so as to form a drain region 1112 and a source region 1111 .
  • Both sides of the P-type active region can be heavily doped with N-type, thereby forming a drain region 1112 and a source region 1111; both sides of the N-type active region can be heavily doped with P-type, thereby forming a drain region 1112 and a source region 1111.
  • a patterned mask layer may first be formed on the surface of the substrate 100 .
  • the patterned mask layer has a mask opening exposing the surface of the substrate, and the mask opening defines the shape and position of the contact hole 100a. Then, the substrate 100 is etched based on the patterned mask layer to form a contact hole 100a.
  • the blocking layer 200 is an insulating dielectric layer that can block current transmission.
  • the barrier layer 200 can be made of silicon dioxide, silicon nitride or silicon oxynitride.
  • the material of the contact layer 310 may be, but not limited to, metal silicide (such as CoSi), which can form a good ohmic contact with the source region 1111 and the drain region 1112 .
  • the barrier layer 200 is formed before the conductive contact structure 300 is formed.
  • the barrier layer 200 is located on the bottom surface of the conductive contact structure 300, thereby effectively preventing the contact layer 310 from concentrating under the conductive contact structure.
  • the contact layer 310 can form a good ohmic contact between the side and at least one of the source region 1111 and the drain region 1112, so as to perform good current transmission, thereby effectively reducing the lateral resistance, thereby effectively increasing the source-drain current. .
  • the contact hole 100a may be formed simultaneously with other through holes at other positions on the same wafer.
  • the openings in the patterned mask layer can also define the shape and position of other through holes with other functions. Then, the contact hole 100a and other via holes can be formed simultaneously based on the patterned mask layer.
  • the depth that the contact hole 100a needs to extend in at least one of the source region 1111 and the drain region 1112 may be relatively large, and may even pass through the source region 1111 and the drain region 1111.
  • At least one of the regions 1112 extends to the active region below at least one of the source region 1111 and the drain region 1112 , resulting in a risk of electrical leakage between the conductive contact structure 300 and the substrate.
  • the barrier layer 200 is formed before the conductive contact structure 300 is formed.
  • the barrier layer 200 is located on the bottom surface of the conductive contact structure 300 , thereby effectively reducing the risk of electric leakage between the conductive contact structure 300 and the substrate.
  • the contact hole 100a can also be formed separately, and this disclosure is not limited thereto.
  • the base 100 includes a substrate 110 formed with an active region 111 . Meanwhile, the base 100 also includes a dielectric layer 120 on the substrate 110 . The contact hole 100 a extends from the surface of the dielectric layer 120 to at least one of the source region 1111 and the drain region 1112 .
  • the contact hole 100 a is formed after the dielectric layer 120 is formed on the substrate 110 , and then the contact hole 100 a is formed, thereby facilitating unified processing and manufacturing of multiple devices.
  • the present disclosure is not limited thereto.
  • the base 100 may only include the substrate 110 .
  • the barrier layer 200 is located inside the contact hole 100a. At this time, the barrier layer 200 may be conveniently formed on the bottom surface of the conductive metal structure 300 .
  • step S300 may include:
  • Step S310 based on the first mask, a barrier material layer 201 is formed on the inner wall of the contact hole 100a, the first mask has a first opening, and the first opening exposes the contact hole 100a, please refer to FIG. 4;
  • step S320 at least part of the barrier material layer 201 located on the sidewall of the contact hole 100 a is removed, and the remaining barrier material layer 201 constitutes the barrier layer 200 , please refer to FIG. 5 .
  • the first mask may be a reticle having a first opening, which may cover the surface of the substrate 100 before performing step S310.
  • the mask only exposes the contact hole 100a, so that a barrier material layer 201 is formed on the inner wall of the contact hole 100a.
  • the first mask may also be the patterned mask layer described above for forming the contact hole 100a. That is, after the contact hole 100a is formed through the patterned mask layer in step S200, the barrier material layer 201a is formed on the inner wall of the contact hole 100a by using it as the first mask.
  • step S320 after removing part of the barrier material layer 201 located on the sidewall of the contact hole 100a, the formed barrier layer 200 is located inside the contact hole 100a and at the bottom thereof.
  • a barrier layer can be provided 200 covers the contact hole 100a extending to the part in the active region 111 outside at least one of the source region 1111 and the drain region 1112, thereby effectively preventing the conductive contact structure 300 from interfering with at least one of the source region 1111 and the drain region 1112.
  • the other active regions 111 are in contact with each other, so as to better prevent electric leakage between the conductive contact structure 300 and the electrodes at the bottom of the substrate.
  • the barrier layer 200 can also be formed in other ways, for example, after the contact hole 100a is formed, a thermal oxidation process is performed to oxidize the hole wall of the contact hole 100a to form an oxide layer, and then remove the The oxide layer on the sides and the oxide layer remaining on the bottom constitute the barrier layer 200 . At this time, the barrier layer 200 is located outside the contact hole 100a and connected to the contact hole 100a.
  • step S310 includes: depositing a barrier material layer 201 on the inner wall of the contact hole 100a by atomic layer deposition based on the first mask, see FIG. 4 .
  • a good-quality barrier material layer 201 can be formed by means of atomic layer deposition.
  • an anisotropic barrier material layer 210 can be grown in the contact hole 100a by using atomic layer deposition.
  • the inner wall of the contact hole 100a includes a bottom wall and side walls.
  • the thickness of the barrier material layer 201 formed on the bottom wall of the contact hole 100a is greater than the thickness of the barrier material layer 201 formed on the side wall of the contact hole 100a.
  • the ratio of the thickness of the barrier material layer 201 formed on the bottom wall of the contact hole 100 a to the thickness of the barrier material layer 201 formed on the side wall of the contact hole 100 a can be controlled within a range of 4:1 to 6:1.
  • the ratio of the thickness of the barrier material layer 201 formed on the bottom wall of the contact hole 100 a to the thickness of the barrier material layer 201 formed on the side wall of the contact hole 100 a can be controlled at about 5:1.
  • step S320 at this time may include: etching the barrier material layer 201 by isotropic etching, please refer to FIG. 5 .
  • the etching speed of the barrier material layer 201 in each direction is the same. Therefore, at this time, the entire barrier material layer 201 will be etched.
  • the thickness of the barrier material layer 201 formed on the side wall of the contact hole 100a is smaller than that of the barrier material layer 201 formed on the bottom wall of the contact hole 100a, after the barrier material layer 201 on the side wall of the contact hole 100a is etched, Part of the barrier material layer 201 on the bottom wall of the contact hole 100a still remains. The remaining part of the barrier material layer 201 constitutes the barrier layer 200 .
  • the barrier material layer 201 on the sidewall of the contact hole 100a can also be removed by other methods. In other methods, the barrier material layer 201 on the bottom wall of the contact hole 100a may not be removed. Alternatively, in other embodiments, the barrier material layer 201 may also be deposited on the inner wall of the contact hole 100a by other methods. The present disclosure is not limited in any respect.
  • step S400 includes:
  • Step S410 based on the second mask, forming a contact material layer 311 on the sidewall of the contact hole 100a and the barrier layer 200, the second mask has a second opening, the second opening exposes the contact hole 100a, please refer to FIG. 6;
  • step S420 the contact material layer 311 is diffused to at least one of the source region 1111 and the drain region 1112 to react and crystallize therewith, so as to form the contact layer 310 , please refer to FIG. 7 .
  • step S410 the second mask and the first mask in step S310 may be the same mask. Of course, the two may also be different masks.
  • the material contacting the raw material layer 311 may be a metal material such as cobalt.
  • step S420 heat treatment may be performed on the structure in which the contact material layer 311 is formed on the inner wall of the contact hole 100a, so that the contact material layer 311 diffuses to at least one of the source region 1111 and the drain region 1112 to react and crystallize with it, to form contact layer 310 .
  • the material of the contact layer 310 may be metal silicide such as cobalt silicide.
  • the contact material layer 311 that has not diffused into at least one of the source region 1111 and the drain region 1112 can remain as an integral part of the conductive contact structure 300 (not shown).
  • the contact material layer 311 not forming the contact layer 310 may also be removed, and the present disclosure is not limited thereto.
  • the contact layer 310 formed in this embodiment is located between the contact hole 100 a and at least one of the source region 1111 and the drain region 1112 , that is, the contact layer 310 is formed outside the contact hole 100 a.
  • the contact layer 310 may also be formed on the inner wall of the contact hole 100a if possible, and the present disclosure is not limited thereto.
  • the conductive contact structure 300 further includes a conductive metal structure 320 .
  • step S400 also includes:
  • Step S430 filling the contact hole 100 a with the conductive metal structure 320 , please refer to FIG. 8 .
  • the material of the conductive metal structure 320 can be at least one of tungsten, molybdenum, aluminum, etc., which can connect the current of at least one of the source region 1111 and the drain region 1112 to the outside.
  • the contact layer 310 is located between the conductive metal structure 320 and at least one of the source region 1111 and the drain region 1112 .
  • the barrier layer 200 is located between the conductive metal structure 320 and the active region 111 located below the contact hole 100a.
  • a semiconductor structure including a substrate 100 , a contact hole 100 a , a barrier layer 200 and a conductive contact structure 300 .
  • the substrate 100 includes an active region 111 .
  • a drain region 1112 and a source region 1111 are formed in the active region 111 .
  • the contact hole 100 a extends from the surface of the substrate 100 to at least one of the source region 1111 and the drain region 1112 .
  • the barrier layer 200 is located on the bottom surface of the conductive contact structure 300 .
  • the conductive contact structure 300 fills the contact hole 100 a and includes a contact layer 310 that contacts at least one of the source region 1111 and the drain region 1112 .
  • the barrier layer 200 is located on the bottom surface of the conductive contact structure 300, thereby effectively preventing the contact layer 310 from concentrating under the conductive contact structure 300.
  • the contact layer 310 can form a good ohmic contact between the side and at least one of the source region 1111 and the drain region 1112, so as to perform good current transmission, thereby effectively reducing the lateral resistance, thereby effectively increasing the source-drain current. .
  • the base 100 includes a substrate 110 and a dielectric layer 120 .
  • the substrate 110 includes an active region 111 .
  • the dielectric layer 120 is located on the substrate 110 .
  • the contact hole 100 a extends from the surface of the dielectric layer 120 to at least one of the source region 1111 and the drain region 1112 .
  • the barrier layer 200 is located inside the contact hole 100a.
  • the contact hole 100a extends from the surface of the substrate 100 to the active region 111 below at least one of the source region 1111 and the drain region 1112, and the barrier layer 200 is thicker than the contact hole 100a extending to the source region 1111 and the drain region 1112. The depth within active region 111 below at least one of regions 1112 (see FIG. 9 ).
  • the contact layer 310 is located between the contact hole 100 a and at least one of the source region 1111 and the drain region 1112 .
  • the conductive contact structure 300 further includes a conductive metal structure 320 .
  • the conductive metal structure 320 fills the contact hole 100 a, and the contact layer 310 is located between the conductive metal structure 300 and at least one of the source region 1111 and the drain region 1112 .
  • the barrier layer 200 is located between the conductive metal structure 320 and the active region 111 located below the contact hole 100a.
  • the material of the conductive metal structure 320 is at least one of tungsten, molybdenum, aluminum and the like.
  • steps in the flow chart of FIG. 1 are displayed sequentially as indicated by the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in FIG. 1 may include multiple steps or stages, and these steps or stages may not necessarily be executed at the same time, but may be executed at different times, and the execution sequence of these steps or stages may also be It is not necessarily performed sequentially, but may be performed alternately or alternately with other steps or at least a part of steps or stages in other steps.

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Abstract

本公开涉及一种半导体结构及其制作方法，其中，半导体结构包括基底、接触孔、阻挡层以及导电接触结构，基底包括有源区，有源区内形成有漏区以及源区；接触孔自基底的表面向源区与漏区中的至少一者延伸；阻挡层位于导电接触结构底面；导电接触结构填充接触孔，且包括接触层，接触层接触源区和/或漏区。本公开可以有效增大源漏电流。

Description

半导体结构及其制作方法
相关申请的交叉引用
本公开要求于2021年07月09日提交中国专利局、申请号为2021107796233、发明名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路技术领域，特别是涉及一种半导体结构及其制作方法。
背景技术
金属-氧化物-半导体场效应晶体管(MOSFET)等元器件作为半导体制造工艺中的常用器件，其通常会在有源区内进行重掺杂而形成源区以及漏区，且会形成深入源区以及漏区的导电接触结构，从而实现将源区与漏区之间电流(导通电流)与外部的连通。
但是，在实际产品中，常会出现因导电接触结构导致导通电流较小、漏电流较大的问题。
发明内容
根据本公开的各种实施例，提供一种半导体结构及其制作方法。
根据本公开的各种实施例，提供一种半导体结构，包括基底、接触孔、 阻挡层以及导电接触结构，
所述基底包括有源区，所述有源区内形成有漏区以及源区；
所述接触孔自所述基底的表面向所述源区与所述漏区中的至少一者延伸；
所述阻挡层位于所述导电接触结构底面；
所述导电接触结构填充所述接触孔，且包括接触层，所述接触层接触所述源区与所述漏区中的至少一者。
根据一些实施例，所述基底包括衬底以及介质层，所述衬底包括所述有源区，所述介质层位于所述衬底上，所述接触孔自所述介质层的表面向所述源区与所述漏区中的至少一者延伸。
根据一些实施例，所述阻挡层位于所述接触孔内部。
根据一些实施例，所述接触孔自所述基底表面延伸至所述源区与所述漏区中的至少一者下方的所述有源区，所述阻挡层覆盖所述接触孔延伸至所述源区与所述漏区中的至少一者外部的所述有源区内的部分。
根据一些实施例，所述接触层位于所述接触孔与所述源区与所述漏区中的至少一者之间。
根据一些实施例，所述导电接触结构还包括导电金属结构，所述导电金属结构填充所述接触孔，且所述接触层位于所述导电金属结构与所述源区与所述漏区中的至少一者之间，所述阻挡层位于所述导电金属结构与位于所述接触孔下方的所述有源区之间。
根据一些实施例，所述导电金属结构的材料为钨、钼、铝中的至少一种。
根据一些实施例，所述接触层的材料为金属硅化物。
根据本公开的各种实施例，还提供一种半导体结构的制作方法，包括：
提供基底，所述基底包括有源区，所述有源区内形成有漏区以及源区；
于所述基底内形成接触孔，所述接触孔自所述基底的表面向所述源区与所述漏区中的至少一者延伸；
形成阻挡层；
形成导电接触结构；
其中，所述阻挡层位于所述导电接触结构底面，所述导电接触结构填充所述接触孔，且包括接触层，所述接触层接触所述源区与所述漏区中的至少一者。
根据一些实施例，所述基底包括衬底以及介质层，所述衬底包括所述有源区，所述介质层位于所述衬底上，所述接触孔自所述介质层的表面向所述源区与所述漏区中的至少一者延伸。
根据一些实施例，所述阻挡层位于所述接触孔内部。
根据一些实施例，所述形成阻挡层，包括：
基于第一掩膜，于所述接触孔的内壁形成阻挡材料层，所述第一掩膜内具有第一开口，所述第一开口暴露所述接触孔；
至少去除位于所述接触孔侧壁的部分所述阻挡材料层，剩余的所述阻挡材料层构成所述阻挡层。
根据一些实施例，所述基于所述第一掩膜，于所述接触孔的内壁形成阻挡材料层包括：
基于所述第一掩膜，通过原子层沉积法，于所述接触孔的内壁沉积阻挡材料层。
根据一些实施例，所述至少去除位于所述接触孔侧壁的部分所述阻挡材料层，包括：
通过各向同性的刻蚀方式刻蚀所述阻挡材料层。
根据一些实施例，所述形成所述导电接触结构，包括：
基于第二掩膜，于所述接触孔的侧壁以及所述阻挡层上形成接触原料层，所述第二掩膜内具有第二开口，所述第二开口暴露所述接触孔；
使所述接触原料层扩散至所述源区与所述漏区中的至少一者而与之反应结晶，以形成接触层。
根据一些实施例，所述接触层的材料为金属硅化物。
根据一些实施例，所述导电接触结构还包括导电金属结构，所述使所述接触原料层扩散至所述源区与所述漏区中的至少一者而与之反应结晶，以形成接触层之后，所述形成导电接触结构还包括：
于所述接触孔内填充导电金属结构。
根据一些实施例，所述导电金属结构的材料为钨、钼、铝中的至少一种。
本公开实施例可以/至少具有以下优点：
阻挡层位于导电接触结构底面。此时，接触层可以通过侧面与源区和/或漏区之间形成良好的欧姆接触，从而进行良好的电流传输，进而有效降低横向导通电阻，从而有效增大导通电流。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的半导体结构的制作方法的流程图；
图2-图7为一实施例中提供的半导体结构的制作过程中的结构示意图；
图8为一实施例中提供的半导体结构的结构示意图；
图9为另一实施例中提供的半导体结构的结构示意图。
附图标记说明：100-基底，110-衬底，111-有源区，1111-源区，1112-漏区，120-介质层，100a-接触孔，200-阻挡层，201-阻挡材料层，300-导电接触结构，310-接触层，311-接触原料层，320-导电金属结构。
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接 或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。
正如背景技术所言，在实际产品中，常会出现导通电流较小且漏电流较大的问题。经发明人研究发现，出现这种问题的原因在于：
导电接触结构的制作流程通常为：首先形成延伸至源区以及漏区的接触孔，然后，在接触孔内沉积一层钴(Co)。随后，进行热处理以使得Co扩散至源区以及漏区(材料通常为重掺杂的硅)内，而与之反应形成硅化钴(CoSi)接触层，从而使得导电接触结构可以通过CoSi而与周围的源区以及漏区形成良好的欧姆接触，进而可以有效降低导电接触结构与源区以及漏区之间的接触电阻。
但是，目前的工艺常常会导致CoSi集中在导电接触结构的下方。而器件是通过沟道横向导通的。因此，CoSi集中在下方，会使横向导通电阻增大，尤其是，如果导电接触结构过深，CoSi会远离导电沟道，更会使得横向导通电阻增大，导通电流变小。
并且，如果导电接触结构过深，可能会超出源、漏掺杂区而和衬底相连，从而会导致漏电流增大。
基于以上原因，本公开提供了一种改善的导电接触结构，提高器件性能的半导体结构及其制作方法。
在一个实施例中，请参阅图1，提供一种半导体结构的制作方法，包括：
步骤S100，提供基底100，基底100包括有源区111，有源区111内形成有漏区1112以及源区1111，请参阅图2；
步骤S200，于基底100内形成接触孔100a，接触孔100a自基底100的表面向源区1111与漏区1112中的至少一者延伸，请参阅图3；
步骤S300，形成阻挡层200，请参阅图5；
步骤S400，形成导电接触结构300，请参阅图8；
其中，阻挡层200位于导电接触结构300底面，导电接触结构300填充接触孔100a，且包括接触层310，接触层310接触源区1111与漏区1112中的至少一者。
在步骤S100中，有源区111可以为P型有源区，也可以为N型有源区。P型有源区可以形成NMOS器件，N型有源区可以形成PMOS器件。
作为示例，更基底100可以包括衬底110。衬底110可以包括但不限于为硅衬底。衬底110内可以形成有P型阱区或者N型阱区，且可以形成有浅沟槽隔离结构。浅沟槽隔离结构将P型阱区或者N型阱区隔离成多个间隔设置的P型有源区或者N型有源区。
有源区111两侧可以通过离子注入等方式进行重掺杂，从而形成有漏区1112以及源区1111。P型有源区两侧可以进行N型重掺杂，从而形成有漏区1112以及源区1111；N型有源区两侧可以进行P型重掺杂，从而形成有漏区1112以及源区1111。
在步骤S200中，可以首先在基底100的表面形成图形化掩膜层。图形化掩膜层内具有暴露基底表面的掩膜开口，掩膜开口定义出接触孔100a的形状及位置。然后，基于图形化掩膜层对基底100进行刻蚀以形成接触孔100a。
在步骤S300中，阻挡层200为可以阻挡电流传输的绝缘介质层。阻挡层 200的材料可以为二氧化硅、氮化硅或者氮氧化硅等。
在步骤S400中，接触层310的材料可以但不限于为金属硅化物(如CoSi)等，其可以与源区1111以及漏区1112形成良好的欧姆接触。
在本实施例中，在形成导电接触结构300之前先形成有阻挡层200。阻挡层200位于导电接触结构300底面，进而可以有效防止接触层310集中在导电接触结构的下方。此时，接触层310可以通过侧面与源区1111与漏区1112中的至少一者之间形成良好的欧姆接触，从而进行良好的电流传输，进而有效降低横向电阻，从而有效增大源漏电流。
这里值得注意的是，在本实施例步骤S200中，为了减小工艺复杂程度，接触孔100a可以与同一晶圆上其他位置处的其他通孔同时形成。此时，图形化掩膜层内的开口除了定义出接触孔100a的形状及位置以外，还可以同时定义出具有其他功能的其他通孔的形状及位置。然后，基于图形化掩膜层可以同时形成接触孔100a及其他通孔。
但是，此时受其他位置处的其他通孔的影响，接触孔100a在源区1111与漏区1112中的至少一者中需要延伸的深度可能较大，甚至可能会穿过源区1111与漏区1112中的至少一者延伸至源区1111与漏区1112中的至少一者下方的有源区，导致导电接触结构300与衬底之间具有漏电风险。
而本实施例，在形成导电接触结构300之前先形成有阻挡层200。阻挡层200位于导电接触结构300底面，进而也可以有效降低导电接触结构300与衬底之间的漏电风险。
当然，在本实施例中，接触孔100a也可以单独形成，本公开对此并没有限制。
在一个实施例中，请参阅图2以及图3，基底100包括形成有有源区111 的衬底110。同时，基底100还包括位于衬底110上的介质层120。接触孔100a自介质层120的表面向源区1111与漏区1112中的至少一者延伸。
即在本实施例中，接触孔100a是在衬底110上形成有介质层120之后，再形成接触孔100a，进而便于多个器件的统一加工制造。
当然，本公开并不以此为限制，例如在一些实施例中，基底100也可以只包括衬底110。
在一个实施例中，阻挡层200位于接触孔100a内部。此时，可以方便地将阻挡层200形成于导电金属结构300底面。
进一步地，此时，步骤S300可以包括：
步骤S310，基于第一掩膜，于接触孔100a的内壁形成阻挡材料层201，第一掩膜内具有第一开口，第一开口暴露接触孔100a，请参阅图4；
步骤S320，至少去除位于接触孔100a侧壁的部分阻挡材料层201，剩余的阻挡材料层201构成阻挡层200，请参阅图5。
在步骤S310中，作为示例，第一掩膜可以为具有第一开口的掩膜版，其可以在进行步骤S310之前覆盖于基底100表面。该掩膜版只暴露接触孔100a，从而于接触孔100a的内壁形成阻挡材料层201。
当然，本公开并不以此为限制。例如，在另一些示例中，第一掩膜也可以为前述说明的用于形成接触孔100a的图形化掩膜层。即在步骤S200通过图形化掩膜层形成接触孔100a之后，继续以其作为第一掩膜，而在接触孔100a的内壁形成阻挡材料层201a。
在步骤S320中，去除位于接触孔100a侧壁的部分阻挡材料层201之后，所形成的阻挡层200即位于接触孔100a内部，且位于其底部。
进一步地，请参阅图9，当接触孔100a位于接触孔100a内部时，且其自 基底表面延伸至源区1111与漏区1112中的至少一者下方的有源区111时，可以设置阻挡层200覆盖接触孔100a延伸至源区1111与漏区1112中的至少一者外部的有源区111内的部分，从而可以有效防止防止导电接触结构300与源区1111与漏区1112中的至少一者之外的有源区111接触，从而更加良好地防止导电接触结构300与衬底底部的电极之间漏电。
当然，在其他实施例中，阻挡层200也可以通过其他方式形成，例如，在形成接触孔100a后，进行热氧化工艺，从而将接触孔100a的孔壁氧化而形成氧化层，之后再去除位于侧面的氧化层，而保留于底部的氧化层构成阻挡层200。此时，阻挡层200位于接触孔100a外部且连接接触孔100a。
在一个实施例中，步骤S310包括：基于第一掩膜，通过原子层沉积法，于接触孔100a的内壁沉积阻挡材料层201，请参阅图4。
通过原子层沉积的方式，可以形成质量良好的阻挡材料层201。
同时，采用原子层沉积的方式，可以在接触孔100a内生长处各向异性的阻挡材料层210。接触孔100a的内壁包括底壁以及侧壁。此时，接触孔100a底壁上形成的阻挡材料层201的厚度大于接触孔100a侧壁上形成的阻挡材料层201的厚度。
更接触孔100a底壁上形成的阻挡材料层201的厚度与接触孔100a侧壁上形成的阻挡材料层201的厚度之比可以控制在4:1至6:1的范围内。例如，接触孔100a底壁上形成的阻挡材料层201的厚度与接触孔100a侧壁上形成的阻挡材料层201的厚度之比可以控制在5:1左右。
基于此，进一步地，此时步骤S320可以包括：通过各向同性的刻蚀方式刻蚀阻挡材料层201，请参阅图5。
各向同性的刻蚀方式刻蚀阻挡材料层201时，阻挡材料层201在各个方 向的刻蚀速度相同。因此，此时整个阻挡材料层201均会被刻蚀。同时，由于接触孔100a侧壁上形成的阻挡材料层201的厚度小于接触孔100a底壁上形成的阻挡材料层201，因此当接触孔100a侧壁上的阻挡材料层201被刻蚀完毕后，接触孔100a底壁上的阻挡材料层201仍会有部分剩余。该部分剩余的阻挡材料层201构成阻挡层200。
当然，位于接触孔100a侧壁上的阻挡材料层201也可以通过其他方式去除。在其他方法中，接触孔100a底壁上的阻挡材料层201也可以不被去除。或者，在其他实施例中，也可以通过其他方法于接触孔100a的内壁沉积阻挡材料层201。本公开对此均没有限制。
在一个实施例中，步骤S400包括：
步骤S410，基于第二掩膜，于接触孔100a的侧壁以及阻挡层200上形成接触原料层311，第二掩膜内具有第二开口，第二开口暴露接触孔100a，请参阅图6；
步骤S420，使接触原料层311扩散至源区1111与漏区1112中的至少一者而与之反应结晶，以形成接触层310，请参阅图7。
在步骤S410中，第二掩膜与步骤S310中的第一掩膜可以为同一掩膜。当然，二者也可以为不同的掩膜。
接触原料层311的材料可以为钴等金属材料。
在步骤S420中，可以对接触孔100a内壁形成有接触原料层311的结构进行热处理，从而使得接触原料层311扩散至源区1111与漏区1112中的至少一者而与之反应结晶，以形成接触层310。
接触层310的材料可以为硅化钴等金属硅化物。
这里，可以理解的是，未扩散至源区1111与漏区1112中的至少一者的 接触原料层311(如与介质层120对准的接触原料层311以及阻挡层200上的接触原料层311)可以保留下来而作为导电接触结构300的组成部分(未图示)。当然，也可以将未形成接触层310的接触原料层311去除，本公开对此没有限制。
本实施例形成的接触层310位于接触孔100a与源区1111与漏区1112中的至少一者之间，即接触层310形成在接触孔100a外部。当然，在其他实施例中，在可实现的情况下，接触层310也可以形成于接触孔100a内部的内壁之上，本公开对此并没有限制。
在一个实施例中，导电接触结构300还包括导电金属结构320。步骤S420之后，步骤S400还包括：
步骤S430，于接触孔100a内填充导电金属结构320，请参阅图8。
作为示例，导电金属结构320的材料可以为钨、钼、铝等之中的至少一种，其可以将源区1111与漏区1112中的至少一者的电流与外部连通。
此时，接触层310位于导电金属结构320与源区1111与漏区1112中的至少一者之间。而阻挡层200位于导电金属结构320与位于接触孔100a下方的有源区111之间。
在一个实施例中，请参阅图8或图9，还提供一种半导体结构，包括基底100、接触孔100a、阻挡层200以及导电接触结构300。
基底100包括有源区111。有源区111内形成有漏区1112以及源区1111。接触孔100a自基底100的表面向源区1111与漏区1112中的至少一者延伸。阻挡层200位于导电接触结构300底面。导电接触结构300填充接触孔100a，且包括接触层310，接触层310接触源区1111与漏区1112中的至少一者。
在本实施例中，阻挡层200位于导电接触结构300底面，进而可以有效 防止接触层310集中在导电接触结构300的下方。此时，接触层310可以通过侧面与源区1111与漏区1112中的至少一者之间形成良好的欧姆接触，从而进行良好的电流传输，进而有效降低横向电阻，从而有效增大源漏电流。
在一个实施例中，基底100包括衬底110以及介质层120。衬底110包括有源区111。介质层120位于衬底110上。接触孔100a自介质层120的表面向源区1111与漏区1112中的至少一者延伸。
在一个实施例中，阻挡层200位于接触孔100a内部。
在一个实施例中，接触孔100a自基底100表面延伸至源区1111与漏区1112中的至少一者下方的有源区111，阻挡层200的厚度大于接触孔100a延伸至源区1111与漏区1112中的至少一者下方的有源区111内的深度(请参阅图9)。
在一个实施例中，接触层310位于接触孔100a与源区1111与漏区1112中的至少一者之间。
在一个实施例中，导电接触结构300还包括导电金属结构320。导电金属结构320填充接触孔100a，且接触层310位于导电金属结构300与源区1111与漏区1112中的至少一者之间。阻挡层200位于导电金属结构320与位于接触孔100a下方的有源区111之间。
在一个实施例中，导电金属结构320的材料为钨、钼、铝等之中的至少一种。
关于半导体结构的具体限定可以参见上文中对于半导体结构制作方法的限定，在此不再赘述。
应该理解的是，虽然图1的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有 明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“一些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种半导体结构，包括基底、接触孔、阻挡层以及导电接触结构，
    所述基底包括有源区，所述有源区内形成有漏区以及源区；
    所述接触孔自所述基底的表面向所述源区与所述漏区中的至少一者延伸；
    所述阻挡层位于所述导电接触结构底面；
    所述导电接触结构填充所述接触孔，且包括接触层，所述接触层接触所述源区与所述漏区中的至少一者。
  2. 根据权利要求1所述的半导体结构，其中，所述基底包括衬底以及介质层，所述衬底包括所述有源区，所述介质层位于所述衬底上，所述接触孔自所述介质层的表面向所述源区与所述漏区中的至少一者延伸。
  3. 根据权利要求1所述的半导体结构，其中，所述阻挡层位于所述接触孔内部。
  4. 根据权利要求3所述的半导体结构，其中，所述接触孔自所述基底表面延伸至所述源区与所述漏区中的至少一者下方的所述有源区，所述阻挡层覆盖所述接触孔延伸至所述源区与所述漏区中的至少一者外部的所述有源区内的部分。
  5. 根据权利要求1所述的半导体结构，其中，所述接触层位于所述接触孔与所述源区与所述漏区中的至少一者之间。
  6. 根据权利要求5所述的半导体结构，其中，所述导电接触结构还包括导电金属结构，所述导电金属结构填充所述接触孔，且所述接触层位于所述导电金属结构与所述源区与所述漏区中的至少一者之间，所述阻挡层位于所述导电金属结构与位于所述接触孔下方的所述有源区之间。
  7. 根据权利要求6所述的半导体结构，其中，所述导电金属结构的材料为钨、钼、铝中的至少一种。
  8. 根据权利要求1所述的半导体结构，其中，所述接触层的材料为金属硅化物。
  9. 一种半导体结构的制作方法，包括：
    提供基底，所述基底包括有源区，所述有源区内形成有漏区以及源区；
    于所述基底内形成接触孔，所述接触孔自所述基底的表面向所述源区与所述漏区中的至少一者延伸；
    形成阻挡层；
    形成导电接触结构；
    其中，所述阻挡层位于所述导电接触结构底面，所述导电接触结构填充所述接触孔，且包括接触层，所述接触层接触所述源区与所述漏区中的至少一者。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，所述基底包括衬底以及介质层，所述衬底包括所述有源区，所述介质层位于所述衬底上，所述接触孔自所述介质层的表面向所述源区与所述漏区中的至少一者延伸。
  11. 根据权利要求9所述的半导体结构的制作方法，其中，所述阻挡层位于所述接触孔内部。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，所述形成阻挡层，包括：
    基于第一掩膜，于所述接触孔的内壁形成阻挡材料层，所述第一掩膜内具有第一开口，所述第一开口暴露所述接触孔；
    至少去除位于所述接触孔侧壁的部分所述阻挡材料层，剩余的所述阻挡 材料层构成所述阻挡层。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，所述基于所述第一掩膜，于所述接触孔的内壁形成阻挡材料层包括：
    基于所述第一掩膜，通过原子层沉积法，于所述接触孔的内壁沉积阻挡材料层。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，所述至少去除位于所述接触孔侧壁的部分所述阻挡材料层，包括：
    通过各向同性的刻蚀方式刻蚀所述阻挡材料层。
  15. 根据权利要求9所述的半导体结构的制作方法，其中，所述形成所述导电接触结构，包括：
    基于第二掩膜，于所述接触孔的侧壁以及所述阻挡层上形成接触原料层，所述第二掩膜内具有第二开口，所述第二开口暴露所述接触孔；
    使所述接触原料层扩散至所述源区与所述漏区中的至少一者而与之反应结晶，以形成接触层。
  16. 根据权利要求15所述的半导体结构的制作方法，其中，所述接触层的材料为金属硅化物。
  17. 根据权利要求15所述的半导体结构的制作方法，其中，所述导电接触结构还包括导电金属结构，所述使所述接触原料层扩散至所述源区与所述漏区中的至少一者而与之反应结晶，以形成接触层之后，所述形成导电接触结构还包括：
    于所述接触孔内填充导电金属结构。
  18. 根据权利要求15所述的半导体结构的制作方法，其中，所述导电金属结构的材料为钨、钼、铝中的至少一种。
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5620912A (en) * 1994-07-21 1997-04-15 Lg Semicon Co., Ltd. Method of manufacturing a semiconductor device using a spacer
US5908313A (en) * 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
US6051472A (en) * 1996-09-26 2000-04-18 Nec Corporation Semiconductor device and method of producing the same
CN1689149A (zh) * 2002-10-07 2005-10-26 因芬尼昂技术股份公司 具局部源极/漏极绝缘场效晶体管及其制造方法
CN101064343A (zh) * 2006-04-25 2007-10-31 国际商业机器公司 半导体器件及其制造方法
US20120313151A1 (en) * 2011-06-07 2012-12-13 Young-Kyu Lee Semiconductor device including contact structure, method of fabricating the same, and electronic system including the same
CN102956493A (zh) * 2011-08-24 2013-03-06 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN103137490A (zh) * 2011-12-05 2013-06-05 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
CN111261709A (zh) * 2018-11-30 2020-06-09 长鑫存储技术有限公司 导电插塞结构、半导体器件及其形成方法
CN111952367A (zh) * 2019-05-15 2020-11-17 长鑫存储技术有限公司 半导体结构及其形成方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5620912A (en) * 1994-07-21 1997-04-15 Lg Semicon Co., Ltd. Method of manufacturing a semiconductor device using a spacer
US6051472A (en) * 1996-09-26 2000-04-18 Nec Corporation Semiconductor device and method of producing the same
US5908313A (en) * 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
CN1689149A (zh) * 2002-10-07 2005-10-26 因芬尼昂技术股份公司 具局部源极/漏极绝缘场效晶体管及其制造方法
CN101064343A (zh) * 2006-04-25 2007-10-31 国际商业机器公司 半导体器件及其制造方法
US20120313151A1 (en) * 2011-06-07 2012-12-13 Young-Kyu Lee Semiconductor device including contact structure, method of fabricating the same, and electronic system including the same
CN102956493A (zh) * 2011-08-24 2013-03-06 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN103137490A (zh) * 2011-12-05 2013-06-05 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
CN111261709A (zh) * 2018-11-30 2020-06-09 长鑫存储技术有限公司 导电插塞结构、半导体器件及其形成方法
CN111952367A (zh) * 2019-05-15 2020-11-17 长鑫存储技术有限公司 半导体结构及其形成方法

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