WO2023279647A1

WO2023279647A1 - Verification method for repair analysis, electronic device, and storage medium

Info

Publication number: WO2023279647A1
Application number: PCT/CN2021/135714
Authority: WO
Inventors: 杨柳
Original assignee: 长鑫存储技术有限公司
Priority date: 2021-07-08
Filing date: 2021-12-06
Publication date: 2023-01-12
Also published as: CN115599576A

Abstract

A verification method for repair analysis, an electronic device, and a storage medium. The method can be applied to a simulation software platform, and comprises: configuring a failure address of a dynamic random access memory that simulates a failure (101); forming a Raw Data document of the failure address (102); performing an operation on the Raw Data document by means of repair analysis to obtain an address document and a repair solution document of the failure address (103); and repairing the failure address in the address document on the basis of the repair solution document, and displaying a repair result (104).

Description

Verification method, electronic device and storage medium of patching algorithm

This application is based on the Chinese patent application with the application number 202110772368.X, the application date is July 08, 2021, and the application name is "Verification method for repair algorithm, electronic equipment and storage medium", and the priority of this Chinese patent application is requested Right, the entire content of this Chinese patent application is hereby incorporated into this application as a reference.

technical field

The present application relates to, but is not limited to, a method for verifying a repair algorithm, an electronic device, and a storage medium.

Background technique

For companies that produce different DRAM (Dynamic Random Access Memory, DRAM) products, the repairing solutions for failed cells of each product will be different.

At present, the verification of the DRAM repair algorithm (Repair Analysis, RA) is generally carried out on the test machine, and the corresponding failure unit is set for a certain die, and the relevant data of the failure unit (also called "Raw Data") is generated on the test machine. ”), the repair plan is calculated by RA, and the matching degree between the set failure unit and the repair plan is manually compared. This verification method takes a lot of time and is prone to omissions. Another verification solution is to debug (Debug) the repair solution on the wafer, that is, directly damage the wafer, perform test repair, and perform RA verification based on the test whether new failure units appear after repair. However, this verification method will cause damage to the wafer, and other tests cannot be performed. Moreover, both of the above two verification methods have the disadvantages of time-consuming, incomplete verification, and high cost.

Contents of the invention

The following is an overview of the subject matter described in detail in this application. This summary is not intended to limit the scope of the claims.

The present application provides a method for verifying a repair algorithm, electronic equipment and a storage medium.

The first aspect of the present application provides a kind of verification method of patching algorithm, is applied to the simulation software platform, comprises: the failure address of the dynamic random access memory of configuration simulation failure; Form the Raw Data document of described failure address; Described Raw The data file is operated by a repairing algorithm to obtain the address file and repair plan file of the invalid address; based on the repair plan file, the invalid address in the address file is repaired, and the repair result is displayed.

According to some embodiments of the present application, the configuration simulates the failure address of the failed DRAM, including:

An address space and an address input window of the simulated failure DRAM are provided, and the failure address input in the address input window based on the address space is received.

An address array of the address space of the simulated failure DRAM is provided, and an address selected from the address array is determined as the failure address.

According to some embodiments of the present application, the method also includes:

Obtaining the product type of the DRAM;

The described Raw Data file is operated through a repair algorithm to obtain the address file and the repair plan file of the failure address, including:

The Raw Data file is operated through the repair algorithm corresponding to the product type to obtain the address file and repair plan file of the failure address.

According to some embodiments of the present application, before performing operations on the Raw Data file through a repair algorithm to obtain the address file of the failure address and the repair plan file, it also includes:

Obtain the data format of the Raw Data file, and the data format is used to indicate that when the Raw Data file is operated by the repair algorithm, the operation is performed in a conventional manner or in a compressed manner.

determining the die generating the failure address;

Determine at least one test site, and the test items included in each test site;

Selecting failure addresses belonging to each test item in each of the test stations from the determined dies.

According to some embodiments of the present application, the Raw Data file forming the failure address includes:

Form the Raw Data file of the failure addresses belonging to each test item in each of the test sites.

According to some embodiments of the present application, the Raw Data file is operated through a repair algorithm to obtain the address file and repair plan file of the failure address, including:

The Raw Data file is respectively calculated according to the test site to which the failure address belongs, to obtain the address file and the repair plan file of the failure address contained in each of the test sites.

The Raw Data file is combined according to at least two combined test sites to which the failure address belongs, to obtain the address file and the repair plan file of the failure address contained in the combined test site.

According to some embodiments of the present application, the repairing of invalid addresses in the address file based on the repairing scheme file, and displaying the repairing results include:

Provide a file selection interface, and perform a repair operation based on the invalidation address file and the corresponding repair plan file selected on the interface;

Display the repair result.

According to some embodiments of the present application, the displaying the repair result includes:

An address array of the address space of the simulated failure DRAM is provided, and a result of whether the selected failure address file can be successfully repaired by the corresponding repair solution file is identified in the address array.

According to some embodiments of the present application, the result of identifying in the address array whether the selected failure address file can be successfully repaired by the corresponding repair solution file includes:

The position of the failure address in the failure address file, the position of the repair solution in the repair solution file, and whether the two match are identified in the address array by at least one of different characters, colors, and symbols.

Based on the export operation of the repair result, generate and export the repair result to the specified directory file.

A second aspect of the present application provides an electronic device, including: at least one processor; and,

A memory connected in communication with the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processing The device can execute the verification method of the patching algorithm described in the first aspect.

A third aspect of the present application provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the method for verifying the repair algorithm described in the first aspect is implemented.

The method for verifying the repair algorithm, the electronic device and the storage medium provided in the embodiments of the present application perform offline verification on the RA algorithm of the DRAM through a simulation software platform. Use the offline verification method to flexibly configure the failure address of the simulated failure DRAM; form the Raw Data file of the failure address; operate the Raw Data file through the repair algorithm to obtain the address file of the failure address and the repair plan file; finally based on The repair plan document repairs the invalid addresses in the address file and displays the repair results, so as to complete the verification process of the RA algorithm without occupying the test machine and causing damage to the wafer, reducing the cost of DRAM production; making up for the current manual Omissions in the comparison method lead to incomplete repair of failed units; the process of online multi-site testing can be simulated to fully verify the results of multi-site repair algorithms and improve the efficiency of algorithm verification.

Other aspects will be apparent to others upon reading and understanding the drawings and detailed description.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the embodiments of the application and together with the description serve to explain the principles of the embodiments of the application. In the drawings, like reference numerals are used to denote like elements. The drawings in the following description are some embodiments of the present application, but not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

Fig. 1 is a flowchart one of a verification method of a repair algorithm according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an invalid address configuration process according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an invalidation address configuration process according to an embodiment of the present application;

FIG. 4 is a second flow chart of a verification method of a repair algorithm according to an embodiment of the present application;

FIG. 5 is a schematic diagram of an invalidation address configuration process according to an embodiment of the present application;

Fig. 6 is a schematic diagram of a Raw Data document according to an embodiment of the present application;

FIG. 7 is a flowchart three of a verification method of a repair algorithm according to an embodiment of the present application;

FIG. 8 is a distribution diagram of repair schemes and failure addresses according to an embodiment of the present application;

FIG. 9 is a flowchart four of a verification method of a patching algorithm according to an embodiment of the present application;

Fig. 10 is a schematic diagram of repair results according to an embodiment of the present application;

Fig. 11 is a schematic diagram of repair results according to an embodiment of the present application;

FIG. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

detailed description

The following will clearly and completely describe the technical solutions in the disclosed embodiments with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

A die is the smallest unit of a wafer. The wafer is processed by the DRAM manufacturing process to form a preset number of DRAMs on each die. Each DRAM contains a preset number of storage units. A cell is assigned a memory address. The verification of the RA algorithm for the DRAM failure address is generally carried out on the test machine. One is to first set the failed unit on the die, generate raw data of the failed unit on the test machine, calculate the repair plan through the RA algorithm, and manually compare the matching degree between the set failed unit and the repair plan. This method takes a lot of time and is prone to omissions. The other is to directly cause damage to the wafer, perform a test repair, and verify the RA algorithm based on whether a new failure unit appears in the test after the repair. However, this verification method will cause damage to the wafer, and other tests cannot be performed. Moreover, both of the above two verification methods have the disadvantages of time-consuming, incomplete verification, and high cost.

This application proposes an offline verification scheme for the RA algorithm of DRAM. This solution does not need to be completed on the test machine, but simulates the DRAM failure address through the simulation software platform, uses the RA algorithm to be verified to calculate the failure address, obtains the failure address and the document of the repair plan, and selects the corresponding failure address and The patching scheme performs patching operations, and flexibly displays the patching results based on the software platform to verify the RA algorithm. This application scheme does not occupy the test machine, and will not cause damage to the wafer, reducing the cost of DRAM production; at the same time, it makes up for the omissions that occur in the current manual comparison method, resulting in incomplete repair of failed units; it can simulate multiple stations on the line The testing process fully verifies the results of the multi-site patching algorithm and improves the efficiency of algorithm verification.

In one embodiment, the method for verifying a repair algorithm as shown in FIG. 1 is applied to a simulation software platform, and includes the following steps.

Step 101: Configure the invalidation address of the dynamic random access memory that simulates invalidation.

The inspector selects or creates the DRAM product information to be simulated to fail on the simulation software platform, and configures the failure address of the DRAM. The failure address may be the storage address of each storage unit located on a certain die on the wafer carrying the DRAM. In this embodiment, the process of configuring the failure address is not limited. For example, the failure address can be configured in the following two ways.

Method 1: providing an address space and an address input window for simulating a failed DRAM, and receiving a failure address input in the address input window based on the address space.

For example, as shown in Figure 2, multiple storage blocks (banks) of DRAM are provided on the simulation software platform, and the address space of the storage units contained in each bank is 16-bit binary in the X direction and 10-bit binary in the Y direction. system, DQ has three bits, and each time a memory unit cell (bit) is read, the subsequent 7 bits are read out, so there are 8 bits, which is 2 to the 3rd power. Row Fail shown in the figure is the storage address of a horizontal storage unit, Col Fail is the storage address of a vertical storage unit, and Single Fail is the storage address of a single-point storage unit. The inspector can input the unit address as the failure unit in the address input window according to the requirement. An example of the input result may be shown in FIG. 2 .

Method 2: Provide an address array simulating the address space of the failed DRAM, and determine an address selected from the address array as the failed address.

For example, as shown in Figure 3, multiple storage blocks (banks) of DRAM are provided on the simulation software platform, and the address space of the storage unit contained on each bank is 16-bit binary in the X direction and 10-bit binary in the Y direction. system. The address spaces of the storage units on these chips can be displayed on the operation interface of the simulation software platform in the form of address arrays. Each small square in the figure can represent not only a storage unit, but also the storage address corresponding to the storage unit. The inspector can check the unit address as the failed unit in the address array according to the requirement.

Step 102: Form a Raw Data file of the invalidation address.

The simulation software platform generates the original data of the failure address, that is, the Raw Data file, according to the failure address input or checked by the inspector. According to the number of failure addresses actually configured, the category of the division group, etc., the generated Raw Data files can also correspond to one or more.

Step 103: the Raw Data file is operated through the repair algorithm to obtain the address file and the repair plan file of the invalid address.

The repair algorithm here is the RA algorithm to be verified. The above-mentioned Raw Data file is calculated by the RA algorithm, and the repair solution for the invalid address can be obtained. In actual operation, based on the quality of the RA algorithm, not every failure address can be calculated to obtain the corresponding repair solution. It is possible that there is no corresponding repair solution for some failure addresses, or there is a repair solution but the corresponding failure address cannot be corrected. repair. Therefore, in this embodiment, after the operation of the repairing algorithm, only the address file and the repairing scheme file having the relationship between the repaired and the repaired are obtained. The address file can be obtained according to the number of previously invalid addresses, the category of the group, etc., and contains one or more files of invalid addresses. There is a one-to-one correspondence between the repair plan document and the address document, and each repair plan document includes (or may not include) a repair plan for repairing invalid addresses in the corresponding address file.

In an exemplary embodiment, the RA algorithm to be verified may be various RA algorithms developed according to the types of DRAM products, and each RA algorithm is dedicated to repairing and analyzing the failure addresses of the corresponding DRAM type products. In an exemplary embodiment, before performing this step, the product type of the dynamic random access memory can be obtained first, and according to the product type of the DRAM to be simulated to fail, the failure address of the DRAM to be simulated to fail can be selected to match more The RA algorithm performs repair analysis, thereby improving the accuracy of repair analysis.

Based on this, this step may include: operating the Raw Data file through the repair algorithm corresponding to the product type to obtain the address file and repair plan file of the invalid address. Therefore, the matching degree between the address file of the invalid address and the repair plan file is improved, and the accuracy of subsequent repair operations is improved.

In addition, when the Raw Data file is operated by the patching algorithm, the operation can be performed in a conventional or compressed manner. Among them, the conventional method is to test each address unit independently to determine whether each address unit is a failure address; the compressed mode is to test the associated multiple address units together, when at least one address unit in the multiple address units is When the address is invalid, it is determined that the plurality of address units are all invalid addresses.

In an exemplary embodiment, before performing this step, the data format of the Raw Data file can be obtained first, and the data format is used to indicate that when the Raw Data file is operated by the patching algorithm, the operation is performed in a conventional manner or in a compressed manner .

In an exemplary embodiment, the simulation software platform provides a selection interface for selecting the data format of the Raw Data file before the detection personnel configures the invalidation address of the dynamic random access memory of the simulated failure, and the detection personnel selects the Raw Data in the interface. The data format of the document, which instructs the simulation software platform to perform the operation of the RA algorithm in a conventional way or in a compressed way.

Step 104: Repair the invalid address in the address file based on the repair plan document, and display the repair result.

After the simulation software platform completes the RA algorithm calculation to obtain the address file and repair plan file of the failed address, it can automatically repair the failed address in the corresponding address file according to the repair plan in the repair plan file, and save the address file in each address file. The result of whether the invalid address is corrected is displayed on the platform interface. Alternatively, the simulation software platform performs a patching operation on the specified address document and the patching scheme document based on the selection operation of the inspector, and displays the patching result.

In this embodiment, the RA algorithm of the DRAM is verified offline through a simulation software platform. Use the offline verification method to flexibly configure the failure address of the simulated failure DRAM; form the Raw Data file of the failure address; operate the Raw Data file through the repair algorithm to obtain the address file of the failure address and the repair plan file; finally based on The repair plan document repairs the invalid addresses in the address file and displays the repair results, so as to complete the verification process of the RA algorithm without occupying the test machine and causing damage to the wafer, reducing the cost of DRAM production; making up for the current manual Omissions in the comparison method lead to incomplete repair of failed units; the process of online multi-site testing can be simulated to fully verify the results of multi-site repair algorithms and improve the efficiency of algorithm verification.

In an exemplary embodiment, it is provided to configure the failover address of DRAM in a multi-site multi-item manner. As shown in Fig. 4, step 101 may include the following sub-steps.

Sub-step 1011: Determine the die that generates the failure address.

After the inspector selects or creates the DRAM product information to be simulated to fail on the simulation software platform, he can select the die for configuring the failure address on the wafer carrying the DRAM product information. For example, n dies on the wafer may be selected as dies configured with failure addresses. The n grains are marked as: Die 1, Die 2,... Die n.

Sub-step 1012: Determine at least one test site and the test items contained in each test site.

In order to simulate the failure environment corresponding to the failure address, at least one test site can be simulated and configured, and each test site corresponds to a different test stage (stage), for example: high temperature test stage (stage00), low temperature test stage (stage01), aging test stage ( stage02). Each test site can include multiple test items. For example, each test site may include m test items. The m test items are respectively marked as: test item 1, test item 2, . . . test item m.

In an exemplary embodiment, the inspector may select at least one test site, and configure a certain number of test items for the selected test site, so as to simulate a real failure environment corresponding to the configured failure address.

Sub-step 1013: Select the failure address of each test item belonging to each test site from the determined die.

In an exemplary embodiment, inspectors configure some address units from the above-mentioned determined die as failure addresses, and associate these failure addresses with the test items in the configured test sites, thereby simulating the actual failure environment, The test site and test item to which the failure source of the failure address in the DRAM product belongs.

For example, as shown in FIG. 5 , it is an operation diagram of the result of configuring failure addresses for multiple test items of multiple test sites. Wherein, when configuring the failure address, reference can still be made to the configuration process in the foregoing embodiments, through manual input and checking in the address space matrix, and the configuration process will not be repeated here.

In an exemplary embodiment, as shown in FIG. 4, step 102 may be:

Sub-step 1021: Form the Raw Data file of the failure address of each test item belonging to each test site.

In an exemplary embodiment, when forming the Raw Data file of the failure address, the number of documents and the failure address contained in each document can also be divided according to the test site and the test item to which the failure address belongs. For example, as shown in Figure 6, the failure address of any test item belonging to any test site is uniquely included in a Raw Data file. In the figure rdm_1.dat, m is the test item number, 1:Site (storage unit) number.

In an exemplary embodiment, as shown in FIG. 4, step 103 may be:

Sub-step 1031: Test the Raw Data file according to the test site to which the failure address belongs, and obtain the address file and repair plan document of the failure address contained in each test site.

In an exemplary embodiment, when performing RA algorithm calculation on the failure address in the Raw Data file, the tester can choose to separately execute the RA algorithm on the Raw Data files belonging to different test sites, so that according to the results contained in each test site obtained, The address file and repair plan file of the failure address, to verify the repair analysis ability of the RA algorithm alone applied to each test site.

In an exemplary embodiment, as an alternative to substep 1031, as shown in FIG. 7, step 103 may also be:

Sub-step 1032: Raw Data file is carried out combination test by at least two combined test sites after failure address belongs, obtains the address file and the repair plan document of the failure address contained in the combined test site.

In an exemplary embodiment, when performing RA algorithm calculation on the failure address in the Raw Data file, the tester can choose to combine the Raw Data files belonging to different test sites and then perform the RA algorithm as a whole, so that according to the obtained combination The address files and repair plan files of the failure addresses contained in the test site verify the repair analysis ability of the RA algorithm applied to the combination of multiple test sites.

As shown in Figure 8, after obtaining the address file of the fail address and the repair solution file (Repair Solution), the addresses covered by the address file and the repair solution file can be clearly identified in the simulation software platform in the form of an address space array. address unit. In this way, when the invalid address in the address file is subsequently repaired using the repair plan in the repair plan file, the address units identified in the two arrays can be directly covered and matched (Cover) to obtain a repair result.

In this embodiment, the failure address of DRAM is divided by setting multi-site multi-test items to form corresponding Raw Data files; the Raw Data files of different test sites are used for RA calculations independently, or for at least two test sites. The RA calculation is performed after the failure address is combined, so as to verify the repair analysis ability of the RA algorithm applied to a single test site or a combination of multiple test sites according to the obtained address document and repair plan document of the failure address.

In an exemplary embodiment, a specific implementation manner of repairing an invalid address in an address file based on a repair plan document and showing a repair result is provided. As shown in Fig. 9, step 104 may include the following sub-steps.

Sub-step 1041: Provide a file selection interface, and perform a repair operation based on the invalidation address file and the corresponding repair plan file selected on the interface.

In an exemplary embodiment, as shown in FIG. 10 , after the RA algorithm is used to complete the operation, the simulation software platform will provide an operation interface for selecting failure address files and corresponding repair solution files. Detectors can select the patch file in the patch file menu (FU File), select the address file in the address file menu (MD File); then click "EXECUTE" to run the patch process. After that, the repair result information will be displayed at the bottom of the operation interface.

In an exemplary embodiment, as shown in FIG. 10 , the manner of displaying the repair result is:

An address array of the address space of the simulated invalid DRAM is provided, and a result of whether the selected invalid address file can be successfully repaired by the corresponding repair solution file is identified in the address array.

In the actual display of repair results, the location of the failure address in the failure address document, the location of the repair solution in the repair solution document, and Whether the two match. The so-called match here means that the invalid address is correctly repaired by the repair scheme. For example, when color is used for marking, the failure address can be marked in red, the repair solution can be marked in green, and the match between the failure address and the repair solution can be marked in yellow.

When inspectors need to focus on the repair results on a certain die, they can click on the array position corresponding to the die, such as (02, 02), and then as shown in Figure 11, the simulation software platform will The repair results of the location are displayed in detail, including the statistics (COUNT) of the address units of the above three colors, so that the repair results can be compared more intuitively.

In addition, the inspector can also perform the export operation of the repair result in the simulation software platform as needed, and the simulation software platform generates and exports the repair result to a specified directory file based on the export operation of the repair result. For example, by clicking "OUTPUT", the inspector can export the repair result for subsequent data statistics and analysis.

In this embodiment, the simulation software platform provides a file selection interface to facilitate the detection personnel to trigger the execution of the repair operation based on the failure address file selected on the interface and the corresponding repair plan file. By marking in the address array whether the failure address file selected by the inspector can be successfully repaired by the corresponding repair plan document, it is convenient for the inspector to verify the correctness of the RA algorithm.

The embodiment of the present application also provides an electronic device, as shown in FIG. 12 , including: at least one processor 201; and a memory 202 communicatively connected to the at least one processor 201; The instructions executed by the at least one processor 201, the instructions are executed by the at least one processor 201, so that the at least one processor 201 can execute the methods corresponding to the above-mentioned Figures 1, 4, 7, and 9 example

Wherein, the memory 202 and the processor 201 are connected by a bus, and the bus may include any number of interconnected buses and bridges, and the bus connects one or more processors 201 and various circuits of the memory 202 together. The bus may also connect together various other circuits such as peripherals, voltage regulators, and power management circuits, all of which are well known in the art and therefore will not be further described herein. The bus interface provides an interface between the bus and the transceivers. A transceiver may be a single element or multiple elements, such as multiple receivers and transmitters, providing a means for communicating with various other devices over a transmission medium. The data processed by the processor 201 is transmitted on the wireless medium through the antenna, and the antenna also receives the data and transmits the data to the processor 201 .

Processor 201 is responsible for managing the bus and general processing, and may also provide various functions including timing, peripheral interface, voltage regulation, power management and other control functions. And the memory 202 may be used to store data used by the processor 201 when performing operations.

The embodiment of the present application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by the processor, the above-mentioned method embodiments corresponding to FIG. 1 , FIG. 4 , FIG. 7 , and FIG. 9 are realized.

That is, those skilled in the art can understand that all or part of the steps in the method of the above-mentioned embodiments can be completed by instructing related hardware through a program, the program is stored in a storage medium, and includes several instructions to make a device ( It may be a single-chip microcomputer, a chip, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc., which can store program codes. .

Each embodiment or implementation manner in this specification is described in a progressive manner, each embodiment focuses on the differences from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

In the description of this specification, descriptions with reference to the terms "embodiments", "exemplary embodiments", "some implementations", "exemplary implementations", "examples" and the like mean that the descriptions are described in conjunction with the implementations or examples. A specific feature, structure, material, or characteristic is included in at least one embodiment or example of the present application.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientation construction and operation, therefore should not be construed as limiting the application.

It can be understood that the terms "first", "second", etc. used in this application can be used to describe various structures in this application, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

In one or more drawings, like elements are indicated with like reference numerals. For the sake of clarity, various parts in the drawings are not drawn to scale. Also, some well-known parts may not be shown. For simplicity, the structure obtained after several steps can be described in one figure. In the following, many specific details of the present application, such as device structures, materials, dimensions, processing techniques and techniques, are described for a clearer understanding of the present application. However, as will be understood by those skilled in the art, the application may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit it; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some or all of the technical features; these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Industrial Applicability

In the method for verifying the repair algorithm, the electronic device, and the storage medium provided in the embodiments of the present application, the RA algorithm of the DRAM is verified offline through a simulation software platform. Use the offline verification method to flexibly configure the failure address of the simulated failure DRAM; form the Raw Data file of the failure address; operate the Raw Data file through the repair algorithm to obtain the address file of the failure address and the repair plan file; finally based on The repair plan document repairs the invalid addresses in the address file and displays the repair results, so as to complete the verification process of the RA algorithm without occupying the test machine and causing damage to the wafer, reducing the cost of DRAM production; making up for the current manual Omissions in the comparison method lead to incomplete repair of failed units; the process of online multi-site testing can be simulated to fully verify the results of multi-site repair algorithms and improve the efficiency of algorithm verification.

Claims

A method for verifying patching algorithms, applied to a simulation software platform, comprising:

Configure the invalidation address of the dynamic random access memory that simulates invalidation;

Form the Raw Data file of the invalidation address;

Operating the Raw Data file through a repair algorithm to obtain the address file and repair plan file of the failure address;

The invalid address in the address file is repaired based on the repair scheme document, and a repair result is displayed.
The method according to claim 1, wherein said configuring the invalidation address of the simulated invalidation dynamic random access memory comprises:

An address space and an address input window of the simulated failure DRAM are provided, and the failure address input in the address input window based on the address space is received.
The method according to claim 1, wherein said configuring the invalidation address of the simulated invalidation dynamic random access memory comprises:

An address array of the address space of the simulated failure DRAM is provided, and an address selected from the address array is determined as the failure address.
The method according to claim 1, said method further comprising:

Obtaining the product type of the DRAM;

The described Raw Data file is operated through a repair algorithm to obtain the address file and the repair plan file of the failure address, including:

The Raw Data file is operated through the repair algorithm corresponding to the product type to obtain the address file and repair plan file of the failure address.
According to the method according to claim 1, before the described Raw Data file is operated through a patching algorithm, and the address file and the patching scheme file of the invalidation address are obtained, it also includes:

Obtain the data format of the Raw Data file, and the data format is used to indicate that when the Raw Data file is operated by the repair algorithm, the operation is performed in a conventional manner or in a compressed manner.
The method according to any one of claims 1-5, wherein said configuring the invalidation address of the simulated invalidation dynamic random access memory comprises:

determining the die generating the failure address;

Determine at least one test site, and the test items included in each test site;

Selecting failure addresses belonging to each test item in each of the test stations from the determined dies.
The method according to claim 6, wherein the Raw Data file forming the failure address comprises:

Form the Raw Data file of the failure addresses belonging to each test item in each of the test sites.
The method according to claim 7, wherein said Raw Data file is operated through a repair algorithm to obtain an address file and a repair plan file of said failure address, including:

The Raw Data file is respectively calculated according to the test site to which the failure address belongs, to obtain the address file and the repair plan file of the failure address contained in each of the test sites.
The method according to claim 7, wherein said Raw Data file is operated through a repair algorithm to obtain an address file and a repair plan file of said failure address, including:

The Raw Data file is combined according to at least two combined test sites to which the failure address belongs, to obtain the address file and the repair plan file of the failure address contained in the combined test site.
The method according to claim 1, wherein said repairing the failure address in said address file based on said repair plan document, and displaying a repair result, comprises:

Provide a file selection interface, and perform a repair operation based on the invalidation address file and the corresponding repair plan file selected on the interface;

Display the repair result.
The method according to claim 10, wherein said displaying repair results comprises:

An address array of the address space of the simulated failure DRAM is provided, and a result of whether the selected failure address file can be successfully repaired by the corresponding repair solution file is identified in the address array.
The method according to claim 11, wherein the result of identifying in the address array whether the selected failure address file can be successfully repaired by the corresponding repair solution file includes:

The location of the failure address in the failure address file, the location of the repair solution in the repair solution file, and whether the two match are identified in the address array by at least one of different text, color, and symbols.
The method according to claim 1, said method further comprising:

Based on the export operation of the repair result, generate and export the repair result to the specified directory file.
An electronic device comprising:

at least one processor; and,

a memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, the instructions are executed by the at least one processor, so that the at least one processor can perform the operation described in any one of claims 1 to 13 The verification method of the patching algorithm described above.
A computer-readable storage medium storing a computer program, the computer program implementing the method for verifying the repair algorithm according to any one of claims 1 to 13 when the computer program is executed by a processor.