201237978 六、發明說明： 【發明所屬之技術領域】 本發明有關於一種缺陷分析方法，且特別是有關於缺 陷篩選及取樣方法。 【先前技術】 積體電路的製造過程包括薄膜沈積、光罩曝光、光微 衫技術、蝕刻等，在製造的過程中，隨機微微粒缺陷(rand〇m partlde defect)及系統性缺陷（systematic defect)等難以避免 地產生，這將影響產品的良率，而產品的良率關係到晶粒 的成本。201237978 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a defect analysis method, and more particularly to a defect screening and sampling method. [Prior Art] The manufacturing process of the integrated circuit includes thin film deposition, mask exposure, optical micro-shirt technology, etching, etc., during the manufacturing process, random microparticle defects (systematic defects) and systematic defects (systematic defects) ) etc. are inevitably generated, which will affect the yield of the product, and the yield of the product is related to the cost of the die.
Ik著设计佈局的特徵尺寸逐漸縮小，影響產品良率有 關的缺陷變得較小，為了擷取晶圓上所有致命的缺陷，代 工廠必須增加其掃描及檢驗器具的靈敏度。因此，被檢 驗出來的缺陷個數也會隨之增加，然而，事實上非致命 的缺陷占所有檢驗出來的缺陷百分比亦會增加。此外， 為了確認出真正潛在性的缺陷，代卫廠將使用電子式掃 描顯微鏡來檢視及分類所有被檢驗出來的缺陷。然而， 代工麻的相卻是有限的，且絲檢視的電子式掃描顯 微鏡的效能可能限制了每個晶圓上被觀察的個數。因此 ’目前的技術在確認出產品上屬於重要類型的缺陷是有 困難的，且具有迖漏辨識出致命性缺陷的風險。 备;又有個陕速且創新的方法來預先地確認系統性缺 陷’代工廠將面g品龐大的產量下滑以及花費大量的學習時 間在量產上。 4/19 201237978 【發明内容】 篩選實施例提供―種智慧型缺陷 缺陷的效率/ 善系統性缺陷的檢測率以及檢視 陷篩i : ^ =目勺:’本發明實施例提供-種智慧型缺 複數個基於佈二::1先::產品的設計佈局處理為 案群中的據其佈局圖案特徵而屬於多個圖 個曰月勺"/重豐多個晶胞中屬於同一個圖案群的多 ==缺陷資料，其中多個缺陷資料中的么： 陷八成图麵 來建立複數個基於佈局的缺 陷有至少一個缺陷聚集佈局圖案的缺 _中的每一::==以取得多個缺陷合成 合成圖案群執行-些缺陷取樣選擇法則，=斷2 缺陷合成圖案群的潛在孚统 群的潛在 :ΐΐ:二為多個不同的缺陷類型;根據多個缺陷 樣:數的多個缺 率分析以產生一缺陷圖案資 絲上所述’本發明實施例所提供的智慧型缺陷筛選與 5/19 201237978 ==:=樣率來達成增加—缺陷的檢 為使能更進一步瞭解本發明之特徵及技術内容，社夫 閱以下有關本發明之詳細說明與附圖 = 任何的限制。 4知a日〕推利乾圍作 【實施方式] 本。兄明書揭露一種智眷刑缺[J々纟A·t 據對每-個基於佈局的缺陷合成;^ =:=缺陷影像來檢視。因此，如果在製‘ 釭中有任何本統性缺陷出現在產品上，則使用 設計者)便可準確地預先知道並處理這些缺陷。 在:揭露書中，產品可以是晶圓、光罩、一印刷電路 電池。圓凸塊、—發光二極體或太陽能 所述的智慧型缺陷篩選鱼取 4 行’或是軟體結合硬體來實施取執 上自動地執行，或是在多A 疋在早獨一台電腦 。 / σ又互作用的電腦上自動地執行 請參照圖1Α’圖1Α是本發明的一每 二 代工薇的示意圖。本實施例的、^歹，°又5十公司與 >、知驻I丨， 座。口舉日日圓為例。整體上央 况《慧型缺陷篩選與取樣方法可 稱工廠20)中執行，或是在 =礙20(以下間 設計公司，執行。設計=路 =二以下簡稱 的設計佈局（deSign layout)iJ2'、一個/體電路設計 ;、、°工廠20。工廠20根據設計 6/19 201237978 邓局使用上百個製造機具及設備在晶圓上製造出許多重複 的晶粒（die)。在製造的過程中，一些缺陷將無法避免地產 生在晶圓上，例如隨機微微粒缺陷、製程關連缺陷（pr〇cess related defects)、系統性缺陷。 這些缺陷是由工廠20中的一缺陷掃描及檢蜍器具所 檢測出來，且此缺陷掃描及檢驗器具根據檢測結果輸出 複數個與缺陷相對應的缺陷資料。工廠2〇中的電腦將被 啟動來執行智慧型缺陷篩選與取樣方法，以分析來自缺陷 掃描及檢驗器具的缺陷資料。並藉由執行缺陷產生率分析 來取得一缺陷圖案資料庫或一缺陷產生預測給設計公司3〇 〇 〔弟一實施例〕 接著’請參考圖1B ’圖1B為本發明的智慧型缺陷 篩選與取樣方法的第一實施例之流程圖。 請一併參考圖1C’圖ic為本發明的智慧型缺陷篩選與 取樣方法的第一實施例之示意圖。 使用者預先將設計佈局110處理為複數個基於佈局的 圖案群（layout based pattern group) LPGi、LPG2、lpg3 (S101)，其中設計佈局11〇是由使用者設計給晶圓，晶 圓10具有一完整晶片佈局（full-chip layout)ll ’且完整 晶片佈局11包括複數個晶粒（die) llDj、1〗D2,、1]d3，藉 由電知攸一設計佈局資料庫祿取出多個晶粒〗1D1、丨1 £>2,、 及]1D3的設計佈局]10，所擷取的設計佈局110具有複 數個佈局圖案（layout pattern)以及位於設計佈局〗10或 晶圓]0中心的第二參考原點(x〇2, y〇2) ’其中多個佈局圖 案具有不相同的佈局圖案特徵。 7/19 201237978 接著，電腦根據佈局圖案特徵將設計佈局110劃分 為複數個晶胞（cell) Cll~Cla、C21 〜C2b、C31 〜C3c(S103) ，其中多個晶胞C11〜Cla、C21〜C2b、C31〜C3c中的一些 晶胞具有相同的佈局圖案特徵，具有相同的佈局圖案特 徵的晶胞便被分配成複數個基於佈局的圖案群LPG!、 LPG2、LPG3中的同一群’每一群基於佈局的圖案群LPG! 、LPG2或LPG3具有不同個數的多個晶胞C11〜Cla、 C21 〜C2b、C31 〜C3c。 然後，電腦將多個晶胞C11〜Cla、C21〜C2b、C31〜C3c 中屬於同一個圖案群LPGi、LPG2或LPG3的多個晶胞重 疊在一起（S105)。 接著’電腦再從一缺陷掃描及檢驗器具（圖未示）擷 取晶圓10上的多個缺陷101的複數筆缺陷資料 130(S107) ’圖1C上顯示了來自缺陷掃描及檢驗器具所 取得的缺陷設計佈局100上的其中一缺陷1 〇3。缺陷1 〇3 的多筆缺陷資料130中的每一筆包括缺陷1〇3的序號 (identification number)、缺陷 1〇3 所屬的晶粒編號（die index)、缺陷103的第一缺陷座標(Xl，yi)及缺陷1〇3的尺 寸。其中第一缺陷座標(X!，yi)是相對於第一參考原點座 才示(x〇i，y〇i)，而第一參考原點座標(x〇1, y〇1)可由缺陷掃描 及檢驗器具所產生’且第一參考原點座標(x〇i，y〇i)可以是 位於缺陷設計佈局100的中心或角落，以作為標記 (marker)。 缺陷資料130更包括產品名稱、缺陷製造過程、批 號及粗略的缺陷影像等，值得注意的是，晶圓1〇上的 第一參考原點座標(x0],y01)並非缺陷103在設計佈局11〇 8/19 201237978 上的精確座標，在一實施例中，缺陷設計佈局100的檔 案規格可以是·丨PG、TIFF、PNG或純文字（text)規格等， 而设計佈局丨10的規格可以是GDS或OASIS規格等。 電腦對缺陷1〇3的第一缺陷座標(Xl, yi)執行座標轉 換’將相對於第一參考原點座標(x〇|, y〇l)的第一缺陷座標 (Xl’yi)轉換為第二缺陷座標y2)，其中第二缺陷座標(χ2, 》’2)疋相對於第二參考原點座標(xo2，yo2),且第二參考原點 座標(x〇2，y〇2)是屬於設計佈局110的設計佈局座標系統 的原點或中心點。 經過座標轉換後，電腦藉由映射多個缺陷〗01至重 疊的多個圖案群LPG]、LPG24 LPG3來建立複數個基於 佈局的缺陷合成圖案群LDPG,、LDPG2、LDPG3(S 109)。 其中每一個缺陷合成圖案群LDPGi、LDPG2或LDPG3 具有不同的佈局圖案及不同的合成缺陷圖案，電腦對具 有至少一個缺陷聚集佈局圖案的缺陷合成圖案群LDPG】 、LDPG2、LDPG3執行佈局圖案匹配，以取得多個缺陷合 成圖案群LDPGi、LDPG2、LDPG3中的每一個獨特的缺陷 合成圖案群(Sill)。 接著’電腦對每一個缺陷合成圖案群LDPG,、LDPG2 、LDPG3執行一些缺陷取樣選擇法則，以判斷多個缺陷 合成圖案群LDPG!、LDPG2、LDPG；?的潛在系統性缺陷優 先順序（Potential systematic defect prioi，ity)(si 13)。 然後’電腦根據多個缺陷合成圖案群LDPG 1、LDPG， 、LDPGs的潛在系統缺陷優先順序將多個缺陷合成圖案 群LDPG】、LDPG2、LDPG3分類為多個不同的缺陷類型 (defect type)(S115)。 9/19 201237978 在一實施例中，缺陷類型可包括系統性缺陷類型及 非系統性缺陷類型，其中系統性缺陷類型可以是頸縮 (necking)、橋接（bridging)、遺漏（missing)、崩塌 (collapsing)或不符設計佈局（design weak)缺陷。而非系 統性缺陷類型包括虛擬圖案（dummy pattern)缺陷、非標 準製程(abnormal process)缺陷、光罩缺陷、隨機微粒缺 陷或非致命性多餘(nuisance)缺陷類型。 多個缺陷合成圖案群LDPG,、LDPG2、LDPG3中的每 一個所包含的一些缺陷佈局圖案1 〇〇被傳送至掃目苗式電 子顯微鏡（SEM)作檢視，其中每一個缺陷合成圖案群 LDPG!、LDPG2或LDPG3所取樣的缺陷佈局圖案1〇〇個數 是根據其所屬的缺陷類型及潛在系統缺 有所不同。舉例來說，系統性缺陷類型的取== 糸統性缺陷_的取樣個數多。藉此，本發明的實施例 陷筛選及取樣方法可精確地監測到缺陷 ，亚即#目田式電子顯微鏡(SEM)的檢視時間而不 漏了任何糸統性缺陷。 夂 …^/岡峨阳兮攻圖案群 成圖案群，根據檢視結果取得— 其中缺陷影像料包括的缺㈣案(训 陷的影像。 ^像為真正的系統'丨 最電腦藉由對缺陷影像標案執行1 “斤以產-缺陷圖案資料庫或 崎其中被檢視的缺陷影像可‘= 形圖案的格•存在缺陷 t碼或夕 卞貝丁寸厍，—進制代碼可 10/19 201237978 疋GDS或〇Asis格式，多邊形可以是jpg、png、tiff 或純文子格式。缺陷圖案資料庫可以儲存至工廠20的 網頁。 〔第一貫施例〕 、π翏考圖2,圖2為本發明的智慧型缺陷篩選與取樣 =法的第二實施例之流程圖。如圖2所示，第二實施例的 3型缺陷篩選與取樣方法與第—實關的智慧型缺陷筛 選與取樣方法大致相同，其差異在於，電腦建立複數個基 於佈局的缺陷合成圖案群LDPGi、ldpg2、ldpg3(s 1 之後’第二實施例的智慧型缺陷篩選與取樣方法更包括 下步驟。 電腦執行的缺陷取樣選擇法則包括計算每—個缺 陷合成圖案群LDPGi、LDPG2或LDPG3的一命中率（S21 。其中命中率是關於每一個缺陷合成圖案群LDPG|、 LDPG2或LDPG3中的多個缺陷101個數與多個缺陷1〇1 所屬的多個晶胞CU〜Cla、C21〜C2b、C31〜C3c個數的關 係。舉例來說，命中率等於個缺陷1〇1個數除以多個晶 胞C11〜Cla、C21〜C2b、C31〜C3c個數，若缺陷合成圖案 群LDPGj、LDPG2或LDPG3的命中率較高，則缺陷合成 圖案群LDPG,、LDPG2或LDPG3的類型較可能為系統性 缺陷類型。 電腦執行的缺陷取樣選擇法則更包括估計每—個 缺陷合成圖案群LDPGj、LDPG2或LDPG3的一致命缺陷 指數(S213)，其中致命缺陷指數是關於多個缺陷1〇丨的 母一個缺陷的缺陷尺寸、缺陷座標偏移及佈局圖案的臣台 界面積（critical area)。舉例來說，當缺陷尺寸較大時， 11/19 201237978 且佈局圖案的線寬(width)及空間（space)較細，則佈局圖 案的臨界面積較大’而致命缺陷指數是正比於缺陷101 所位於的佈局圖案的臨界面積，且致命缺陷指數代表佈 局圖案中的缺陷位置的失敗可能性（failure probability) ’例如佈局圖案是呈現開路(open)或短路(short)具有較高 的失敗可能性。 電腦執行的缺陷取樣選擇法則更包括對每一個缺 陷合成圖案群群LDPG,、LDPG24 LDPG3執行一統計聚 集分部分析（S215)。統計聚集分部分析是指找尋每一個 缺陷合成圖案群群LDPG!、LDPG2或LDPG3上缺陷出現 頻率的分布統計，由統計結果所得到的統計尖端位置 (statistic peak coordinate)代表缺陷經常出現的位置，也 就疋此位置出現系統性缺陷的機會高於隨機微粒缺陷。 電腦執行的缺陷取樣選擇法則更包括對每一個晶 粒11D!、11D2,或11D3中的多個晶胞cil〜Cla、C21〜C2b 、C31〜C3c的佈局圖案執行晶圓圖特徵圖案分析 (wafermap signature pattern analysis)(S217)。晶圓圖特徵 圖案为析疋參,日，?、來自聚焦曝光矩陣（focus exposure matrix (FEM))或製程視窗認證測試（process wind〇w qualification (PWQ) test)。舉例來說，當晶粒 11Dl、11Ε)2, 或1ID3的臨界尺寸厚度的變化是非標準變異時，則系統 性缺陷可能存在。 在一實施例中’使用者可藉由電腦設定上述不同的 缺陷取樣選擇法則所佔有的權重來安排每一個缺陷合 成圖案群LDPGi、LDPG2或LDPG3所取樣的缺陷佈局圖 案100個數是根據其所屬的缺陷類型及潛在系統缺陷優 12/19 201237978 先順序。 除此之外’電腦執行的缺陷取樣選擇法則更包括^ 多個缺陷合成圖案群LDPGi、LDPG:、LDPGs中過濾虛擬 的佈局圖案（empty field or dummy pattern)缺陷來增進系 統性缺陷的檢測率以及檢視缺陷的效率。 電腦還可以藉由設計確認(design check)來分析設令十 佈局110是屬於不符設計佈局（design weak)的缺陷類型 ’不符設計佈局的缺陷類型可以是違反設計規則（design rule)、微影製程 / 化學拋光（lith〇graphy/chemieal mechanical polishing (CMP))模擬熱點及已存在的缺陷 圖案測試。 當缺陷分布的區域是在較異常高缺陷個數的晶較 llDt、11D2,或IID3，電腦還可以將缺陷1〇1分析為異常 製程缺陷類型，此缺陷分布的區域特別是指缺陷分布的 形狀為環狀等，且位於中心區域或邊緣的晶粒11Di、Iid 或 iid3。 2' 電腦還可藉由檢查缺陷的位置是在設計佈局〗10上 的一些重複標線（repeated reticle)或是光罩修復位置 (mask repair position)上，則電腦將缺陷1〇]分析為 缺陷類型。 罩 當缺陷101具有不同的尺寸大小，或隨機分布在曰 圓圖上，則電腦可將缺陷1〇1分析為隨機顆粒缺陷類= 〔第三實施例〕 請參考圖3,圖3為本發明的智慧型缺陷篩選與取樣 方法的第三實施例之流程圖。如圖3所示，第二每 不一貝、施例的 13/19 201237978 樣方法與第一實施例的智陷筛 L、取樣方法纽㈣，其差異在於，㈣ 圖案貪料庫或-缺陷產生率賴（SU9)之後三實 例的智慧型賴篩選與取樣方法更包括以下㈣。、匕 庫公司Γ從工廠20的網站下載缺陷圖案資料 庫（21)。汉计么司3〇的使用者從一設計 中擷取一個新設計佈局⑽3)。藉由電腦對新設計佈^ 的複數個新設計佈局圖案與缺陷資料庫 圖案執行圖案匹配(S325)。 〇1_局 電腦根據執行圖案匹配辨識出在新設計佈局中的 一潛在系統性缺陷圖案的位置（5327)。最後，使用者藉 由圖案匹配的結果修復在製造過程中的潛在系統性ς 陷圖案（S329)。 〔第三實施例〕 請參考圖4’圖4為本發明的智慧型缺陷篩選與取樣 方法的第四貫施例之流程圖。如圖4所示，第四實施例的 智慧型缺㈣選與取樣方法與第—實關的智慧型缺陷筛 選與取樣方法大致相同，其差異在於，電腦藉產生—缺陷 圖案資料庫或一缺陷產生率預測（S119)之後，第四實= 例的兔慧型缺陷篩選與取樣方法更包括以下步驟。 —工廠20藉由智慧型缺陷篩選與取樣方法估算晶圓忉 中每一層的缺陷產生率預測（S421)。藉由加入所有缺陷 檢驗層的缺陷產生率分析數據來執行合成缺陷產生率 分析（S423)。之後，根據缺陷產生率分析產生一批次(丨的) 及晶圓的缺陷產生率報告（S425)。 14/I9 201237978 工廠20上傳批次及晶圓的缺陷產生率報告至一工 廠網站（S427)。最後客戶或是設計者可根據批次及晶圓 的缺陷產生率報告估計出整體的良好晶粒交貨品質預 測（S429)。藉此，客戶或是設計者不僅可知道正在製造 的缺陷良率，更可以知道即將出貨的整體良好晶粒的品 質。 1. 設計佈局圖案上所有的缺陷可整體地被預先 或即時地監視，並可迅速地被修復，而非單 一地被一一檢查。 2. 智慧型缺陷篩選及取樣方法可增進系統性缺陷 的檢測率以及檢視缺陷的效率。 3. 設計公司可即時掌握整體良好晶粒的品質及 缺陷的產生。 4. 設計佈局可被預先地修復以提高產品的產量 〇 綜合上述，本發明所提供的實施例具有以下可能的 效果。 以上所述僅為本發明之實施例，其並非用以侷限本發 明之專利範圍。 【圖式簡單說明】 圖1A是本發明的一實施例之設計公司與代工廠的示 意圖。 圖1B為本發明的智慧型缺陷篩選與取樣方法的第一 15/19 201237978 實施例之流程圖。 圖1C為本發明的智慧型缺關選與取樣方法的第一實 施例之示意圖。 圖2為本發明的智慧型缺陷筛選與取樣方法的第二實 施例之流程圖。 ' 圖3為本發明的智慧型缺陷篩選與取樣方法的第三實 施例之流程圖。 圖4為本發明的智慧型缺陷筛選與取樣方法的第四實 施例之流程圖。 【主要元件符號說明】 2〇 :代工廠 30 :積體電路設計公司 10 .晶圓 11 :完整晶片佈局 110 :設計佈局 100 :缺陷佈局圖案 101、103 :缺陷 11D!、11D2 ' ]id3、UDn :晶粒 Cll〜Cla ' C21 〜C2b、C31 〜C3c :晶胞 LPGj〜LPG3 :基於佈局的圖案群 LDPG^LDPG3 :基於佈局的缺陷合成圖案群 (xi’yi)、（x2，y2):缺陷座標 (x〇i，y〇i)、（x02，y〇2广原點座標 S10卜S119、S211〜S217、S32卜S329、S42卜S429 :智慧型 缺陷篩選及取樣方法步驟 16/19Ik's feature size of the design layout is gradually shrinking, and the defects affecting the yield of the product become smaller. In order to capture all fatal defects on the wafer, the foundry must increase the sensitivity of its scanning and inspection instruments. As a result, the number of defects detected will increase, however, in fact, non-fatal defects will increase the percentage of defects detected. In addition, in order to identify the true potential defects, the Dairy Factory will use an electronic scanning microscope to examine and classify all defects detected. However, the phase of OEM is limited, and the performance of the silk-scanned electronic scanning microscope may limit the number of observations on each wafer. Therefore, the current technology is difficult to identify defects that are important types of products, and there is a risk of identifying fatal defects. There is also a fast and innovative way to pre-identify systemic defects. The foundry will face a huge decline in production and spend a lot of learning time on mass production. 4/19 201237978 [Summary] The screening embodiment provides the efficiency of the kind of intelligent defect defect/the detection rate of the good system defect and the inspection trap i: ^ = the object: 'The present invention provides a kind of wisdom deficiency Multiple based on cloth 2::1 first:: The design layout of the product is treated as a plurality of maps according to the layout pattern characteristics of the group, and the plurality of cells belong to the same pattern group. More == defect data, which is among the multiple defect data: trapping eight layers to create a plurality of layout-based defects with at least one defect aggregation layout pattern of each of the missing_::== to obtain multiple Defect Synthesis Synthetic Pattern Group Execution - Some Defect Sampling Selection Rules, = Break 2 Defective Potential Pattern Group Potential Latent Group: ΐΐ: Two are multiple different defect types; based on multiple defects: multiple defects Rate analysis to generate a defect pattern on the silk of the 'intelligent defect screening provided by the embodiment of the present invention and 5/19 201237978 ==:= sample rate to achieve an increase - the defect detection is enabled to further understand this Characteristics and technical content of the invention Cardiff Co. reading the following detailed description and the accompanying drawings relating to the present invention any limitations =. 4 know a day] push and dry work [Embodiment] This. The brothers book reveals a lack of wisdom and punishment [J々纟A·t according to each of the layout-based defect synthesis; ^ =:= defect image to view. Therefore, if any of the defects in the system are present on the product, the designer can accurately know and handle these defects in advance. In the disclosure, the product can be a wafer, a photomask, or a printed circuit battery. Round bumps, light-emitting diodes or solar-powered smart defect screening fish take 4 lines' or software-incorporated hardware to implement automatic execution, or in a single A computer in the early morning . / σ interacts with the computer automatically. Please refer to Fig. 1A. Fig. 1 is a schematic diagram of a second generation of the present invention. In this embodiment, ^ 歹, ° and 5 companies and >, know the station I 丨, seat. Take the Japanese yen as an example. The overall situation of the "Hyper-type defect screening and sampling method can be called factory 20" is implemented, or in the case of = 20 (the following design company, implementation. Design = road = two below the design layout (deSign layout) iJ2' , one / body circuit design; , ° factory 20. Factory 20 according to design 6/19 201237978 Deng Bureau uses hundreds of manufacturing tools and equipment to make a lot of repeated die on the wafer. In the manufacturing process Some defects will inevitably occur on the wafer, such as random microparticle defects, pr〇cess related defects, and systemic defects. These defects are detected by a defect in the factory 20 and inspection equipment. Detected, and the defect scanning and inspection apparatus outputs a plurality of defect data corresponding to the defect according to the detection result. The computer in the factory 2〇 is activated to perform the intelligent defect screening and sampling method to analyze the defect scanning and Inspect the defect data of the appliance and obtain a defect pattern database or a defect generation prediction by performing a defect generation rate analysis to the design company. Embodiment 1 Next, please refer to FIG. 1B. FIG. 1B is a flowchart of a first embodiment of a smart defect screening and sampling method according to the present invention. Please refer to FIG. 1C' FIGic for the smart defect screening and the present invention. A schematic diagram of a first embodiment of the sampling method. The user pre-processes the design layout 110 into a plurality of layout based pattern groups LPGi, LPG2, lpg3 (S101), wherein the design layout 11 is by the user Designed for the wafer, the wafer 10 has a full-chip layout ll ' and the complete wafer layout 11 includes a plurality of dies llDj, 1 D2, 1] d3, by means of electronics A design layout database takes out a plurality of crystal grains 1D1, 丨1 £>2, and 1D3 design layout] 10, the designed layout 110 has a plurality of layout patterns and is located in the design Layout 10 or wafer] 0 center second reference origin (x〇2, y〇2) 'The multiple layout patterns have different layout pattern features. 7/19 201237978 Next, the computer will be based on the layout pattern features Design layout 110 is divided into a plurality of cells C11 to Cla, C21 to C2b, and C31 to C3c (S103), wherein some of the plurality of unit cells C11 to Cla, C21 to C2b, and C31 to C3c have the same layout pattern characteristics. The cells having the same layout pattern feature are assigned to the same group of the plurality of layout-based pattern groups LPG!, LPG2, and LPG3. Each group of layout-based pattern groups LPG!, LPG2, or LPG3 has a different number of Unit cells C11 to Cla, C21 to C2b, and C31 to C3c. Then, the computer overlaps a plurality of cells belonging to the same pattern group LPGi, LPG2 or LPG3 among the plurality of unit cells C11 to Cla, C21 to C2b, and C31 to C3c (S105). Then, the computer retrieves a plurality of defect defects 130 of the plurality of defects 101 on the wafer 10 from a defect scanning and inspection apparatus (not shown) (S107). FIG. 1C shows the obtained from the defect scanning and inspection apparatus. The defect is designed on one of the 100 defects on the layout 1 〇 3. Each of the plurality of defect data 130 of the defect 1 〇3 includes an identification number of the defect 1〇3, a die index to which the defect 1〇3 belongs, and a first defect coordinate of the defect 103 (X1, Yi) and the size of the defect 1〇3. The first defect coordinate (X!, yi) is shown relative to the first reference origin (x〇i, y〇i), and the first reference origin coordinate (x〇1, y〇1) may be defective. The scan and inspection appliance generates 'and the first reference origin coordinate (x〇i, y〇i) may be located at the center or corner of the defect design layout 100 as a marker. The defect data 130 further includes the product name, the defect manufacturing process, the batch number, and the rough defect image. It is worth noting that the first reference origin coordinate (x0), y01 on the wafer 1 is not the defect 103 in the design layout 11精确8/19 201237978 precision coordinates, in one embodiment, the defect design layout 100 file specification can be 丨 PG, TIFF, PNG or text (text) specifications, and the design layout 丨 10 specifications can It is a GDS or OASIS specification. The computer performs coordinate conversion on the first defect coordinate (X1, yi) of the defect 1〇3 to convert the first defect coordinate (Xl'yi) relative to the first reference origin coordinate (x〇|, y〇l) into a second defect coordinate y2), wherein the second defect coordinate (χ2, ′′′2) 疋 is relative to the second reference origin coordinate (xo2, yo2), and the second reference origin coordinate (x〇2, y〇2) It is the origin or center point of the design layout coordinate system belonging to the design layout 110. After the coordinate conversion, the computer creates a plurality of layout-based defect synthesis pattern groups LDPG, LDPG2, and LDPG3 (S 109) by mapping a plurality of defects 001 to a plurality of overlapping pattern groups LPG] and LPG24 LPG3. Each of the defect synthesis pattern groups LDPGi, LDPG2 or LDPG3 has different layout patterns and different synthetic defect patterns, and the computer performs layout pattern matching on the defect synthesis pattern group LDPG], LDPG2, and LDPG3 having at least one defect aggregation layout pattern, A unique defect synthesis pattern group (Sill) of each of the plurality of defect synthesis pattern groups LDPGi, LDPG2, and LDPG3 is obtained. Then, the computer performs some defect sampling selection rules for each defect synthesis pattern group LDPG, LDPG2, and LDPG3 to determine the potential systematic defect priority order of multiple defect synthesis pattern groups LDPG!, LDPG2, LDPG; Prioi, ity) (si 13). Then, the computer classifies the plurality of defect synthesis pattern groups LDPG, LDPG2, and LDPG3 into a plurality of different defect types according to the priority system defect order of the plurality of defect synthesis pattern groups LDPG 1, LDPG, and LDPGs (S115) ). 9/19 201237978 In an embodiment, the defect type may include a systematic defect type and a non-systematic defect type, wherein the system defect type may be necking, bridging, missing, collapse ( Collapsing) or does not conform to the design weakness. Non-systematic defect types include dummy pattern defects, abnormal process defects, mask defects, random particle defects, or non-fatal nuisance defect types. A plurality of defective layout patterns LDPG, LDPG2, and LDPG3 each contain a defect layout pattern 1 〇〇 is transmitted to a scanning electron microscope (SEM) for inspection, wherein each defective pattern group LDPG! The number of defect layout patterns sampled by LDPG2 or LDPG3 is different depending on the type of defect to which it belongs and the potential system. For example, the number of systematic defect types == 糸 性 _ _ is more than the number of samples. Thereby, the embodiment of the present invention can accurately monitor the defects, i.e., the viewing time of the SEM, without missing any deficiencies.夂...^/Gangyangyang attacking the pattern group into a pattern group, according to the results of the inspection - the defect image material includes the missing (four) case (the image of the training trap. ^ like the real system The execution of the standard 1 "Jian production-defect pattern database or the defect image that is inspected by Saki can be '= shape pattern grid ・There is defect t code or Xibei Beiding inch code, the code can be 10/19 201237978 疋GDS Or 〇Asis format, the polygon can be jpg, png, tiff or pure text sub-format. The defect pattern database can be stored in the webpage of the factory 20. [First embodiment], π翏考图2, Figure 2 is the A flow chart of a second embodiment of the smart defect screening and sampling method. As shown in FIG. 2, the third type defect screening and sampling method of the second embodiment and the first-order intelligent defect screening and sampling method are roughly The difference is that the computer establishes a plurality of layout-based defect synthesis pattern groups LDPGi, ldpg2, and ldpg3 (after 1 'the smart defect screening and sampling method of the second embodiment further includes the following steps. The selection rule includes calculating a hit rate of each of the defective composite pattern groups LDPGi, LDPG2 or LDPG3 (S21), wherein the hit ratio is about the number of defects and the number of defects in each of the defective synthetic pattern groups LDPG|, LDPG2 or LDPG3 The relationship between the number of cells CU~Cla, C21~C2b, and C31~C3c to which the defect 1〇1 belongs. For example, the hit rate is equal to one defect 1〇1 number divided by multiple unit cells C11~Cla , C21~C2b, C31~C3c, if the hit ratio of the defect synthesis pattern group LDPGj, LDPG2 or LDPG3 is high, the type of the defect synthesis pattern group LDPG, LDPG2 or LDPG3 is more likely to be a system defect type. The defect sampling selection rule further includes estimating a fatal defect index (S213) of each of the defective synthetic pattern groups LDPGj, LDPG2 or LDPG3, wherein the fatal defect index is a defect size and a defect of a female defect of a plurality of defects 1〇丨. The coordinate offset and the layout area of the layout pattern. For example, when the defect size is large, 11/19 201237978 and the layout pattern has a narrow line width and space, the layout is fine. pattern The critical area is larger' and the fatal defect index is proportional to the critical area of the layout pattern in which the defect 101 is located, and the fatal defect index represents the failure probability of the defect position in the layout pattern. For example, the layout pattern is an open circuit ( Open) or short has a high probability of failure. The computer-implemented defect sampling selection rule further includes performing a statistical aggregation segmentation analysis (S215) for each defective composite pattern group LDPG, and LDPG24 LDPG3. Statistical clustering analysis refers to finding the distribution statistics of the frequency of defects on each defect composite pattern group LDPG!, LDPG2 or LDPG3. The statistical peak coordinate obtained from the statistical results represents the location where the defects often appear. There is also a higher chance of systemic defects in this location than random particle defects. The defect sampling selection rule executed by the computer further includes performing a wafer pattern feature pattern analysis (wafermap) on a layout pattern of a plurality of unit cells cil~Cla, C21~C2b, C31~C3c in each of the crystal grains 11D!, 11D2, or 11D3. Signature pattern analysis) (S217). Wafer pattern features are 疋 ,, 日, ?, from the focus exposure matrix (FEM) or process wind 〇 w qualification (PWQ) test. For example, when the change in the critical dimension thickness of the grain 11D1, 11Ε)2, or 1ID3 is a non-standard variation, a systematic defect may exist. In an embodiment, the user can arrange the number of defect layout patterns sampled by each defect synthesis pattern group LDPGi, LDPG2 or LDPG3 by the computer to set the weights of the different defect sampling selection rules. Defect type and potential system defect excellent 12/19 201237978 first order. In addition, the 'computer-implemented defect sampling selection rule includes ^ multiple defect synthesis pattern group LDPGi, LDPG:, LDPGs filter empty layout pattern (empty field or dummy pattern) defects to improve the detection rate of systemic defects and View the efficiency of defects. The computer can also analyze the design ten by the design check. The layout 110 is a defect type that does not conform to the design weakness. The defect type that does not conform to the design layout may be a design rule or a lithography process. / lith〇graphy/chemieal mechanical polishing (CMP) simulates hot spots and existing defect pattern tests. When the area of the defect distribution is llDt, 11D2, or IID3 in the number of abnormally high defects, the computer can also analyze the defect 1〇1 as an abnormal process defect type, and the area of the defect distribution especially refers to the shape of the defect distribution. The crystal grains 11Di, Iid or iid3 which are annular or the like and located at a central region or edge. 2' The computer can also analyze the defect as a defect by checking the location of the defect on some repeated reticle or mask repair position on the design layout 10. Types of. When the defects 101 have different sizes or are randomly distributed on the circle diagram, the computer can analyze the defects 1〇1 into random particle defects = [Third embodiment] Please refer to FIG. 3, which is the present invention. A flowchart of a third embodiment of the smart defect screening and sampling method. As shown in FIG. 3, the second method of the 13/19 201237978 method of the second embodiment, the method of the first embodiment of the wisdom trap screen L, the sampling method button (4), the difference is that (4) the pattern of the greedy library or the defect The wisdom-based screening and sampling methods of the three instances after the generation rate (SU9) include the following (4).匕 The library company downloaded the defect pattern database from the website of the factory 20 (21). The user of Hanji's 3〇 draws a new design layout from a design (10)3). Pattern matching is performed by the computer on a plurality of new design layout patterns of the new design and the defect database pattern (S325). 〇1_ The computer recognizes the location of a potential systematic defect pattern in the new design layout based on the execution pattern matching (5327). Finally, the user repairs the potential systematic defect pattern in the manufacturing process by the result of the pattern matching (S329). [Third Embodiment] Please refer to Fig. 4'. Fig. 4 is a flow chart showing a fourth embodiment of the smart defect screening and sampling method of the present invention. As shown in FIG. 4, the intelligent missing (four) selection and sampling method of the fourth embodiment is substantially the same as the intelligent defect screening and sampling method of the first-real control, and the difference is that the computer generates a defect pattern database or a After the defect generation rate prediction (S119), the fourth embodiment of the rabbit genital defect screening and sampling method further includes the following steps. - Factory 20 estimates the defect generation rate for each layer in the wafer defect by intelligent defect screening and sampling methods (S421). The synthetic defect generation rate analysis is performed by adding the defect generation rate analysis data of all the defect inspection layers (S423). Thereafter, a batch (丨) and wafer defect generation rate report (S425) is generated based on the defect generation rate analysis. 14/I9 201237978 Factory 20 uploads batch and wafer defect generation rate reports to the factory website (S427). Finally, the customer or designer can estimate the overall good die delivery quality prediction based on the batch and wafer defect rate report (S429). In this way, the customer or the designer can not only know the defect yield being manufactured, but also know the quality of the overall good grain to be shipped. 1. All defects on the design layout pattern can be monitored in advance or in advance, and can be quickly repaired, rather than being checked individually. 2. Intelligent defect screening and sampling methods can improve the detection rate of systemic defects and the efficiency of viewing defects. 3. The design company can instantly grasp the quality of the overall good grain and the generation of defects. 4. The design layout can be pre-fixed to increase the yield of the product. 〇 In summary, the embodiments provided by the present invention have the following possible effects. The above is only an embodiment of the present invention, and is not intended to limit the scope of the patents of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic illustration of a design company and a foundry according to an embodiment of the present invention. 1B is a flow chart of a first 15/19 201237978 embodiment of the smart defect screening and sampling method of the present invention. Fig. 1C is a schematic view showing a first embodiment of the smart-type selection and sampling method of the present invention. 2 is a flow chart of a second embodiment of the smart defect screening and sampling method of the present invention. Figure 3 is a flow chart showing a third embodiment of the smart defect screening and sampling method of the present invention. Fig. 4 is a flow chart showing a fourth embodiment of the smart defect screening and sampling method of the present invention. [Main component symbol description] 2〇: Foundry 30: Integrated circuit design company 10. Wafer 11: Complete wafer layout 110: Design layout 100: Defect layout pattern 101, 103: Defect 11D!, 11D2 ']id3, UDn : Grains C11 to Cla 'C21 to C2b, C31 to C3c: Unit cells LPGj to LPG3: Pattern-based pattern group LDPG^LDPG3: Layout-based defect pattern group (xi'yi), (x2, y2): defect Coordinates (x〇i, y〇i), (x02, y〇2 Guangyuan coordinates S10, S119, S211~S217, S32, S329, S42, S429: Smart defect screening and sampling method steps 16/19