CN115599576A

CN115599576A - Method for verifying patching algorithm, electronic equipment and storage medium

Info

Publication number: CN115599576A
Application number: CN202110772368.XA
Authority: CN
Inventors: 杨柳
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-07-08
Filing date: 2021-07-08
Publication date: 2023-01-13
Also published as: WO2023279647A1

Abstract

The embodiment of the invention relates to the technical field of communication, and discloses a verification method of a patching algorithm, electronic equipment and a storage medium, wherein the method can be applied to a simulation software platform and comprises the following steps: configuring a failure address of a dynamic random access memory simulating failure; forming a Raw Data document of the failure address; calculating the Raw Data document by a patching algorithm to obtain an address document and a patching scheme document of the failure address; and patching the failed address in the address document based on the patching scheme document, and displaying a patching result. The scheme can effectively improve the verification efficiency of the RA algorithm, cannot damage the wafer, and is complete in verification.

Description

Method for verifying patching algorithm, electronic equipment and storage medium

Technical Field

The embodiment of the invention relates to the technical field of integrated circuits, in particular to a verification method of a patching algorithm, electronic equipment and a storage medium.

Background

For companies producing different Dynamic Random Access Memory (DRAM) products, the repair schemes for the failed cells of each product are different.

At present, verification of a DRAM (DRAM Repair Analysis, RA) is generally performed on a test machine, a corresponding failure unit is set for a certain die, related Data (also called Raw Data) of the failure unit is generated on the test machine, a Repair scheme is obtained through RA calculation, and the set matching degree of the failure unit and the Repair scheme is manually compared, which takes a lot of time and is prone to omission. Another verification scheme is a Debug (Debug) patch scheme on the wafer, i.e. directly damaging the wafer, and performing test patch, taking the test after patch as a reference to test whether a new failed unit appears to verify the RA. But the verification mode can cause wafer damage, and other tests can not be carried out. And the two verification methods have the defects of time consumption, incomplete verification and high cost.

Disclosure of Invention

An object of the embodiments of the present invention is to provide a method, an electronic device, and a storage medium for verifying a repair algorithm, which can effectively improve the efficiency of verifying an RA algorithm, do not damage a wafer, and complete verification.

In order to solve the above technical problem, in a first aspect, an embodiment of the present invention provides a method for verifying a patch algorithm, which is applied to a simulation software platform, and includes: configuring a failure address of a dynamic random access memory simulating failure; forming a Raw Data document of the failure address; calculating the Raw Data document by a patching algorithm to obtain an address document and a patching scheme document of the failure address; and patching the failed address in the address document based on the patching scheme document, and displaying a patching result.

In a second aspect, an embodiment of the present invention provides an electronic device, including: at least one processor; and (c) a second step of,

a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of verifying a patching algorithm of the first aspect.

In a third aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores a computer program, where the computer program is executed by a processor to implement the verification method for the patching algorithm of the first aspect.

Compared with the prior art, the embodiment of the invention carries out offline verification on the RA algorithm of the DRAM through a simulation software platform. Flexibly configuring failure addresses of the dynamic random access memories simulating failure by using an offline verification mode; forming a Raw Data document of the failed address; calculating the Raw Data document by a patching algorithm to obtain an address document of the failure address and a patching scheme document; finally, repairing the failed address in the address document based on the repair scheme document, and displaying the repair result, thereby completing the verification process of the RA algorithm under the conditions of not occupying a test machine and not damaging the wafer, and reducing the production cost of the DRAM; the method can make up the missing caused by the manual comparison mode at present, so as to cause incomplete repair of the failure unit; the method can simulate the flow of online multi-station testing, fully verify the result of the multi-station repairing algorithm and improve the efficiency of algorithm verification.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

FIG. 1 is a first flowchart illustrating a verification method of a patching algorithm according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a failed address configuration process according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a failed address configuration process according to an embodiment of the invention;

FIG. 4 is a flowchart illustrating a method for verifying a patch algorithm according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a failed address configuration process according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a Raw Data document according to an embodiment of the present invention;

FIG. 7 is a specific flow chart three of a verification method of a patching algorithm according to an embodiment of the present invention;

FIG. 8 is a distribution diagram of a fix-up scheme and failed addresses according to an embodiment of the invention;

FIG. 9 is a detailed flowchart IV of a verification method of a patching algorithm according to an embodiment of the present invention;

FIG. 10 is a graph illustrating repair results according to an embodiment of the present invention;

FIG. 11 is a schematic illustration of a repair result according to an embodiment of the invention;

fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

The crystal grain is the minimum unit of a wafer (wafer), the wafer is processed by a DRAM manufacturing process, a preset number of DRAMs are formed on each crystal grain, each DRAM comprises a preset number of memory units, and each memory unit is endowed with a memory address. Verification of the RA algorithm for DRAM failure addresses is typically performed on a test bench. One is to set the failure unit on the crystal grain first, generate Raw Data of the failure unit on the testing machine, obtain the repairing scheme by the calculation of RA algorithm, compare the matching degree of the failure unit and repairing scheme set manually, the verification mode takes a lot of time, easy to miss. And the other method directly damages the wafer, executes test patching and carries out the verification of the RA algorithm by taking whether a new failure unit appears in the test after patching as a reference. But the verification mode can cause wafer damage, and other tests can not be carried out. And the two verification methods have the defects of time consumption, incomplete verification and high cost.

The application provides an offline verification scheme for the RA algorithm of a DRAM. The scheme is not required to be completed on a test machine, a DRAM failure address is configured through simulation of a simulation software platform, the RA algorithm to be verified is adopted to calculate the failure address, documents of the failure address and a repair scheme of the failure address are obtained, the corresponding failure address and the repair scheme are selected to carry out repair calculation, and a repair result is flexibly displayed on the basis of the software platform, so that the RA algorithm is verified. The scheme of the application does not occupy a test machine table, and cannot damage wafers, so that the production cost of the DRAM is reduced; meanwhile, the incomplete repair of the failure unit caused by the omission in the manual comparison mode at present is made up; the method can simulate the flow of online multi-station testing, fully verify the result of the multi-station repairing algorithm and improve the efficiency of algorithm verification.

In one embodiment, the verification method of the patching algorithm shown in fig. 1 is applied to a simulation software platform and comprises the following steps.

Step 101: configuring the failure address of the dynamic random access memory simulating the failure.

And (4) selecting or creating DRAM product information to be simulated to be failed on the simulation software platform by a detection person, and configuring the failure address of the DRAM. The failing address may be embodied as a memory address of each memory cell on a die on a wafer carrying the DRAM. In this embodiment, the process of configuring the invalid address is not limited. The failing address can be configured in two ways, for example.

The first method is as follows: an address space and an address input window of the dynamic random access memory simulating the failure are provided, and a failure address input in the address input window based on the address space is received.

For example, as shown in fig. 2, a plurality of memory blocks (banks) of a DRAM are provided on an analog software platform, each bank includes memory cells having an address space of 16 bits 2 in the X direction and 10 bits 2 in the Y direction, and DQ having three bits, and 7 bits after each read of a cell (bit) of the memory cell are read, so that there are 8 bits which are 3 times of 2. Shown in the figure, row Fail is a storage address of a horizontal Row of memory cells, col Fail is a storage address of a vertical Row of memory cells, and Single Fail is a storage address of a Single-point memory cell. The detection personnel can input the unit address as the failure unit in the address input window according to the requirement. A sample input result may be as shown in fig. 2.

The second method comprises the following steps: an address array is provided that simulates an address space of a failed dynamic random access memory and an address selected from the address array is determined to be a failed address.

For example, as shown in fig. 3, a plurality of memory blocks (banks) of a DRAM are provided on an analog software platform, and each bank includes memory cells having an address space of 16 bits 2 in the X direction and 10 bits 2 in the Y direction. The address space of the memory locations on these dies may be displayed in the form of an address array on the operating interface of the simulation software platform. Each small square in the figure can represent a memory unit, and can also represent a memory address corresponding to the memory unit. The detection personnel can automatically select the unit address as the failure unit in the address array according to the requirement.

Step 102: a Raw Data document of the failing address is formed.

And the simulation software platform generates original Data of the failure address, namely a Raw Data document, according to the failure address input or selected by the detection personnel. The generated Raw Data documents can also correspond to one or more according to the number of the failure addresses actually configured, the classification of the divided groups and the like.

Step 103: and (5) calculating the Raw Data document by a patching algorithm to obtain an address document of the failure address and a patching scheme document.

The repair algorithm is an RA algorithm to be verified, and the Raw Data document is operated through the RA algorithm to obtain a repair scheme aiming at the failure address. In actual operation, based on the quality of the RA algorithm, not every failing address can be operated to obtain a corresponding repair scheme, and there is a possibility that a corresponding repair scheme does not exist for a part of failing addresses, or a corresponding failing address cannot be correctly repaired due to the existence of a repair scheme. Therefore, in the embodiment, only the address document and the patching scheme document having the relationship between patching and patching are obtained after the operation of the patching algorithm. The address document may be one or more documents containing the failing address by the number of the preceding failing addresses, the category of the divided group, or the like. The fix-up scheme documents correspond to the address documents one by one, and each fix-up scheme document contains (or may not contain) a fix-up scheme for fixing up the failed address in the corresponding address document.

In one example, the RA algorithm to be verified may be a plurality of RA algorithms developed according to types of DRAM products, each RA algorithm being dedicated to patch analysis of failed addresses of the corresponding DRAM type product. Correspondingly, before the step is executed, the product type of the dynamic random access memory can be obtained, and according to the product type of the DRAM to be simulated and failed, an RA algorithm matched with the failed address of the DRAM to be simulated and failed can be selected for repair analysis, so that the accuracy of repair analysis is improved.

Based on this, the step may specifically include: and (4) calculating the Raw Data document by a patching algorithm corresponding to the product type to obtain an address document of the failure address and a patching scheme document. Therefore, the matching degree between the address document of the failed address and the patching scheme document is improved, and the accuracy of the subsequent patching operation is improved.

In addition, when the Raw Data document is operated by the patching algorithm, the operation can be performed in a conventional mode or a compression mode. The conventional method is that each address unit is independently tested, and whether each address unit is a failure address is respectively determined; the compression mode is to test a plurality of associated address units together, and when at least one address unit in the address units is a failure address, the address units are determined to be all failure addresses.

Correspondingly, before executing the step, the Data format of the Raw Data document can be obtained, and the Data format is used for indicating that when the Raw Data document is operated by a patching algorithm, the operation is carried out in a conventional mode or a compression mode.

Specifically, before the detection person configures the failure address of the dynamic random access memory for simulating the failure, the simulation software platform provides a selection interface for selecting the Data format of the Raw Data document, and the detection person selects the Data format of the Raw Data document in the interface, so that the simulation software platform is instructed to perform the operation of the RA algorithm in a conventional manner or in a compression manner.

Step 104: and patching the failed address in the address document based on the patching scheme document, and displaying a patching result.

After the simulation software platform finishes the RA algorithm operation to obtain the address document and the patching scheme document of the failed address, the patching operation can be automatically carried out on the failed address in the corresponding address document according to the patching scheme in the patching scheme document, and the result of whether the failed address in each address document is correctly patched is displayed on a platform interface. Or the simulation software platform carries out patching operation on the specified address document and the patching scheme document based on the selection operation of the detection personnel, and displays the patching result.

In this embodiment, the RA algorithm of the DRAM is verified offline through the simulation software platform. Flexibly configuring failure addresses of the dynamic random access memories simulating failure by using an offline verification mode; forming a Raw Data document of the failed address; calculating the Raw Data document by a patching algorithm to obtain an address document of a failure address and a patching scheme document; finally, repairing the failed address in the address document based on the repair scheme document, and displaying the repair result, thereby completing the verification process of the RA algorithm under the conditions of not occupying a test machine and not damaging the wafer, and reducing the production cost of the DRAM; the method can make up the incompleteness of the repair of the failure unit caused by the omission of the manual comparison mode at present; the method can simulate the flow of online multi-station testing, fully verify the result of the multi-station repairing algorithm and improve the efficiency of algorithm verification.

In one embodiment, a multi-site and multi-item configuration of failed addresses of a DRAM is provided. As shown in fig. 4, step 101 specifically includes the following sub-steps.

Substep 1011: the die that generated the failing address is determined.

After a detection person selects or creates the DRAM product information to be simulated as the failure on the simulation software platform, the crystal grain for configuring the failure address can be selected on the wafer carrying the DRAM product information. For example, n grains on wafer may be selected as the grains that configure the invalidation address. The n grains are labeled as: die 1, die 2, \8230anddie n.

Substep 1012: at least one test site is determined, and the test items contained in each test site.

To simulate the failure environment corresponding to the failure address, at least one test station may be configured in a simulated manner, where each test station corresponds to a different test stage (stage), for example: a high temperature test stage (stage 00), a low temperature test stage (stage 01) and an aging test stage (stage 02). Each test site may include a plurality of test items. For example, each test site may include m test items. The m test items are labeled as: test item 1, test item 2, \8230, test item m.

Specifically, the inspector may select at least one test site and configure a certain number of test items for the selected test site for simulating a real failure environment corresponding to the configured failure address.

Substep 1013: and selecting the failure address of each test item in each test site from the determined crystal grains.

Specifically, a detection person configures part of address units from the determined die as failure addresses, and associates the failure addresses with test items in each configured test site, so as to simulate the test site and the test item to which the failure address in the DRAM product belongs in an actual failure environment.

For example, as shown in FIG. 5, a diagram of the resulting operations for configuring fail addresses for multiple test items at a multiple test site is shown. When configuring the invalid address, the configuration process in the two manners of manual input and selection in the address space matrix may still be referred to in the foregoing embodiment, and details of the configuration process are not repeated here.

On this basis, as shown in fig. 4, step 102 may specifically be:

substep 1021: and forming a Raw Data document of the failure address of each test item in each test site.

Specifically, when forming Raw Data documents of the invalidation addresses, the number of documents and the invalidation addresses contained in each document may also be divided according to the test sites and test items to which the invalidation addresses belong. For example, as shown in fig. 6, the failing address of any test item belonging to any test site is uniquely contained in one Raw Data document. In rdm _1.Dat, m is a test item number, 1.

On this basis, as shown in fig. 4, step 103 may specifically be:

substep 1031: and respectively testing the Raw Data document according to the test sites to which the failure addresses belong to obtain the address document and the repair scheme document of the failure addresses contained in each test site.

Specifically, when performing RA algorithm calculation on the failure address in the Raw Data document, a tester may select to individually execute the RA algorithm on the Raw Data documents of different test sites, so as to verify the repair analysis capability of the RA algorithm individually applied to each test site according to the obtained address document and repair scheme document of the failure address included in each test site.

As an alternative to sub-step 1031, as shown in fig. 7, step 103 may further specifically be:

sub-step 1032: and performing combined test on the Raw Data document according to at least two combined test sites to which the failure addresses belong to obtain an address document and a repair scheme document of the failure addresses contained in the combined test sites.

Specifically, when performing RA algorithm calculation on the failure address in the Raw Data document, a tester may select to combine the Raw Data documents belonging to different test sites and then integrally execute the RA algorithm, so as to verify the capability of applying the RA algorithm to repair analysis under the multi-test-site combination according to the address document and the repair scheme document of the failure address included in the combined test site.

As shown in fig. 8, after obtaining the address document of the failed address (fail address) and the Repair Solution document (Repair Solution), the address unit covered by the address document and the Repair Solution document may be clearly identified in the simulation software platform in the form of an address space array. Therefore, when the patching operation is carried out on the failure address in the address document by adopting the patching scheme in the patching scheme document, the address units marked in the two arrays can be directly subjected to coverage matching (Cover) to obtain a patching result.

In the embodiment, the failure addresses of the DRAM are divided in a mode of setting a plurality of sites and a plurality of test items to form corresponding Raw Data documents; RA operation is carried out on the Raw Data documents of different test sites independently, or RA operation is carried out after the failure addresses of at least two test sites are combined, so that the repair analysis capability of the RA algorithm applied to a single test site or a combination of multiple test sites is verified according to the obtained address documents and repair scheme documents of the failure addresses.

In one embodiment, a specific implementation manner for patching the failed address in the address document based on the patching scheme document and displaying the patching result is provided. As shown in fig. 9, step 104 specifically includes the following sub-steps.

Substep 1041: and providing a file selection interface, and executing patching operation based on the failure address document and the corresponding patching scheme document selected on the interface.

Specifically, as shown in fig. 10, after the RA algorithm is used to complete the operation, the simulation software platform provides an operation interface for selecting the fail address document and the corresponding patch plan document. The detection personnel can select a patching scheme document in a patching scheme document menu (FU File) and select an address document in an address document menu (MD File); and then click "EXECUTE" to run the patching process. And then, the repairing result information is presented under the operation interface.

Illustratively, as shown in fig. 10, the way to show the repair result is:

an address array is provided that models the address space of a failed dynamic random access memory and identifies in the address array the result of whether the selected failed address document can be successfully patched by the corresponding patching scheme document.

When the actual patching result is displayed, the position of the failed address in the failed address document, the position of the patching scheme in the patching scheme document and whether the two are matched can be distinguished and identified in the address array by at least one of different characters, colors and symbols. What is called a match here is that the failed address is correctly patched by the patching scheme. For example, when color is used for marking, the failing address may be marked red, the fix-up scheme may be marked green, and the failing address matching the fix-up scheme implementation is marked yellow.

When the inspector needs to mainly check the repair result on a certain die, the inspector can click the array position corresponding to the die, such as the (02, 02) position, and then the simulation software platform performs detailed display on the repair result of the array position, including statistics (COUNT) on the address units of the three colors, as shown in fig. 11, so that the repair result can be compared more intuitively.

In addition, the detection personnel can also execute the export operation of the repair result in the simulation software platform according to the requirement, and the simulation software platform generates and exports the repair result to the specified directory file based on the export operation of the repair result. For example, the detector can export the repairing result by clicking "OUTPUT" for data statistics and analysis.

In this embodiment, the simulation software platform provides a file selection interface, so that a detection person can conveniently trigger and execute a repair operation based on the fail address document selected on the interface and the corresponding repair scheme document. The result of whether the failure address document selected by the detection personnel can be successfully repaired by the corresponding repair scheme document is identified in the address array, so that the detection personnel can conveniently verify the correctness of the RA algorithm.

An embodiment of the present application further provides an electronic device, as shown in fig. 12, including: at least one processor 201; and a memory 202 communicatively coupled to the at least one processor 201; wherein the memory stores instructions executable by the at least one processor 201, and the instructions are executed by the at least one processor 201 to enable the at least one processor 201 to execute the method embodiments corresponding to fig. 1, 4, 7, and 9

Where the memory 202 and the processor 201 are coupled in a bus, the bus may comprise any number of interconnected buses and bridges that couple one or more of the various circuits of the processor 201 and the memory 202 together. The bus may also connect various other circuits such as peripherals, voltage regulators, power management circuits, etc., which are well known in the art, and therefore, will not be described any further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor 201 is transmitted over a wireless medium through an antenna, which further receives the data and transmits the data to the processor 201.

The processor 201 is responsible for managing the bus and general processing and may also provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. While the memory 202 may be used to store data used by the processor 201 in performing operations.

An embodiment of the present application further provides a computer-readable storage medium storing a computer program. The computer program, when executed by the processor, implements the method embodiments corresponding to fig. 1, 4, 7, and 9.

That is, as can be understood by those skilled in the art, all or part of the steps in the method for implementing the embodiments described above may be implemented by a program instructing related hardware, where the program is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a processor (processor) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and various media capable of storing program codes.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.

Claims

1. A verification method of a patching algorithm is applied to a simulation software platform and is characterized by comprising the following steps:

configuring a failure address of a dynamic random access memory simulating failure;

forming a Raw Data document of the failure address;

calculating the Raw Data document by a patching algorithm to obtain an address document and a patching scheme document of the failure address;

and patching the failed address in the address document based on the patching scheme document, and displaying a patching result.

2. The method of claim 1, wherein the configuring simulates a failing address of a failing dynamic random access memory, comprising:

providing an address space and an address input window of the dynamic random access memory simulating the failure, and receiving the failure address input in the address input window based on the address space.

3. The method of claim 1, wherein the configuring simulates a failing address of a failing dynamic random access memory, comprising:

providing an address array simulating an address space of the failed dynamic random access memory, and determining an address selected from the address array as the failed address.

4. The method of claim 1, further comprising:

acquiring the product type of the dynamic random access memory;

the operation of the Raw Data document by the patching algorithm to obtain the address document of the failure address and the patching scheme document comprises the following steps:

and calculating the Raw Data document by a patching algorithm corresponding to the product type to obtain an address document and a patching scheme document of the failure address.

5. The method of claim 1, wherein before the performing the operation on the Raw Data document by the patching algorithm to obtain the address document of the failed address and the patching scheme document, further comprising:

and acquiring a Data format of the Raw Data document, wherein the Data format is used for indicating that the Raw Data document is operated in a conventional mode or a compression mode when the Raw Data document is operated by the patching algorithm.

6. The method of any of claims 1-5, wherein the configuring simulates the failing address of the failing DRAM comprises:

determining a die that generated the failing address;

determining at least one test site and test items contained in each test site;

and selecting the failure address of each test item in each test site from the determined crystal grains.

7. The method of claim 6, wherein forming the Raw Data document of the invalidation address comprises:

and forming a Raw Data document of the failure address of each test item in each test site.

8. The method of claim 7, wherein said subjecting said Raw Data document to a fix-up algorithm to obtain an address document and a fix-up scheme document of said failed address comprises:

and respectively calculating the Raw Data document according to the test sites to which the failure addresses belong to obtain the address document and the repair scheme document of the failure addresses contained in each test site.

9. The method of claim 7, wherein the operating the Raw Data document with a patching algorithm to obtain an address document and a patching scheme document of the failed address comprises:

and performing combined operation on the Raw Data document according to at least two combined test sites to which the failure addresses belong to obtain an address document and a repair scheme document of the failure addresses contained in the combined test sites.

10. The method of claim 1, wherein the patching the failed address in the address document based on the patching scheme document and showing patching results comprises:

providing a file selection interface, and executing patching operation based on the failure address document selected on the interface and the corresponding patching scheme document;

and displaying the repairing result.

11. The method of claim 10, wherein the displaying the repair results comprises:

providing an address array of the address space of the simulated failing dynamic random access memory, and identifying in the address array the result of whether the selected failing address document can be successfully patched by the corresponding patching scheme document.

12. The method of claim 11, wherein said identifying in the address array the result of whether the selected failed address document can be successfully patched by the corresponding patching scheme document, comprises:

and identifying the position of the failure address in the failure address document, the position of the repair scheme in the repair scheme document and whether the two are matched in the address array in a way of at least one of different characters, colors and symbols.

13. The method of claim 1, further comprising:

and generating and exporting the patching result to the specified directory file based on the exporting operation of the patching result.

14. An electronic device, comprising:

at least one processor; and (c) a second step of,

a memory communicatively coupled to the at least one processor; wherein, the first and the second end of the pipe are connected with each other,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method of validating a patching algorithm as claimed in any of claims 1 to 13.

15. A computer-readable storage medium storing a computer program, wherein the computer program is configured to implement a method for verifying a fixing algorithm according to any one of claims 1 to 13 when executed by a processor.