CN115017869A - UVM register model rapid generation method and system - Google Patents

Abstract

The invention discloses a rapid UVM register model generation method and a rapid UVM register model generation system, wherein the rapid UVM register model generation method comprises the following steps: the method comprises the following steps: converting the excel table of the setting register into UVMRAL model information; the rapid UVM register model generation method and system can solve the problems of low efficiency, high error rate and incapability of multiplexing of manually compiling a fussy UVM register model, can immediately output the UVM register model meeting the requirement by only needing one table in a module excel format provided by a designer, is efficient and reusable, and ensures the accuracy of the UVM register model.

Description

UVM register model rapid generation method and system

Technical Field

The invention relates to a rapid UVM register model generation method and system, and belongs to the technical field of chip verification.

Background

In the chip verification stage, firstly, the register configuration of the module to be tested is required, and the configuration is incorrect, which directly results in the failure of verification, so that the importance of the register configuration on the chip verification can be seen.

In the verification process using uvm as the verification methodology, the configuration process of the register depends on the register model, which mainly consists of three categories uvm _ reg _ block, uvm _ reg and uvm _ reg _ field, uvm _ reg _ block consists of uvm _ reg and uvm _ reg consists of uvm _ reg _ field.

When the number of registers of the verification module is large, hundreds of uvm _ reg _ block, uvm _ reg and uvm _ reg _ field classes exist in a register model, and a verifier needs to manually knock out the classes one register by one register according to a register table (excel) of a specific module to be tested, so that the task is heavy and the efficiency is low; and once the register table has large changes, the classes need to be knocked out again, and the efficiency and the progress of chip verification are affected.

In view of this, it is urgently needed to design a new chip verification method so as to overcome the above-mentioned defects of low efficiency, high error rate and non-reusability.

Disclosure of Invention

The present invention provides a method and a system for fast generating a UVM register model, so as to solve the problems in the background art.

In order to achieve the purpose, the invention provides the following technical scheme: a rapid UVM register model generation method and a rapid UVM register model generation system are disclosed, wherein the rapid UVM register model generation method comprises the following steps: the method comprises the following steps:

converting the excel table of the setting register into UVM RAL model information;

generating a model required by a UVM verification environment according to RAL model information obtained by conversion

The step of converting the excel table of the setting register into UVM RAL model information comprises the following steps:

step A: opening an excel document through a python script, checking all sheet forms, and acquiring a form through a sheet name;

and B: obtaining the size of the table through a python script, traversing each row, searching out effective cells, and obtaining the rows and columns of the effective cells and information in the cells;

and C: analyzing the effective unit cells into UVM RAL model information in a text format through a python script;

step D: and converting the UVM RAL model information in the text format obtained by analysis into text information required by the verification environment through a self script of a simulation tool.

As a preferred technical solution of the present invention, the UVM RAL model text information includes four levels of contents: system, block, register, field;

analyzing the given excel through python to obtain the name of the sheet form as the system in the RAL; and acquiring the form size, traversing each row and each column, and analyzing the form size into three levels, namely block, register and field, according to the content in the coordinates.

As a preferred technical scheme of the invention, the register block comprises a plurality of registers (uvm _ reg), and each register (uvm _ reg) consists of a plurality of fields (uvm _ reg _ field); a single field (uvm _ reg _ filtered) contains multiple bits.

As a preferred technical solution of the present invention, each register field in the register model has two values: mirror value (mirror value) which represents the known state of the current hardware and expected value (desired value) which is the value of the software object modified by the register model and the hardware value updated by the value (actual value).

As a preferred technical solution of the present invention, the UVM RAL model text information includes four levels of contents: system, block, register, field;

analyzing the given excel through python to obtain the name of the sheet form as the system in the RAL; and acquiring the form size, traversing each row and each column, and analyzing the form size into three levels, namely block, register and field, according to the content in the coordinates.

As a preferred technical solution of the present invention, the step of converting the register table information into the UVM RAL model text information includes:

step a: firstly, traversing the content in the nrows, if a certain line does not have any information or contains invalid information in front and the corresponding first column is not the character ADDR given by us, judging the line as an invalid line, and directly skipping cell analysis;

step b: entering the next line of judgment until the content of the cell is analyzed to be ADDR; after the ADDR is identified, the line is not analyzed any more, and the traversal of the following line is continued;

step c: if the content of the first column is address (0x00-0xxx), the second column is characters in NAME, and is different from the adjacent upper and lower columns, the third column is characters in MEMBER, the fourth column is characters in FIELD, the fifth column is characters in RESET _ VALUE, and the sixth column is characters in TYPE, the generation of a register text message can be completed by intercepting the cells of the row;

step d: if the character in the second column is the same as the previous line or the next line, all the same adjacent lines are found, and the cells of the same lines are operated, so that the generation of the multi-field register text information can be completed.

As a preferred technical scheme of the invention, the register of the single-domain segment comprises a field below a register; a register of multi-domain section, a plurality of fields are printed under a register, each field comprises bit width, attributes of various read-write types and reset values; the script can judge and intercept the information, standardize the case and case, detect the total bit width and the like, and finally print the information to the specified text according to a preset form.

As a preferred embodiment of the present invention, the block may include a plurality of registers, the system may include a plurality of blocks, and the offset address of the register may be changed in the system.

As a preferred technical solution of the present invention, the model further includes: and analyzing the register model generated by the script into a module which can be embedded into a verification environment by combining the self script of the simulation tool.

As a preferred technical solution of the present invention, in the step D, the UVM RAL model information is converted into text information required by the verification environment through a script carried by the simulation tool, a communication bridge between the register model and the bus needs to be established, so that operations of the register model and operations on the bus can be mutually converted, and for the operations of the register model, Driver is not directly "readable", and similarly, bus transactions collected by Monitor are not recognized by the register model, and the register cannot be updated and checked correspondingly, and at this time, an adapter is required to complete conversion from the register transaction to the bus transaction. The method comprises the following steps:

the method comprises the following steps: the register sequence stores the relevant information with the target register into uvm _ reg _ item instance (uvm _ reg _ bus _ op) and sends the information to the adapter;

step two: after the adaptor receives uvm _ reg _ item (uvm _ reg _ bus _ op), the bus _ reg _ item is converted into a bus _ seq _ item bus transaction type which can be recognized by a bus, and the adaptor sends the bus _ seq _ item to a sequence and then to a Driver;

step three: after the bus acquires information such as address, data, operation mode and the like from the bus _ seq _ item, initiating read-write access of the bus;

step four: if the bus has a feedback signal returned, the signal becomes a bus transaction of the bus _ seq _ item, the bus sequence returns to the adapter according to the path of the response item, the adapter processes the signal to generate uvm _ reg _ bus _ op, and finally the signal is used as a return value to a method related to the register operation.

As a preferred technical solution of the present invention, the method for integrating the adapter of the UVM RAL register model includes the following steps:

step 1: for the integration of the register model, the mode of transmission from the top layer is generally inclined, namely the register model handle is finally transmitted from the test layer;

step 2: after the register model is created, the build function is explicitly called, and because uvm _ reg _ block is an object type, the build function is not automatically executed;

and step 3: in the connect _ phase stage of the top-level environment, a map component of a register model is connected with a bus sequence and an adapter in a uvm _ reg _ map: set _ sequence mode, so that a register information map, a bus sequence bus side excitation driver and an adapter register level and hardware bus level bridge are associated together, and only through the step, the adapter bridge function can be completed.

Compared with the prior art, the invention has the beneficial effects that: the rapid generation method and the rapid generation system for the UVM register model can solve the problems of low efficiency, high error rate and incapability of reusing of manually writing a fussy UVM register model, can immediately output the UVM register model meeting the requirements only by a table in a module excel format provided by a designer, is efficient and reusable, ensures the accuracy of the UVM register model, integrates a predictor (instantiated by a parameterization class UVM _ reg _ predictor) in a top-level environment through displaying the prediction requirement, captures a bus transaction on a bus through a monitor, captures an effective transaction through the monitor, sends the effective transaction to the predictor, realizes transaction information conversion by using the bridging effect of an adapter, updates related information of the converted register model into a map, completes the update of the register model, and displays that the prediction is more accurate for predicting the register value.

Drawings

FIG. 1 is a schematic diagram of script-based register model generation

FIG. 2 is a diagram of a register table format.

FIG. 3 is a diagram of register model information in text format.

FIG. 4 is a diagram of an uvm register model.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1 to 4, the present invention provides a method and a system for fast generating a UVM register model, where the method for fast generating a UVM register model includes: the method comprises the following steps:

converting the excel table of the setting register into UVM RAL model information;

generating a model required by a UVM verification environment according to the RAL model information obtained by conversion

The step of converting the setting register excel table into the UVM RAL model information comprises the following steps:

step A: opening an excel document through a python script, checking all sheet forms, and acquiring a form through a sheet name;

and B: obtaining the size of the table through a python script, traversing each row, searching out effective cells, and obtaining the rows and columns of the effective cells and information in the cells;

and C: analyzing the effective cells into UVM RAL model information in a text format through a python script;

step D: and converting the UVM RAL model information in the text format obtained by analysis into text information required by the verification environment through a self script of a simulation tool.

Wherein the register block is composed of a plurality of registers (uvm _ reg), each register (uvm _ reg) is composed of a plurality of fields (uvm _ reg _ field); a single field (uvm _ reg _ filtered) contains multiple bits.

Further, there are two values in the field of each register in the register model: mirror value (mirror value) which represents the known state of the current hardware and expected value (desired value) which is the value of the software object modified by the register model and the hardware value updated by the value (actual value).

Wherein the UVM RAL model text information includes four levels of content: system, block, register, field;

analyzing the given excel through python to obtain the name of the sheet form as the system in the RAL; and acquiring the form size, traversing each row and each column, and analyzing the form size into three levels, namely block, register and field, according to the content in the coordinates.

Preferably, the step of converting into UVM RAL model text information according to register table information includes:

step a: firstly, traversing the content in the nrows, if a certain line does not have any information or contains invalid information in front and the corresponding first column is not the character ADDR given by us, judging the line as an invalid line, and directly skipping cell analysis;

step b: entering the next line of judgment until the content of the cell is analyzed to be ADDR; after the ADDR is identified, the line is not analyzed any more, and the traversal of the following line is continued;

step c: if the content of the first column is address (0x00-0xxx), the second column is characters in NAME, and is different from the adjacent upper and lower columns, the third column is characters in MEMBER, the fourth column is characters in FIELD, the fifth column is characters in RESET _ VALUE, and the sixth column is characters in TYPE, the generation of a register text message can be completed by intercepting the cells of the row;

step d: if the characters in the second column are the same as the previous line or the next line, all the same adjacent lines are found out, and the cells of the same lines are operated, so that the generation of the multi-field section register text information can be completed.

The register of the single-domain segment comprises a field below a register; a register of multi-domain section, a plurality of fields are printed under a register, each field comprises bit width, attributes of various read-write types and reset values; the script can judge and intercept the information, standardize the case and case, detect the total bit width and the like, and finally print the information to the specified text according to a preset form.

The block may contain a plurality of registers, the system may contain a plurality of blocks, and the offset address of the register may be changed in the system.

Preferably, in step D, the UVM RAL model information is converted into text information required by the verification environment through a script carried by the simulation tool, a communication bridge between the register model and the bus needs to be established, so that operations of the register model and operations on the bus can be mutually converted, and drivers cannot directly "read" the operations of the register model. The method comprises the following steps:

the method comprises the following steps: the register sequence stores the relevant information with the target register into uvm _ reg _ item instance (uvm _ reg _ bus _ op) and sends the information to the adapter;

step two: after the adapter receives uvm _ reg _ item (uvm _ reg _ bus _ op), the adapter converts the bus _ seq _ item into a bus _ seq _ item bus transaction type which can be recognized by the bus, and then the adapter sends the bus _ seq _ item to the sequence and then to the Driver;

step three: after the bus acquires information such as address, data, operation mode and the like from the bus _ seq _ item, initiating read-write access of the bus;

step four: if the bus has a feedback signal returned, the signal becomes a bus transaction of the bus _ seq _ item, the bus sequence returns to the adapter according to the path of the response item, the adapter processes the signal to generate uvm _ reg _ bus _ op, and finally the signal is used as a return value to a method related to the register operation.

Furthermore, the method for integrating the adapter of the UVM RAL register model comprises the following steps:

step 1: for the integration of the register model, the mode of transmission from the top layer is generally inclined, namely the register model handle is finally transmitted from the test layer;

step 2: after the register model is created, the build function is explicitly called, and because uvm _ reg _ block is an object type, the build function is not automatically executed;

and step 3: the connect _ phase stage of the top-level environment needs to connect the map component of the register model with the bus sequence and the adapter in a uvm _ reg _ map: set _ sequence mode, which will associate the register information map, the bus sequence bus side excitation driver and the bridge of the adapter register level and the hardware bus level, and only through this step, the bridge function of the adapter can be completed

The model further comprises: and analyzing the register model generated by the script into a module which can be embedded into a verification environment by combining the self script of the simulation tool.

Defining a register table, which in one embodiment includes a base address, a register name, a width of a register sub-field, a name, and read and write attributes, can be seen in FIG. 2.

Converting the set register table into UVM RAL model information; the parse register table is read by the python script. Reading the register table line by line, analyzing the content of each line, selecting the line meeting the requirement, and outputting the line in a format of a text file to obtain a UVM RAL model text, wherein the output text can refer to FIG. 3.

According to the UVM RAL model text obtained by the analysis, taking EDA tool manufacturer synopsys as an example, the script ralgen provided by itself can be used to analyze the UVM model into a register model capable of matching with the UVM environment, and the output register model is shown in fig. 4.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (10)

1. A rapid UVM register model generation method and a rapid UVM register model generation system are disclosed, wherein the rapid UVM register model generation method comprises the following steps: the method comprises the following steps:

converting the excel table of the setting register into UVM RAL model information;

generating a model required by a UVM verification environment according to the RAL model information obtained by conversion

The method is characterized in that the step of converting the excel table of the setting register into UVM RAL model information comprises the following steps:

step A: opening an excel document through a python script, checking all sheet forms, and acquiring a form through a sheet name;

and B, step B: obtaining the size of the table through a python script, traversing each row, searching out effective cells, and obtaining the rows and columns of the effective cells and information in the cells;

and C: analyzing the effective unit cells into UVM RAL model information in a text format through a python script;

step D: and converting the UVM RAL model information in the text format obtained by analysis into text information required by the verification environment through a self script of a simulation tool.

2. The method and system for rapidly generating a UVM register model according to claim 1, wherein: the register block is composed of a plurality of registers (uvm _ reg), each register (uvm _ reg) is composed of a plurality of fields (uvm _ reg _ field); a single field (uvm _ reg _ filtered) contains multiple bits.

3. The method and system for rapidly generating a UVM register model according to claim 1, wherein: there are two values in the field of each register in the register model: mirror value (mirror value) which represents the known state of the current hardware and expected value (desired value) which is the value of the software object modified by the register model and the hardware value updated by the value (actual value).

4. The method and system for rapidly generating a UVM register model according to claim 1, wherein: the UVM RAL model text information contains four levels of content: system, block, register, field;

analyzing the given excel through python to obtain the name of the sheet form as the system in the RAL; and acquiring the form size, traversing each row and each column, and analyzing the form size into three levels, namely block, register and field, according to the content in the coordinates.

5. The method and system for rapidly generating UVM register model according to claim 4, wherein: the step of converting the register table information into UVM RAL model text information comprises the following steps:

a, step a: firstly, traversing the content in the nrows, if a certain line does not have any information or contains invalid information in front and the corresponding first column is not the character ADDR given by us, judging the line as an invalid line, and directly skipping cell analysis;

step b: entering the next line of judgment until the content of the cell is analyzed to be ADDR; after the ADDR is identified, the line is not analyzed any more, and the traversal of the following line is continued;

step c: if the content of the first column is address (0x00-0xxx), the second column is characters in NAME, and is different from the adjacent upper and lower columns, the third column is characters in MEMBER, the fourth column is characters in FIELD, the fifth column is characters in RESET _ VALUE, and the sixth column is characters in TYPE, the generation of a register text message can be completed by intercepting the cell of the row;

step d: if the character in the second column is the same as the previous line or the next line, all the same adjacent lines are found, and the cells of the same lines are operated, so that the generation of the multi-field register text information can be completed.

6. The method and system for rapidly generating a UVM register model according to claim 5, wherein: the register of the single-domain segment comprises a field below a register; a register of multi-domain section, a plurality of fields are printed under a register, each field comprises bit width, attributes of various read-write types and reset values; the script can judge and intercept the information, standardize the case and case, detect the total bit width and the like, and finally print the information to the specified text according to a preset form.

7. The method and system for rapidly generating a UVM register model according to claim 1, wherein: the block may contain a plurality of registers, the system may contain a plurality of blocks, and the offset address of the register may be changed in the system.

8. The method and system for rapidly generating a UVM register model according to claim 1, wherein: the model further comprises: and analyzing the register model generated by the script into a module which can be embedded into a verification environment by combining the self script of the simulation tool.

9. The method and system for rapidly generating a UVM register model according to claim 1, wherein: in the step D, the UVM RAL model information is converted into text information required by the verification environment through the script carried by the simulation tool, a communication bridge between the register model and the bus needs to be established, so that the operation of the register model and the operation on the bus can be mutually converted, and the Driver cannot directly read and understand the operation of the register model. The method comprises the following steps:

the method comprises the following steps: the register sequence stores the relevant information with the target register into uvm _ reg _ item instance (uvm _ reg _ bus _ op) and sends the information to the adapter;

step two: after the adapter receives uvm _ reg _ item (uvm _ reg _ bus _ op), the adapter converts the bus _ seq _ item into a bus _ seq _ item bus transaction type which can be recognized by the bus, and then the adapter sends the bus _ seq _ item to the sequence and then to the Driver;

step three: after the bus acquires information such as address, data, operation mode and the like from the bus _ seq _ item, initiating read-write access of the bus;

step four: if the bus has a feedback signal returned, the signal becomes a bus transaction of the bus _ seq _ item, the bus sequence returns to the adapter according to the path of the response item, the adapter processes the signal to generate uvm _ reg _ bus _ op, and finally the signal is used as a return value to a method related to the register operation.

10. The method and system for rapidly generating a UVM register model according to claim 1, wherein: the method for integrating the adapter of the UVM RAL register model comprises the following steps:

step 1: for the integration of the register model, the mode of transmission from the top layer is generally inclined, namely the register model handle is finally transmitted from the test layer;

step 2: after the register model is created, the build function is explicitly called, and because uvm _ reg _ block is an object type, the build function is not automatically executed;

and step 3: in the connect _ phase stage of the top-level environment, a map component of a register model is connected with a bus sequence and an adapter in a uvm _ reg _ map: set _ sequence mode, so that a register information map, a bus sequence bus side excitation driver and an adapter register level and hardware bus level bridge are associated together, and only through the step, the adapter bridge function can be completed.

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