WO2023279647A1 - Procédé de vérification pour analyse de réparations, dispositif électronique et support de stockage - Google Patents

Procédé de vérification pour analyse de réparations, dispositif électronique et support de stockage Download PDF

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Publication number
WO2023279647A1
WO2023279647A1 PCT/CN2021/135714 CN2021135714W WO2023279647A1 WO 2023279647 A1 WO2023279647 A1 WO 2023279647A1 CN 2021135714 W CN2021135714 W CN 2021135714W WO 2023279647 A1 WO2023279647 A1 WO 2023279647A1
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address
file
repair
failure
raw data
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PCT/CN2021/135714
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English (en)
Chinese (zh)
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杨柳
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions

Definitions

  • the present application relates to, but is not limited to, a method for verifying a repair algorithm, an electronic device, and a storage medium.
  • DRAM Dynamic Random Access Memory
  • the verification of the DRAM repair algorithm (Repair Analysis, RA) is generally carried out on the test machine, and the corresponding failure unit is set for a certain die, and the relevant data of the failure unit (also called “Raw Data”) is generated on the test machine. ”), the repair plan is calculated by RA, and the matching degree between the set failure unit and the repair plan is manually compared.
  • This verification method takes a lot of time and is prone to omissions.
  • Another verification solution is to debug (Debug) the repair solution on the wafer, that is, directly damage the wafer, perform test repair, and perform RA verification based on the test whether new failure units appear after repair.
  • this verification method will cause damage to the wafer, and other tests cannot be performed.
  • both of the above two verification methods have the disadvantages of time-consuming, incomplete verification, and high cost.
  • the present application provides a method for verifying a repair algorithm, electronic equipment and a storage medium.
  • the first aspect of the present application provides a kind of verification method of patching algorithm, is applied to the simulation software platform, comprises: the failure address of the dynamic random access memory of configuration simulation failure; Form the Raw Data document of described failure address; Described Raw The data file is operated by a repairing algorithm to obtain the address file and repair plan file of the invalid address; based on the repair plan file, the invalid address in the address file is repaired, and the repair result is displayed.
  • the configuration simulates the failure address of the failed DRAM, including:
  • An address space and an address input window of the simulated failure DRAM are provided, and the failure address input in the address input window based on the address space is received.
  • the configuration simulates the failure address of the failed DRAM, including:
  • An address array of the address space of the simulated failure DRAM is provided, and an address selected from the address array is determined as the failure address.
  • the method also includes:
  • the described Raw Data file is operated through a repair algorithm to obtain the address file and the repair plan file of the failure address, including:
  • the Raw Data file is operated through the repair algorithm corresponding to the product type to obtain the address file and repair plan file of the failure address.
  • the Raw Data file before performing operations on the Raw Data file through a repair algorithm to obtain the address file of the failure address and the repair plan file, it also includes:
  • the data format of the Raw Data file is used to indicate that when the Raw Data file is operated by the repair algorithm, the operation is performed in a conventional manner or in a compressed manner.
  • the configuration simulates the failure address of the failed DRAM, including:
  • the Raw Data file forming the failure address includes:
  • the Raw Data file is operated through a repair algorithm to obtain the address file and repair plan file of the failure address, including:
  • the Raw Data file is respectively calculated according to the test site to which the failure address belongs, to obtain the address file and the repair plan file of the failure address contained in each of the test sites.
  • the Raw Data file is operated through a repair algorithm to obtain the address file and repair plan file of the failure address, including:
  • the Raw Data file is combined according to at least two combined test sites to which the failure address belongs, to obtain the address file and the repair plan file of the failure address contained in the combined test site.
  • the repairing of invalid addresses in the address file based on the repairing scheme file, and displaying the repairing results include:
  • the displaying the repair result includes:
  • An address array of the address space of the simulated failure DRAM is provided, and a result of whether the selected failure address file can be successfully repaired by the corresponding repair solution file is identified in the address array.
  • the result of identifying in the address array whether the selected failure address file can be successfully repaired by the corresponding repair solution file includes:
  • the position of the failure address in the failure address file, the position of the repair solution in the repair solution file, and whether the two match are identified in the address array by at least one of different characters, colors, and symbols.
  • the method also includes:
  • a second aspect of the present application provides an electronic device, including: at least one processor; and,
  • a memory connected in communication with the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processing
  • the device can execute the verification method of the patching algorithm described in the first aspect.
  • a third aspect of the present application provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the method for verifying the repair algorithm described in the first aspect is implemented.
  • the method for verifying the repair algorithm, the electronic device and the storage medium perform offline verification on the RA algorithm of the DRAM through a simulation software platform.
  • Use the offline verification method to flexibly configure the failure address of the simulated failure DRAM; form the Raw Data file of the failure address; operate the Raw Data file through the repair algorithm to obtain the address file of the failure address and the repair plan file; finally based on The repair plan document repairs the invalid addresses in the address file and displays the repair results, so as to complete the verification process of the RA algorithm without occupying the test machine and causing damage to the wafer, reducing the cost of DRAM production; making up for the current manual Omissions in the comparison method lead to incomplete repair of failed units; the process of online multi-site testing can be simulated to fully verify the results of multi-site repair algorithms and improve the efficiency of algorithm verification.
  • Fig. 1 is a flowchart one of a verification method of a repair algorithm according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of an invalid address configuration process according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of an invalidation address configuration process according to an embodiment of the present application.
  • FIG. 4 is a second flow chart of a verification method of a repair algorithm according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of an invalidation address configuration process according to an embodiment of the present application.
  • Fig. 6 is a schematic diagram of a Raw Data document according to an embodiment of the present application.
  • FIG. 7 is a flowchart three of a verification method of a repair algorithm according to an embodiment of the present application.
  • FIG. 8 is a distribution diagram of repair schemes and failure addresses according to an embodiment of the present application.
  • FIG. 9 is a flowchart four of a verification method of a patching algorithm according to an embodiment of the present application.
  • Fig. 10 is a schematic diagram of repair results according to an embodiment of the present application.
  • Fig. 11 is a schematic diagram of repair results according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • a die is the smallest unit of a wafer.
  • the wafer is processed by the DRAM manufacturing process to form a preset number of DRAMs on each die.
  • Each DRAM contains a preset number of storage units.
  • a cell is assigned a memory address.
  • the verification of the RA algorithm for the DRAM failure address is generally carried out on the test machine.
  • One is to first set the failed unit on the die, generate raw data of the failed unit on the test machine, calculate the repair plan through the RA algorithm, and manually compare the matching degree between the set failed unit and the repair plan.
  • This method takes a lot of time and is prone to omissions.
  • the other is to directly cause damage to the wafer, perform a test repair, and verify the RA algorithm based on whether a new failure unit appears in the test after the repair.
  • this verification method will cause damage to the wafer, and other tests cannot be performed.
  • both of the above two verification methods have the disadvantages of time-consuming, incomplete verification, and high cost.
  • This application proposes an offline verification scheme for the RA algorithm of DRAM.
  • This solution does not need to be completed on the test machine, but simulates the DRAM failure address through the simulation software platform, uses the RA algorithm to be verified to calculate the failure address, obtains the failure address and the document of the repair plan, and selects the corresponding failure address and
  • the patching scheme performs patching operations, and flexibly displays the patching results based on the software platform to verify the RA algorithm.
  • This application scheme does not occupy the test machine, and will not cause damage to the wafer, reducing the cost of DRAM production; at the same time, it makes up for the omissions that occur in the current manual comparison method, resulting in incomplete repair of failed units; it can simulate multiple stations on the line
  • the testing process fully verifies the results of the multi-site patching algorithm and improves the efficiency of algorithm verification.
  • the method for verifying a repair algorithm as shown in FIG. 1 is applied to a simulation software platform, and includes the following steps.
  • Step 101 Configure the invalidation address of the dynamic random access memory that simulates invalidation.
  • the inspector selects or creates the DRAM product information to be simulated to fail on the simulation software platform, and configures the failure address of the DRAM.
  • the failure address may be the storage address of each storage unit located on a certain die on the wafer carrying the DRAM.
  • the process of configuring the failure address is not limited.
  • the failure address can be configured in the following two ways.
  • Method 1 providing an address space and an address input window for simulating a failed DRAM, and receiving a failure address input in the address input window based on the address space.
  • FIG. 2 For example, as shown in Figure 2, multiple storage blocks (banks) of DRAM are provided on the simulation software platform, and the address space of the storage units contained in each bank is 16-bit binary in the X direction and 10-bit binary in the Y direction.
  • DQ has three bits, and each time a memory unit cell (bit) is read, the subsequent 7 bits are read out, so there are 8 bits, which is 2 to the 3rd power.
  • Row Fail shown in the figure is the storage address of a horizontal storage unit
  • Col Fail is the storage address of a vertical storage unit
  • Single Fail is the storage address of a single-point storage unit.
  • the inspector can input the unit address as the failure unit in the address input window according to the requirement.
  • An example of the input result may be shown in FIG. 2 .
  • Method 2 Provide an address array simulating the address space of the failed DRAM, and determine an address selected from the address array as the failed address.
  • multiple storage blocks (banks) of DRAM are provided on the simulation software platform, and the address space of the storage unit contained on each bank is 16-bit binary in the X direction and 10-bit binary in the Y direction. system.
  • the address spaces of the storage units on these chips can be displayed on the operation interface of the simulation software platform in the form of address arrays.
  • Each small square in the figure can represent not only a storage unit, but also the storage address corresponding to the storage unit. The inspector can check the unit address as the failed unit in the address array according to the requirement.
  • Step 102 Form a Raw Data file of the invalidation address.
  • the simulation software platform generates the original data of the failure address, that is, the Raw Data file, according to the failure address input or checked by the inspector. According to the number of failure addresses actually configured, the category of the division group, etc., the generated Raw Data files can also correspond to one or more.
  • Step 103 the Raw Data file is operated through the repair algorithm to obtain the address file and the repair plan file of the invalid address.
  • the repair algorithm here is the RA algorithm to be verified.
  • the above-mentioned Raw Data file is calculated by the RA algorithm, and the repair solution for the invalid address can be obtained.
  • not every failure address can be calculated to obtain the corresponding repair solution. It is possible that there is no corresponding repair solution for some failure addresses, or there is a repair solution but the corresponding failure address cannot be corrected. repair. Therefore, in this embodiment, after the operation of the repairing algorithm, only the address file and the repairing scheme file having the relationship between the repaired and the repaired are obtained.
  • the address file can be obtained according to the number of previously invalid addresses, the category of the group, etc., and contains one or more files of invalid addresses. There is a one-to-one correspondence between the repair plan document and the address document, and each repair plan document includes (or may not include) a repair plan for repairing invalid addresses in the corresponding address file.
  • the RA algorithm to be verified may be various RA algorithms developed according to the types of DRAM products, and each RA algorithm is dedicated to repairing and analyzing the failure addresses of the corresponding DRAM type products.
  • the product type of the dynamic random access memory can be obtained first, and according to the product type of the DRAM to be simulated to fail, the failure address of the DRAM to be simulated to fail can be selected to match more The RA algorithm performs repair analysis, thereby improving the accuracy of repair analysis.
  • this step may include: operating the Raw Data file through the repair algorithm corresponding to the product type to obtain the address file and repair plan file of the invalid address. Therefore, the matching degree between the address file of the invalid address and the repair plan file is improved, and the accuracy of subsequent repair operations is improved.
  • the operation can be performed in a conventional or compressed manner.
  • the conventional method is to test each address unit independently to determine whether each address unit is a failure address;
  • the compressed mode is to test the associated multiple address units together, when at least one address unit in the multiple address units is When the address is invalid, it is determined that the plurality of address units are all invalid addresses.
  • the data format of the Raw Data file can be obtained first, and the data format is used to indicate that when the Raw Data file is operated by the patching algorithm, the operation is performed in a conventional manner or in a compressed manner .
  • the simulation software platform provides a selection interface for selecting the data format of the Raw Data file before the detection personnel configures the invalidation address of the dynamic random access memory of the simulated failure, and the detection personnel selects the Raw Data in the interface.
  • the data format of the document which instructs the simulation software platform to perform the operation of the RA algorithm in a conventional way or in a compressed way.
  • Step 104 Repair the invalid address in the address file based on the repair plan document, and display the repair result.
  • the simulation software platform After the simulation software platform completes the RA algorithm calculation to obtain the address file and repair plan file of the failed address, it can automatically repair the failed address in the corresponding address file according to the repair plan in the repair plan file, and save the address file in each address file.
  • the result of whether the invalid address is corrected is displayed on the platform interface.
  • the simulation software platform performs a patching operation on the specified address document and the patching scheme document based on the selection operation of the inspector, and displays the patching result.
  • the RA algorithm of the DRAM is verified offline through a simulation software platform.
  • Use the offline verification method to flexibly configure the failure address of the simulated failure DRAM; form the Raw Data file of the failure address; operate the Raw Data file through the repair algorithm to obtain the address file of the failure address and the repair plan file; finally based on The repair plan document repairs the invalid addresses in the address file and displays the repair results, so as to complete the verification process of the RA algorithm without occupying the test machine and causing damage to the wafer, reducing the cost of DRAM production; making up for the current manual Omissions in the comparison method lead to incomplete repair of failed units; the process of online multi-site testing can be simulated to fully verify the results of multi-site repair algorithms and improve the efficiency of algorithm verification.
  • step 101 may include the following sub-steps.
  • Sub-step 1011 Determine the die that generates the failure address.
  • n dies on the wafer may be selected as dies configured with failure addresses.
  • the n grains are marked as: Die 1, Die 2,... Die n.
  • Sub-step 1012 Determine at least one test site and the test items contained in each test site.
  • each test site can be simulated and configured, and each test site corresponds to a different test stage (stage), for example: high temperature test stage (stage00), low temperature test stage (stage01), aging test stage ( stage02).
  • stage00 high temperature test stage
  • stage01 low temperature test stage
  • stage02 aging test stage
  • Each test site can include multiple test items.
  • each test site may include m test items. The m test items are respectively marked as: test item 1, test item 2, . . . test item m.
  • the inspector may select at least one test site, and configure a certain number of test items for the selected test site, so as to simulate a real failure environment corresponding to the configured failure address.
  • Sub-step 1013 Select the failure address of each test item belonging to each test site from the determined die.
  • inspectors configure some address units from the above-mentioned determined die as failure addresses, and associate these failure addresses with the test items in the configured test sites, thereby simulating the actual failure environment, The test site and test item to which the failure source of the failure address in the DRAM product belongs.
  • FIG. 5 it is an operation diagram of the result of configuring failure addresses for multiple test items of multiple test sites.
  • FIG. 5 it is an operation diagram of the result of configuring failure addresses for multiple test items of multiple test sites.
  • step 102 may be:
  • Sub-step 1021 Form the Raw Data file of the failure address of each test item belonging to each test site.
  • the number of documents and the failure address contained in each document can also be divided according to the test site and the test item to which the failure address belongs.
  • the failure address of any test item belonging to any test site is uniquely included in a Raw Data file.
  • rdm_1.dat m is the test item number, 1:Site (storage unit) number.
  • step 103 may be:
  • Sub-step 1031 Test the Raw Data file according to the test site to which the failure address belongs, and obtain the address file and repair plan document of the failure address contained in each test site.
  • the tester when performing RA algorithm calculation on the failure address in the Raw Data file, can choose to separately execute the RA algorithm on the Raw Data files belonging to different test sites, so that according to the results contained in each test site obtained, The address file and repair plan file of the failure address, to verify the repair analysis ability of the RA algorithm alone applied to each test site.
  • step 103 may also be:
  • Sub-step 1032 Raw Data file is carried out combination test by at least two combined test sites after failure address belongs, obtains the address file and the repair plan document of the failure address contained in the combined test site.
  • the tester when performing RA algorithm calculation on the failure address in the Raw Data file, the tester can choose to combine the Raw Data files belonging to different test sites and then perform the RA algorithm as a whole, so that according to the obtained combination
  • the address files and repair plan files of the failure addresses contained in the test site verify the repair analysis ability of the RA algorithm applied to the combination of multiple test sites.
  • the addresses covered by the address file and the repair solution file can be clearly identified in the simulation software platform in the form of an address space array. address unit.
  • the address units identified in the two arrays can be directly covered and matched (Cover) to obtain a repair result.
  • the failure address of DRAM is divided by setting multi-site multi-test items to form corresponding Raw Data files; the Raw Data files of different test sites are used for RA calculations independently, or for at least two test sites.
  • the RA calculation is performed after the failure address is combined, so as to verify the repair analysis ability of the RA algorithm applied to a single test site or a combination of multiple test sites according to the obtained address document and repair plan document of the failure address.
  • step 104 may include the following sub-steps.
  • Sub-step 1041 Provide a file selection interface, and perform a repair operation based on the invalidation address file and the corresponding repair plan file selected on the interface.
  • the simulation software platform will provide an operation interface for selecting failure address files and corresponding repair solution files. Detectors can select the patch file in the patch file menu (FU File), select the address file in the address file menu (MD File); then click "EXECUTE" to run the patch process. After that, the repair result information will be displayed at the bottom of the operation interface.
  • the manner of displaying the repair result is:
  • An address array of the address space of the simulated invalid DRAM is provided, and a result of whether the selected invalid address file can be successfully repaired by the corresponding repair solution file is identified in the address array.
  • the location of the failure address in the failure address document In the actual display of repair results, the location of the failure address in the failure address document, the location of the repair solution in the repair solution document, and Whether the two match.
  • the so-called match means that the invalid address is correctly repaired by the repair scheme. For example, when color is used for marking, the failure address can be marked in red, the repair solution can be marked in green, and the match between the failure address and the repair solution can be marked in yellow.
  • the inspector can also perform the export operation of the repair result in the simulation software platform as needed, and the simulation software platform generates and exports the repair result to a specified directory file based on the export operation of the repair result. For example, by clicking "OUTPUT", the inspector can export the repair result for subsequent data statistics and analysis.
  • the simulation software platform provides a file selection interface to facilitate the detection personnel to trigger the execution of the repair operation based on the failure address file selected on the interface and the corresponding repair plan file.
  • a file selection interface to facilitate the detection personnel to trigger the execution of the repair operation based on the failure address file selected on the interface and the corresponding repair plan file.
  • the embodiment of the present application also provides an electronic device, as shown in FIG. 12 , including: at least one processor 201; and a memory 202 communicatively connected to the at least one processor 201; The instructions executed by the at least one processor 201, the instructions are executed by the at least one processor 201, so that the at least one processor 201 can execute the methods corresponding to the above-mentioned Figures 1, 4, 7, and 9 example
  • the memory 202 and the processor 201 are connected by a bus, and the bus may include any number of interconnected buses and bridges, and the bus connects one or more processors 201 and various circuits of the memory 202 together.
  • the bus may also connect together various other circuits such as peripherals, voltage regulators, and power management circuits, all of which are well known in the art and therefore will not be further described herein.
  • the bus interface provides an interface between the bus and the transceivers.
  • a transceiver may be a single element or multiple elements, such as multiple receivers and transmitters, providing a means for communicating with various other devices over a transmission medium.
  • the data processed by the processor 201 is transmitted on the wireless medium through the antenna, and the antenna also receives the data and transmits the data to the processor 201 .
  • Processor 201 is responsible for managing the bus and general processing, and may also provide various functions including timing, peripheral interface, voltage regulation, power management and other control functions. And the memory 202 may be used to store data used by the processor 201 when performing operations.
  • the embodiment of the present application also provides a computer-readable storage medium storing a computer program.
  • the computer program is executed by the processor, the above-mentioned method embodiments corresponding to FIG. 1 , FIG. 4 , FIG. 7 , and FIG. 9 are realized.
  • a storage medium includes several instructions to make a device ( It may be a single-chip microcomputer, a chip, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc., which can store program codes. .
  • the RA algorithm of the DRAM is verified offline through a simulation software platform.
  • Use the offline verification method to flexibly configure the failure address of the simulated failure DRAM; form the Raw Data file of the failure address; operate the Raw Data file through the repair algorithm to obtain the address file of the failure address and the repair plan file; finally based on The repair plan document repairs the invalid addresses in the address file and displays the repair results, so as to complete the verification process of the RA algorithm without occupying the test machine and causing damage to the wafer, reducing the cost of DRAM production; making up for the current manual Omissions in the comparison method lead to incomplete repair of failed units; the process of online multi-site testing can be simulated to fully verify the results of multi-site repair algorithms and improve the efficiency of algorithm verification.

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Abstract

Procédé de vérification pour analyse de réparations, dispositif électronique et support de stockage. Le procédé peut s'appliquer à une plateforme logicielle de simulation et consiste : à configurer une adresse de défaillance d'une mémoire vive dynamique simulant une défaillance (101) ; à former un document de données brutes de l'adresse de défaillance (102) ; à réaliser une opération sur le document de données brutes par analyse de réparations, pour obtenir un document d'adresses et un document de solutions de réparation de l'adresse de défaillance (103) ; et à réparer l'adresse de défaillance du document d'adresses selon le document de solutions de réparation, puis à afficher un résultat de réparation (104).
PCT/CN2021/135714 2021-07-08 2021-12-06 Procédé de vérification pour analyse de réparations, dispositif électronique et support de stockage WO2023279647A1 (fr)

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CN110968985A (zh) * 2018-09-30 2020-04-07 长鑫存储技术有限公司 集成电路修补算法确定方法及装置、存储介质、电子设备
CN111143211A (zh) * 2019-12-24 2020-05-12 上海华岭集成电路技术股份有限公司 离线快速检测测试设置准确性的方法

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CN115934588A (zh) * 2023-03-10 2023-04-07 长鑫存储技术有限公司 失效地址处理方法、装置及电子设备
CN115934588B (zh) * 2023-03-10 2023-08-04 长鑫存储技术有限公司 失效地址处理方法、装置及电子设备

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