WO2023279486A1 - 静电保护电路及芯片 - Google Patents

静电保护电路及芯片 Download PDF

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Publication number
WO2023279486A1
WO2023279486A1 PCT/CN2021/113406 CN2021113406W WO2023279486A1 WO 2023279486 A1 WO2023279486 A1 WO 2023279486A1 CN 2021113406 W CN2021113406 W CN 2021113406W WO 2023279486 A1 WO2023279486 A1 WO 2023279486A1
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Prior art keywords
node
transistor
protection circuit
electrostatic protection
inverter group
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PCT/CN2021/113406
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English (en)
French (fr)
Inventor
许杞安
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长鑫存储技术有限公司
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Publication of WO2023279486A1 publication Critical patent/WO2023279486A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current

Definitions

  • the present disclosure relates to but not limited to an electrostatic protection circuit and chip.
  • the resistor (R) is usually selected as a diffusion resistor of 5000 ohms
  • the capacitor (C) is usually selected as a 20 picofarad NMOS capacitor, but such a resistor (R) And the capacitor (C) will occupy a large layout space, and the large capacitor will also cause a large leakage current.
  • the disclosure provides an electrostatic protection circuit and a chip.
  • the first aspect of the embodiments of the present disclosure provides an electrostatic protection circuit, which is connected between a power supply VDD and a ground VSS, and the electrostatic protection circuit includes:
  • a filtering branch comprising a first node
  • a first inverter group the input terminal of which is connected to the first node, and the output terminal of which is connected to the second node;
  • a switching transistor connected between the third node and the ground VSS, the gate of which is connected to the second node;
  • a clamping transistor the gate of which is connected to the fourth node for shunting the electrostatic pulse
  • a feedback transistor which is connected between the power supply VDD and the third node, and whose gate is connected to the fourth node, for delaying the turn-on time of the clamping transistor;
  • the second inverter group has its input terminal connected to the third node, and its output terminal connected to the fourth node.
  • a second aspect of the embodiments of the present disclosure provides a chip, one or more pins of the chip are electrically connected to the above electrostatic protection circuit.
  • the electrostatic protection circuit delays the turn-on time of the clamp transistor by setting the feedback transistor at the third node and the fourth node, effectively prolonging the static pulse shunt time of the clamp transistor, reducing the RC time constant and layout
  • the area improves the performance of the electrostatic protection circuit, thereby solving the problem of large leakage current caused by a large capacitance value, and the problem of increasing the layout area with a large RC time constant, and improving the electrostatic protection ability of the product.
  • Fig. 1 is a schematic diagram of a first electrostatic protection circuit according to an exemplary embodiment.
  • Fig. 2 is a schematic diagram of a second electrostatic protection circuit according to an exemplary embodiment.
  • Fig. 3 is a schematic diagram of a third electrostatic protection circuit according to an exemplary embodiment.
  • Fig. 4 is a schematic diagram of a fourth electrostatic protection circuit according to an exemplary embodiment.
  • 1-4 are schematic diagrams of electrostatic protection circuits provided by the present disclosure.
  • the electrostatic protection circuit 100 is connected between the power supply VDD and the ground VSS, and includes: a filtering branch 10, a first inverter group 11, a switching transistor 12, a clamp Transistor 13 , feedback transistor 14 and second inverter group 15 .
  • the filtering branch 10 includes a filtering resistor 101 and a filtering capacitor 102 .
  • the filter resistor 101 and the filter capacitor 102 are connected in series between the power supply VDD and the ground VSS, and a first node N1 is provided on the path between the two.
  • One end of the filter resistor 101 is connected to the power supply VDD, and the other end is connected to the first node N1.
  • One end of the filter capacitor 102 is connected to the ground VSS, and the other end is connected to the first node N1.
  • the input terminals of the first inverter group 11 are connected to the first node N1, and the output terminals of the first inverter group 11 are connected to the second node N2.
  • the switching transistor 12 has a first terminal, a second terminal and a third terminal.
  • the first end of the switching transistor 12 is connected to the third node N3, the second end is connected to the ground VSS, and the third end, ie, the gate, is connected to the second node N2.
  • the clamp transistor 13 has a first terminal, a second terminal and a third terminal. Wherein, the first end of the clamping transistor 13 is connected to the power supply VDD, the second end is connected to the ground VSS, and the third end, ie, the gate, is connected to the fourth node N4 for shunting the electrostatic pulse.
  • the feedback transistor 14 has a first terminal, a second terminal and a third terminal, the first terminal of the feedback transistor 14 is connected to the power supply VDD, the second terminal is connected to the third node N3, and the third terminal, namely the gate, is connected to the fourth node N4 , the feedback transistor 14 is used to delay the turn-on time of the clamp transistor 13 .
  • the input terminal of the second inverter group 15 is connected to the third node N3, and the output terminal of the second inverter group 15 is connected to the fourth node N4.
  • the electrostatic protection circuit 100 in this embodiment further includes a first resistor 16, wherein one end of the first resistor 16 is connected to the fourth node N4, and the other end of the first resistor 16 is connected to the ground VSS, so that the clamping transistor 13 is at a low potential or at a high potential, so that the clamping transistor 13 is turned off.
  • the electrostatic protection circuit in this embodiment also includes a parasitic diode 17, one end of which is connected to the power supply VDD, and the other end is connected to the ground VSS, and is connected in parallel with the clamping transistor 13 for conducting the connection between the ground VSS and the power supply VDD. path between.
  • the clamping transistor 13 is an N-type transistor, the first terminal of the clamping transistor 13 is a drain and is connected to the power supply VDD; the second terminal of the clamping transistor 13 is a source and is connected to the ground VSS; The three terminals are gates, and are connected to the fourth node N4.
  • the feedback transistor 14 is a P-type transistor, the first end of the feedback transistor 14 is a source, and is connected to the power supply VDD; its second end is a drain, and is connected to the third node N3; its third end is a gate, And connected to the fourth node N4.
  • the switch transistor 12 is an N-type transistor, the first end of the switch transistor 12 is a drain, and is connected to the third node N3; its second end is a source, and is connected to the ground VSS; its third end is a gate, And connected to the second node N2.
  • both the first inverter group 11 and the second inverter group 15 include an odd number of inverters. Inverters, such as 1, 3 or 5 inverters. In this embodiment, an inverter is used as an example in the first inverter group 11 and the second inverter group 15 for illustration.
  • the first inverter group 11 and the second inverter group 15 both include a P-type transistor and an N-type transistor, wherein the gate of the P-type transistor in each inverter and the N-type transistor in the inverter The gate of the P-type transistor is connected as an input terminal, and the drain of the P-type transistor is connected with the drain of the N-type transistor as an output terminal.
  • the ESD occurrence state in the electrostatic protection circuit 100 in this embodiment includes PS mode and NS mode, wherein, the PS mode refers to when the power supply VDD is floating, and the electrostatic discharge ESD relative to the positive voltage discharges at a certain input pin to the ground VSS ;NS mode refers to when the power supply VDD is floating, and the ESD of a relatively negative voltage discharges from a certain input pin to the ground VSS pin.
  • PS mode refers to when the power supply VDD is floating, and the electrostatic discharge ESD relative to the positive voltage discharges at a certain input pin to the ground VSS
  • NS mode refers to when the power supply VDD is floating, and the ESD of a relatively negative voltage discharges from a certain input pin to the ground VSS pin.
  • the fourth node N4 When the power supply VDD starts and works normally, the fourth node N4 is connected to the ground VSS through the first resistor 16. At this time, the fourth node N4 is at a low potential, the clamping transistor 13 is in a cut-off state, and the electrostatic protection circuit is turned off. In the above state, the feedback transistor 14 is turned on, and the third node N3 is at a high potential.
  • the second inverter group 15 After the high potential passes through the second inverter group 15, wherein the P-type transistors in the second inverter group 15 are in a cut-off state, The N-type transistors in the second inverter group 15 are turned on, so as to further ensure that the fourth node N4 is at a low potential, further ensure that the clamping transistor 13 is in an off state, and further ensure that the electrostatic protection circuit 100 is turned off.
  • the filter branch 10 composed of the filter resistor 101 and the filter capacitor 102 keeps the first node N1 at a low potential.
  • the P-type transistors in the first inverter group 11 are in a conducting state, the P-type transistors in the first inverter group 11
  • the N-type transistor is in a cut-off state, so that the second node N2 is at a high potential.
  • the switching transistor 12 is turned on, so that the third node N3 is at a low potential.
  • the low potential of the third node N3 undergoes phase inversion in the second inverter group 15, wherein the P-type transistors in the second inverter group 15 are in a conducting state, and the P-type transistors in the second inverter group 15
  • the N-type transistor is in a cut-off state, so that the fourth node N4 is at a high potential, and the clamping transistor 13 is turned on to discharge the electrostatic current.
  • the potential of the first node N1 gradually rises, trying to turn off the P-type transistors in the first inverter group 11, and trying to turn on the N-type transistors in the first inverter group 11, Therefore, it is attempted to raise the potential of the second node N2 to a low potential, so as to turn off the switch transistor 12 .
  • the feedback transistor 14 since the fourth node N4 is at a high potential, the feedback transistor 14 is in a cut-off state, so that the third node N3 cannot be raised to a high potential through the feedback transistor 14, so that the time for the third node N3 to maintain a low potential can be prolonged , so as to ensure that the fourth node N4 maintains the high potential for a longer time.
  • the feedback circuit formed by the feedback transistor 14 can keep the fourth node N4 at a high potential for a longer time during the electrostatic action time, so as to effectively ensure that the clamping transistor 13 is turned on and discharges the electrostatic current during the electrostatic action time.
  • the clamp transistor 13 When NS mode static electricity occurs, the clamp transistor 13 is in the conduction state. At this time, the static discharge current is discharged through the parasitic diode 17 connected in parallel with the clamp transistor 13. After the static discharge current passes through the parasitic diode 17, it flows from the ground VSS to Power supply VDD.
  • the electrostatic protection circuit in this embodiment can effectively extend the duration of electrostatic discharge even if a capacitor with a smaller capacity is used to reduce the RC time constant, avoid damage to electronic devices by electrostatic current, and reduce capacitance and resistance Occupying the area of the semiconductor layout can also effectively reduce the leakage current.
  • the electrostatic protection circuit 200 is connected between the power supply VDD and the ground VSS, and includes: a filtering branch 20, a first inverter group 21, a switching transistor 22, a clamp Transistor 23 , feedback transistor 24 and second inverter group 25 .
  • the filtering branch 20 includes a filtering resistor 201 and a filtering capacitor 202 .
  • the filter resistor 201 and the filter capacitor 202 are connected in series between the power supply VDD and the ground VSS, and a first node N1 is provided on the path between the two.
  • One end of the filter resistor 201 is connected to the power supply VDD, and the other end is connected to the first node N1.
  • One end of the filter capacitor 202 is connected to the ground VSS and the other end is connected to the first node N1.
  • the input terminals of the first inverter group 21 are connected to the first node N1, and the output terminals of the first inverter group 21 are connected to the second node N2.
  • the switching transistor 22 has a first terminal, a second terminal and a third terminal.
  • the first end of the switching transistor 22 is connected to the third node N3, the second end is connected to the ground VSS, and the third end, ie, the gate, is connected to the second node N2.
  • the clamping transistor 23 has a first terminal, a second terminal and a third terminal. Wherein, the first terminal of the clamping transistor 23 is connected to the power supply VDD, the second terminal is connected to the ground VSS, and the third terminal, that is, the gate is connected to the fourth terminal.
  • the node N4 is used for shunting the electrostatic pulse.
  • the feedback transistor 24 has a first terminal, a second terminal and a third terminal, the first terminal of the feedback transistor 24 is connected to the power supply VDD, the second terminal is connected to the third node N3, and the third terminal, namely the gate, is connected to the fourth node N4 , which is used to delay the turn-on time of the clamp transistor 23 .
  • the input terminal of the second inverter group 25 is connected to the third node N3, and the output terminal of the second inverter group 25 is connected to the fourth node N4.
  • the electrostatic protection circuit 200 in this embodiment further includes a first resistor 26, wherein one end of the first resistor 26 is connected to the fourth node N4, and the other end of the first resistor 26 is connected to the ground VSS, so that the clamping transistor 23 is at a low potential or at a high potential, so that the clamping transistor 23 is turned off.
  • the electrostatic protection circuit 200 in this embodiment further includes a parasitic diode 27, one end of which is connected to the power supply VDD, the other end is connected to the ground VSS, and is connected in parallel with the clamping transistor 23 for conducting the ground VSS to the power supply VDD pathway between.
  • the clamping transistor 23 is an N-type transistor, the first end of the clamping transistor 23 is a drain, and is connected to the power supply VDD; its second end is a source, and is connected to the ground VSS; The three terminals are gates, and are connected to the fourth node N4.
  • the feedback transistor 24 is a P-type transistor, the first end of the feedback transistor 24 is a source, and is connected to the power supply VDD; its second end is a drain, and is connected to the third node N3; its third end is a gate, And connected to the fourth node N4.
  • the switch transistor 22 is a P-type transistor, the first end of the switch transistor 22 is a drain, and is connected to the third node N3; its second end is a source, and is connected to the ground VSS; its third end is a gate, And connected to the second node N2.
  • the clamping transistor 23 is an N-type transistor
  • the feedback transistor 24 is a P-type transistor
  • the switch transistor 22 is a P-type transistor
  • the first inverter group 21 includes an even number of inverters, such as 2, 4 or 6 inverters
  • the second inverter group 25 includes an odd number of inverters, such as 1, 3 or 5 inverters.
  • the first inverter group 21 includes two inverters arranged in series
  • the second inverter group 25 includes one inverter.
  • Two inverters in the first inverter group 21 and one inverter in the second inverter group 25 all include a P-type transistor and an N-type transistor, wherein the P-type transistor in each inverter The gate of the transistor is connected to the gate of the N-type transistor in the inverter as an input end, and the drain of the P-type transistor is connected to the drain of the N-type transistor as an output end.
  • the ESD occurrence state in the electrostatic protection circuit 200 in this embodiment includes PS mode and NS mode, wherein, the PS mode refers to when the power supply VDD is floating, and the electrostatic discharge ESD relative to the positive voltage discharges at a certain input pin to the ground VSS ;NS mode refers to when the power supply VDD is floating, and the ESD of a relatively negative voltage discharges to the ground VSS at an input pin.
  • PS mode refers to when the power supply VDD is floating, and the electrostatic discharge ESD relative to the positive voltage discharges at a certain input pin to the ground VSS
  • NS mode refers to when the power supply VDD is floating, and the ESD of a relatively negative voltage discharges to the ground VSS at an input pin.
  • the fourth node N4 When the power supply starts and works normally, the fourth node N4 is connected to the ground VSS through the first resistor 26 , at this time, the fourth node N4 is at a low potential, the clamping transistor 23 is in a cut-off state, and the electrostatic protection circuit is turned off. In the above state, the feedback transistor 24 is turned on, and the third node N3 is at a high potential.
  • the second inverter group 25 After the high potential passes through the second inverter group 25, wherein the P-type transistors in the second inverter group 25 are in a cut-off state, The N-type transistors in the second inverter group 25 are turned on, so as to further ensure that the fourth node N4 is at a low potential, further ensure that the clamping transistor 23 is in an off state, and further ensure that the electrostatic protection circuit 200 is turned off.
  • the filter branch 20 composed of the filter resistor 201 and the filter capacitor 202 keeps the first node N1 at a low potential. After the low potential of the first node N1 undergoes two phase inversions of the two inverters of the first inverter group 21 , the second node N2 is at a low potential. At this time, the switching transistor 22 is turned on, so that the third node N3 is at a low potential.
  • the N transistors in the second inverter group 25 After the low potential of the third node N3 undergoes phase inversion in the second inverter group 25, wherein the P-type transistors in the second inverter group 25 are in the conduction state, the N transistors in the second inverter group 25 The type transistor is in the cut-off state, so that the fourth node N4 is at a high potential, and the clamp transistor is turned on to discharge the electrostatic current.
  • the time for the node N4 to maintain the high potential is prolonged, so that the time for the fourth node N4 to maintain the low potential during the electrostatic action time is prolonged, so as to effectively ensure that the clamping transistor 23 is turned on and discharges the electrostatic current during the electrostatic action time.
  • the clamping transistor 23 When NS mode static electricity occurs, the clamping transistor 23 is in the conduction state. At this time, the static discharge current is completed through the parasitic diode 27 connected in parallel with the clamping transistor 23. After the electrostatic discharge current passes through the parasitic diode 27, it flows from the ground VSS to Power supply VDD.
  • the electrostatic protection circuit in this embodiment can effectively extend the duration of electrostatic discharge even if a capacitor with a smaller capacity is used to reduce the RC time constant, avoid damage to electronic devices by electrostatic current, and reduce capacitance and resistance Occupying the area of the semiconductor layout can also effectively reduce the leakage current.
  • the electrostatic protection circuit 300 is connected between the power supply VDD and the ground VSS, and includes: a filtering branch 30, a first inverter group 31, a switching transistor 32, a clamp Transistor 33 , feedback transistor 34 and second inverter group 35 .
  • the filtering branch 30 includes a filtering resistor 301 and a filtering capacitor 302 .
  • the filter resistor 301 and the filter capacitor 302 are connected in series between the power supply VDD and the ground VSS, and a first node N1 is set on the path between the two.
  • One end of the filter resistor 301 is connected to the power supply VDD, and the other end is connected to the first node N1.
  • a node N1, one end of the filtering capacitor 302 is connected to the ground VSS and the other end is connected to the first node N1.
  • the input terminals of the first inverter group 31 are connected to the first node N1, and the output terminals of the first inverter group 31 are connected to the second node N2.
  • the switching transistor 32 has a first terminal, a second terminal and a third terminal.
  • the first terminal of the switch transistor 32 is connected to the third node N3, the second terminal is connected to the ground VSS, and the third terminal, ie, the gate, is connected to the second node N2.
  • the clamping transistor 33 has a first terminal, a second terminal and a third terminal, wherein the first terminal of the clamping transistor 33 is connected to the power supply VDD, the second terminal is connected to the ground VSS, and the third terminal, that is, the gate is connected to the fourth terminal.
  • the node N4 is used for shunting the electrostatic pulse.
  • the feedback transistor 34 has a first terminal, a second terminal and a third terminal, the first terminal of the feedback transistor 34 is connected to the power supply VDD, the second terminal is connected to the third node N3, and the third terminal, namely the gate, is connected to the fourth node N4 , which is used to delay the turn-on time of the clamp transistor 33 .
  • the input terminal of the second inverter group 35 is connected to the third node N3, and the output terminal of the second inverter group 35 is connected to the fourth node N4.
  • the electrostatic protection circuit 300 in this embodiment further includes a second resistor 36, wherein one end of the second resistor 36 is connected to the fourth node N4, and the other end of the second resistor 36 is connected between the power supply VDD, so that the clamping transistor 33 is at a low potential or at a high potential, so that the clamping transistor 33 is in an off state.
  • the electrostatic protection circuit 300 in this embodiment also includes a parasitic diode 37, one end of which is connected to the power supply VDD, and the other end is connected to the ground VSS, and is connected in parallel with the clamping transistor 33, for conducting the ground VSS to the power supply VDD pathway between.
  • the clamping transistor 33 is a P-type transistor, the first terminal of the clamping transistor 33 is a drain and is connected to the power supply VDD, the second terminal is a source and is connected to the ground VSS, and the second terminal of the clamping transistor 33 is a source and is connected to the ground VSS.
  • the three terminals are gates, and are connected to the fourth node N4.
  • the feedback transistor 34 is an N-type transistor, the first end of the feedback transistor 34 is a source, and is connected to the power supply VDD; its second end is a drain, and is connected to the third node N3; its third end is a gate, And connected to the fourth node N4.
  • the switch transistor 32 is an N-type transistor, the first end of the switch transistor 32 is a drain, and is connected to the third node N3; its second end is a source, and is connected to the ground VSS; its third end is a gate, And connected to the second node N2.
  • the first inverter group 31 includes an odd number of inverters, such as 1 or 3 Or 5 inverters
  • the second inverter group 35 includes an even number of inverters, such as 2, 4 or 6 inverters.
  • the first inverter group 31 includes one inverter
  • the second inverter group 35 includes two serially arranged inverters as an example for illustration.
  • One inverter in the first inverter group 31 and the two inverters in the second inverter group 35 all include a P-type transistor and an N-type transistor, wherein the P-type transistor in each inverter The gate of the transistor is connected to the gate of the N-type transistor in the inverter as an input end, and the drain of the P-type transistor is connected to the drain of the N-type transistor as an output end.
  • the ESD occurrence states in the electrostatic protection circuit 300 in this embodiment include PS mode and NS mode, wherein, the PS mode refers to when the power supply VDD pin is floating, and the electrostatic discharge ESD relative to the positive voltage ground is at a certain input pin to ground VSS Discharge; NS mode refers to when the VDD pin of the power supply is floating, and the ESD of the relative negative voltage discharges on a certain input pin to the ground VSS pin.
  • PS mode refers to when the power supply VDD pin is floating, and the electrostatic discharge ESD relative to the positive voltage ground is at a certain input pin to ground VSS Discharge
  • NS mode refers to when the VDD pin of the power supply is floating, and the ESD of the relative negative voltage discharges on a certain input pin to the ground VSS pin.
  • the electrostatic discharge process in PS mode and NS mode are taken as examples to illustrate . .
  • the fourth node N4 When the power supply starts and works normally, the fourth node N4 is connected to the power supply VDD through the second resistor 36, at this time, the fourth node N4 is at a high potential, the clamping transistor 33 is in a cut-off state, and the electrostatic protection circuit is turned off. In the above state, the feedback transistor 34 is turned on, and the third node N3 is at a high potential. After the high potential is reversed twice by the second inverter group 35, the fourth node N4 continues to be at a high potential, so that It is further ensured that the clamping transistor 33 is in an off state, and the electrostatic protection circuit 300 is further ensured to be turned off.
  • the filter branch 30 composed of the filter resistor 301 and the filter capacitor 302 keeps the first node N1 at a low potential.
  • the low potential of the first node N1 causes the second node N2 to be at a high potential after the phase inversion of the first inverter group 31 is performed.
  • the switching transistor 32 is turned on, so that the third node N3 is at a low potential.
  • the low potential of the third node N3 undergoes two phase inversions in the second inverter group 35 , so that the fourth node N4 is at a low potential, and the clamping transistor 33 is turned on to discharge the electrostatic current.
  • the potential of the first node N1 gradually rises, after the phase inversion of the first inverter group 31, the potential of the second node N2 is reduced to a low potential, so that the switching transistor 32 is closed.
  • the feedback transistor 34 is in a cut-off state, so that the third node N3 cannot be raised to a high potential, so that the time for the third node N3 to maintain a low potential can be prolonged, thereby ensuring that the fourth node N3 is at a low potential.
  • the time that the node N4 maintains the low potential is lengthened.
  • the time for the fourth node N4 to maintain a low potential during the electrostatic action time is prolonged, so as to effectively ensure that the clamping transistor 33 is turned on and discharges the electrostatic current during the electrostatic action time.
  • the clamping transistor 33 When NS mode static electricity occurs, the clamping transistor 33 is in the conduction state. At this time, the static discharge current is completed through the parasitic diode 37 connected in parallel with the clamping transistor 33. After the electrostatic discharge current passes through the parasitic diode 37, it flows from the ground VSS to Power supply VDD.
  • the electrostatic protection circuit in this embodiment can effectively extend the duration of electrostatic discharge even if a capacitor with a smaller capacity is used to reduce the RC time constant, avoid damage to electronic devices by electrostatic current, and reduce capacitance and resistance Occupying the area of the semiconductor layout can also effectively reduce the leakage current.
  • the electrostatic protection circuit 400 is connected between the power supply VDD and the ground VSS, and includes: a filtering branch 40, a first inverter group 41, a switching transistor 42, a clamp Transistor 43 , feedback transistor 44 and second inverter group 45 .
  • the filtering branch 40 includes a filtering resistor 401 and a filtering capacitor 402 .
  • the filter resistor 401 and the filter capacitor 402 are connected in series between the power supply VDD and the ground VSS, and a first node N1 is provided on the path between the two.
  • One end of the filter resistor 401 is connected to the power supply VDD, and the other end is connected to the first node N1.
  • One end of the filter capacitor 402 is connected to the ground VSS and the other end is connected to the first node N1.
  • the input terminals of the first inverter group 41 are connected to the first node N1, and the output terminals of the first inverter group 41 are connected to the second node N2.
  • the switching transistor 42 has a first terminal, a second terminal and a third terminal.
  • the first end of the switching transistor 42 is connected to the third node N3, the second end is connected to the ground VSS, and the third end, ie, the gate, is connected to the second node N2.
  • the clamping transistor 43 has a first terminal, a second terminal and a third terminal, wherein the first terminal of the clamping transistor 43 is connected to the power supply VDD, the second terminal is connected to the ground VSS, and the third terminal, that is, the gate, is connected to the fourth terminal.
  • the node N4 is used for shunting the electrostatic pulse.
  • the feedback transistor 44 has a first terminal, a second terminal and a third terminal, the first terminal of the feedback transistor 44 is connected to the power supply VDD, the second terminal is connected to the third node N3, and the third terminal, namely the gate, is connected to the fourth node N4 , used to delay the turn-on time of the clamp transistor 43 .
  • the input terminal of the second inverter group 45 is connected to the third node N3, and the output terminal of the second inverter group 45 is connected to the fourth node N4.
  • the electrostatic protection circuit in this embodiment further includes a second resistor 46, wherein one end of the second resistor 46 is connected to the fourth node N4, and the other end of the second resistor 46 is connected between the power supply VDD, so that the clamping transistor 43 is at a low potential or at a high potential, so that the clamping transistor 43 is in an off state.
  • the electrostatic protection circuit in this embodiment also includes a parasitic diode 47, one end of which is connected to the power supply VDD, and the other end is connected to the ground VSS, and is connected in parallel with the clamping transistor 43 for conducting the connection between the ground VSS and the power supply VDD. path between.
  • the clamping transistor 43 is a P-type transistor, the first end of the clamping transistor 43 is a drain and is connected to the power supply VDD; the second end of the clamping transistor 43 is a source and is connected to the ground VSS; The three terminals are gates, and are connected to the fourth node N4.
  • the feedback transistor 44 is an N-type transistor, the first end of the feedback transistor 44 is a source, and is connected to the power supply VDD; its second end is a drain, and is connected to the third node N3; its third end is a gate, And connected to the fourth node N4.
  • the switch transistor 42 is a P-type transistor, the first end of the switch transistor 42 is a drain, and is connected to the third node N3, the second end is a source, and is connected to the ground VSS, and the third end is a gate, And connected to the second node N2.
  • the clamping transistor 43 is a P-type transistor
  • the feedback transistor 44 is an N-type transistor
  • the switch transistor 42 is a P-type transistor
  • the first inverter group 41 includes an even number of inverters
  • the second inverter Group 45 includes an even number of inverters, such as 2, 4 or 6 inverters.
  • description is made by taking the example that the first inverter group 41 includes two inverters arranged in series, and the second inverter group 45 includes two inverters arranged in series.
  • the two inverters in the first inverter group 41 and the two inverters in the second inverter group 45 all include a P-type transistor and an N-type transistor, wherein the P in each inverter
  • the gate of the N-type transistor is connected to the gate of the N-type transistor in the inverter as an input terminal
  • the drain of the P-type transistor is connected to the drain of the N-type transistor as an output terminal.
  • the ESD occurrence state in the electrostatic protection circuit 200 in this embodiment includes PS mode and NS mode, wherein, the PS mode refers to when the power supply VDD is floating, and the electrostatic discharge ESD relative to the positive voltage discharges at a certain input pin to the ground VSS ;NS mode refers to when the power supply VDD is floating, and the ESD of a relatively negative voltage discharges from a certain input pin to the ground VSS pin.
  • PS mode refers to when the power supply VDD is floating, and the electrostatic discharge ESD relative to the positive voltage discharges at a certain input pin to the ground VSS
  • NS mode refers to when the power supply VDD is floating, and the ESD of a relatively negative voltage discharges from a certain input pin to the ground VSS pin.
  • the fourth node N4 When the power supply starts and works normally, the fourth node N4 is connected to the power supply VDD through the second resistor 46. At this time, the fourth node N4 is at a high potential, the clamping transistor 43 is in a cut-off state, and the electrostatic protection circuit is turned off. In the above state, the feedback transistor 44 is turned on, and the third node N3 is at a high potential. After the high potential is reversed twice by the second inverter group 45, the fourth node N4 continues to be at a high potential, so that It is further ensured that the clamping transistor 43 is in an off state, and the electrostatic protection circuit 400 is further ensured to be turned off.
  • the filter branch 40 composed of the filter resistor 401 and the filter capacitor 402 keeps the first node N1 at a low potential.
  • the low potential of the first node N1 causes the second node N2 to be at a low potential after two phase inversions by the first inverter group 41 .
  • the switch transistor 42 is turned on, so that the third node N3 is at a low potential.
  • the low potential of the third node N3 undergoes two phase inversions in the second inverter group 45 , so that the fourth node N4 is at a low potential, and the clamping transistor 43 is turned on to discharge the electrostatic current.
  • the time for the node N4 to maintain the low potential is extended, so that the time for the fourth node N4 to maintain the low potential during the electrostatic action time is prolonged, so as to effectively ensure that the clamping transistor 43 is turned on and discharges the electrostatic current during the electrostatic action time.
  • the clamping transistor 43 When NS mode static electricity occurs, the clamping transistor 43 is in the conduction state. At this time, the static discharge current is completed through the parasitic diode 47 connected in series with the clamping transistor 43. After the electrostatic discharge current passes through the parasitic diode 47, it flows from the ground VSS to Power supply VDD.
  • the electrostatic protection circuit in this embodiment can effectively extend the duration of electrostatic discharge even if a capacitor with a smaller capacity is used to reduce the RC time constant, avoid damage to electronic devices by electrostatic current, and reduce capacitance and resistance Occupying the area of the semiconductor layout can also effectively reduce the leakage current.
  • a chip is provided, one or more pins of the chip are electrically connected to the electrostatic protection circuit of the above-mentioned embodiment.
  • a feedback transistor is set between the third node and the fourth node to control and prolong the turn-on time of the electrostatic protection circuit under electrostatic action, so that a smaller capacitor can be used, and a smaller capacitor can be used.
  • a large capacitance can effectively solve the problem of large leakage current caused by large capacitance.
  • adopting a smaller capacitor can reduce the RC time constant, thereby reducing the overall layout area and improving the performance of the electrostatic protection circuit.
  • the electrostatic protection circuit of the present disclosure realizes electrostatic protection for PS mode and NS mode, effectively improves the electrostatic protection capability of semiconductor component products, and the electrostatic protection circuit will not affect the performance and normal functions of the chip, effectively improving Improve the reliability and competitiveness of semiconductor component products.
  • the electrostatic protection circuit and chip provided by the embodiments of the present disclosure, by setting the feedback transistors at the third node and the fourth node, delays the turn-on time of the clamp transistor, effectively prolongs the static pulse shunt time of the clamp transistor, and reduces the RC time
  • the constant and layout area improve the performance of the electrostatic protection circuit, thereby solving the problem of large leakage current caused by large capacitance value, and the problem of increasing layout area with large RC time constant, and improving the electrostatic protection ability of the product.

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Abstract

本公开公布了一种静电保护电路及芯片，静电保护电路被连接在电源VDD和地VSS之间，包括滤波支路、第一反相器组、开关晶体管、钳位晶体管、反馈晶体管和第二反相器组；第一反相器组的两端与第一节点和第二节点连接；开关晶体管的栅极与第二节点连接；钳位晶体管的栅极与第四节点连接；反馈晶体管的栅极与第四节点连接；第二反相器组的两端与第三节点和第四节点连接。

Description

静电保护电路及芯片
本公开基于申请号为202110774914.3，申请日为2021年07月08日，申请名称为“静电保护电路及芯片”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种静电保护电路及芯片。
背景技术
现代半导体的制程越来越先进，半导体器件越来越小，接合深度越来越浅，氧化层越来越薄，半导体集成电路的可靠性面临的挑战也越来越大，尤其是静电保护变得愈发重要。常规的集成电路产品一般均具备静电保护设计，而在该类产品中的静电保护所对应的保护电路中，为保证静电发生的时间内钳位晶体管能充分泄放静电电流，RC时间常数通常为0.1-1μs。此时才能区分出静电和电源启动的瞬态状态，其中电阻(R)通常选为5000欧姆的扩散电阻，电容(C)通常选为20皮法的NMOS电容，但此类的电阻(R)和电容(C)就会占用较大的布局空间，同时大电容也会导致较大的漏电电流。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种静电保护电路及芯片。
本公开实施例的第一方面提供了一种静电保护电路，其被连接在电源VDD和地VSS之间，所述静电保护电路包括：
滤波支路，其包括第一节点；
第一反相器组，其输入端与所述第一节点连接，其输出端与第二节点连接；
开关晶体管，其被连接在第三节点与所述地VSS之间，其栅极与所述第二节点连接；
钳位晶体管，其栅极与第四节点连接，用于静电脉冲分流；
反馈晶体管，其被连接在所述电源VDD和所述第三节点之间，其栅极与第四节点连接，用于延迟所述钳位晶体管的开启时间；
第二反相器组，其输入端与所述第三节点连接，其输出端与所述第四节点连接。
本公开实施例的第二方面提供了一种芯片，芯片的一个或多个管脚电连接上述的静电保护电路。
本公开实施例提供的静电保护电路，通过在第三节点和第四节点设置反馈晶体管，延迟钳位晶体管的开启时间，有效延长了钳位晶体管的静电脉冲分流时间，减小RC时间常数和布局面积，提高了静电保护电路的性能，从而解决了电容值较大导致较大漏电电流的问题，以及较大的RC时间常数增加布局面积的问题，提高了对产品的静电保护能力。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的第一种静电保护电路的示意图。
图2是根据一示例性实施例示出的第二种静电保护电路的示意图。
图3是根据一示例性实施例示出的第三种静电保护电路的示意图。
图4是根据一示例性实施例示出的第四种静电保护电路的示意图。
具体实施方式
下面结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的 实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
图1-图4是本公开所提供的静电保护电路的示意图。
根据本公开的一个实施例，参考图1，该静电保护电路100被连接在电源VDD和地VSS之间，其包括：滤波支路10、第一反相器组11、开关晶体管12、钳位晶体管13、反馈晶体管14和第二反相器组15。
其中，滤波支路10包括滤波电阻器101和滤波电容器102。滤波电阻器101和滤波电容器102被串联在电源VDD和地VSS之间，并在两者之间的通路上设置第一节点N1。滤波电阻器101的一端连接至电源VDD，另一端连接至第一节点N1。滤波电容器102的一端连接至地VSS，另一端连接至第一节点N1。
第一反相器组11的输入端连接至第一节点N1，第一反相器组11的输出端连接至第二节点N2。
开关晶体管12具有第一端、第二端和第三端。开关晶体管12的第一端连接至第三节点N3，第二端连接至地VSS，第三端即栅极连接至第二节点N2。
钳位晶体管13具有第一端、第二端和第三端。其中，钳位晶体管13的第一端连接至电源VDD，第二端连接至地VSS，第三端即栅极连接至第四节点N4，用于实现静电脉冲分流。
反馈晶体管14具有第一端、第二端和第三端，反馈晶体管14的第一端连接至电源VDD，第二端连接至第三节点N3，第三端即栅极连接至第四节点N4，反馈晶体管14用于延迟钳位晶体管13的开启时间。
第二反相器组15的输入端连接至第三节点N3，第二反相器组15的输出端连接至第四节点N4。
本实施例中的静电保护电路100还包括第一电阻16，其中，第一电阻16的一端连接至第四节点N4，第一电阻16的另一端连接至地VSS之间，以使钳位晶体管13处于低电位或处于高电位，从而使钳位晶体管13处于关闭状态。
本实施例中的静电保护电路还包括寄生二极管17，该寄生二极管17的一端连接至电源VDD，另一端连接至地VSS，并与钳位晶体管13并联，用于导通地VSS至电源VDD之间的通路。
在本实施例中，钳位晶体管13为N型晶体管，该钳位晶体管13的第一端是漏极，且连接至电源VDD；其第二端是源极，且连接至地VSS；其第三端是栅极，且连接至第四节点N4。
反馈晶体管14为P型晶体管，该反馈晶体管14的第一端是源极，且连接至电源VDD；其第二端是漏极，且连接至第三节点N3；其第三端为栅极，且连接至第四节点N4。
开关晶体管12为N型晶体管，该开关晶体管12的第一端是漏极，且连接至第三节点N3；其第二端是源极，且连接至地VSS；其第三端是栅极，且连接至第二节点N2。
其中，当钳位晶体管13选用N型晶体管，反馈晶体管14选用P型晶体管，开关晶体管12选用N型晶体管时，第一反相器组11和第二反相器组15中均包括单数个反相器，比如1个、3个或5个反相器。本实施例中，以第一反相器组11和第二反相器组15中均以一个反相器为例进行说明。
第一反相器组11和第二反相器组15均包括一个P型晶体管和一个N型晶体管，其中，每个反相器中的P型晶体管的栅极和该反相器中的N型晶体管的栅极连接，作为输入端，该P型晶体管的漏极和该N型晶体管的漏极连接，作为输出端。
关于本公开实施例中的静电保护电路100的工作状态，可以分为正常工作和ESD发生两种状态。本实施例中的静电保护电路100中的ESD发生状态包括PS模式和NS模式，其中，PS模式是指当电源VDD浮接，而相对正电压的静电放电ESD在某一输入脚对地VSS放电；NS模式是指当电源VDD浮接，而相对负电压的ESD在某一输入脚对地VSS脚放电，下面分别以PS模式和NS模式两种模式下的静电放电过程为例进行说明。
当电源VDD启动和正常工作时，第四节点N4通过第一电阻16连接至地VSS，此时第四节点N4处于低电位，钳位晶体管13处于截止状态，静电保护电路关闭。在上述状态下，反馈晶体管14导通，第三节点N3处于高电位，该高电位经过第二反相器组15后，其中，第二反相器组15中的P型晶 体管处于截止状态，第二反相器组15中的N型晶体管处于导通状态，从而进一步保证第四节点N4处于低电位，进一步保证钳位晶体管13处于截止状态，并进一步保证关闭静电保护电路100。
当PS模式静电发生时，滤波电阻器101和滤波电容器102所组成的滤波支路10使第一节点N1处于低电位。第一节点N1的低电位经过第一反相器组11中的相位反转后，其中，第一反相器组11中的P型晶体管处于导通状态，第一反相器组11中的N型晶体管处于截止状态，从而使第二节点N2处于高电位。此时，开关晶体管12导通，使第三节点N3处于低电位。第三节点N3的低电位经过第二反相器组15中的相位反转后，其中，第二反相器组15中的P型晶体管处于导通状态，第二反相器组15中的N型晶体管处于截止状态，从而使第四节点N4处于高电位，钳位晶体管13导通开始泄放静电电流。
在静电作用的时间内，第一节点N1的电位逐渐升高，试图将第一反相器组11中的P型晶体管关闭，并试图导通第一反相器组11中的N型晶体管，从而试图将第二节点N2的电位升至低电位，以将开关晶体管12关闭。但此时，由于第四节点N4处于高电位，反馈晶体管14处于截止状态，从而使得第三节点N3无法通过反馈晶体管14而升至高电位，这样就可以使第三节点N3维持低电位的时间加长，从而保证第四节点N4维持高电位的时间加长。这样，反馈晶体管14形成的反馈电路可维持第四节点N4在静电作用时间内处于高电位的时间加长，以有效保证钳位晶体管13在静电作用时间内导通并泄放静电电流。
当NS模式静电发生时，钳位晶体管13处于导通状态，此时通过与钳位晶体管13并联的寄生二极管17来完成泄放静电电流，经过静电泄放电流通过寄生二极管17，由地VSS流向电源VDD。
本实施例中的静电保护电路，即使在使用较小容量的电容，减小RC时间常数的前提下，仍然能够有效延长静电放电时长，避免静电电流对电子器件的损坏，减小了电容、电阻占用半导体版图的面积，还能有效降低漏电电流。
根据本公开的一个实施例，参考图2，该静电保护电路200被连接在电 源VDD和地VSS之间，其包括：滤波支路20、第一反相器组21、开关晶体管22、钳位晶体管23、反馈晶体管24和第二反相器组25。
其中，滤波支路20包括滤波电阻器201和滤波电容器202。滤波电阻器201和滤波电容器202被串联在电源VDD和地VSS之间，并在两者之间的通路上设置第一节点N1。滤波电阻器201的一端连接至电源VDD，另一端连接至第一节点N1。滤波电容器202的一端连接至地VSS另一端连接至第一节点N1。
第一反相器组21的输入端连接至第一节点N1，第一反相器组21的输出端连接至第二节点N2。
开关晶体管22具有第一端、第二端和第三端。开关晶体管22的第一端连接至第三节点N3，第二端连接至地VSS，第三端即栅极连接至第二节点N2。
钳位晶体管23具有第一端、第二端和第三端.其中，钳位晶体管23的第一端连接至电源VDD，第二端连接至地VSS，第三端即栅极连接至第四节点N4，用于实现静电脉冲分流。
反馈晶体管24具有第一端、第二端和第三端，反馈晶体管24的第一端连接至电源VDD，第二端连接至第三节点N3，第三端即栅极连接至第四节点N4，用于延迟钳位晶体管23的开启时间。
第二反相器组25的输入端连接至第三节点N3，第二反相器组25的输出端连接至第四节点N4。
本实施例中的静电保护电路200还包括第一电阻26，其中，第一电阻26的一端连接至第四节点N4，第一电阻26的另一端连接至地VSS之间，以使钳位晶体管23处于低电位或处于高电位，从而使钳位晶体管23处于关闭状态。
本实施例中的静电保护电路200还包括寄生二极管27，该寄生二极管27的一端连接至电源VDD，另一端连接至地VSS，并与钳位晶体管23并联，用于导通地VSS至电源VDD之间的通路。
在本实施例中，钳位晶体管23为N型晶体管，该钳位晶体管23的第一端是漏极，且连接至电源VDD；其第二端是源极，且连接至地VSS；其第三 端是栅极，且连接至第四节点N4。
反馈晶体管24为P型晶体管，该反馈晶体管24的第一端是源极，且连接至电源VDD；其第二端是漏极，且连接至第三节点N3；其第三端为栅极，且连接至第四节点N4。
开关晶体管22为P型晶体管，该开关晶体管22的第一端是漏极，且连接至第三节点N3；其第二端是源极，且连接至地VSS；其第三端是栅极，且连接至第二节点N2。
其中，当钳位晶体管23选用N型晶体管，反馈晶体管24选用P型晶体管，开关晶体管22选用P型晶体管时，第一反相器组21中包括双数个反相器，比如2个、4个或6个反相器，第二反相器组25中包括单数个反相器，比如1个、3个或5个反相器。本实施例中，以第一反相器组21中包括两个串联设置的反相器，第二反相器组25中包括一个反相器为例进行说明。
第一反相器组21中的两个反相器和第二反相器组25的一个反相器中均包括一个P型晶体管和一个N型晶体管，其中每个反相器中的P型晶体管的栅极和该反相器中的N型晶体管的栅极连接，作为输入端，该P型晶体管的漏极和该N型晶体管的漏极连接，作为输出端。
关于本公开实施例中的静电保护电路200的工作状态，可以分为正常工作和ESD发生两种状态。本实施例中的静电保护电路200中的ESD发生状态包括PS模式和NS模式，其中，PS模式是指当电源VDD浮接，而相对正电压的静电放电ESD在某一输入脚对地VSS放电；NS模式是指当电源VDD浮接，而相对负电压的ESD在某一输入脚对地VSS放电，下面分别以PS模式和NS模式两种模式下的静电放电过程为例进行说明。
当电源启动和正常工作时，第四节点N4通过第一电阻26连接至地VSS，此时第四节点N4处于低电位，钳位晶体管23处于截止状态，静电保护电路关闭。在上述状态下，反馈晶体管24导通，第三节点N3处于高电位，该高电位经过第二反相器组25后，其中，第二反相器组25中的P型晶体管处于截止状态，第二反相器组25中的N型晶体管处于导通状态，从而进一步保证第四节点N4处于低电位，进一步保证钳位晶体管23处于截止状态，并进一步保证关闭静电保护电路200。
当PS模式静电发生时，滤波电阻器201和滤波电容器202所组成的滤波 支路20使第一节点N1处于低电位。第一节点N1的低电位经过第一反相器组21两个反相器的两次相位反转后，从而使第二节点N2处于低电位。此时，开关晶体管22导通，使第三节点N3处于低电位。第三节点N3的低电位经过第二反相器组25中相位反转后，其中，第二反相器组25中的P型晶体管处于导通状态，第二反相器组25中的N型晶体管处于截止状态，从而使第四节点N4处于高电位，钳位晶体管导通开始泄放静电电流。
在静电作用的时间内，当第一节点N1的电位逐渐升高时，经过第一反相器组21的两次相位反转后，将第二节点N2的电位升至高电位，以使开关晶体管22处于截止状态。此时，由于第四节点N4处于高电位，反馈晶体管24处于截止状态，从而使得第三节点N3无法被升至高电位，这样就可以使第三节点N3维持低电位的时间加长，从而保证第四节点N4维持高电位的时间加长，使第四节点N4在静电作用时间内维持低电位的时间加长，以有效保证钳位晶体管23在静电作用时间内导通并泄放静电电流。
当NS模式静电发生时，钳位晶体管23处于导通状态，此时通过与钳位晶体管23并联的寄生二极管27来完成泄放静电电流，经过静电泄放电流通过寄生二极管27，由地VSS流向电源VDD。
本实施例中的静电保护电路，即使在使用较小容量的电容，减小RC时间常数的前提下，仍然能够有效延长静电放电时长，避免静电电流对电子器件的损坏，减小了电容、电阻占用半导体版图的面积，还能有效降低漏电电流。
根据本公开的一个实施例，参考图3，该静电保护电路300被连接在电源VDD和地VSS之间，其包括：滤波支路30、第一反相器组31、开关晶体管32、钳位晶体管33、反馈晶体管34和第二反相器组35。
其中，滤波支路30包括滤波电阻器301和滤波电容器302。滤波电阻器301和滤波电容器302被串联在电源VDD和地VSS之间，并在两者之间的通路上设置第一节点N1，滤波电阻器301的一端连接至电源VDD，另一端连接至第一节点N1，滤波电容器302的一端连接至地VSS另一端连接至第一节点N1。
第一反相器组31的输入端连接至第一节点N1，第一反相器组31的输出 端连接至第二节点N2。
开关晶体管32具有第一端、第二端和第三端。开关晶体管32的第一端连接至第三节点N3，第二端连接至地VSS，第三端即栅极连接至第二节点N2。
钳位晶体管33具有第一端、第二端和第三端，其中，钳位晶体管33的第一端连接至电源VDD，第二端连接至地VSS，第三端即栅极连接至第四节点N4，用于实现静电脉冲分流。
反馈晶体管34具有第一端、第二端和第三端，反馈晶体管34的第一端连接至电源VDD，第二端连接至第三节点N3，第三端即栅极连接至第四节点N4，用于延迟钳位晶体管33的开启时间。
第二反相器组35的输入端连接至第三节点N3，第二反相器组35的输出端连接至第四节点N4。
本实施例中的静电保护电路300还包括第二电阻36，其中，第二电阻36的一端连接至第四节点N4，第二电阻36的另一端连接至电源VDD之间，以使钳位晶体管33处于低电位或处于高电位，从而使钳位晶体管33处于关闭状态。
本实施例中的静电保护电路300还包括寄生二极管37，该寄生二极管37的一端连接至电源VDD，另一端连接至地VSS，并与钳位晶体管33并联，用于导通地VSS至电源VDD之间的通路。
在本实施例中，钳位晶体管33为P型晶体管，该钳位晶体管33的第一端是漏极，且连接至电源VDD，其第二端是源极，且连接至地VSS，其第三端是栅极，且连接至第四节点N4。
反馈晶体管34为N型晶体管，该反馈晶体管34的第一端是源极，且连接至电源VDD；其第二端是漏极，且连接至第三节点N3；其第三端为栅极，且连接至第四节点N4。
开关晶体管32为N型晶体管，该开关晶体管32的第一端是漏极，且连接至第三节点N3；其第二端是源极，且连接至地VSS；其第三端是栅极，且连接至第二节点N2。
其中，当钳位晶体管33选用P型晶体管，反馈晶体管34选用N型晶体管，开关晶体管32选用N型晶体管时，第一反相器组31中包括单数个反相 器，比如1个、3个或5个反相器，第二反相器组35中包括双数个反相器，比如2个、4个或6个反相器。本实施例中，以第一反相器组31中包括一个反相器，第二反相器组35中包括两个串联设置的反相器为例进行说明。
第一反相器组31中的一个反相器和第二反相器组35的两个反相器中均包括一个P型晶体管和一个N型晶体管，其中每个反相器中的P型晶体管的栅极和该反相器中的N型晶体管的栅极连接，作为输入端，该P型晶体管的漏极和该N型晶体管的漏极连接，作为输出端。
关于本公开实施例中的静电保护电路300的工作状态，可以分为正常工作和ESD发生两种状态。本实施例中的静电保护电路300中的ESD发生状态包括PS模式和NS模式，其中，PS模式是指当电源VDD脚浮接，而相对正电压地静电放电ESD在某一输入脚对地VSS放电；NS模式是指当电源VDD脚浮接，而相对负电压的ESD在某一输入脚对地VSS脚放电，下面分别以PS模式和NS模式两种模式下的静电放电过程为例进行说明。。
当电源启动和正常工作时，第四节点N4通过第二电阻36连接至电源VDD，此时第四节点N4处于高电位，钳位晶体管33处于截止状态，静电保护电路关闭。在上述状态下，反馈晶体管34导通，第三节点N3处于高电位，该高电位经过第二反相器组35的两次相位反转后，从而使第四节点N4继续处于高电位，以进一步保证钳位晶体管33处于截止状态，并进一步保证关闭静电保护电路300。
当PS模式静电发生时，滤波电阻器301和滤波电容器302所组成的滤波支路30使第一节点N1处于低电位。第一节点N1的低电位经过第一反相器组31的相位反转后，使第二节点N2处于高电位。此时，开关晶体管32导通，使第三节点N3处于低电位。第三节点N3的低电位经过第二反相器组35中两次相位反转后，从而使第四节点N4处于低电位，钳位晶体管33导通开始泄放静电电流。
在静电作用的时间内，当第一节点N1的电位逐渐升高时，经过第一反相器组31的相位反转后，将第二节点N2的电位降至低电位，以使开关晶体管32处于截止状态。此时，由于第四节点N4处于低电位，反馈晶体管34处于截止状态，从而使得第三节点N3无法被升至高电位，这样就可以使第三节点N3维持低电位的时间加长，从而保证第四节点N4维持低电位的时间 加长。使第四节点N4在静电作用时间内维持低电位的时间加长，以有效保证钳位晶体管33在静电作用时间内导通并泄放静电电流。
当NS模式静电发生时，钳位晶体管33处于导通状态，此时通过与钳位晶体管33并联的寄生二极管37来完成泄放静电电流，经过静电泄放电流通过寄生二极管37，由地VSS流向电源VDD。
本实施例中的静电保护电路，即使在使用较小容量的电容，减小RC时间常数的前提下，仍然能够有效延长静电放电时长，避免静电电流对电子器件的损坏，减小了电容、电阻占用半导体版图的面积，还能有效降低漏电电流。
根据本公开的一个实施例，参考图4，该静电保护电路400被连接在电源VDD和地VSS之间，其包括：滤波支路40、第一反相器组41、开关晶体管42、钳位晶体管43、反馈晶体管44和第二反相器组45。
其中，滤波支路40包括滤波电阻器401和滤波电容器402。滤波电阻器401和滤波电容器402被串联在电源VDD和地VSS之间，并在两者之间的通路上设置第一节点N1。滤波电阻器401的一端连接至电源VDD，另一端连接至第一节点N1。滤波电容器402的一端连接至地VSS另一端连接至第一节点N1。
第一反相器组41的输入端连接至第一节点N1，第一反相器组41的输出端连接至第二节点N2。
开关晶体管42具有第一端、第二端和第三端。开关晶体管42的第一端连接至第三节点N3，第二端连接至地VSS，第三端即栅极连接至第二节点N2。
钳位晶体管43具有第一端、第二端和第三端，其中，钳位晶体管43的第一端连接至电源VDD，第二端连接至地VSS，第三端即栅极连接至第四节点N4，用于实现静电脉冲分流。
反馈晶体管44具有第一端、第二端和第三端，反馈晶体管44的第一端连接至电源VDD，第二端连接至第三节点N3，第三端即栅极连接至第四节点N4，用于延迟钳位晶体管43的开启时间。
第二反相器组45的输入端连接至第三节点N3，第二反相器组45的输出 端连接至第四节点N4。
本实施例中的静电保护电路还包括第二电阻46，其中，第二电阻46的一端连接至第四节点N4，第二电阻46的另一端连接至电源VDD之间，以使钳位晶体管43处于低电位或处于高电位，从而使钳位晶体管43处于关闭状态。
本实施例中的静电保护电路还包括寄生二极管47，该寄生二极管47的一端连接至电源VDD，另一端连接至地VSS，并与钳位晶体管43并联，用于导通地VSS至电源VDD之间的通路。
在本实施例中，钳位晶体管43为P型晶体管，该钳位晶体管43的第一端是漏极，且连接至电源VDD；其第二端是源极，且连接至地VSS；其第三端是栅极，且连接至第四节点N4。
反馈晶体管44为N型晶体管，该反馈晶体管44的第一端是源极，且连接至电源VDD；其第二端是漏极，且连接至第三节点N3；其第三端为栅极，且连接至第四节点N4。
开关晶体管42为P型晶体管，该开关晶体管42的第一端是漏极，且连接至第三节点N3，其第二端是源极，且连接至地VSS，其第三端是栅极，且连接至第二节点N2。
其中，当钳位晶体管43选用P型晶体管，反馈晶体管44选用N型晶体管，开关晶体管42选用P型晶体管时，第一反相器组41中包括双数个反相器，第二反相器组45中包括双数个反相器，，比如2个、4个或6个反相器。本实施例中，以第一反相器组41中包括两个串联设置的反相器，第二反相器组45中包括两个串联设置的反相器为例进行说明。
第一反相器组41中的两个反相器和第二反相器组45的两个反相器中均包括一个P型晶体管和一个N型晶体管，其中每个反相器中的P型晶体管的栅极和该反相器中的N型晶体管的栅极连接，作为输入端，该P型晶体管的漏极和该N型晶体管的漏极连接，作为输出端。
关于本公开实施例中的静电保护电路400的工作状态，可以分为正常工作和ESD发生两种状态。本实施例中的静电保护电路200中的ESD发生状态包括PS模式和NS模式，其中，PS模式是指当电源VDD浮接，而相对正电压的静电放电ESD在某一输入脚对地VSS放电；NS模式是指当电源VDD 浮接，而相对负电压的ESD在某一输入脚对地VSS脚放电，下面分别以PS模式和NS模式两种模式下的静电放电过程为例进行说明。
当电源启动和正常工作时，第四节点N4通过第二电阻46连接至电源VDD，此时第四节点N4处于高电位，钳位晶体管43处于截止状态，静电保护电路关闭。在上述状态下，反馈晶体管44导通，第三节点N3处于高电位，该高电位经过第二反相器组45的两次相位反转后，从而使第四节点N4继续处于高电位，以进一步保证钳位晶体管43处于截止状态，并进一步保证关闭静电保护电路400。
当PS模式静电发生时，滤波电阻器401和滤波电容器402所组成的滤波支路40使第一节点N1处于低电位。第一节点N1的低电位经过第一反相器组41的两次相位反转后，使第二节点N2处于低电位。此时，开关晶体管42导通，使第三节点N3处于低电位。第三节点N3的低电位经过第二反相器组45中两次相位反转后，从而使第四节点N4处于低电位，钳位晶体管43导通开始泄放静电电流。
在静电作用的时间内，当第一节点N1的电位逐渐升高时，经过第一反相器组41的两次相位反转后，将第二节点N2的电位升至高电位，使开关晶体管42处于截止状态。此时，由于第四节点N4处于低电位，反馈晶体管44处于截止状态，从而使得第三节点N3无法被升至高电位，这样就可以使第三节点N3维持低电位的时间加长，从而保证第四节点N4维持低电位的时间加长，使第四节点N4在静电作用时间内维持低电位的时间加长，以有效保证钳位晶体管43在静电作用时间内导通并泄放静电电流。
当NS模式静电发生时，钳位晶体管43处于导通状态，此时通过与钳位晶体管43串联的寄生二极管47来完成泄放静电电流，经过静电泄放电流通过寄生二极管47，由地VSS流向电源VDD。
本实施例中的静电保护电路，即使在使用较小容量的电容，减小RC时间常数的前提下，仍然能够有效延长静电放电时长，避免静电电流对电子器件的损坏，减小了电容、电阻占用半导体版图的面积，还能有效降低漏电电流。
根据本公开的又一个方面，提供一种芯片，该芯片的一或多个管脚电连接上述实施例的静电保护电路。
本公开的静电保护电路中，通过在第三节点和第四节点之间设置反馈晶体管，以控制并延长静电保护电路在静电作用时的开启时间，从而可使用较小的电容，而采用较小的电容能有效解决大电容所导致的较大漏电电流的问题。且采用较小的电容可减小RC时间常数，从而使总体版图布局面积减小，提高了静电保护电路的性能。同时，本公开的静电保护电路实现了对PS模式和NS模式的静电保护，有效提高了半导体元件产品的静电保护能力，且该静电保护电路不会对芯片的性能和正常功能产生影响，有效提高了半导体元件产品的可靠性和竞争力。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的静电保护电路及芯片，通过在第三节点和第四节点设置反馈晶体管，延迟钳位晶体管的开启时间，有效延长了钳位晶体管的静电脉冲分流时间，减小RC时间常数和布局面积，提高了静电保护电路的性 能，从而解决了电容值较大导致较大漏电电流的问题，以及较大的RC时间常数增加布局面积的问题，提高了对产品的静电保护能力。

Claims (15)

  1. 一种静电保护电路，其被连接在电源VDD和地VSS之间，包括：
    滤波支路，其包括第一节点；
    第一反相器组，其输入端与所述第一节点连接，其输出端与第二节点连接；
    开关晶体管，其被连接在第三节点与所述地VSS之间，其栅极与所述第二节点连接；
    钳位晶体管，其栅极与第四节点连接，用于静电脉冲分流；
    反馈晶体管，其被连接在所述电源VDD和所述第三节点之间，其栅极与第四节点连接，用于延迟所述钳位晶体管的开启时间；
    第二反相器组，其输入端与所述第三节点连接，其输出端与所述第四节点连接。
  2. 根据权利要求1所述的静电保护电路，其中，所述钳位晶体管为N型晶体管；
    所述反馈晶体管为P型晶体管；
    所述开关晶体管为N型晶体管。
  3. 根据权利要求2所述的静电保护电路，其中，所述第一反相器组包括单数个反相器；
    所述第二反相器组包括单数个反相器。
  4. 根据权利要求1所述的静电保护电路，其中，所述钳位晶体管为N型晶体管；
    所述反馈晶体管为P型晶体管；
    所述开关晶体管为P型晶体管。
  5. 根据权利要求4所述的静电保护电路，其中，所述第一反相器组包括双数个反相器；
    所述第二反相器组包括单数个反相器。
  6. 根据权利要求2至5任一项所述的静电保护电路，其中，所述静电保护电路还包括第一电阻，其被连接在所述第四节点与所述地VSS之间。
  7. 根据权利要求1所述的静电保护电路，其中，所述钳位晶体管为P型晶体管；
    所述反馈晶体管为N型晶体管；
    所述开关晶体管为N型晶体管。
  8. 根据权利要求7所述的静电保护电路，其中，所述第一反相器组包括单数个反相器；
    所述第二反相器组包括双数个反相器。
  9. 根据权利要求1所述的静电保护电路，其中，所述钳位晶体管为P型晶体管；
    所述反馈晶体管为N型晶体管；
    所述开关晶体管为P型晶体管。
  10. 根据权利要求9所述的静电保护电路，其中，所述第一反相器组包括双数个反相器；
    所述第二反相器组包括双数个反相器。
  11. 根据权利要求7至10任一项所述的静电保护电路，其中，所述静电保护电路还包括第二电阻，其被连接在所述第四节点与所述电源VDD之间。
  12. 根据权利要求1所述的静电保护电路，其中，所述静电保护电路还包括寄生二极管，其被连接在所述电源VDD和所述地VSS之间，所述寄生二极管用于导通所述地VSS至所述电源VDD之间的通路。
  13. 根据权利要求1所述的静电保护电路，其中，所述滤波支路包括：
    滤波电阻器，其被连接在所述电源VDD和所述第一节点之间；
    滤波电容器，其被连接在所述地VSS和所述第一节点之间。
  14. 根据权利要求1所述的静电保护电路，其中，所述第一反相器组或所述第二反相器组中的反相器包括：
    一个P型晶体管；
    一个N型晶体管，与所述P型晶体管串联连接；
    所述P型晶体管的栅极和所述N型晶体管的栅极连接，作为输入端；
    所述P型晶体管的漏极和所述N型晶体管的漏极连接，作为输出端。
  15. 一种芯片，所述芯片的一个或多个管脚电连接如权利要求1-14任一项所述的静电保护电路。
PCT/CN2021/113406 2021-07-08 2021-08-19 静电保护电路及芯片 WO2023279486A1 (zh)

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CN102801146A (zh) * 2012-08-24 2012-11-28 北京大学 电源钳位esd保护电路
CN104362606A (zh) * 2014-11-20 2015-02-18 辽宁大学 用于集成电路的静电放电电源钳制电路及其控制方法
CN105098743A (zh) * 2014-05-04 2015-11-25 中芯国际集成电路制造(上海)有限公司 动态静电放电钳位电路
US20190006841A1 (en) * 2017-06-29 2019-01-03 Dialog Semiconductor (Uk) Limited Compact, High Performance, and Robust RC Triggered ESD Clamp
CN110445114A (zh) * 2019-09-06 2019-11-12 深圳讯达微电子科技有限公司 一种允许快速上电的多重rc钳位esd保护电路

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102801146A (zh) * 2012-08-24 2012-11-28 北京大学 电源钳位esd保护电路
CN105098743A (zh) * 2014-05-04 2015-11-25 中芯国际集成电路制造(上海)有限公司 动态静电放电钳位电路
CN104362606A (zh) * 2014-11-20 2015-02-18 辽宁大学 用于集成电路的静电放电电源钳制电路及其控制方法
US20190006841A1 (en) * 2017-06-29 2019-01-03 Dialog Semiconductor (Uk) Limited Compact, High Performance, and Robust RC Triggered ESD Clamp
CN110445114A (zh) * 2019-09-06 2019-11-12 深圳讯达微电子科技有限公司 一种允许快速上电的多重rc钳位esd保护电路

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