WO2023279419A1 - 存储器及其制造方法 - Google Patents

存储器及其制造方法 Download PDF

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Publication number
WO2023279419A1
WO2023279419A1 PCT/CN2021/106510 CN2021106510W WO2023279419A1 WO 2023279419 A1 WO2023279419 A1 WO 2023279419A1 CN 2021106510 W CN2021106510 W CN 2021106510W WO 2023279419 A1 WO2023279419 A1 WO 2023279419A1
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Prior art keywords
transistor
layer
substrate
gate
transistors
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PCT/CN2021/106510
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English (en)
French (fr)
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张魁
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长鑫存储技术有限公司
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Priority to US17/448,884 priority Critical patent/US20230005913A1/en
Publication of WO2023279419A1 publication Critical patent/WO2023279419A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench

Definitions

  • Embodiments of the present application relate to but are not limited to a memory and a manufacturing method thereof.
  • DRAM Dynamic Random Access Memory
  • a common DRAM unit consists of a transistor (Transistor) and a capacitor (Capacitor) to form a 1TlC structure, and the logic state is distinguished by whether the charge is stored on the capacitor.
  • Transistor Transistor
  • Capacitor Capacitor
  • embodiments of the present application provide a memory and a manufacturing method thereof.
  • the memory includes:
  • a transistor array comprising a plurality of transistors on the surface of the substrate; conduction channels of the transistors extend in a direction perpendicular to the surface of the substrate;
  • Storage layer is located on one side of the conduction channel of each transistor, and communicates with the conduction channel of the transistor, and is used for storing charges and performing charge transfer with the conduction channels connected .
  • the manufacturing method of the memory includes:
  • a transistor array comprising a plurality of transistors is formed on the surface of the substrate; wherein the conduction channels of the transistors extend in a direction perpendicular to the surface of the substrate;
  • a storage layer is formed on the side of each transistor in a direction perpendicular to the surface of the substrate; the storage layer communicates with the transistors and is used for storing charges and transferring charges to the conductive channels connected thereto.
  • FIG. 1 is a first structural schematic diagram of a memory according to an embodiment of the present application
  • FIG. 2 is a second structural schematic diagram of a memory according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram III of a memory according to an embodiment of the present application.
  • FIG. 4 is a structural schematic diagram 4 of a memory according to an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a method for manufacturing a memory according to an embodiment of the present application.
  • FIG. 6A is a schematic diagram of substrate doping in a memory manufacturing method according to an embodiment of the present application.
  • FIG. 6B is a schematic diagram of forming a conductive channel by etching in a method for fabricating a memory according to an embodiment of the present application
  • FIG. 7 is a schematic diagram of forming a source electrode in a manufacturing method of a memory according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a memory according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a substrate of a memory according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of forming a conductive channel in a memory according to an embodiment of the present application.
  • FIG. 11 is a first schematic diagram of forming a transistor source in a memory according to an embodiment of the present application.
  • FIG. 12 is a second schematic diagram of forming a transistor source in a memory according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of isolation between transistors in a memory according to an embodiment of the present application.
  • FIG. 14 is a schematic diagram of a groove for accommodating a storage layer formed in a memory according to an embodiment of the present application.
  • FIG. 15 is a schematic diagram of forming a storage layer in a memory according to an embodiment of the present application.
  • 16 is a schematic diagram of an insulating layer forming an isolation storage layer in a memory according to an embodiment of the present application.
  • FIG. 17 is a schematic diagram of forming a trench for accommodating a gate in a memory according to an embodiment of the present application.
  • FIG. 18 is a schematic diagram of forming a gate of a transistor in a memory according to an embodiment of the present application.
  • FIG. 19 is a schematic diagram of forming a drain of a transistor in a memory according to an embodiment of the present application.
  • FIG. 20 is a schematic diagram of forming bit lines in a memory according to an embodiment of the present application.
  • DRAM digital versatile memory
  • a common DRAM uses a capacitor to store charges, and the value of a binary bit (bit) is represented by the amount of charge stored, that is, a storage unit can be used to represent a logic state of a bit. Due to phenomena such as leakage current in the transistor, the stored charge is prone to loss, thereby affecting the stability of data storage. Therefore, DRAM needs to be periodically charged and discharged, and the stored data is refreshed to realize dynamic storage.
  • the embodiment of the present application provides a memory, which uses a storage layer connected to the conductive channel of the transistor to realize charge transfer and storage, thereby eliminating the need for capacitors, realizing a 1T0C memory cell structure, and effectively reducing the size of the memory.
  • the memory 100 includes:
  • a transistor array comprising a plurality of transistors 120 on the surface of the substrate 110; the conductive channel 121 of the transistor 120 extends in a direction perpendicular to the surface of the substrate 110;
  • Storage layer 130 the storage layer 130 is located on one side of the conduction channel 121 of each transistor 120, and communicates with the conduction channel 121 of the transistor 120, for storing charges and communicating with the Conductive channels for charge transfer.
  • the substrate may be a semiconductor substrate made of silicon material or other wafer materials.
  • the device structure of the memory can be formed on the surface of the substrate through various semiconductor device processes. For example, through various processes such as doping, photolithography, deposition, and cleaning, a layered patterned structure to form a semiconductor device.
  • a plurality of transistors are formed on the surface of the substrate, and the transistors are arranged in pairs on the surface of the substrate. Multiple pairs of transistors can be arranged in rows and columns to form a transistor array to form a memory.
  • the conduction channel of the transistor extends along a direction perpendicular to the surface of the substrate, which can occupy less surface area of the substrate than transistors formed parallel to the surface of the substrate, thereby improving the utilization rate of the substrate area.
  • charge storage is realized through the storage layer connected to the conductive channel of each transistor, and the storage layer can transfer charge with the conductive channel to realize the change of the logic state of the storage unit.
  • the storage layer can be a semiconductor material or a metal material, and can be used to store electrons or holes.
  • the storage layer is connected to the conductive channel. When a voltage is applied to the transistor, charge accumulation occurs in the conductive channel and forms a potential difference with the storage layer, thereby transferring charges to the storage layer and changing the amount of charge in the storage layer. In this way, charge transfer between the storage layer and the conduction channel can be realized by controlling the transistor, and charges can be stored in the storage layer.
  • the storage layer is distributed on the side of each transistor and communicated with the conduction channel of the transistor, and the storage layer also extends along the direction perpendicular to the substrate surface, so it occupies a small surface area of the substrate.
  • the above-mentioned memory structure of the embodiment of the present application not only saves the manufacturing space required for the capacitor structure in the memory, but also adopts the verticalization method in the form to further save the occupation of the surface area of the substrate, effectively increasing the memory unit per unit area quantity.
  • the embodiment of the present application also realizes charge storage through the storage layer, which replaces the function of the original capacitor and realizes a 1T0C storage unit structure, which is beneficial to the development of small size and high integration of the memory.
  • the source 122 of the transistor 120 is located at one end of the conductive channel 121 close to the surface of the substrate 110 ;
  • the drain 123 of the transistor 120 is located at an end of the conductive channel 121 away from the surface of the substrate 110 .
  • the transistor includes a source, a gate, and a drain.
  • the voltage control of the gate and the voltage difference between the source and the drain realize the state switching of the charge on or off between the source and the drain.
  • the direction in which the conduction channel of the transistor extends is perpendicular to the surface of the substrate. Therefore, the source and drain of the transistor are located at both ends of the conduction channel, that is, the end close to the surface of the substrate and the end far away from the surface of the substrate. one end of the substrate surface.
  • the structure of the transistor can effectively utilize the height space above the substrate and save the surface area of the substrate surface, so that more storage units can be integrated per unit area of the substrate surface, improving the storage efficiency of the memory.
  • the source of the transistor is covered with a first insulating layer; the height of the first insulating layer relative to the surface of the substrate is higher than the height of the source relative to the surface of the substrate high.
  • the source of the transistor can be covered by a first insulating layer, so as to protect and isolate the source from the storage layer.
  • the first insulating layer can be evenly distributed on the substrate surface with a certain thickness, the first insulating layer of this thickness can completely cover the source of the transistor, and the height of the first insulating layer relative to the substrate surface is higher than that of the source relative to the substrate. The height of the bottom surface.
  • the material of the first insulating layer may be materials such as silicon oxide and silicon nitride, or may be organic materials or the like.
  • the side of the transistor connected to the storage layer has a second insulating layer, the second insulating layer covers the storage layer, and the second insulating layer communicates with the first insulating layer .
  • each transistor can be isolated from each other by the second insulating layer, and the second insulating layer can extend from the position where the first insulating layer is located, that is, the bottom of the conductive channel of the transistor to the bottom of the conductive channel. top.
  • the second insulating layer is isolated from the first insulating layer, and the storage layer is also isolated from other transistors and other storage layers through the insulating layer.
  • the first insulating layer covers the source of the transistor, and the first insulating layer communicates with the second insulating layer, an integral insulating layer can be formed, so that the source of the transistor and the storage layer are isolated from each other and protected by the insulating layer. covered, thereby reducing charge movement between the source and the storage layer, and facilitating the storage layer to store charges stably.
  • first insulating layer and the second insulating layer may be made of the same material or different materials.
  • the memory further includes:
  • At least one bit line 140 is located on a side of the transistor 120 away from the surface of the substrate 110 and connected to the drain 123 of the transistor 120 .
  • a plurality of transistors of the memory can be arranged to form a transistor array in a row and column structure, and each column of transistors can be connected through a bit line, so as to facilitate the control of reading and writing data of the entire column of transistors through the bit line.
  • the bit line can be a linear thin film made of conductive material, connected to the drain of the transistor, and capable of generating charge transfer with the drain of the transistor.
  • the potential level of the bit line determines the state of the transistor for reading and writing data. Therefore, a voltage can be applied to the bit line of the memory through an external circuit, thereby changing the potential level of the bit line.
  • the bit line is connected to drains of transistors in the same column in the transistor array.
  • one bit line may cover multiple transistors, that is, transistors in the same column of the transistor array are controlled by the same bit line. In this way, through the cooperation of the bit line and the word line in the memory, precise control of each transistor is realized.
  • the gate 124 of the transistor 120 is located on the opposite side of the storage layer 130 communicating with the conductive channel 121 , and the conductive channel 121 of the transistor 120 Located between the gate 124 and the storage layer 130 . Since the conduction channel of the transistor in the embodiment of the present application extends along a direction perpendicular to the substrate surface, the charge flow between the source and drain of the transistor is also along the direction along which the conduction channel extends.
  • the gate of the transistor controls the conduction performance of the conduction channel from one side of the conduction channel, and the gate of the transistor is located on the side of the conduction channel and is parallel to the conduction channel.
  • the storage layer corresponding to the transistor communicates with one side of the conductive channel of the transistor, so the gate of the transistor is located on the other side of the conductive channel, which is opposite to the side where the storage layer is located, so that the conductive channel of the transistor is located on the other side of the conductive channel. between the gate and the storage layer.
  • the gate includes:
  • Gate oxide layer and gate conductive layer
  • the gate oxide layer is located between the gate conductive layer and the conductive channel;
  • the gate oxide layer wraps the gate conductive layer and is connected to the conductive channel.
  • the conductivity of the conductive channel can be controlled by the field effect generated between the potential of the gate conductive layer and the conductive channel. That is to say, the on or off state of the conductive channel can be switched by the voltage applied to the gate conductive layer.
  • the gate oxide layer and the gate conductive layer may form a two-layer structure parallel to the conductive channel, and the outer side of the gate conductive layer may be isolated by an insulating material, so as to be independent from the gates of adjacent transistors.
  • the gate oxide layer can also wrap the gate conductive layer, so that the inner side and the outer side of the gate conductive layer are separated by the gate oxide layer.
  • the memory also includes:
  • the gate protection layer covers the side of the gate away from the surface of the substrate.
  • the gate protection layer overlies the gate and may be flush with the drain of the transistor, thereby isolating the gate from the drain and the gate from other structures on top of the transistor, such as bit lines.
  • the gate protection layer may be made of oxide or insulating materials such as silicon nitride.
  • the gate protection layer can also be a thin film of the same material as the gate oxide layer, and communicate with the gate oxide layer, so as to protect and isolate the gate conductive layer.
  • gates of the transistors in the same row in the transistor array are connected; wherein the connected gates are word lines of the transistors in the same row.
  • the gates of the transistors are shared by multiple transistors, that is to say, the gates cover the conduction channels of the multiple transistors from the sides in the shape of strips.
  • the transistors in the same row are controlled by the same gate, and this gate also constitutes the word line of the transistors in this row.
  • the word line and the bit line of the transistor array form a structure in which rows and columns are controlled separately, so that precise read and write control for each transistor can be realized.
  • the embodiment of the present application also provides a method for manufacturing a memory, as shown in FIG. 5 , the method includes:
  • Step S101 forming a transistor array including a plurality of transistors on the surface of the substrate; wherein, the conduction channels of the transistors extend in a direction perpendicular to the surface of the substrate;
  • Step S102 forming a storage layer on the side of each transistor in a direction perpendicular to the surface of the substrate; the storage layer is connected to the transistors for storing charges and conducting charge transfer with the conductive channels connected thereto.
  • forming a plurality of transistors on the surface of the substrate may be synchronously forming a transistor array forming a row-column structure on the surface of the substrate.
  • treatments such as doping and ion implantation may be performed on a certain thickness of the substrate surface so that a certain thickness of the substrate has stronger conductivity.
  • the doped semiconductor layer on the surface of the substrate is shown in FIG. 6A , and the upper layer of the substrate 110 is the processed semiconductor layer, which may be referred to as the active layer 111 here.
  • a plurality of conductive channels distributed in rows and columns may be formed by processes such as photolithography.
  • the process of forming the conductive channel 121 may include: covering the surface of the active layer with a mask layer 610, and then removing part of the semiconductor material of the active layer through patterned illumination, etching and other processes, The remaining part is the conduction channel 121 of a plurality of transistors.
  • the bottom of the remaining substrate is the substrate of the memory, which is used as a carrier of the transistor array, and is also used to provide ground potential and connect to the source or drain of the transistor.
  • structures such as the source, the gate and the drain of the transistor can also be formed at adjacent positions of the conduction channel of the transistor to form a transistor array of the memory.
  • the formed conductive channel extends vertically relative to the surface of the substrate, thus occupying a very small surface area of the substrate and improving the integration of the memory.
  • a storage layer can be formed correspondingly, and the storage layer can be connected to the conductive channel of the transistor. Therefore, the semiconductor material or metal material used for the storage layer can be covered on the side of the conductive channel of the transistor to form a thin film.
  • the formation of the storage layer on the side of each of the transistors in a direction perpendicular to the surface of the substrate includes:
  • each conductive channel stands vertically on the bottom layer of the substrate. Grooves are formed between them. Therefore, a memory layer can be formed in the trench on one side of the conductive channel of each transistor and cover the side surface of the conductive channel.
  • semiconductor materials or metal materials including single crystal silicon (Si), germanium (Ge), silicon germanium (Si-Ge), aluminum antimony (Al-Sb) or gallium antimony (Ga-Sb) and other materials are deposited in the trenches, including physical vapor deposition (PVD, Physical Vapor Deposition) and chemical vapor deposition (CVD, Chemical Vapor Deposition), so that one side of the conductive channel of the transistor is covered with the above-mentioned semiconductor material or metal material form the storage layer.
  • PVD Physical Vapor Deposition
  • CVD Chemical Vapor Deposition
  • forming a transistor array comprising a plurality of transistors on the surface of the substrate includes:
  • a plurality of drains of the transistors are formed at one end of the conductive channel away from the surface of the substrate.
  • the transistor includes a source, a gate, and a drain.
  • the voltage control of the gate and the voltage difference between the source and the drain realize the state switching of the charge on or off between the source and the drain.
  • the direction in which the conduction channel of the transistor extends is perpendicular to the surface of the substrate. Therefore, the source and drain of the transistor are located at both ends of the conduction channel, that is, the end close to the surface of the substrate and the end far away from the surface of the substrate. one end of the substrate surface.
  • the source of the transistor can be formed at the end of the conductive channel close to the substrate surface. At this time, the source is connected to the substrate, so the source can pass through the substrate. grounded. The drain of the transistor can then be formed at the end of the conductive channel away from the substrate surface, so that the charge transfer of the transistor follows the conductive path formed from the source to the drain through the conductive channel.
  • the order of forming structures such as the source, drain, gate, and storage layer of the conductive channel is not limited here, and the source, drain, and gate of the above-mentioned conductive channel can be formed first, and then the storage layer can be formed , it is also possible to form the storage layer after forming the source of the conductive channel, and then form the drain, the gate and so on.
  • the above formation sequence can be comprehensively considered according to the production plan, the shape of each layer of photomask, the characteristics of each layer of material, and the equipment parameter requirements of the process.
  • forming a conductive channel perpendicular to the substrate surface on the substrate surface includes:
  • the substrate can be a semiconductor substrate made of silicon material or other wafer materials.
  • the surface layer of the substrate can be doped with a certain thickness of semiconductor material, which can be N-type doped or P-type doped. miscellaneous.
  • doping or ion implantation with trivalent or pentavalent ions such as phosphorus ions or boron ions makes the surface layer of the substrate form a P-type semiconductor or an N-type semiconductor. The purpose of this is to improve the conductivity of the semiconductor material so that it can form the conductive channel of the transistor.
  • the patterned etching is performed to remove the semiconductor material other than the position where the conductive channel needs to be formed, and the above-mentioned conductive channel is formed by retaining part of the semiconductor material.
  • the pattern retained by the patterned etching is the shape of the conductive channel, which can be a square column with a cross section, a rectangular column with a cross section, a diamond-shaped column with a cross section, or a circular cross section.
  • the pillars, these pillars constitute the conductive channel of the transistor.
  • forming the source 122 of the transistor 120 at one end of the conductive channel 121 close to the surface of the substrate 110 includes:
  • the heavily doped dielectric layer 710 is activated at high temperature, and the source electrode 122 is formed at the end of the conductive channel 121 close to the surface of the substrate 110 .
  • the heavily doped medium layer can be a semiconductor material containing dopant ions opposite in polarity to the conduction channel, for example, if the conduction channel is N-type doped, then the heavily doped medium layer is P-type doped; the conduction channel If the channel is P-type doped, then the heavily doped dielectric layer is N-type doped.
  • the conductive ions in the heavily doped dielectric layer are activated and transferred into the conductive channel, so that the conductive channel is re-implanted with ions of opposite polarity at the end close to the substrate surface, thereby forming the source of the transistor .
  • the heavily doped dielectric layer After being activated at high temperature and forming a source at the bottom of the conductive channel, the heavily doped dielectric layer can be removed by etching. In order to prevent the residual heavily doped dielectric layer material on the substrate surface, a part of the substrate can be over-etched during the etching process, so that part of the source of the transistor is embedded in the substrate, and a part is exposed on the substrate. above.
  • forming the drain of the transistor at an end of the conductive channel away from the surface of the substrate includes:
  • Ion implantation or doping is performed on the single crystal silicon layer to form the drain.
  • the method also includes:
  • a first insulating layer is formed around the source of the transistor; wherein a height of the first insulating layer relative to the substrate surface is higher than a height of the source relative to the substrate surface.
  • a storage layer corresponding to the transistor may be further formed on the side of the conduction channel of the transistor.
  • the storage layer and the source cannot communicate with each other. Therefore, the source of the transistor can be isolated and protected by forming a first insulating layer covering the source, and then the storage layer corresponding to the transistor can be formed.
  • the material of the first oxide layer may be an insulating thin film formed of silicon oxide, silicon nitride or other organic materials.
  • the method also includes:
  • a second insulating layer is formed on a side where the transistor is communicated with the storage layer; wherein, the second insulating layer covers the storage layer and the second insulating layer communicates with the first insulating layer.
  • a second insulating layer may be formed between the transistors, and the second insulating layer is communicated with the first insulating layer.
  • the second insulating layer can wrap the storage layer and the transistor to prevent charge leakage and improve storage performance.
  • Materials of the second insulating layer and the first insulating layer may be the same or different.
  • the process of forming the second insulating layer may be to deposit an insulating material to fill up the trenches between the transistors, so as to achieve the function of isolating the storage layers of the transistors.
  • the method also includes:
  • At least one bit line is formed on the side of the transistor away from the surface of the substrate; wherein the bit line is connected to the drain of the transistor.
  • the above-mentioned second oxide layer is filled in the trenches between the transistors so that the end of the transistor away from the substrate surface is in an approximate plane.
  • the uppermost layer can be coated with metal materials
  • the conductive layer is formed by semiconductor materials or other materials with strong electrical conductivity.
  • bit line is connected to the drain of the transistor so that charge transfer can be performed.
  • forming a transistor array including a plurality of transistors on the surface of the substrate further includes:
  • the gate of the transistor is formed on the other side of the conduction channel opposite to the side connected with the storage layer; wherein the conduction channel of the transistor is located between the gate and the storage layer.
  • the gate of the transistor can be formed on the side of the conductive channel of the transistor opposite to the side where the storage layer is formed. Therefore, the process of forming the gate can be before or after forming the storage layer.
  • each transistor and the corresponding storage layer have the same structure and are neatly arranged on the surface of the substrate to form an array structure of storage cells.
  • forming the gate of the transistor on the other side of the conductive channel opposite to the side connected to the storage layer includes:
  • a gate conductive layer connected to the gate oxide layer is formed on one side of the gate oxide layer; wherein the gate gate oxide layer is located between the gate conductive layer and the conductive channel; Or the gate oxide layer wraps the gate conductive layer and is connected to the conductive channel.
  • the gate of the transistor includes a gate oxide layer and a gate conductive layer.
  • the gate oxide layer can be formed first on one side of the transistor conductive channel, and then the gate conductive layer is formed; the gate oxide layer can also be formed first, and then The intermediate etching of the gate oxide layer forms a trench, and then a gate conductive layer is formed in the trench, so that the gate conductive layer is wrapped by the gate oxide layer.
  • the method also includes:
  • a gate protection layer covering the gate is formed at an end of the gate away from the surface of the substrate.
  • an insulating gate protective layer may be covered above the gate.
  • the gate protection layer may be made of oxide or insulating materials such as silicon nitride.
  • the gate protection layer can also be a thin film of the same material as the gate oxide layer, and communicate with the gate oxide layer, thereby protecting and isolating the gate conductive layer.
  • forming the gate of the transistor on the other side of the conductive channel opposite to the side connected to the storage layer includes:
  • the gate connected to the same row of transistors is formed in the trench; wherein the gate is a word line of the same row of transistors.
  • a through trench may be formed on the other side of the conductive channel of the transistor relative to the storage layer, so as to form a common gate of a row of transistors. In this way, the gates shared by the transistors in this row become the corresponding word lines.
  • the embodiment of the present application provides a schematic diagram of a memory, that is, a DRAM with a vertical channel and non-capacitive structure, that is, a 1T0C DRAM.
  • the conduction channel 811 of the transistor is perpendicular to the substrate 810 surface, and the source electrode 812 is positioned at one end near the substrate 810 surface; the drain electrode 813 is positioned at the substrate 810 surface away from one end.
  • One side of each transistor has a memory layer 814 in communication with the conduction channel 811 of the transistor.
  • the gate 815 of the transistor is located on the opposite outer side of the transistor.
  • Each transistor is filled with insulating material to isolate each other. Since no capacitor is needed, the size of each memory cell (transistor and its corresponding memory layer) can be reduced to 2F2, (F is the minimum size of the memory cell, and F2 represents the unit area). At the same time, since the conductive channel 811 is in Extending in a direction perpendicular to the surface of the substrate 810 , the length of the conductive channel 811 can be increased without occupying too much surface area of the substrate 810 .
  • the top view of the memory is shown in part (2) of FIG. 8 , the top of each transistor is covered with a conductive material and connects the entire row of transistors, thereby forming a bit line 821 .
  • the gate of the transistor runs through the entire row of transistors to form a word line.
  • the gate is not shown in part (2) of the top view in FIG.
  • the section corresponding to part (1) of the sectional view in FIG. 8 is located at the line 80 corresponding to part (2) of the top view.
  • the method for forming the above structure comprises the steps:
  • Step 1 As shown in FIG. 9 , perform P-type or N-type doping to a certain thickness on the silicon substrate 900 to form an active layer 910 ;
  • Step 2 cover the active layer 910 with the mask layer 920 and perform patterned etching to remove the active layer other than the conductive channel, and the remaining semiconductor structure is the conductive channel 911 .
  • the conductive channel 911 can be in different shapes such as square and rhombus.
  • the above-mentioned mask layer 920 may be silicon nitride.
  • part (1) in FIG. 10 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • Step 3 As shown in FIG. 11 , a heavily doped dielectric layer 930 is deposited in the gap between the conductive channels on the surface of the substrate, and the dopant ions are of the opposite type to the active region.
  • part (1) in FIG. 11 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • Step 4 As shown in FIG. 12 , after depositing the heavily doped dielectric layer, activate it at high temperature to form the source 912 or drain at the bottom of the active region, that is, the bottom of the conductive channel 911 , and then remove the heavily doped dielectric layer by etching .
  • a part of the substrate may be over-etched.
  • part (1) in FIG. 12 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • Step 5 deposit an oxide layer 940 on the surface of the substrate, the surface of the oxide layer 940 may be slightly higher than the surface of the source 912, effectively isolating the source.
  • An insulating dielectric 950 may then be filled over the oxide layer 940 .
  • the material of the insulating dielectric layer 950 may be an inorganic material such as silicon oxide or silicon nitride, or an organic insulating material.
  • part (1) in FIG. 13 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • Step 6 pattern etching is performed to form a trench 951 or a hole structure in the insulating medium 950 on one side of the active region to leak out the conductive channel 911 of the transistor.
  • the above-mentioned oxide layer 940 is used as an etching stop layer to prevent the etching from leaking out of the source.
  • part (1) in FIG. 14 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • Step 7 as shown in FIG. 15 , at least one of a semiconductor material layer or a metal material layer is formed in the trench 951 .
  • the semiconductor layer can be a Si layer, and the semiconductor material can include at least one of Ge, Si-Ge, Al-Sb and Ga-Sb, the valence band of the semiconductor material layer is higher than the active region, and there can also be quantum dots in the semiconductor , used to store electrons, that is, to form a storage layer 960 connected to the conductive channel 911 .
  • part (1) in FIG. 15 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • Step 8 as shown in FIG. 16 , fill the trench 951 with an oxide layer 941 so that the oxide layer 940 communicates with the oxide layer 941 and wraps the storage layer 960 corresponding to the transistor.
  • part (1) in FIG. 16 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • Step 9 as shown in FIG. 17 , patterned etching opens the trench 970 in the isolation layer on the other side of the conductive channel 911 to expose the active region, and uses the oxide layer 940 as an etching stop layer to prevent the trench from exposing the source pole.
  • part (1) in FIG. 17 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • Step 10 deposit a gate oxide layer 971 and a gate metal layer 972 in the trench 970 and etch back to the level of the active region, and fill the gate protection layer 973 .
  • part (1) in FIG. 18 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • Step 11 as shown in FIG. 19 , remove the conductive channel 911 , that is, the mask layer on the top of the active layer, and epitaxially grow a single crystal silicon layer, and then ion implant or doping to form a transistor drain 913 .
  • part (1) in FIG. 19 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • Step 12 as shown in FIG. 20 , a conductive layer is formed on the top of the transistor structure, and then a bit line 980 connected to the drain 913 is formed by patterned etching.
  • part (1) in FIG. 20 is a cross-sectional view
  • part (2) is a top view, wherein the black line 90 indicates the cross-sectional position of part (1).
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be used as a single unit, or two or more units can be integrated into one unit; the above-mentioned integration
  • the unit can be realized in the form of hardware or in the form of hardware plus software functional unit.
  • the embodiment of the present application provides a memory and a manufacturing method thereof, and the manufacturing method is applied to the industrial production of the memory.
  • the storage layer located on the side of the transistor is used to realize the storage of charges and the transfer of charges to the conductive channel, thereby realizing a storage unit without capacitance, saving the area occupied by each storage unit and the complexity.
  • the design of the transistor and the storage layer adopts the method of extending perpendicular to the surface of the substrate, which effectively utilizes the structural space in the vertical direction and saves the surface area of the memory, which is more conducive to the design and manufacture of miniaturized and highly integrated memory.

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Abstract

本申请实施例公开了一种存储器及其制造方法，所述存储器包括：衬底；所述衬底表面包括多个晶体管的晶体管阵列；所述晶体管的导电沟道在垂直于衬底表面的方向延伸；存储层；所述存储层位于每个所述晶体管的导电沟道的一侧，且与所述晶体管的导电沟道相连通，用于存储电荷以及与相连通的所述导电沟道进行电荷传递。

Description

存储器及其制造方法
相关申请的交叉引用
本申请基于申请号为202110757209.2、申请日为2021年07月05日、申请名称为“存储器及其制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种存储器及其制造方法。
背景技术
随着半导体市场需求的不断增长，半导体存储器技术迅速发展，存储器的制造技术，特别是动态随机存储器(DRAM，Dynamic Random Access Memory)技术得到了迅猛的发展，并在存储器市场中占据了主要位置。常见的DRAM单元由一个晶体管(Transistor)和一个电容器(Capacitor)构成1TlC结构，通过电容器上是否存储电荷区分逻辑状态。然而，目前市场对存储器的存储性能和单元尺寸提出越来越高的要求，给存储器的设计与制造带来了严峻的挑战。
发明内容
有鉴于此，本申请实施例提供一种存储器及其制造方法。
第一方面，所述存储器包括：
衬底；
在所述衬底表面包括多个晶体管的晶体管阵列；所述晶体管的导电沟道在垂直于衬底表面的方向延伸；
存储层；所述存储层位于每个所述晶体管的导电沟道的一侧，且与所述晶体管的导电沟道相连通，用于存储电荷以及与相连通的所述导电沟道进行电荷传递。
第二方面，存储器的制造方法包括：
在衬底表面形成包括多个晶体管的晶体管阵列；其中，所述晶体管的导电沟道在垂直于衬底表面的方向延伸；
在每个所述晶体管侧面垂直于所述衬底表面的方向形成存储层；所述存储层连通所述晶体管，用于存储电荷以及与相连通的所述导电沟道进行电荷传递。
附图说明
图1为本申请实施例的一种存储器的结构示意图一；
图2为本申请实施例的一种存储器的结构示意图二；
图3为本申请实施例的一种存储器的结构示意图三；
图4为本申请实施例的一种存储器的结构示意图四；
图5为本申请实施例的一种存储器的制作方法流程示意图；
图6A为本申请实施例的一种存储器的制作方法中对衬底掺杂的原理图；
图6B为本申请实施例的一种存储器的制作方法中刻蚀形成导电沟道的原理图；
图7为本申请实施例的一种存储器的制作方法中形成源极的原理图；
图8为本申请实施例的一种存储器的示意图；
图9为本申请实施例的一种存储器的衬底示意图；
图10为本申请实施例的一种存储器中形成导电沟道的示意图；
图11为本申请实施例的一种存储器中形成晶体管源极的示意图一；
图12为本申请实施例的一种存储器中形成晶体管源极的示意图二；
图13为本申请实施例的一种存储器中晶体管之间相互隔离的示意图；
图14为本申请实施例的一种存储器中形成容纳存储层的沟槽的示意图；
图15为本申请实施例的一种存储器中形成存储层的示意图；
图16为本申请实施例的一种存储器中形成隔离存储层的绝缘层的示意图；
图17为本申请实施例的一种存储器中形成容纳栅极的沟槽的示意图；
图18为本申请实施例的一种存储器中形成晶体管栅极的示意图；
图19为本申请实施例的一种存储器中形成晶体管漏极的示意图；
图20为本申请实施例的一种存储器中形成位线的示意图。
具体实施方式
本申请技术方案可以应用于半导体存储器的设计与制造，例如，常用的DRAM等半导体存储器。通常的DRAM采用电容实现电荷的存储，通过电荷的存储量来表示一个二进制比特(bit)的取值，即一个存储单元可以用于表示一个比特位的逻辑状态。由于晶体管存在漏电电流等现象，会导致存储的电荷容易发生流失，进而影响数据存储的稳定性。因此，对于DRAM需要周期性地充放电，刷新存储数据从而实现动态存储。
考虑到电容结构需要两个电容极板以及介质层等结构，需要占用较大的空间尺寸，导致单个存储单元的尺寸难以缩小，存储器的整体尺寸也受到该瓶颈的限制。因此，本申请实施例提供一种存储器，采用与晶体管的导电沟道连通的存储层实现电荷的传递和存储，进而不需要电容器，实现1T0C的存储单元结构，有效减少存储器的尺寸。
下面结合附图和实施例对本申请的技术方案进一步详细阐述。
本申请实施例提供一种存储器，如图1所示，存储器100包括：
衬底110；
在所述衬底110表面包括多个晶体管120的晶体管阵列；所述晶体管120的导电沟道121在垂直于衬底110表面的方向延伸；
存储层130；所述存储层130位于每个所述晶体管120的导电沟道121的一侧，且与所述晶体管120的导电沟道121相连通，用于存储电荷以及与相连通的所述导电沟道进行电荷传递。
这里，衬底可以为硅材料或者其他晶圆材料制作的半导体衬底。存储器的器件结构都可以在该衬底的表面通过各种半导体器件的工艺制程来制作形成，例如，通过掺杂、光刻、沉积以及清洗等各种工艺制程，在衬底表面形成具有分层的图形化结构，进而形成半导体器件。
在本申请实施例中，在衬底表面形成多个晶体管，并且晶体管以成对的方式排布在衬底表面。多对晶体管可以排布成行列从而形成晶体管阵列构成存储器。
这里，晶体管的导电沟道沿着垂直于衬底表面的方向延伸，相比于平行于衬底表面形成的晶体管可以占用更少的衬底表面积，提高衬底面积的利用率。
在本公开实施例中，通过与每个晶体管的导电沟道连通的存储层来实现电荷的存储，并且存储层能够与导电沟道进行电荷传递，实现存储单元逻辑状态的改变。存储层可以为半导体材料或者金属材料，可以用于存储电子或空穴。存储层与导电沟道连通，当晶体管上施加有电压时，导电沟道内产生电荷积累并与存储层形成电势差，从而与存储层发生电荷传输，改变存储层的电荷量。这样，就可以通过对晶体管的控制实现存储层与导电沟道之间的电荷传递，并在存储层中存储电荷。
存储层分布于每个晶体管的侧面与晶体管的导电沟道连通，存储层也是沿垂直于衬底表面的方向延伸，因此占用的衬底表面积很少。
本申请实施例的上述存储器结构，不仅节省了存储器中电容结构所需的制造空间，并且在形态上采用垂直化的方式进一步节省了对衬底表面积的占用，有效增大了单位面积的存储单元数量。本申请实施例还通过存储层实现了电荷存储，代替了原有电容的功能，实现1T0C的存储单元结构，有利于存储器小尺寸、高集成度的发展。
在一些实施例中，如图2所示，所述晶体管120的源极122位于所述导电沟道121靠近所述衬底110表面的一端；
所述晶体管120的漏极123位于所述导电沟道121远离所述衬底110表面的一端。
晶体管包括源极、栅极和漏极，通过栅极的电压控制，以及源极和漏极之间的电压差，实现源极和漏极之间的电荷导通或断开的状态切换。在本申请实施例中，晶体管导电沟道延伸的方向为垂直于衬底表面的方向，因此，晶体管的源极与漏极分别位于导电沟道的两端，即靠近衬底表面的一端和远离衬底表面的一端。
如此，晶体管的结构可以有效利用衬底上方的高度空间，节省衬底表面的表面积，从而使得单位面积的衬底表面可以集成更多的存储单元，提高存储器的存储效能。
在一些实施例中，所述晶体管的源极周围覆盖有第一绝缘层；所述第一绝缘层的相对于所述衬底表面的高度高于所述源极相对于所述衬底表面的高度。
在晶体管的源极周围可以通过第一绝缘层来覆盖晶体管源极，从而达到保护以及隔离源极与存储层的作用。第一绝缘层可以以一定的厚度均匀分布在衬底表面，该厚度的第一绝缘层可以完全覆盖住晶体管的源极，第一绝缘层相对于衬底表面的高度高于源极相对于衬底表面的高度。
这里，第一绝缘层的材料可以是氧化硅、氮化硅等材料，也可以是有机物材料等。
在一些实施例中，所述晶体管连通有所述存储层的一侧具有第二绝缘层，所述第二绝缘层覆盖所述存储层且所述第二绝缘层与所述第一绝缘层连通。由于在本申请实施例中，每个晶体管之间可以通过第二绝缘层相互隔离，并且第二绝缘层可以由第一绝缘层所在的位置即晶体管的导电沟道底部一直延伸至导电沟道的顶部。并且第二绝缘层与第一绝缘层相互隔离，并且存储层与其他晶体管以及其他存储层之间也通过绝缘层相互隔离。
此外，由于第一绝缘层覆盖在晶体管的源极上，第一绝缘层与第二绝缘层连通，可以形成一个整体的绝缘层，使得晶体管的源极以及存储层都相互隔离，并且被绝缘层所覆盖，从而减少源极与存储层之间产生电荷移动，便于存储层稳定地存储电荷。
这里，第一绝缘层与第二绝缘层可以为相同材料，也可以为不同材料。
在一些实施例中，如图3所示，所述存储器还包括：
至少一条位线140，位于所述晶体管120远离所述衬底110表面的一侧，与所述晶体管120的漏极123连接。
在本申请实施例中，存储器的多个晶体管可以排布形成行列结构的晶体管阵列，每一列晶体管可以通过位线连接，从而便于通过位线控制整列晶体管的读写数据。
位线可以为导电材料构成的线性薄膜，与晶体管的漏极连接，能够与晶体管的漏极产生电荷传递。位线的电势高低决定了晶体管进行数据读写的状态，因此，可以通过外部的电路向存储器的位线施加电压，从而改变位线的电势高低。
在一些实施例中，所述位线连通所述晶体管阵列中位于同一列的晶体管的漏极。
在本申请实施例中，一条位线可以覆盖多个晶体管，即在晶体管阵列处于同一列的晶体管由同一位线控制。这样，通过位线与存储器中的字线的配合，实现对每一晶体管的精确控制。
在一些实施例中，如图4所示，所述晶体管120的栅极124位于与所述导电沟道121连通的所述存储层130相对的另一侧，所述晶体管120的导电沟道121位于所述栅极124与所述存储层130之间。由于本申请实施例中的晶体管的导电沟道沿垂直于衬底表面的方向延伸，因此，晶体管源极与漏极之间的电荷流动也是沿着导电沟道延伸的方向。晶体管的栅极则从导电沟道的一侧控制导电沟道的导通性能，晶体管的栅极位于导电沟道的侧面，与导电沟道成平行的状态。
晶体管对应的存储层与晶体管的导电沟道的一侧连通，因此，晶体管的栅极则位于导电沟道的另一侧，该侧与存储层所在的一侧相对，使得晶体管的导电沟道位于栅极和存储层之间。
在一些实施例中，所述栅极包括：
栅极氧化层和栅极导电层；
所述栅极氧化层位于所述栅极导电层与所述导电沟道之间；或
所述栅极氧化层包裹所述栅极导电层，且与所述导电沟道相连。
在本申请实施例中，晶体管的导电沟道与晶体管的栅极导电层之间具有栅极氧化层，用于隔离栅极导电层与导电沟道。这样，导电沟道的导电性能可以通过栅极导电层的电势与导电沟道之间产生的场效应来控制。也就是说，导电沟道的导通或截止状态可以通过栅极导电层上所加的电压来切换。
上述栅极氧化层可以与栅极导电层形成平行于导电沟道的两层结构，栅极导电层的外侧可以通过绝缘材料进行隔离，从而与相邻晶体管的栅极之间相互独立。此外，栅极氧化层也可以包裹上述栅极导电层，使得栅极导电层的内侧和外侧均由栅极氧化层隔离开。
在一些实施例中，所述存储器还包括：
栅极保护层，覆盖于所述栅极远离所述衬底表面的一侧。
栅极保护层覆盖在栅极上方可以与晶体管的漏极平齐，从而隔离栅极与漏极以及栅极与晶体管顶部的其他结构，例如位线。
栅极保护层可以由氧化物或者如氮化硅等绝缘材料构成。当然，栅极保护层也可以为与栅极氧化层相同材料的薄膜，并与栅极氧化层连通，从而保护并隔离栅极导电层。
在一些实施例中，所述晶体管阵列中位于同一行的所述晶体管的栅极连通；其中，所述连通的栅极为所述同一行晶体管的字线。
在本申请实施例中，晶体管的栅极是由多个晶体管共用的，也就是说，栅极是以长条的形状从侧面覆盖多个晶体管的导电沟道。
这样，位于同一行的晶体管由同一栅极控制，这一栅极也就构成了这一行晶体管的字线。
这样，对于存储器整体，晶体管阵列的字线和位线形成了行列分别控制的结构，从而可以实现针对每个晶体管的精准的读写控制。
本申请实施例还提供一种存储器的制造方法，如图5所示，该方法包括：
步骤S101、在衬底表面形成包括多个晶体管的晶体管阵列；其中，所述晶体管的导电沟道在垂直于衬底表面的方向延伸；
步骤S102、在每个所述晶体管侧面垂直于所述衬底表面的方向形成存储层；所述存储层连通所述晶体管，用于存储电荷以及与相连通的所述导电沟道进行电荷传递。
这里，在衬底表面形成多个晶体管，可以是在衬底表面同步形成构成行列结构的晶体管阵列。
在本申请实施例中，可以在衬底表面一定厚度进行掺杂、离子注入等处理使得衬底的一定厚度具有更强的导电性能。此时，衬底表面的掺杂后的半导体层如图6A所示，衬底110的上层为进行处理后的半导体层，这里可以称之为有源层111。
然后可以通过光刻等工艺形成行列分布的多个导电沟道。如图6B所示，在形成导电沟道121的过程可以包括：在上述有源层表面覆盖掩膜层610，然后通过图形化的光照、刻蚀等工艺，去除部分有源层的半导体材料，保留的部分则为多个晶体管的导电沟道121。剩余的衬底底部则为存储器的衬底，作为晶体管阵列的载体，同时用于提供地电位与晶体管的源极或者漏极连接。此外，还可以在晶体管导电沟道的各相邻位置分别形成晶体管的源极、栅极以及漏极等结构，形成存储器的晶体管阵列。这样，形成的导电沟道相对于衬底表面是垂直延伸的，因此可以占用极少的衬底表面积，提升存储器的集成度。
针对每一晶体管可以对应形成一存储层，该存储层可以与晶体管的导电沟道连通，因此，可以在晶体管的导电沟道侧面覆盖存储层所使用的半导体材料或者金属材料，形成薄膜。
如此，就形成了均匀分布的晶体管阵列以及每一晶体管的对的存储层。在存储器使用的过程中，可以通过针对每一晶体管的控制，实现在对应存储层的电荷流动以及电荷存储。针对整个存储器，则可以通过对不同位置的晶体管控制，实现数据的读写和存储功能。
在一些实施例中，所述在每个所述晶体管侧面垂直于所述衬底表面的方向形成存储层，包括：
在所述晶体管的导电沟道一侧形成沟槽；
在所述沟槽中沉积半导体材料或金属材料，覆盖所述沟槽的侧壁和底部；
刻蚀去除所述沟槽底部的所述半导体材料或金属材料，形成所述存储层。
在衬底上形成晶体管的导电沟道的过程中，需要去除各晶体管之间有源层的半导体材料，使得每个导电沟道垂直立在衬底的底层上，上述过程在各导电沟道之间形成了沟槽。因此，可以在每个晶体管的导电沟道一侧的沟槽内形成存储层，并覆盖在导电沟道的侧面上。
示例性地，可以通过将半导体材料或者金属材料，包括如单晶硅(Si)、锗(Ge)、硅锗(Si-Ge)、铝锑(Al-Sb)或者镓锑(Ga-Sb)等材料沉积在上述沟槽内，包括物理气相沉积(PVD，Physical Vapor Deposition)以及化学气相沉积(CVD，Chemical Vapor Deposition)等方式，使得晶体管导电沟道的一侧覆盖有上述半导体材料或者金属材料形成存储层。
如此，就形成了均匀分布的晶体管阵列以及对应的存储层。在存储器使用的过程中，可以通过针对每一晶体管的控制，实现在对应存储层的电荷流动以及电荷存储。针对整个存储器，则可以通过对不同位置的晶体管控制，实现数据的读写和存储功能。
在一些实施例中，所述在衬底表面形成包括多个晶体管的晶体管阵列，包括：
在所述衬底表面形成垂直于所述衬底表面的多个导电沟道；
在所述导电沟道靠近所述衬底表面的一端形成多个所述晶体管的源极；
在所述导电沟道远离所述衬底表面的一端形成多个所述晶体管的漏极。
晶体管包括源极、栅极和漏极，通过栅极的电压控制，以及源极和漏极之间的电压差，实现源极和漏极之间的电荷导通或断开的状态切换。在本申请实施例中，晶体管导电沟道延伸的方向为垂直于衬底表面的方向，因此，晶体管的源极与漏极分别位于导电沟道的两端，即靠近衬底表面的一端和远离衬底表面的一端。
在本申请实施例中，可以在形成导电沟道之后，先在导电沟道靠近衬底表面的一端形成晶体管的源极，此时源极是与衬底连通的，因此源极可以通过衬底接地。然后可以在导电沟道远离衬底表面的一端形成晶体管的漏极，这样，晶体管的电荷传输则沿着为源极到漏极通过导电沟道形成的导电通路。
需要说明的是，形成导电沟道源极、漏极、栅极以及存储层等结构的顺序这里不做限定，可以先形成上述导电沟道的源极、漏极和栅极后再形成存储层，也可以在形成导电沟道的源极后形成存储层，再形成漏极以及栅极等等。在实际应用中，可以根据生产规划、各层光罩的形态、各层材料特性以及工艺制程的设备参数需求等综合考虑上述形成顺序。
在一些实施例中，所述在所述衬底表面形成垂直于所述衬底表面的导电沟道，包括：
在硅材料衬底上进行掺杂，形成有源层；
在所述有源层进行图形化刻蚀，形成垂直于所述衬底表面的导电沟道。
衬底可以为硅材料或者其他晶圆材料制作的半导体衬底，在形成晶体管的过程中， 可以先对衬底的表层一定厚度的半导体材料进行掺杂，可以为N型掺杂或P型掺杂。例如，通过磷离子或硼离子等三价或五价离子进行掺杂或者离子注入，使得衬底的表层形成P型半导体或者N型半导体。这样做的目的是提升半导体材料的导电性能，使其能够构成晶体管的导电沟道。
然后进行图形化刻蚀，去除需要形成导电沟道的位置以外的半导体材料，保留部分半导体材料则形成上述导电沟道。这里，图形化刻蚀所保留下的图形即为导电沟道的形状，可以为截面为正方形的柱体、截面为长方形的柱体、截面为菱形的柱体或者截面为圆形等各种形状的柱体，这些柱体就构成了晶体管的导电沟道。
在一些实施例中，如图7A所示，所述在所述导电沟道121靠近所述衬底110表面的一端形成所述晶体管120的源极122，包括：
在所述衬底表面沉积重掺杂介质层710；
高温激活所述重掺杂介质层710，在所述导电沟道121靠近所述衬底110表面的一端形成所述源极122。
这里，重掺杂介质层可以为含有与导电沟道极性相反的掺杂离子的半导体材料，例如，导电沟道为N型掺杂，那么重掺杂介质层为P型掺杂；导电沟道为P型掺杂，那么重掺杂介质层为N型掺杂。
这样，通过高温激活，重掺杂介质层中的导电离子被活化，从而传递至导电沟道内，使得导电沟道在靠近衬底表面的端部重新注入相反极性的离子，从而形成晶体管源极。
在高温激活并在导电沟道底部形成源极后，可以再通过刻蚀的方法去除重掺杂介质层。为了防止衬底表面有残留的重掺杂介质层材料，可以在刻蚀的过程中过刻蚀掉衬底的一部分，从而使得晶体管的源极有一部分嵌入在衬底内，一部分暴露在衬底以上。
在一些实施例中，所述在所述导电沟道远离所述衬底表面的一端形成所述晶体管的漏极，包括：
在所述导电沟道远离所述衬底表面的一端外延生长单晶硅层；
在所述单晶硅层进行离子注入或掺杂形成所述漏极。
在形成上述漏极时，可以在晶体管导电沟道远离衬底表面的一端外延生长单晶硅并进一步进行掺杂或者离子注入，形成P型或N型半导体。需要说明的是，形成漏极的掺杂极性与导电沟道的极性也为相反极性，从而形成PNP或者NPN结构的晶体管。
在一些实施例中，所述方法还包括：
在所述晶体管的源极周围形成第一绝缘层；其中，所述第一绝缘层的相对于所述衬底表面的高度高于所述源极相对于所述衬底表面的高度。
在形成晶体管的源极之后，可以进一步在晶体管导电沟道的侧面形成晶体管对应的存储层。但存储层与源极之间不能互通，因此，这里可以通过形成覆盖源极的第一绝缘层来隔离和保护晶体管的源极，然后在形成晶体管对应的存储层。
这里，第一氧化层的材料可以为氧化硅、氮化硅或者其他有机材料等形成的绝缘的薄膜。
在一些实施例中，所述方法还包括：
在所述晶体管连通有所述存储层的一侧形成第二绝缘层；其中，所述第二绝缘层覆 盖所述存储层且所述第二绝缘层与所述第一绝缘层连通。
这里形成每晶体管对应的存储层之后，可以在各晶体管之间形成第二绝缘层，并使得第二绝缘层与第一绝缘层连通。这样，第二绝缘层可以包裹住存储层以及晶体管，防止电荷泄漏，提升存储性能。
第二绝缘层与第一绝缘层的材料可以相同也可以不同。并且，形成第二绝缘层的过程可以是通过沉积绝缘材料填满各晶体管之间的沟槽，从而达到隔绝各晶体管的存储层的作用。
在一些实施例中，所述方法还包括：
在所述晶体管远离所述衬底表面的一侧形成至少一条位线；其中，所述位线与所述晶体管的漏极连接。
在本申请实施例中，通过在各晶体管之间的沟槽内填充上述第二氧化层，使得晶体管远离衬底表面的一端处于近似的平面内，这时，可以在最上层涂布金属材料、具有较强导电性能的半导体材料或者其他材料形成导电层。
然后在导电层通过图形化的刻蚀去除多余的导电材料，保留线性的导电材料从而形成上述位线。
这里，位线与晶体管的漏极连接，从而可以进行电荷传递。
在一些实施例中，所述在衬底表面形成包括多个晶体管的晶体管阵列，还包括：
在所述导电沟道的连通有所述存储层一侧相对的另一侧形成所述晶体管的栅极；其中，所述晶体管的导电沟道位于所述栅极与所述存储层之间。
可以在晶体管导电沟道与形成存储层的一侧相对的另一侧形成晶体管的栅极，因此，形成栅极的过程可以在形成上述存储层之前也可以在形成存储层之后。
在形成栅极以及存储层后，每一晶体管以及对应的存储层都具有相同的结构，并整齐地排布在衬底表面，形成存储单元的阵列结构。
在一些实施例中，所述在所述导电沟道的连通有所述存储层一侧相对的另一侧形成所述晶体管的栅极，包括：
在所述导电沟道的所述另一侧形成连通所述导电沟道的栅极氧化层；
在所述栅极氧化层的一侧形成连通所述栅极氧化层的栅极导电层；其中，所述栅极栅极氧化层位于所述栅极导电层与所述导电沟道之间；或所述栅极氧化层包裹所述栅极导电层，且与所述导电沟道相连。
晶体管的栅极包括栅极氧化层以及栅极导电层，可以在晶体管导电沟道的一侧先形成栅极氧化层，然后再形成栅极导电层；也可以先形成栅极氧化层，再在栅极氧化层的中间刻蚀形成沟槽，然后在沟槽内形成栅极导电层，从而使得栅极导电层被栅极氧化层所包裹。
在一些实施例中，所述方法还包括：
在所述栅极远离所述衬底表面的一端形成覆盖所述栅极的栅极保护层。
由于栅极导电层的顶部，即远离衬底表面的一端可能会暴露出来，为了保护栅极导电层，使其不受外界干扰，可以在栅极上方覆盖绝缘的栅极保护层。
栅极保护层可以由氧化物或者如氮化硅等绝缘材料构成。当然，栅极保护层也可以 为与栅极氧化层相同材料的薄膜，并与栅极氧化层连通，从而保护并隔离栅极导电层。
在一些实施例中，所述在所述导电沟道的连通有所述存储层一侧相对的另一侧形成所述晶体管的栅极，包括：
在所述晶体管阵列中同一行晶体管的一侧形成贯通的沟槽；
在所述沟槽内形成连通所述同一行晶体管的所述栅极；其中，所述栅极为所述同一行晶体管的字线。
在形成栅极的过程中，可以在晶体管的导电沟道相对于存储层的另一侧形成贯通的沟槽，从而形成一行晶体管共用的栅极。这样，这一行晶体管共用的栅极就行成了对应的字线。
本申请实施例还提供如下示例：
如图8所示，本申请实施例提供一种存储器的示意图，即一种垂直沟道的无电容结构的DRAM，即1T0C DRAM。如图8表示的存储器的剖面图部分(1)所示，晶体管的导电沟道811垂直于衬底810表面，源极812位于靠近衬底810表面的一端；漏极813位于远离衬底810表面的一端。每个晶体管的一侧具有存储层814，与晶体管的导电沟道811连通。此外，晶体管的栅极815位于晶体管相对的外侧。每个晶体管之间则填充有绝缘材料相互隔离。由于不需要电容，每个存储单元(晶体管及其对应的存储层)在尺寸上可以缩小至2F2，(F为存储器单元的最小外形尺寸，F2则表示单位面积)同时，由于导电沟道811在垂直于衬底810表面的方向上延伸，因此可以增加导电沟道811的长度，而不会占用过多衬底810的表面积。
存储器的俯视图如图8中的部分(2)所示，在每一晶体管的顶部覆盖有导电材料并连通整列的晶体管，从而形成位线821。晶体管的栅极则贯通整行晶体管形成字线，图8中的俯视图的部分(2)中未示出栅极，但可以看到栅极顶部与字线所在位置一致的栅极保护层822。图8中剖面图的部分(1)对应的剖面位于俯视图的部分(2)对应的直线80处。
形成上述结构的方法包括如下步骤：
步骤1、如图9所示，在硅衬底900一定厚度进行P型或N型掺杂，形成有源层910；
步骤2、如图10所示，在上述有源层910覆盖掩膜层920，并进行图形化的刻蚀，去除导电沟道以外的有源层，剩余的半导体结构则为导电沟道911。导电沟道911可以为方形、菱形等不同形状。上述掩膜层920可以为氮化硅。其中，图10中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
步骤3、如图11所示，在衬底表面各导电沟道之间的间隙沉积重掺杂介质层930，掺杂离子是有源区相反的类型。其中，图11中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
步骤4、如图12所示，沉积重掺杂介质层后高温激活，使有源区底部即导电沟道911的底部形成源极912或者漏极，然后可以通过刻蚀去除重掺杂介质层。这里，为了完全去除重掺杂介质层，可以过刻蚀一部分衬底。其中，图12中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
步骤5、如图13所示，在衬底表面沉积氧化层940，氧化层940的表面可以略高于 源极912表面，有效隔离源极。然后可以在氧化层940上方填充绝缘介质950。绝缘介质层950的材料可以是氧化硅或者氮化硅等无机物，也可以是有机绝缘材料。其中，图13中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
步骤6、如图14所示，图形化刻蚀，在有源区一侧的绝缘介质950形成沟槽951或者孔结构，漏出晶体管的导电沟道911。以上述氧化层940作为刻蚀的停止层，防止刻蚀漏出源极。其中，图14中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
步骤7、如图15所示，在沟槽951中形成半导体材料层或者金属材料层中的至少一种。半导体层可以是Si层，并且半导体材料可以包括Ge，Si-Ge，Al-Sb和Ga-Sb中的至少一种，半导体材料层的价带比有源区高，半导体中还可以有量子点，用来储存电子，即形成与导电沟道911连通的存储层960。其中，图15中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
步骤8、如图16所示，在沟槽951填充氧化层941，使得氧化层940与氧化层941连通，并包裹晶体管对应的存储层960。其中，图16中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
步骤9、如图17所示，图形化刻蚀在导电沟道911另一侧的隔离层中打开沟槽970，露出有源区，以氧化层940为刻蚀停止层，防止沟槽露出源极。其中，图17中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
步骤10、如图18所示，在上述沟槽970中沉积栅极氧化层971、栅极金属层972并回刻至有源区水平的位置，并填充栅极保护层973。其中，图18中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
步骤11、如图19所示，去除导电沟道911即有源层顶部的掩膜层，并外延生长单晶硅层，然后离子注入或者掺杂形成晶体管漏极913。其中，图19中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
步骤12、如图20所示，晶体管结构的顶部形成导电层，然后通过图形化刻蚀形成连接漏极913的位线980。其中，图20中的部分(1)为剖面图，部分(2)为俯视图，其中的黑线90表示部分(1)的剖面位置。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者 装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本申请各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本申请的实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本申请是实施例提供一种存储器及其制造方法，该制造方法应用于存储器的工业生产。通过本申请实施例的技术方案，利用位于晶体管侧面的存储层实现电荷的存储以及与导电沟道之间的电荷传递，从而实现了无电容的存储单元，节省了每个存储单元的占用面积和复杂度。并且，晶体管及存储层的设计采用垂直于衬底表面方向延伸的方式，有效利用垂直方向的结构空间，节省存储器的表面积，从而更加利于小型化和高集成度的存储器设计与制造。

Claims (23)

  1. 一种存储器，包括：
    衬底；
    在所述衬底表面包括多个晶体管的晶体管阵列；所述晶体管的导电沟道在垂直于衬底表面的方向延伸；
    存储层；所述存储层位于每个所述晶体管的导电沟道的一侧，且与所述晶体管的导电沟道相连通，用于存储电荷以及与相连通的所述导电沟道进行电荷传递。
  2. 根据权利要求1所述的存储器，其中，所述晶体管的源极位于所述导电沟道靠近所述衬底表面的一端；
    所述晶体管的漏极位于所述导电沟道远离所述衬底表面的一端。
  3. 根据权利要求2所述的存储器，其中，所述晶体管的源极周围覆盖有第一绝缘层；所述第一绝缘层的相对于所述衬底表面的高度高于所述源极相对于所述衬底表面的高度。
  4. 根据权利要求3所述的存储器，其中，所述晶体管连通有所述存储层的一侧具有第二绝缘层，所述第二绝缘层覆盖所述存储层且所述第二绝缘层与所述第一绝缘层连通。
  5. 根据权利要求2所述的存储器，还包括：
    至少一条位线，位于所述晶体管远离所述衬底表面的一侧，与所述晶体管的漏极连接。
  6. 根据权利要求5所述的存储器，其中，所述位线连通所述晶体管阵列中位于同一列的晶体管的漏极。
  7. 根据权利要求1至6任一所述的存储器，其中，所述晶体管的栅极位于与所述导电沟道连通的所述存储层相对的另一侧，所述晶体管的导电沟道位于所述栅极与所述存储层之间。
  8. 根据权利要求7所述的存储器，其中，所述栅极包括：
    栅极氧化层和栅极导电层；
    所述栅极氧化层位于所述栅极导电层与所述导电沟道之间；或
    所述栅极氧化层包裹所述栅极导电层，且与所述导电沟道相连。
  9. 根据权利要求8所述的存储器，还包括：
    栅极保护层，覆盖于所述栅极远离所述衬底表面的一侧。
  10. 根据权利要求7所述的存储器，其中，所述晶体管阵列中位于同一行的所述晶体管的栅极连通；其中，所述连通的栅极为所述同一行晶体管的字线。
  11. 一种存储器的制造方法，包括：
    在衬底表面形成包括多个晶体管的晶体管阵列；其中，所述晶体管的导电沟道在垂直于衬底表面的方向延伸；
    在每个所述晶体管侧面垂直于所述衬底表面的方向形成存储层；所述存储层连通所述晶体管，用于存储电荷以及与相连通的所述导电沟道进行电荷传递。
  12. 根据权利要求11所述的方法，其中，所述在每个所述晶体管侧面垂直于所述衬底表面的方向形成存储层，包括：
    在所述晶体管的导电沟道一侧形成沟槽；
    在所述沟槽中沉积半导体材料或金属材料，覆盖所述沟槽的侧壁和底部；
    刻蚀去除所述沟槽底部的所述半导体材料或金属材料，形成所述存储层。
  13. 根据权利要求11所述的方法，其中，所述在衬底表面形成包括多个晶体管的晶体管阵列，包括：
    在所述衬底表面形成垂直于所述衬底表面的多个导电沟道；
    在所述导电沟道靠近所述衬底表面的一端形成多个所述晶体管的源极；
    在所述导电沟道远离所述衬底表面的一端形成多个所述晶体管的漏极。
  14. 根据权利要求13所述的方法，其中，所述在所述衬底表面形成垂直于所述衬底表面的导电沟道，包括：
    在硅材料衬底上进行掺杂，形成有源层；
    在所述有源层进行图形化刻蚀，形成垂直于所述衬底表面的导电沟道。
  15. 根据权利要求13所述的方法，其中，所述在所述导电沟道靠近所述衬底表面的一端形成所述晶体管的源极，包括：
    在所述衬底表面沉积重掺杂介质层；
    高温激活所述重掺杂介质层，在所述导电沟道靠近所述衬底表面的一端形成所述源极。
  16. 根据权利要求13所述的方法，其中，所述在所述导电沟道远离所述衬底表面的一端形成所述晶体管的漏极，包括：
    在所述导电沟道远离所述衬底表面的一端外延生长单晶硅层；
    在所述单晶硅层进行离子注入或掺杂形成所述漏极。
  17. 根据权利要求13所述的方法，还包括：
    在所述晶体管的源极周围形成第一绝缘层；其中，所述第一绝缘层的相对于所述衬底表面的高度高于所述源极相对于所述衬底表面的高度。
  18. 根据权利要求17所述的方法，还包括：
    在所述晶体管连通有所述存储层的一侧形成第二绝缘层；其中，所述第二绝缘层覆盖所述存储层且所述第二绝缘层与所述第一绝缘层连通。
  19. 根据权利要求13所述的方法，还包括：
    在所述晶体管远离所述衬底表面的一侧形成至少一条位线；其中，所述位线与所述晶体管的漏极连接。
  20. 根据权利要求11至19任一所述的方法，其中，所述在衬底表面形成包括多个晶体管的晶体管阵列，还包括：
    在所述导电沟道的连通有所述存储层一侧相对的另一侧形成所述晶体管的栅极；其中，所述晶体管的导电沟道位于所述栅极与所述存储层之间。
  21. 根据权利要求20所述的方法，其中，所述在所述导电沟道的连通有所述存储层一侧相对的另一侧形成所述晶体管的栅极，包括：
    在所述导电沟道的所述另一侧形成连通所述导电沟道的栅极氧化层；
    在所述栅极氧化层的一侧形成连通所述栅极氧化层的栅极导电层；其中，所述栅极栅极氧化层位于所述栅极导电层与所述导电沟道之间；或所述栅极氧化层包裹所述栅极导电层，且与所述导电沟道相连。
  22. 根据权利要求21所述的方法，还包括：
    在所述栅极远离所述衬底表面的一端形成覆盖所述栅极的栅极保护层。
  23. 根据权利要求20所述的方法，其中，所述在所述导电沟道的连通有所述存储层一侧相对的另一侧形成所述晶体管的栅极，包括：
    在所述晶体管阵列中同一行晶体管的一侧形成贯通的沟槽；
    在所述沟槽内形成连通所述同一行晶体管的所述栅极；其中，所述栅极为所述同一行晶体管的字线。
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