WO2023245762A1 - 存储芯片测试方法及装置、介质及设备 - Google Patents

存储芯片测试方法及装置、介质及设备 Download PDF

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WO2023245762A1
WO2023245762A1 PCT/CN2022/105255 CN2022105255W WO2023245762A1 WO 2023245762 A1 WO2023245762 A1 WO 2023245762A1 CN 2022105255 W CN2022105255 W CN 2022105255W WO 2023245762 A1 WO2023245762 A1 WO 2023245762A1
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memory chip
read
tck
preset time
predicted value
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PCT/CN2022/105255
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English (en)
French (fr)
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WO2023245762A9 (zh
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赵北游
李钰
史腾
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长鑫存储技术有限公司
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Priority to US18/155,676 priority Critical patent/US20230410929A1/en
Publication of WO2023245762A1 publication Critical patent/WO2023245762A1/zh
Publication of WO2023245762A9 publication Critical patent/WO2023245762A9/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

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  • the present disclosure relates to the field of integrated circuit technology, and specifically, to a memory chip testing method, a memory chip testing device, a computer-readable storage medium and electronic equipment.
  • DRAM Dynamic Random Access Memory
  • LPDDR5 Low Power Double Data Rate 5, Low Power Double Data Rate 5
  • Wck2ck Leveling write clock (WCK) to clock leveing
  • WK write clock
  • the Wck2ck Leveling function is mainly used to detect the phase relationship between the system clock CK and the read and write clock WCK, it is difficult for the computer to directly measure the phase between the two clocks to obtain the Wck2ck Leveling verification result.
  • a memory chip testing method includes: sending a mode register write command to the memory chip, controlling the memory chip to enter a read-write clock equalization test mode; and setting a first preset time, after waiting for the first preset time, send a read and write clock signal to the memory chip; according to the first preset time and the system clock cycle, determine the predicted value of the read and write clock balance; after sending all After reading and writing the clock signal, wait for a second preset time, detect the test data output port of the memory chip, and obtain a test value; compare the test value and the predicted value to determine whether there is an abnormality in the memory chip.
  • determining the predicted value of the read and write clock balance based on the first preset time and the system clock cycle includes: placing the cutoff time point at the remaining time The corresponding tCK value is used as the predicted value.
  • the method further includes: when tis>tCK*5/8 and tis ⁇ tCK*7/8, determining that the predicted value is 0; when tis>tCK/8 And when tis ⁇ tCK*3/8, the predicted value is determined to be 1.
  • comparing the test value and the predicted value to determine whether there is an abnormality in the memory chip includes: if the test value and the predicted value are inconsistent, determining There is an abnormality in the memory chip.
  • the read and write clock signal is a read and write clock signal that includes a cycle length of 7.5.
  • the second preset time is less than or equal to 20 ns.
  • a memory chip testing device includes: a signal sending module for sending a mode register write command to the memory chip to control the memory chip to enter a read-write clock equalization test mode; Set a first preset time, and after waiting for the first preset time, send a read and write clock signal to the memory chip; a prediction value determination module, configured to determine based on the first preset time and the system clock cycle The predicted value of the read-write clock balance; the test value determination module, used to wait for the second preset time after sending the read-write clock signal, detect the test data output port of the memory chip, and obtain the test value; the determination module , used to compare the test value and the predicted value to determine whether there is an abnormality in the memory chip.
  • the predicted value determination module is configured to use the corresponding value of tCK at the cut-off time point of the remaining time as the predicted value.
  • the predicted value determination module is configured to determine that the predicted value is 0 when tis>tCK*5/8 and tis ⁇ tCK*7/8; when tis> When tCK/8 and tis ⁇ tCK*3/8, the predicted value is determined to be 1.
  • the determination module is configured to determine that there is an abnormality in the memory chip if the test value is inconsistent with the predicted value.
  • the read and write clock signal is a read and write clock signal that includes a cycle length of 7.5.
  • the second preset time is less than or equal to 20 ns.
  • a computer-readable storage medium is provided, a computer program is stored thereon, and when the computer program is executed by a processor, the above-mentioned memory chip testing method is implemented.
  • an electronic device including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the operation via executing the executable instructions. Perform the above memory chip testing method.
  • Figure 1 schematically shows a flow chart of a memory chip testing method according to an exemplary embodiment of the present disclosure
  • Figure 2 schematically shows a read-write clock balancing function timing diagram 1 according to an exemplary embodiment of the present disclosure
  • Figure 3 schematically shows the read and write clock balancing function timing diagram 2 according to an exemplary embodiment of the present disclosure
  • FIG. 4 schematically illustrates a corresponding relationship diagram between reference values and predicted values according to an exemplary embodiment of the present disclosure
  • Figure 5 schematically shows a block diagram of a memory chip testing device according to an exemplary embodiment of the present disclosure
  • FIG. 6 schematically shows a module diagram of an electronic device according to an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.
  • a semiconductor memory chip includes a plurality of memory cells in a memory array, each memory cell storing at least one bit of information.
  • DRAM is an example of such a semiconductor memory. This solution is preferably used in DRAM. Accordingly, the following description of embodiments is made with reference to DRAM as a non-limiting example.
  • the Wck2ck Leveling of the memory chip needs to be functionally tested to screen out chips that work normally.
  • exemplary embodiments of the present disclosure provide a memory chip testing method for testing the read and write clock balancing Wck2ck Leveling function of the memory chip.
  • the memory chip testing method includes:
  • Step S110 Send a mode register write command to the memory chip to control the memory chip to enter the read-write clock equalization test mode;
  • Step S120 set a first preset time, wait for the first preset time, and then send a read and write clock signal to the memory chip;
  • Step S130 determine the predicted value of read and write clock balance based on the first preset time and the system clock cycle
  • Step S140 After sending the read and write clock, wait for the second preset time, detect the test data output port of the memory chip, and obtain the test value;
  • Step S150 Compare the test value and the predicted value to determine whether there is an abnormality in the memory chip.
  • the memory chip testing method by sending a mode register write command to the memory chip, the memory chip can be controlled to enter the read-write clock equalization test mode; after entering the read-write clock equalization test mode, wait for the first preset By setting the time, the read and write clock can be sent to the memory chip; then, the predicted value of the read and write clock balance can be determined based on the set first preset time and the system clock cycle; using the predicted value and the test data of the memory chip The test value at the output port can determine whether there is an abnormality in the memory chip, thereby testing the read and write clock balancing function of the memory chip.
  • step S110 a mode register write command is sent to the memory chip to control the memory chip to enter the read-write clock equalization test mode.
  • the mode register write command MRW Command is used to write data to the mode register of the DRAM.
  • the mode register write command is completed through the cooperation of the clock enable CKE signal, the chip select CS signal and the command/address signal, such as CA[5:0] (the set of CA signals can be marked as CA[5:0]).
  • the address and data of the mode register are conveyed through CA[5:0].
  • the cycle time of the mode register write command is controlled by the tMRW parameter.
  • sending mode register write commands to the memory chip is executed by the memory chip controller.
  • LPDDR5 DRAM Controller sends mode register write commands to LPDDR5 DRAM.
  • the memory chip by sending a mode register write command to the memory chip through the memory chip controller, the memory chip can be controlled to enter the read and write clock equalization test mode, that is, to enter the Wck2ck Leveling mode.
  • the Wck2ck Leveling mode is a mode for testing the Wck2ck Leveling function of the memory chip, that is, the read and write clock balancing function.
  • the read-write clock balancing function is mainly used to detect the phase relationship between the system clock CK and the read-write clock WCK. By detecting the phase relationship between the system clock CK and the read-write clock WCK, it can be determined Whether the timing of the memory chip is running normally.
  • the read-write clock balance test function of the memory chip can be tested to determine whether there is an abnormality in the memory chip.
  • step S120 a first preset time is set, and after waiting for the first preset time, a read and write clock signal is sent to the memory chip.
  • the first preset time needs to be set in advance to ensure that the predicted value of the read and write clock balance determined based on the first preset time and the system clock cycle is a fixed value, so that Facilitates comparison of fixed predicted values with test values.
  • the read-write clock balancing function timing diagram shown in Figure 2 it can be seen that after the memory chip controller sends the mode register write command MRW-1 to the memory chip, to the T3 moment of the system clock CK, and after waiting for the tWLMRD time, The memory chip controller begins to send the read and write clock signal WCK to the memory chip. Therefore, the first preset time is the sum of the time period from when the mode register write command MRW-1 is sent to the memory chip to the T3 time of the system clock CK and the tWLMRD time.
  • the frequency of the read and write clock signal WCK sent is twice the frequency of the system clock CK.
  • the length of the read and write clock signal WCK sent at one time includes a read and write clock signal of 7.5 cycles. .
  • the read and write clock signal WCK is a clock signal that is used during reading and writing.
  • step S130 a predicted value of read and write clock balance is determined based on the first preset time and the system clock cycle.
  • the memory chip enters the read and write clock equalization test mode after receiving the mode register write command. After waiting for the first preset time to send the read and write clock signal, the memory chip starts writing the mode register after receiving the mode register write command.
  • the time interval tWCKIS from the input of the command to the receipt of the first rising edge of the read and write clock signal is the first preset time. Based on the first preset time, the predicted value of the read and write clock balance can be calculated.
  • the memory chip after receiving the mode register write command, the memory chip usually receives the read and write clock signals sent by the memory chip controller multiple times. For example, refer to Figure 3 when sending multiple read and write clocks. As shown in the timing diagram, after receiving the mode register write command, the memory chip also receives three read and write clock signals, namely the first read and write clock signal, the second read and write clock signal and the third read and write clock signal.
  • the first preset time from when the memory chip receives the mode register write command to when it receives the first rising edge of the first read and write clock signal can be marked as tWCKIS1.
  • the first preset time of the first rising edge of the second read-write clock signal can be marked as tWCKIS2.
  • the memory chip starts from receiving the mode register write command to receiving the first rising edge of the third read-write clock signal.
  • the preset time can be marked as tWCKIS3.
  • the starting points of these three first preset times are the same, but the end points are different.
  • the third first preset time tWCKIS3 is greater than the second first preset time tWCKIS2, and the second first preset time tWCKIS2 is greater than the first preset time tWCKIS2.
  • the preset first preset time tWCKIS it can be known that it is the sum of N times the system clock cycle tCK and the remaining time tis, that is, the first preset time tWCKIS minus N After multiple system clock cycles tCK, there is still remaining time tis.
  • the value of tCK corresponding to the deadline of the remaining time is used as the predicted value of read and write clock balance, that is, the deadline of the remaining time tis is The value of the system clock cycle tCK corresponding to the point is determined as the predicted value.
  • the predicted value is a definite 0 or a definite 1.
  • the remaining time tis in the process of determining the predicted value, can be determined first based on the first preset time tWCKIS and the system clock cycle tCK, and then the read-write clock can be determined based on the range of the remaining time tis.
  • the specific value of the balanced predicted value can be determined by the system clock cycle tCK.
  • the position of the rising edge of the read-write clock signal WCK can represent the value of the read-write clock balance tWCK2CK.
  • the remaining time tis can be used to determine the specific position of the rising edge of the read-write clock signal WCK.
  • the quotient of the first preset time tWCKIS and the system clock cycle tCK may be rounded down [ tWCKIS/tCK], determine [tWCKIS/tCK] as the above N. That is to say, N is the quotient of the first preset time and the system clock cycle, rounded down.
  • the predicted value can be determined based on the range of the remaining time tis.
  • the predicted value DQ determined according to the range of the remaining time tis is as follows:
  • a predicted value of 0 means that the rising edge of the read and write clock signal WCK has a value of 0 in the interval.
  • a predicted value of 1 means that the rising edge of the read and write clock signal WCK has a value of 1 in the interval.
  • the predicted value 0/1 means that the rising edge of the read and write clock signal WCK predicts that the value DQ will flip from 0 to 1 or from 1 to 0 at a certain point in the interval. According to the standard, if the flip point falls between -1/8tCK and 1/8tCK, the design of the memory chip meets the requirements.
  • the aforementioned setting of the first preset time so that the predicted value of the read-write clock balance is a fixed value refers to setting the first preset time so that the predicted value DQ is a definite 0 or a certain value. 1, that is, the range of the remaining time tis satisfies tis>tCK*5/8 and tis ⁇ tCK*7/8, or satisfies tis>tCK/8 and tis ⁇ tCK*3/8. Therefore, the size of the set first preset time can be determined according to the range of the remaining time tis.
  • the predicted value of the read and write clock balance corresponding to each read and write clock can be calculated. Specifically, you can first determine the remaining time tis, and replace the first preset time tWCKIS in the remaining time tis formula with the first first preset time tWCKIS1 corresponding to the first read and write clock, and the second corresponding to the second read and write clock. A first preset time tWCKIS2, and a third first preset time tWCKIS3 corresponding to the third read-write clock.
  • Different read and write clock signals can obtain different remaining times tis1, tis2, tis3..., and then according to the range of different remaining times, the predicted value of read and write clock balance is determined.
  • Each read and write clock signal corresponds to a predicted value of read and write clock balance.
  • the obtained predicted values of read and write clock balance corresponding to multiple read and write clock signals can be used to predict whether there is an abnormality in the memory chip.
  • step S140 after sending the read and write clock signals, wait for the second preset time, detect the test data output port of the memory chip, and obtain the test value.
  • the test value can be obtained by detecting the data port of the memory chip. .
  • the experimental results are usually obtained before the second preset time tWLO and are maintained.
  • the time point at which the experimental results of the memory chip will be released is uncertain, sooner or later.
  • tWLO a latest time is specified, that is, the results must be available before tWLO at the latest, and after tWLO. Keep the value of the previous result.
  • the second preset time tWLO is not a fixed value, and a maximum value of 20 ns is usually specified. Therefore, in the exemplary embodiment of the present disclosure, the second preset time tWLO is less than or equal to 20 ns. For example, after waiting for 20ns after sending the read and write clock, the test value can be obtained by detecting the data port of the memory chip.
  • Step S150 Compare the test value and the predicted value to determine whether there is an abnormality in the memory chip.
  • the test value after obtaining the test value through the test data output port of the memory chip, it can be combined with the previously determined predicted value of read and write clock balance to determine whether there is an abnormality in the memory chip.
  • the memory chip testing method provided by the exemplary embodiment of the present disclosure is used to determine that the test value is inconsistent with the predicted value, you need to find the cause and change the circuit design of the memory chip; if it is during the testing process, use this method If the memory chip testing method provided by the disclosed exemplary embodiment determines that the test value is inconsistent with the predicted value, it is necessary to screen out the memory chips that work normally to ensure product quality; if it is during the use of the system, the disclosed exemplary implementation can be used The method provides a pre-check whether the memory chip is working properly, predicts risks in advance, and prevents data loss due to read and write errors.
  • test data output port of the memory chip can be detected. Get the test value.
  • Each test value corresponds to a predicted value. As long as one of the multiple pairs of predicted values and test values is inconsistent with the predicted value, it can be determined that the memory chip is abnormal and needs to be processed accordingly.
  • the memory chip testing method can control the memory chip to enter the read-write clock equalization test mode by sending a mode register write command to the memory chip; after entering the read-write clock equalization test mode After waiting for the set first preset time, the read and write clock signals can be sent to the memory chip; then, the predicted value of the read and write clock balance can be determined based on the first preset time and the system clock cycle; using the predicted value and the test value at the memory chip test data output port can test whether there is an abnormality in the memory chip, thereby testing the read and write clock balancing function of the memory chip; in addition, by sending multiple read and write clock signals, it can be determined Multiple pairs of test values and predicted values can improve the accuracy of the read and write clock balancing function test.
  • the memory chip testing device 500 may include: a signal sending module 510, a prediction value determination module 520, a test value determination module 530 and a determination module 540, wherein:
  • the signal sending module 510 can be used to send a mode register write command to the memory chip, control the memory chip to enter the read and write clock equalization test mode; set the first preset time, wait for the first preset time, and then send the read command to the memory chip. write clock signal;
  • the predicted value determination module 520 may be used to determine the predicted value of read and write clock balance according to the first preset time and the system clock cycle;
  • the test value determination module 530 can be used to wait for the second preset time after sending the read and write clock signals, detect the test data output port of the memory chip, and obtain the test value;
  • the determination module 540 can be used to compare the test value and the predicted value to determine whether there is an abnormality in the memory chip.
  • the predicted value determination module 520 may be configured to use the corresponding value of tCK at the cutoff time point of the remaining time as the predicted value.
  • N is the quotient of the first preset time and the system clock cycle, rounded down.
  • the predicted value determination module 530 may be used to determine that the predicted value is 0 when tis>tCK*5/8 and tis ⁇ tCK*7/8; when tis>tCK/8 And when tis ⁇ tCK*3/8, the predicted value is determined to be 1.
  • the determination module 540 may be used to determine that there is an abnormality in the memory chip if the test value and the predicted value are inconsistent.
  • the read and write clock signal is a read and write clock signal that includes a cycle length of 7.5.
  • the second preset time is less than or equal to 20 ns.
  • modules or units of the memory test apparatus are mentioned in the above detailed description, this division is not mandatory.
  • the features and functions of two or more modules or units described above may be embodied in one module or unit.
  • the features and functions of one module or unit described above may be further divided into being embodied by multiple modules or units.
  • an electronic device capable of implementing the above method is also provided.
  • FIG. 6 An electronic device 600 according to this embodiment of the invention is described below with reference to FIG. 6 .
  • the electronic device 600 shown in FIG. 6 is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present invention.
  • electronic device 600 is embodied in the form of a general computing device.
  • the components of the electronic device 600 may include, but are not limited to: the above-mentioned at least one processing unit 610, the above-mentioned at least one storage unit 620, a bus 630 connecting different system components (including the storage unit 620 and the processing unit 610), and the display unit 640.
  • the storage unit 620 stores program code, and the program code can be executed by the processing unit 610, so that the processing unit 610 performs various examples according to the present invention described in the "Exemplary Method" section of this specification.
  • sexual implementation steps For example, the processing unit 610 can execute step S110 as shown in FIG. 1 to send a mode register write command to the memory chip and control the memory chip to enter the read-write clock equalization test mode; step S120 to set the first preset time.
  • Step S130 determine the predicted value of the read and write clock balance according to the first preset time and the system clock cycle
  • Step S140 after sending the read and write clock Wait for the second preset time, detect the test data output port of the memory chip, and obtain the test value
  • step S150 compare the test value and the predicted value to determine whether there is an abnormality in the memory chip.
  • the storage unit 620 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 6201 and/or a cache storage unit 6202, and may further include a read-only storage unit (ROM) 6203.
  • RAM random access storage unit
  • ROM read-only storage unit
  • Storage unit 620 may also include a program/utility 6204 having a set of (at least one) program modules 6206, such program modules 6205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, Each of these examples, or some combination, may include the implementation of a network environment.
  • Bus 630 may be a local area representing one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, a graphics acceleration port, a processing unit, or using any of a variety of bus structures. bus.
  • Electronic device 600 may also communicate with one or more external devices 670 (e.g., keyboard, pointing device, Bluetooth device, etc.), may also communicate with one or more devices that enable a user to interact with electronic device 600, and/or with Any device (eg, router, modem, etc.) that enables the electronic device 600 to communicate with one or more other computing devices. This communication may occur through input/output (I/O) interface 650.
  • the electronic device 600 may also communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN), and/or a public network, such as the Internet) through the network adapter 660. As shown, network adapter 660 communicates with other modules of electronic device 600 via bus 630.
  • network adapter 660 communicates with other modules of electronic device 600 via bus 630.
  • the example embodiments described here can be implemented by software, or can be implemented by software combined with necessary hardware. Therefore, the technical solution according to the embodiment of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to cause a computing device (which may be a personal computer, a server, a terminal device, a network device, etc.) to execute a method according to an embodiment of the present disclosure.
  • a computing device which may be a personal computer, a server, a terminal device, a network device, etc.
  • a computer-readable storage medium is also provided, on which a program product capable of implementing the method described above in this specification is stored.
  • various aspects of the present invention can also be implemented in the form of a program product, which includes program code.
  • the program product is run on a terminal device, the program code is used to cause the The terminal device performs the steps according to various exemplary embodiments of the present invention described in the "Exemplary Method" section above in this specification.
  • the program product for implementing the above method according to an embodiment of the present invention can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer.
  • a terminal device such as a personal computer.
  • the program product of the present invention is not limited thereto.
  • a readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, apparatus or device.
  • the program product may take the form of any combination of one or more readable media.
  • the readable medium may be a readable signal medium or a readable storage medium.
  • the readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave carrying readable program code therein. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.
  • a readable signal medium may also be any readable medium other than a readable storage medium that can send, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or device.
  • Program code embodied on a readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical cable, RF, etc., or any suitable combination of the foregoing.
  • Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., as well as conventional procedural Programming language—such as "C" or a similar programming language.
  • the program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server execute on.
  • the remote computing device may be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device, such as provided by an Internet service. (business comes via Internet connection).
  • LAN local area network
  • WAN wide area network

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Abstract

一种存储芯片测试方法及装置(500)、介质和电子设备(600)。该存储芯片测试方法包括：向存储芯片发送模式寄存器写入命令，控制存储芯片进入读写时钟均衡测试模式(S110)；设定第一预设时间，等待第一预设时间后，向存储芯片发送读写时钟信号(S120)；根据第一预设时间和系统时钟周期，确定读写时钟均衡的预测值(S130)；发完读写时钟信号后等待第二预设时间，检测存储芯片的测试数据输出端口，获取测试值(S140)；比较测试值和预测值，判断存储芯片是否存在异常(S150)。该方法能够保证产品质量，防止因读写错误而造成数据丢失，提高测试精度。

Description

存储芯片测试方法及装置、介质及设备
相关申请的交叉引用
本申请要求于2022年06月21日提交的申请号为202210709222.5、名称为“存储芯片测试方法及装置、介质及设备”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种存储芯片测试方法、存储芯片测试装置、计算机可读存储介质及电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由于具有结构简单，密度高，功耗低，价格低廉等优点，在计算机领域和电子行业中受到了广泛的应用。
LPDDR5(Low Power Double Data Rate 5，低功率双倍数据速率5)是DRAM中的一种设计规范，通常需要使用自动检测的方法对设计的芯片进行Wck2ck Leveling(write clock(WCK)to clock leveing，读写时钟均衡)等功能验证。
由于LPDDR5中，Wck2ck Leveling功能主要用来检测系统时钟CK和读写时钟WCK两者之间的相位关系，计算机很难直接测量两个时钟之间的相位而得到Wck2ck Leveling的验证结果。
发明内容
根据本公开的第一方面，提供一种存储芯片测试方法，所述方法包括：向存储芯片发送模式寄存器写入命令，控制所述存储芯片进入读写时钟均衡测试模式；设定第一预设时间，等待所述第一预设时间后，向所述存储芯片发送读写时钟信号；根据所述第一预设时间和系统时钟周期，确定所述读写时钟均衡的预测值；发完所述读写时钟信号后等待第二预设时间，检测所述存储芯片的测试数据输出端口，获取测试值；比较所述测试值和所述预测值，判断所述存储芯片是否存在异常。
在本公开的一种示例性实施方式中，所述设定第一预设时间，包括：设定所述第一预设时间的长度tWCKIS满足tWCKIS＝N*tCK+tis，其中，tCK为所述系统时钟周期，N为正整数，tis为剩余时间，所述剩余时间的截止时间点处于tCK的非上升沿且非下降沿区间。
在本公开的一种示例性实施方式中，所述根据所述第一预设时间和系统时钟周期，确定所述读写时钟均衡的预测值，包括：将处于所述剩余时间的截止时间点时对应的tCK的值作为所述预测值。
在本公开的一种示例性实施方式中，所述方法还包括：当tis>tCK*5/8且tis<tCK*7/8时，确定所述预测值为0；当tis>tCK/8且tis<tCK*3/8时，确定所述预测值为1。
在本公开的一种示例性实施方式中，所述比较所述测试值和所述预测值，判断所述存储芯片是否存在异常，包括：如果所述测试值和所述预测值不一致，则判定所述存储芯片存在异常。
在本公开的一种示例性实施方式中，所述读写时钟信号为包含7.5个周期长度的读写时钟信号。
在本公开的一种示例性实施方式中，所述第二预设时间小于或等于20ns。
根据本公开的第二方面，提供一种存储芯片测试装置，所述装置包括：信号发送模块，用于向存储芯片发送模式寄存器写入命令，控制所述存储芯片进入读写时钟均衡测试模式；设定第一预设时间，等待所述第一预设时间后，向所述存储芯片发送读写时钟信号；预测 值确定模块，用于根据所述第一预设时间和系统时钟周期，确定所述读写时钟均衡的预测值；测试值确定模块，用于发完所述读写时钟信号后等待第二预设时间，检测所述存储芯片的测试数据输出端口，获取测试值；判定模块，用于比较所述测试值和所述预测值，判断所述存储芯片是否存在异常。
在本公开的一种示例性实施方式中，所述信号发送模块，用于设定所述第一预设时间的长度tWCKIS满足tWCKIS＝N*tCK+tis，其中，tCK为所述系统时钟周期，N为正整数，tis为剩余时间，所述剩余时间的截止时间点处于tCK的非上升沿且非下降沿区间。
在本公开的一种示例性实施方式中，所述预测值确定模块，用于将处于所述剩余时间的截止时间点时对应的tCK的值作为所述预测值。
在本公开的一种示例性实施方式中，所述预测值确定模块，用于当tis>tCK*5/8且tis<tCK*7/8时，确定所述预测值为0；当tis>tCK/8且tis<tCK*3/8时，确定所述预测值为1。
在本公开的一种示例性实施方式中，所述判定模块，用于如果所述测试值和所述预测值不一致，则判定所述存储芯片存在异常。
在本公开的一种示例性实施方式中，所述读写时钟信号为包含7.5个周期长度的读写时钟信号。
在本公开的一种示例性实施方式中，所述第二预设时间小于或等于20ns。
根据本公开的第三方面，提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现上述的存储芯片测试方法。
根据本公开的第四方面，提供一种电子设备，包括：处理器；以及存储器，用于存储所述处理器的可执行指令；其中，所述处理器配置为经由执行所述可执行指令来执行上述的存储芯片测试方法。
附图说明
图1示意性示出了根据本公开的示例性实施例的一种存储芯片测试方法的流程图；
图2示意性示出了根据本公开的示例性实施例的一种读写时钟均衡功能时序图一；
图3示意性示出了根据本公开的示例性实施例的读写时钟均衡功能时序图二；
图4示意性示出了根据本公开的示例性实施例的参考值与预测值的对应关系图；
图5示意性示出了根据本公开的示例性实施例的一种存储芯片测试装置的方框图；
图6示意性示出了根据本公开的示例性实施例的一种电子设备的模块示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
附图中所示的流程图仅是示例性说明，不是必须包括所有的步骤。例如，有的步骤还可以分解，而有的步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。另外，下面所有的术语“第一”、“第二”、“第三”仅是为了区分的目的，不应作为本公开内容的限制。
半导体存储芯片用于计算机、服务器、诸如移动电话等手持设备、打印机和许多其他电子设备和应用。半导体存储芯片在存储阵列中包括多个存储单元，每个存储单元存储信息的至少一位。DRAM为这种半导体存储器的实例。本方案优选地用于DRAM中。因此，接下来的实施例描述是参考作为非限制性示例的DRAM进行的。
在DRAM集成电路设备中，特别是LPDDR5 DRAM中，无论是在设计阶段、测试阶段，还是在使用阶段，都需要使用自动检测的方法对存储芯片进行功能验证，例如，进行写功能、读功能、刷新功能、Command Bus Training(命令总线训练)功能，以及Wck2ck Leveling读写时钟均衡等功能进行验证。
除了在LPDDR5的设计过程中进行上述的功能验证之外，在LPDDR5的测试过程中，需要对存储芯片的Wck2ck Leveling进行功能测试，筛选出工作正常的芯片。另外，在LPDDR5的使用过程中，需要对存储芯片的Wck2ck Leveling能否正常工作进行自动检测，防止系统读写出错。
基于此，本公开示例性实施方式提供了一种对存储芯片的读写时钟均衡Wck2ck Leveling功能进行测试的存储芯片测试方法。参照图1，该存储芯片测试方法包括：
步骤S110，向存储芯片发送模式寄存器写入命令，控制存储芯片进入读写时钟均衡测试模式；
步骤S120，设定第一预设时间，等待第一预设时间后，向存储芯片发送读写时钟信号；
步骤S130，根据第一预设时间和系统时钟周期，确定读写时钟均衡的预测值；
步骤S140，发完读写时钟后等待第二预设时间，检测存储芯片的测试数据输出端口，获取测试值；
步骤S150，比较测试值和预测值，判断存储芯片是否存在异常。
本公开示例性实施方式提供的存储芯片测试方法中，通过向存储芯片发送模式寄存器写入命令，可以控制存储芯片进入读写时钟均衡测试模式；在进入读写时钟均衡测试模式后等待第一预设时间，可以向存储芯片发送读写时钟；接着，可以根据设定的第一预设时间和系统时钟周期就可以确定出读写时钟均衡的预测值；利用该预测值和存储芯片的测试数据输出端口处的测试值就可以对存储芯片是否存在异常进行判断，从而实现对存储芯片的读写时钟均衡功能的测试。
下面将结合实施例对本公开示例性实施方式提供的存储芯片测试方法进行详细说明：
在步骤S110中，向存储芯片发送模式寄存器写入命令，控制存储芯片进入读写时钟均衡测试模式。
本公开示例性实施方式中，模式寄存器写入命令MRW Command是用来向DRAM的模式寄存器写数据的。模式寄存器写入命令是通过时钟使能CKE信号，芯片选择CS信号以及命令/地址信号，如CA[5:0](CA信号的集合可以被标记为CA[5:0])的配合完成。模式寄存器的地址以及数据都是通过CA[5:0]来传达。模式寄存器写入命令的周期时间由tMRW参数控制的。
在实际应用中，向存储芯片发送模式寄存器写入命令是由存储芯片控制器执行的，例如，是LPDDR5 DRAM Controller向LPDDR5 DRAM发送模式寄存器写入命令。
本公开示例性实施方式中，通过存储芯片控制器向存储芯片发送模式寄存器写入命令，可以控制存储芯片进入到读写时钟均衡测试模式，即进入Wck2ck Leveling模式。其中，Wck2ck Leveling模式是对存储芯片的Wck2ck Leveling功能，即读写时钟均衡功能进行测试的模式。
具体的，读写时钟均衡功能主要是用来检测系统时钟CK和读写时钟WCK两者之间相位关系的功能，通过检测系统时钟CK和读写时钟WCK两者之间的相位关系，可以确定存储芯片的时序是否运行正常。
本公开示例性实施方式中，在存储芯片进入到读写时钟均衡测试模式之后，就可以对存储芯片的读写时钟均衡测试功能进行测试，以确定存储芯片是否存在异常。
在步骤S120中，设定第一预设时间，等待第一预设时间后，向存储芯片发送读写时钟信号。
本公开示例性实施方式中，第一预设时间是需要提前设定的，以确保根据第一预设时间和系统时钟周期所确定的读写时钟均衡的预测值为一个固定不变值，从而便于使用固定的预测值与测试值进行比较。
参照图2所示的读写时钟均衡功能时序图可以看出，在存储芯片控制器向存储芯片发送模式寄存器写入命令MRW-1之后，至系统时钟CK的T3时刻，再等待tWLMRD时间后，存储芯片控制器开始向存储芯片发送读写时钟信号WCK。因此，第一预设时间是向存储芯片发送模式寄存器写入命令MRW-1至系统时钟CK的T3时刻的时间段与tWLMRD时间之和。
本公开示例性实施方式中，可以将第一预设时间的长度tWCKIS设定为满足tWCKIS＝N*tCK+tis，其中，tCK为系统时钟周期，N为正整数，tis为剩余时间，并且，剩余时间的截止时间点处于tCK的非上升沿且非下降沿区间。由于剩余时间的截止时间点既不处于系统时钟周期tCK的上升沿，也不处于系统时钟周期tCK的下降沿，因此，剩余时间的截止时间点所对应的系统时钟周期tCK就是确定的0或者确定的1，不存在0到1或1到0转换的情况。
在实际应用中，所发送的读写时钟信号WCK的频率是系统时钟CK的频率的两倍，在一次所发送的读写时钟信号WCK的长度中，包含有7.5个周期长度的读写时钟信号。其中，读写时钟信号WCK是在读写时均会使用到的时钟信号。
在步骤S130中，根据第一预设时间和系统时钟周期，确定读写时钟均衡的预测值。
本公开示例性实施方式中，存储芯片从收到模式寄存器写入命令起，就进入到了读写时钟均衡测试模式，在等待第一预设时间发送读写时钟信号后，从收到模式寄存器写入命令到收到读写时钟信号的第一个上升沿的时间间隔tWCKIS就是第一预设时间，根据该第一预设时间就可以计算读写时钟均衡的预测值。
在实际应用中，存储芯片在收到模式寄存器写入命令后，通常会多次收到存储芯片控制器发送的读写时钟信号，例如，参照图3所示的发送多个读写时钟时的时序图所示，存储芯片在收到模式寄存器写入命令后，还陆续收到了三个读写时钟信号，即第一读写时钟信号、第二读写时钟信号和第三读写时钟信号。
存储芯片从收到模式寄存器写入命令到收到第一读写时钟信号的第一个上升沿的第一预设时间可以标记为tWCKIS1，存储芯片从收到模式寄存器写入命令到收到第二读写时钟信号的第一个上升沿的第一预设时间可以标记为tWCKIS2，存储芯片从收到模式寄存器写入命令到收到第三读写时钟信号的第一个上升沿的第一预设时间可以标记为tWCKIS3。这三个第一预设时间的起点相同，但终点不同，第三个第一预设时间tWCKIS3大于第二个第一预设时间tWCKIS2，第二个第一预设时间tWCKIS2大于第一个第一预设时间tWCKIS1。
本公开示例性实施方式中，根据预先设定的第一预设时间tWCKIS可知，其为N倍的系统时钟周期tCK与剩余时间tis之和，也就是说，第一预设时间tWCKIS减去N倍的系统时钟周期tCK后，还有剩余时间tis，本公开实施例将处于剩余时间的截止时间点时对应的tCK的值作为读写时钟均衡的预测值，也就是将剩余时间tis的截止时间点对应的系统时钟周期tCK的值确定为预测值。该预测值为确定的0或者确定的1。
以下对预测值的具体取值的确定进行详细说明：
本公开示例性实施方式中，在确定预测值的过程中，可以先根据第一预设时间tWCKIS和系统时钟周期tCK，确定出剩余时间tis，再根据剩余时间tis所在的范围，确定读写时钟均衡的预测值的具体取值。其中，上述的剩余时间tis所在的范围可以由系统时钟周期tCK来确定。读写时钟信号WCK上升沿的位置可以代表读写时钟均衡tWCK2CK的值，将tWCK2CK映射到剩余时间tis上，就可以使用剩余时间tis判断读写时钟信号WCK上升沿所在的具体位置。
本公开示例性实施方式中，在根据第一预设时间tWCKIS和系统时钟周期tCK确定剩余时间tis的过程中，可以将第一预设时间tWCKIS和系统时钟周期tCK的商值向下取整[tWCKIS/tCK]，将[tWCKIS/tCK]确定为上述的N。也就是说，N为第一预设时间与系统时钟周期的商值向下取整。
那么，剩余时间tis＝tWCKIS-[tWCKIS/tCK]*tCK。
在确定出剩余时间tis后，就可以根据剩余时间tis所在的范围，确定预测值。本公开示例性实施方式中，参考图4，根据剩余时间tis所在的范围确定的预测值DQ如下：
当tis>tCK*5/8且tis<tCK*7/8时，确定预测值DQ为0；
当tis>tCK/8且tis<tCK*3/8时，确定预测值DQ为1；
当0<tis<tCK/8、或者3/8*tCK<tis<tCK*5/8、或者7/8*tCK<tis<tCK时，确定预测值DQ为0或1。
其中，预测值为0表示读写时钟信号WCK的上升沿在所在区间内的值均为0，预测值为1表示读写时钟信号WCK的上升沿在所在区间内的值均为1，预测值为0/1表示读写时钟信号WCK的上升沿在所在区间内的某一点预测值DQ会出现由0到1或者由1到0的翻转。根据标准规定，如果翻转点落在-1/8tCK到1/8tCK之间，则存储芯片的设计是满足要求的。
需要说明的是，前述通过设定第一预设时间，以使读写时钟均衡的预测值为固定值，指的就是通过设定第一预设时间，使得预测值DQ为确定的0或确定的1，也就是使得剩余时间tis所在的范围满足tis>tCK*5/8且tis<tCK*7/8，或者满足tis>tCK/8且tis<tCK*3/8。因此，可以根据剩余时间tis的范围来确定所设定的第一预设时间的大小。
在如图3所示发送多个读写时钟的情况下，可以计算每个读写时钟所对应的读写时钟均衡的预测值。具体可以先确定剩余时间tis，将剩余时间tis公式里面的第一预设时间tWCKIS分别替换为第一读写时钟对应的第一个第一预设时间tWCKIS1、第二读写时钟对应的第二个第一预设时间tWCKIS2、第三读写时钟对应的第三个第一预设时间tWCKIS3。不同的读写时钟信号可以获得不同的剩余时间tis1、tis2、tis3……，再根据不同的剩余时间所在的范围，确定读写时钟均衡的预测值。每一个读写时钟信号均对应有一个读写时钟均衡的预测值。所获得的多个读写时钟信号对应的读写时钟均衡的预测值均可以用于对存储芯片是否存在异常进行预测。
在步骤S140中，发完读写时钟信号后等待第二预设时间，检测存储芯片的测试数据输出端口，获取测试值。
如图2所示，在发完读写时钟信号WCK，也就是在发完7.5个01翻转toggle之后，再等待第二预设时间tWLO后，可以通过检测存储芯片的数据端口，来获取测试值。
在本公开示例性实施方式中，在第二预设时间tWLO之前通常会得到实验结果，并保持。但在实际应用中，存储芯片的实验结果出来的时间点是不确定的，或早或晚，对于tWLO就规定了一个最晚时间，就是最晚要在tWLO之前必须出结果，tWLO之后都是保持前面的结果的值。
在实际应用中，第二预设时间tWLO不是固定值，通常会规定一个最大值为20ns，因此，本公开示例性实施方式中，第二预设时间tWLO小于或等于20ns。例如，在发完读写 时钟后等待20ns之后，可以通过检测存储芯片的数据端口获取测试值。
步骤S150，比较测试值和预测值，判断存储芯片是否存在异常。
本公开示例性实施方式中，在通过存储芯片的测试数据输出端口获取到测试值之后，就可以结合之前所确定的读写时钟均衡的预测值对存储芯片是否存在异常进行判断。
具体的，如果从存储芯片的测试数据输出端口获得的测试值与预测值不一致，则可以判定存储芯片存在异常。如果是在验证过程中，运用本公开示例性实施方式提供的存储芯片测试方法确定出测试值与预测值不一致，则需要寻找原因并更改存储芯片的电路设计；如果是在测试过程中，运用本公开示例性实施方式提供的存储芯片测试方法确定出测试值与预测值不一致，则需要筛选出正常工作的存储芯片，以保证产品质量；如果是在系统使用过程中，可以运用本公开示例性实施方式提供的预先检查存储芯片是否正常工作，提前预知风险，防止因为读写错误而造成数据丢失。
对于如图3所示具有多个读写时钟的情况而言，每个读写时钟在发完之后，再等待第二预设时间tWLO后，均可以通过检测存储芯片的测试数据输出端口，来获取到测试值。每个测试值均对应有一个预测值，只要多对预测值和测试值中，有一对测试值和预测值不一致，即可判定存储芯片存在异常，需要进行相应的处理。
综上所述，本公开示例性实施方式提供的存储芯片测试方法，通过向存储芯片发送模式寄存器写入命令，可以控制存储芯片进入读写时钟均衡测试模式；在进入读写时钟均衡测试模式后等待设定的第一预设时间，可以向存储芯片发送读写时钟信号；接着，可以根据该第一预设时间和系统时钟周期就可以确定出读写时钟均衡的预测值；利用该预测值和存储芯片测试数据输出端口处的测试值就可以对存储芯片是否存在异常进行测试，从而实现对存储芯片的读写时钟均衡功能的测试；另外，通过发送多次读写时钟信号，可以确定出多对测试值和预测值，可以提高读写时钟均衡功能测试的精度。
需要说明的是，尽管在附图中以特定顺序描述了本发明中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
此外，在本示例实施例中，还提供了一种存储芯片测试装置。参照图5，该存储芯片测试装置500可以包括：信号发送模块510、预测值确定模块520、测试值确定模块530和判定模块540，其中：
信号发送模块510，可以用于向存储芯片发送模式寄存器写入命令，控制存储芯片进入读写时钟均衡测试模式；设定第一预设时间，等待第一预设时间后，向存储芯片发送读写时钟信号；
预测值确定模块520，可以用于根据第一预设时间和系统时钟周期，确定读写时钟均衡的预测值；
测试值确定模块530，可以用于发完读写时钟信号后等待第二预设时间，检测存储芯片的测试数据输出端口，获取测试值；
判定模块540，可以用于比较测试值和预测值，判断存储芯片是否存在异常。
在本公开的一种示例性实施方式中，信号发送模块510可以用于设定第一预设时间的长度tWCKIS满足tWCKIS＝N*tCK+tis，其中，tCK为系统时钟周期，N为正整数，tis为剩余时间，剩余时间的截止时间点处于tCK的非上升沿且非下降沿区间。
在本公开的一种示例性实施方式中，预测值确定模块520可以用于将处于剩余时间的截止时间点时对应的tCK的值作为预测值。
在本公开的一种示例性实施方式中，N为第一预设时间与系统时钟周期的商值向下取整。
在本公开的一种示例性实施方式中，预测值确定模块530可以用于当tis>tCK*5/8且 tis<tCK*7/8时，确定预测值为0；当tis>tCK/8且tis<tCK*3/8时，确定预测值为1。
在本公开的一种示例性实施方式中，判定模块540可以用于如果测试值和预测值不一致，则判定存储芯片存在异常。
在本公开的一种示例性实施方式中，读写时钟信号为包含7.5个周期长度的读写时钟信号。
在本公开的一种示例性实施方式中，第二预设时间小于或等于20ns。
上述中各存储芯片测试装置的虚拟模块的具体细节已经在对应的存储器测试方法中进行了详细的描述，因此，此处不再赘述。
应当注意，尽管在上文详细描述中提及了存储器测试装置的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
在本公开的示例性实施例中，还提供了一种能够实现上述方法的电子设备。
所属技术领域的技术人员能够理解，本发明的各个方面可以实现为系统、方法或程序产品。因此，本发明的各个方面可以具体实现为以下形式，即：完全的硬件实施方式、完全的软件实施方式(包括固件、微代码等)，或硬件和软件方面结合的实施方式，这里可以统称为“电路”、“模块”或“系统”。
下面参照图6来描述根据本发明的这种实施方式的电子设备600。图6显示的电子设备600仅仅是一个示例，不应对本发明实施例的功能和使用范围带来任何限制。
如图6所示，电子设备600以通用计算设备的形式表现。电子设备600的组件可以包括但不限于：上述至少一个处理单元610、上述至少一个存储单元620、连接不同系统组件(包括存储单元620和处理单元610)的总线630、显示单元640。
其中，所述存储单元620存储有程序代码，所述程序代码可以被所述处理单元610执行，使得所述处理单元610执行本说明书上述“示例性方法”部分中描述的根据本发明各种示例性实施方式的步骤。例如，所述处理单元610可以执行如图1中所示的步骤S110，向存储芯片发送模式寄存器写入命令，控制存储芯片进入读写时钟均衡测试模式；步骤S120，设定第一预设时间，等待第一预设时间后，向存储芯片发送读写时钟信号；步骤S130，根据第一预设时间和系统时钟周期，确定读写时钟均衡的预测值；步骤S140，发完读写时钟后等待第二预设时间，检测存储芯片的测试数据输出端口，获取测试值；步骤S150，比较测试值和预测值，判断存储芯片是否存在异常。
存储单元620可以包括易失性存储单元形式的可读介质，例如随机存取存储单元(RAM)6201和/或高速缓存存储单元6202，还可以进一步包括只读存储单元(ROM)6203。
存储单元620还可以包括具有一组(至少一个)程序模块6206的程序/实用工具6204，这样的程序模块6205包括但不限于：操作系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或某种组合中可能包括网络环境的实现。
总线630可以为表示几类总线结构中的一种或多种，包括存储单元总线或者存储单元控制器、外围总线、图形加速端口、处理单元或者使用多种总线结构中的任意总线结构的局域总线。
电子设备600也可以与一个或多个外部设备670(例如键盘、指向设备、蓝牙设备等)通信，还可与一个或者多个使得用户能与该电子设备600交互的设备通信，和/或与使得该电子设备600能与一个或多个其它计算设备进行通信的任何设备(例如路由器、调制解调器等等)通信。这种通信可以通过输入/输出(I/O)接口650进行。并且，电子设备600还可以通过网络适配器660与一个或者多个网络(例如局域网(LAN)，广域网(WAN)和/或公共网络，例如因特网)通信。如图所示，网络适配器660通过总线630与电子设备600的其它模块通信。应当明白，尽管图中未示出，可以结合电子设备600使用其它硬件 和/或软件模块，包括但不限于：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、RAID系统、磁带驱动器以及数据备份存储系统等。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、终端装置、或者网络设备等)执行根据本公开实施方式的方法。
在本公开的示例性实施例中，还提供了一种计算机可读存储介质，其上存储有能够实现本说明书上述方法的程序产品。在一些可能的实施方式中，本发明的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当所述程序产品在终端设备上运行时，所述程序代码用于使所述终端设备执行本说明书上述“示例性方法”部分中描述的根据本发明各种示例性实施方式的步骤。
根据本发明的实施方式的用于实现上述方法的程序产品，其可以采用便携式紧凑盘只读存储器(CD-ROM)并包括程序代码，并可以在终端设备，例如个人电脑上运行。然而，本发明的程序产品不限于此，在本文件中，可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
所述程序产品可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以为但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可读程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。可读信号介质还可以是可读存储介质以外的任何可读介质，该可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于无线、有线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言的任意组合来编写用于执行本发明操作的程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、C++等，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算设备，或者，可以连接到外部计算设备(例如利用因特网服务提供商来通过因特网连接)。
此外，上述附图仅是根据本发明示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指 出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (16)

  1. 一种存储芯片测试方法，所述方法包括：
    向存储芯片发送模式寄存器写入命令，控制所述存储芯片进入读写时钟均衡测试模式；
    设定第一预设时间，等待所述第一预设时间后，向所述存储芯片发送读写时钟信号；
    根据所述第一预设时间和系统时钟周期，确定所述读写时钟均衡的预测值；
    发完所述读写时钟信号后等待第二预设时间，检测所述存储芯片的测试数据输出端口，获取测试值；
    比较所述测试值和所述预测值，判断所述存储芯片是否存在异常。
  2. 根据权利要求1所述的方法，其中，所述设定第一预设时间，包括：
    设定所述第一预设时间的长度tWCKIS满足tWCKIS＝N*tCK+tis，其中，tCK为所述系统时钟周期，N为正整数，tis为剩余时间，所述剩余时间的截止时间点处于tCK的非上升沿且非下降沿区间。
  3. 根据权利要求2所述的方法，其中，所述根据所述第一预设时间和系统时钟周期，确定所述读写时钟均衡的预测值，包括：
    将处于所述剩余时间的截止时间点时对应的tCK的值作为所述预测值。
  4. 根据权利要求2或3所述的方法，其中，所述方法还包括：
    当tis>tCK*5/8且tis<tCK*7/8时，确定所述预测值为0；
    当tis>tCK/8且tis<tCK*3/8时，确定所述预测值为1。
  5. 根据权利要求1所述的方法，其中，所述比较所述测试值和所述预测值，判断所述存储芯片是否存在异常，包括：
    如果所述测试值和所述预测值不一致，则判定所述存储芯片存在异常。
  6. 根据权利要求1所述的方法，其中，所述读写时钟信号为包含7.5个周期长度的读写时钟信号。
  7. 根据权利要求1所述的方法，其中，所述第二预设时间小于或等于20ns。
  8. 一种存储芯片测试装置，所述装置包括：
    信号发送模块，用于向存储芯片发送模式寄存器写入命令，控制所述存储芯片进入读写时钟均衡测试模式；设定第一预设时间，等待所述第一预设时间后，向所述存储芯片发送读写时钟信号；
    预测值确定模块，用于根据所述第一预设时间和系统时钟周期，确定所述读写时钟均衡的预测值；
    测试值确定模块，用于发完所述读写时钟信号后等待第二预设时间，检测所述存储芯片的测试数据输出端口，获取测试值；
    判定模块，用于比较所述测试值和所述预测值，判断所述存储芯片是否存在异常。
  9. 根据权利要求8所述的装置，其中，所述信号发送模块，用于设定所述第一预设时间的长度tWCKIS满足tWCKIS＝N*tCK+tis，其中，tCK为所述系统时钟周期，N为正整数，tis为剩余时间，所述剩余时间的截止时间点处于tCK的非上升沿且非下降沿区间。
  10. 根据权利要求9所述的装置，其中，所述预测值确定模块，用于将处于所述剩余时间的截止时间点时对应的tCK的值作为所述预测值。
  11. 根据权利要求9或10所述的装置，其中，所述预测值确定模块，用于当tis>tCK*5/8且tis<tCK*7/8时，确定所述预测值为0；当tis>tCK/8且tis<tCK*3/8时，确定所述预测值为1。
  12. 根据权利要求8所述的装置，其中，所述判定模块，用于如果所述测试值和所述预测值不一致，则判定所述存储芯片存在异常。
  13. 根据权利要求8所述的装置，其中，所述读写时钟信号为包含7.5个周期长度的 读写时钟信号。
  14. 根据权利要求8所述的装置，其中，所述第二预设时间小于或等于20ns。
  15. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1-7中任意一项所述的存储芯片测试方法。
  16. 一种电子设备，包括：
    处理器；以及
    存储器，用于存储所述处理器的可执行指令；
    其中，所述处理器配置为经由执行所述可执行指令来执行权利要求1-7中任意一项所述的存储芯片测试方法。
PCT/CN2022/105255 2022-06-21 2022-07-12 存储芯片测试方法及装置、介质及设备 WO2023245762A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291400A (ja) * 2000-04-07 2001-10-19 Mitsubishi Electric Corp 半導体メモリ用のテスト回路
CN105654993A (zh) * 2016-02-22 2016-06-08 深圳市同创国芯电子有限公司 用于ddr3 sdram控制器的功能验证方法及平台
CN109697996A (zh) * 2017-10-23 2019-04-30 爱思开海力士有限公司 半导体器件及其操作方法
CN113223566A (zh) * 2021-05-21 2021-08-06 长江先进存储产业创新中心有限责任公司 存储器的控制系统及其控制方法
CN114155903A (zh) * 2020-09-07 2022-03-08 长鑫存储技术有限公司 测试系统以及测试方法
CN114333965A (zh) * 2020-09-30 2022-04-12 长鑫存储技术有限公司 存储器和存储器的测试方法
CN114627947A (zh) * 2020-12-14 2022-06-14 三星电子株式会社 半导体存储器装置和包括半导体存储器装置的测试系统

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291400A (ja) * 2000-04-07 2001-10-19 Mitsubishi Electric Corp 半導体メモリ用のテスト回路
CN105654993A (zh) * 2016-02-22 2016-06-08 深圳市同创国芯电子有限公司 用于ddr3 sdram控制器的功能验证方法及平台
CN109697996A (zh) * 2017-10-23 2019-04-30 爱思开海力士有限公司 半导体器件及其操作方法
CN114155903A (zh) * 2020-09-07 2022-03-08 长鑫存储技术有限公司 测试系统以及测试方法
CN114333965A (zh) * 2020-09-30 2022-04-12 长鑫存储技术有限公司 存储器和存储器的测试方法
CN114627947A (zh) * 2020-12-14 2022-06-14 三星电子株式会社 半导体存储器装置和包括半导体存储器装置的测试系统
CN113223566A (zh) * 2021-05-21 2021-08-06 长江先进存储产业创新中心有限责任公司 存储器的控制系统及其控制方法

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