WO2023240752A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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Publication number
WO2023240752A1
WO2023240752A1 PCT/CN2022/108097 CN2022108097W WO2023240752A1 WO 2023240752 A1 WO2023240752 A1 WO 2023240752A1 CN 2022108097 W CN2022108097 W CN 2022108097W WO 2023240752 A1 WO2023240752 A1 WO 2023240752A1
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Prior art keywords
groove
substrate
sacrificial layer
layer
insulating layer
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English (en)
French (fr)
Inventor
冯道欢
李晓杰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US18/093,969 priority Critical patent/US12439583B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a method of manufacturing a semiconductor structure and a semiconductor structure.
  • Fin Field-Effect Transistors are usually provided in the manufacturing method of semiconductor structures.
  • Fin field effect transistors include a fin structure and a gate structure arranged on a substrate.
  • the gate structure surrounds and surrounds the fin structure, and then forms a channel region in the area where the fin structure is covered by the gate structure.
  • the source and drain regions are located on both sides of the channel region.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including:
  • Part of the intermediate structure and part of the substrate are removed to form a fin structure.
  • forming a groove in the substrate includes:
  • a portion of the substrate is etched along the first opening to form the groove.
  • forming a barrier layer on the sidewall of the groove includes:
  • the second sacrificial layer located at the bottom of the groove is removed, and the second sacrificial layer located at the sidewall of the groove constitutes the barrier layer.
  • forming a second sacrificial layer on the sidewalls and bottom of the groove includes:
  • a second insulating layer is formed on the first insulating layer, and the first insulating layer and the second insulating layer constitute the second sacrificial layer.
  • removing the second sacrificial layer located at the bottom of the groove includes:
  • anisotropic dry etching to remove the second insulating layer located at the bottom of the groove
  • the substrate is cleaned with a cleaning solution to remove the first insulating layer located at the bottom of the groove.
  • the first sacrificial layer and the second sacrificial layer also cover the substrate;
  • the second sacrificial layer located on the substrate is removed.
  • forming a first sacrificial layer on the substrate includes: in a possible implementation, the first sacrificial layer includes a third insulating layer, a fourth insulating layer and a fifth Insulating layer, the third insulating layer covers the surface of the substrate, the fourth insulating layer is located between the third insulating layer and the fifth insulating layer, the fifth insulating layer covers the surface of the substrate. A side of the fourth insulating layer facing away from the substrate.
  • epitaxially growing a channel material based on the groove bottom of the groove to form an intermediate structure in the groove also includes:
  • the channel material protrudes from the groove
  • Part of the channel material and the fifth insulating layer on the substrate are removed through a chemical mechanical polishing process to form the intermediate structure, and the top surface of the intermediate structure is flush with the fourth insulating layer. flat.
  • removing part of the intermediate structure and part of the substrate includes:
  • the intermediate structure and the substrate are etched using the third sacrificial layer as a mask to form the fin structure.
  • forming a third sacrificial layer on the intermediate structure, and patterning the third sacrificial layer includes:
  • the third sacrificial layer is etched using the sacrificial sidewall as a mask to form an etching pattern.
  • the method further includes:
  • An isolation layer is formed on the bottom sidewall of the fin structure and the substrate surface.
  • the present disclosure also provides a semiconductor structure formed according to the above-mentioned manufacturing method of a semiconductor structure, including: a substrate, and fin structures spaced apart above the substrate.
  • each of the fin structures includes an upper structure and a lower structure, and the upper structure and the lower structure are made of different materials.
  • the semiconductor structure further includes an isolation layer, the top surface of the isolation layer is higher than the bottom surface of the upper structure, the isolation layer covers the surface of the substrate, and covers the The bottom side of the fin structure.
  • Embodiments of the present disclosure provide a manufacturing method of a semiconductor structure and a semiconductor structure.
  • the manufacturing method of a semiconductor structure includes: providing a substrate, forming a groove in the substrate; forming a barrier layer on the sidewall of the groove; based on the groove
  • the channel material is epitaxially grown at the bottom of the groove to form an intermediate structure within the groove; part of the intermediate structure and part of the substrate are removed to form a fin structure.
  • the embodiment of the present disclosure uses the channel material grown on the bottom of the groove to form a fin structure with a stable internal lattice arrangement, which is beneficial to improving the performance of the transistor.
  • Figure 1 is a step flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a substrate provided in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram of forming grooves in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 5 is a schematic structural diagram of forming a second sacrificial layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 6 is a schematic structural diagram of forming a barrier layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 7 is a schematic structural diagram of filling channel materials in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 8 is a schematic structural diagram of removing part of the channel material through a chemical mechanical polishing process in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 9 is a schematic structural diagram of forming a third sacrificial layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of forming a second photoresist layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 12 is a schematic structural diagram of forming a fourth sacrificial layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 14 is a schematic structural diagram of removing the mask block in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 15 is a schematic structural diagram of a dielectric block formed in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 16 is a schematic structural diagram of a fin structure formed in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 17 is a schematic structural diagram of forming an isolation material in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 18 is a schematic structural diagram of forming an isolation layer in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
  • the manufacturing process of fin structures in semiconductor structures is usually divided into two types: Gate-first (gate first) process school and Gate-last (gate last) process school.
  • the Gate-first process has the advantages of relatively simple manufacturing steps, low manufacturing cost, and good heat resistance of the semiconductor structure produced. Therefore, it is widely used in DRAM (Dynamic Random Access Memory, Dynamic Random Access Memory).
  • DRAM Dynamic Random Access Memory
  • the fin structure in Random Access Memory is being produced.
  • the steps of using the gate-first process to make a fin structure include: after forming a groove on the substrate, growing silicon germanium based on the two sidewalls and the bottom surface of the groove, and then removing part of the substrate and part of the silicon germanium to form the fin structure .
  • the inventor of the present application discovered during actual research that the lattice structure of silicon germanium formed based on the growth of the above three faces is relatively chaotic, which in turn leads to poor performance of the formed transistor.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure.
  • the manufacturing method of the semiconductor structure includes: providing a substrate, forming a groove in the substrate; forming a barrier layer on the sidewall of the groove; epitaxially growing a channel material based on the bottom of the groove to form an intermediate structure in the groove ;Remove part of the intermediate structure and part of the substrate to form a fin structure.
  • the embodiment of the present disclosure is based on the growth of channel material on the bottom of the groove.
  • the internal lattice arrangement of the formed fin structure is stable, which is conducive to improving the performance of the transistor. performance.
  • a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:
  • S101 Provide a substrate and form a groove in the substrate.
  • a semiconductor structure includes a substrate 10 .
  • the substrate 10 can provide a structural basis for subsequent structures and processes.
  • the material of the substrate 10 can include any one or more of silicon, germanium, silicon germanium, silicon carbide, silicon-on-insulator substrate 10 and germanium-on-insulator substrate 10 By.
  • the material of the substrate 10 may be silicon.
  • the step of forming the groove 101 in the substrate 10 includes: forming a first sacrificial layer 20 on the substrate 10 , and etching the first sacrificial layer 20 to form a first opening 201 .
  • the first sacrificial layer 20 is formed on the substrate 10 , including: the first sacrificial layer 20 includes a third insulating layer 21 , a fourth insulating layer 22 and a fifth insulating layer 23 , where the third insulating layer 21 Covering the surface of the substrate 10 , the fourth insulating layer 22 is located between the third insulating layer 21 and the fifth insulating layer 23 .
  • the fifth insulating layer 23 covers the side of the fourth insulating layer 22 facing away from the substrate 10 .
  • the material of the first sacrificial layer 20 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride, for example, the material of the third insulating layer 21 and the fifth insulating layer 23
  • the material may be silicon oxide
  • the fourth insulating layer 22 may be made of silicon nitride.
  • the first sacrificial layer 20 may also include other insulating structures, which are not specifically limited in the embodiments of the present disclosure.
  • the step of etching the first sacrificial layer 20 to form the first opening 201 includes: forming a first photoresist layer 301 on the first sacrificial layer 20 , and the first photoresist layer 301 has a first photolithography pattern to The first photoresist layer 301 is used as a mask to etch the first sacrificial layer 20 to form the first opening 201 .
  • the step of forming the groove 101 in the substrate 10 further includes etching a portion of the substrate 10 along the first opening 201 to form the groove 101 .
  • a wet etching or dry etching process can be used to remove part of the substrate 10 using the first sacrificial layer 20 as a mask.
  • the formed grooves 101 provide a structural basis for subsequent structures and processes.
  • the step of forming the barrier layer 401 on the sidewall of the groove 101 includes: forming a second sacrificial layer 40 on the sidewall of the groove 101 and the bottom of the groove.
  • forming the second sacrificial layer 40 on the side walls and bottom of the groove 101 includes: forming a first insulating layer 41 on the side walls and bottom of the groove 101; forming a third insulating layer 41 on the first insulating layer 41.
  • the two insulating layers 42 , the first insulating layer 41 and the second insulating layer 42 constitute the second sacrificial layer 40 .
  • the material of the second sacrificial layer 40 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride.
  • the material of the first insulating layer 41 may be silicon nitride.
  • the material of the second insulating layer 42 may be silicon oxide.
  • the stacked arrangement of silicon nitride and silicon oxide is beneficial to improving the insulation effect of the second sacrificial layer 40 .
  • the second sacrificial layer 40 may also include other insulating structures, which are not specifically limited in the embodiments of the present disclosure.
  • the step of forming the barrier layer 401 on the sidewalls of the groove 101 further includes: removing the second sacrificial layer 40 located on the bottom of the groove 101 .
  • the sacrificial layer 40 and the second sacrificial layer 40 located on the sidewall of the groove 101 constitute the barrier layer 401 .
  • the second sacrificial layer 40 located at the side walls of the groove 101 is is barrier layer 401.
  • barrier layer 401 it is helpful to prevent the sidewalls of the groove 101 from being exposed, thereby preventing subsequent structures formed in the groove 101 from coming into contact with the sidewalls of the groove 101 .
  • the step of removing the second sacrificial layer 40 located at the bottom of the groove 101 includes: using anisotropic dry etching to remove the second insulating layer 42 located at the bottom of the groove 101 .
  • anisotropic dry etching to remove the second insulating layer 42 located at the bottom of the groove 101 .
  • anisotropic dry etching Through the anisotropic dry etching process, etching back is prevented during the etching process, thereby preventing the second insulating layer 42 covering the sidewall from being etched away.
  • the substrate 10 can be cleaned using a cleaning solution to remove the first insulating layer 41 located at the bottom of the groove 101 .
  • Removing the first insulating layer 41 with the cleaning solution can avoid damage to the surface of the substrate 10 during the etching process and avoid affecting the subsequent growth of channel material at the bottom of the groove 101, which is conducive to further improving the performance of the formed transistor. .
  • the cleaning liquid can be, for example, phosphoric acid, which is beneficial to ensuring the removal effect of the first insulating layer 41 while reducing the impact on the surface of the substrate 10 during the removal process, which is beneficial to further improving the transistor quality. performance.
  • the step of removing the second sacrificial layer 40 located at the bottom of the groove 101 also includes: using dry etching to directly remove the first insulating layer 41 and the second insulating layer 42, which is beneficial to Simplify the manufacturing steps of semiconductor structures and improve the manufacturing efficiency of semiconductor structures.
  • the first sacrificial layer 20 also covers the substrate 10 . While the second sacrificial layer 40 is formed on the sidewalls and bottom of the groove 101 , the second sacrificial layer 40 also covers the substrate 10 . On the first sacrificial layer 20 located on the substrate 10 . In this embodiment, while removing the second sacrificial layer 40 located at the bottom of the groove 101, it also includes: removing the second sacrificial layer 40 located on the substrate 10, which is beneficial to simplifying the manufacturing steps of the semiconductor structure and improving the semiconductor structure. production efficiency. Furthermore, after removing the second sacrificial layer 40 on the substrate 10, the top surface of the first sacrificial layer 20 is flush with the top surface of the remaining second sacrificial layer 40, which is beneficial to improving the regularity of the semiconductor structure.
  • the channel material 501 can only grow epitaxially in a certain direction based on the bottom of the groove 101, so that the lattice arrangement inside the channel material 501 is stable, and thus It is beneficial to improve the stability of the formed intermediate structure 50 and to improve the performance of the formed transistor.
  • the channel material 501 can be silicon germanium. Since the channel material 501 contains the germanium element, the hole mobility of the formed intermediate structure 50 can be improved, thereby reducing the resistance of the intermediate structure 50, which is conducive to further improving the formation of the intermediate structure 50. performance of the transistor. Furthermore, since the lattice constants formed by the germanium element and the silicon element are different, when the lattice of the germanium element and the silicon element is grown in the groove 101, it is beneficial to increase the internal stress of the formed intermediate structure 50, thereby improving the intermediate structure 50. Electrical properties of structure 50. Furthermore, the channel material 501 is silicon germanium, which is also beneficial to improving the heat resistance of the semiconductor structure.
  • the step of forming the intermediate structure 50 also includes: the channel material 501 protrudes from the groove 101 .
  • the channel material 501 is made to protrude from the groove 101 to avoid gaps in the groove 101.
  • the step of forming the intermediate structure 50 further includes: removing part of the channel material 501 and the fifth insulating layer 23 located on the substrate 10 through a chemical mechanical polishing process to form the intermediate structure 50 , and the top surface of the intermediate structure 50 is flush with the fourth insulation layer 22 .
  • the top of the intermediate structure 50 and the fifth insulating layer 23 located on the substrate 10 are polished simultaneously.
  • the materials of the fifth insulating layer 23 and the fourth insulating layer 22 in the first sacrificial layer 20 are different, it is helpful for the chemical mechanical polishing equipment to identify and stop grinding when it reaches the fourth insulating layer 22, ensuring the accuracy of grinding. . Furthermore, using a chemical mechanical polishing process is also beneficial to ensuring the flatness of the top surface of the formed intermediate structure 50, which is beneficial to improving the performance of subsequently formed transistors.
  • the intermediate structure 50 after forming the intermediate structure 50, it also includes:
  • the step of removing part of the intermediate structure 50 and part of the substrate 10 includes: forming a third sacrificial layer 60 on the intermediate structure 50 and patterning the third sacrificial layer 60 .
  • the third sacrificial layer 60 includes a sixth insulating layer 61 , a seventh insulating layer 62 and an eighth insulating layer 63 , wherein the sixth insulating layer 61 covers the intermediate structure 50 and the fourth insulating layer 22
  • the seventh insulating layer 62 is located between the sixth insulating layer 61 and the eighth insulating layer 63
  • the eighth insulating layer 63 covers the side of the seventh insulating layer 62 facing away from the substrate 10 .
  • the third sacrificial layer 60 may also include other insulating structures, which are not specifically limited in the embodiments of the present disclosure.
  • the third sacrificial layer 60 may also include a hard mask layer 64 .
  • the hard mask layer 64 is located on the side of the eighth insulating layer 63 away from the substrate 10 .
  • the material of the hard mask layer 64 is For example, it may be polysilicon.
  • the step of patterning the third sacrificial layer 60 includes: forming a mask block 801 on the third sacrificial layer 60 , and the orthographic projection of the mask block 801 on the substrate 10 Located within the intermediate structure 50.
  • the step of forming the mask block 801 on the third sacrificial layer 60 includes: forming a mask layer 81 on the third mask layer 81 , and forming a mask block 801 on a side of the mask layer 81 away from the substrate 10 Anti-reflective layer 82.
  • the material of the mask layer 81 may include one of silicon nitride and silicon oxynitride; the material of the anti-reflection layer 82 may be, for example, organosiloxane or carbon coating ( Spin-On-Carbon, SOC).
  • a second photoresist layer 302 is formed on a side of the anti-reflection layer 82 facing away from the substrate 10 , and the second photoresist layer 302 has a second photolithography pattern. After the second photoresist layer 302 is formed, part of the anti-reflection layer 82 and part of the mask layer 81 are removed through a photolithography process to form an anti-reflection block 802 and a mask block 801. It is worth mentioning that by providing the anti-reflection layer 82, it is beneficial to absorb the photoreflected light in the photolithography process, thereby improving the photolithography accuracy of the photolithography process.
  • the step of patterning the third sacrificial layer 60 further includes: forming a third sacrificial layer 60 on the surface of the third sacrificial layer 60 and the sidewalls and top surface of the mask block 801 .
  • the fourth sacrificial layer 90 may be made of oxide, and the fourth sacrificial layer 90 also covers the side walls and top surface of the anti-reflective block 802 .
  • the step of patterning the third sacrificial layer 60 further includes: removing the fourth sacrificial layer 90 located on the top surface of the third sacrificial layer 60 and the mask block 801 to form a sacrificial layer. Side walls 91.
  • the fourth sacrificial layer 90 on the side walls of the mask block 801 is retained.
  • the fourth sacrificial layer 90 is the sacrificial sidewall 91.
  • the sacrificial sidewall 91 also covers the sidewall of the anti-reflective block 802 .
  • the orthographic projection of the formed sacrificial sidewall 91 on the substrate 10 is located in the intermediate structure 50, so that part of the intermediate structure 50 within the orthographic projection of the sacrificial sidewall 91 is subsequently retained to form a fin structure.
  • the step of patterning the third sacrificial layer 60 further includes removing the anti-reflection block 802 and the mask block 801 to avoid affecting subsequent processes.
  • the step of patterning the third sacrificial layer 60 further includes: etching the third sacrificial layer 60 using the sacrificial sidewalls 91 as a mask to form an etching pattern.
  • etching the third sacrificial layer 60 using the sacrificial sidewall 91 as a mask includes etching the hard mask layer 64 using the sacrificial sidewall 91 as a mask to form a hard mask module 641 .
  • the eighth insulating layer 63 , the seventh insulating layer 62 and the sixth insulating layer 61 are sequentially etched using the hard mask module 641 as a mask to form an etching pattern.
  • the spacing between the formed sacrificial sidewalls 91 can be adjusted, and thereby the spacing between the formed fin structures can be adjusted.
  • spacing refers to the distance between adjacent fin structures in a direction parallel to the substrate 10 .
  • the size of the formed mask block 801 can be adjusted to control the spacing between fin structures within a reasonable range, which is beneficial to reducing the spacing between field effect transistors formed by adjacent fin structures. The distance ensures the integration of semiconductor devices and at the same time helps reduce the interference between adjacent transistors.
  • the width of the formed sacrificial sidewall 91 can be adjusted, thereby adjusting the width of the formed fin structure.
  • “width” refers to the distance of the fin structure in a direction parallel to the substrate 10 and perpendicular to its extension direction.
  • the upper structure 502 contains germanium element. Since certain surface defects or impurities are inevitable on the surface of the semiconductor structure, the germanium element on the surface will inevitably have defects such as lattice defects, and the electrical performance after powering on will be affected to a certain extent. . The width of the upper structure 502 is too narrow, so that most germanium elements may be affected by surface defects.
  • the width of the upper structure 502 is relatively wide, so that the germanium elements located in the width direction thereof are not affected by surface defects as much as possible.
  • the thickness of the deposited fourth sacrificial layer 90 can be adjusted to adjust the width of the formed fin structure, thereby improving the electrical performance of the formed transistor.
  • the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which includes: providing a substrate 10, forming a groove 101 in the substrate 10; forming a barrier layer 401 on the sidewalls of the groove 101; and forming a groove bottom based on the groove 101.
  • the channel material 501 is epitaxially grown to form an intermediate structure 50 within the groove 101; a portion of the intermediate structure 50 and a portion of the substrate 10 are removed to form a fin structure.
  • the embodiment of the present disclosure grows the channel material 501 on the bottom of the groove 101.
  • the internal lattice arrangement of the formed fin structure is stable, which is conducive to Improve transistor performance.
  • the fin structure after forming the fin structure, it also includes: forming an isolation layer 701 on the bottom sidewall of the fin structure and the surface of the substrate 10 .
  • an isolation material 70 may be formed on the surface of the substrate 10 , the sidewalls and the top surface of the fin structure.
  • the isolation material 70 covering the top surface and part of the sidewalls of the fin structure is removed to form an isolation layer 701 .
  • the isolation material 70 may be an insulating material such as oxide or nitride.
  • the top surface of the isolation layer 701 is higher than the bottom surface of the upper structure 502, so that the subsequently formed gate structure is disposed around the upper structure 502, thereby causing the formed channel region to be located within the upper structure 502, to avoid being in the lower structure.
  • a parasitic channel is formed in 102 to improve the performance of the formed transistor.
  • Embodiments of the present disclosure also provide a semiconductor structure.
  • the manufacturing method of the semiconductor structure includes: providing a substrate 10, forming a groove 101 in the substrate 10; forming a barrier layer 401 on the sidewall of the groove 101; based on the groove
  • the channel material 501 is epitaxially grown at the bottom of the trench 101 to form an intermediate structure 50 within the trench 101; part of the intermediate structure 50 and part of the substrate 10 are removed to form a fin structure.
  • the semiconductor structure in the embodiment of the present disclosure grows the channel material 501 based on the bottom of the groove 101 during the manufacturing process to form a fin.
  • the internal lattice arrangement of the structure is stable, which is beneficial to improving the performance of the transistor.
  • the semiconductor structure includes: a substrate 10 and fin structures spaced above the substrate 10 .
  • Each fin structure includes an upper structure 502 and a lower structure 102 , and the upper structure 502 and the lower structure 102 are made of different materials. Since the materials of the upper structure 502 and the lower structure 102 are different, formation of parasitic channels in the lower structure 102 is avoided, thereby improving the performance of the formed transistor.
  • the material of the lower structure 102 may include silicon
  • the material of the upper structure 502 may include silicon germanium. It is worth mentioning that since the material of the upper structure 502 contains germanium element, the hole mobility of the formed fin structure can be increased, thereby reducing the resistance of the fin structure, which is beneficial to further improving the performance of the formed transistor. Furthermore, since the lattice constants formed by the germanium element and the silicon element are different, when the germanium element and the silicon element are grown in the groove 101 to form a lattice, it is beneficial to increase the internal stress of the formed fin structure, thereby increasing the intermediate stress. Electrical properties of structure 50. Furthermore, the material of the upper structure 502 is silicon germanium, which is also beneficial to improving the heat resistance of the semiconductor structure.
  • the semiconductor structure further includes an isolation layer 701.
  • the top surface of the isolation layer 701 is higher than the bottom surface of the upper structure 502.
  • the isolation layer 701 covers the surface of the substrate 10 and covers the bottom side of the fin structure.
  • the material of the isolation layer 701 may be an insulating material such as oxide or nitride.
  • the subsequently formed gate structure is arranged around the upper structure 502 so that the formed channel region is located within the upper structure 502, thereby avoiding the formation of parasitic channels in the lower structure 102 and further improving the performance of the formed transistor.
  • the top surface of the isolation layer 701 is higher than the bottom surface of the superstructure 502, which is also beneficial to improving the mechanical structural stability of the fin structure, ensuring the height of the fin structure, and reducing the collapse of the semiconductor structure during heat treatment and actual use. Risk of failure.
  • “height” refers to the distance from the top surface of the upper structure 502 to the top surface of the isolation layer 701 .

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本公开提供一种半导体结构的制作方法及半导体结构，涉及半导体技术领域。半导体结构的制作方法包括：提供衬底，在衬底中形成凹槽；在凹槽的侧壁上形成阻挡层；基于凹槽的槽底外延生长沟道材料，以在凹槽内形成中间结构；去除部分中间结构和部分衬底，以形成鳍片结构。对比于基于凹槽的两个侧壁以及底面生长硅锗，本公开实施例基于凹槽的槽底生长沟道材料，形成的鳍片结构内部晶格排列稳定，有利于提高晶体管的性能。

Description

半导体结构的制作方法及半导体结构
本申请要求于2022年6月13日提交中国专利局、申请号为202210663531.3、申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构的制作方法及半导体结构。
背景技术
半导体结构的制作方法中通常设置有鳍式场效应晶体管(FinFET，Fin Field-Effect Transistor)。鳍式场效应晶体管包括设置在衬底上的鳍片结构和栅极结构，栅极结构对鳍片结构呈包围、围绕的形式，进而在鳍片结构被栅极结构覆盖的区域形成沟道区，源区和漏区位于沟道区的两侧。
然而，相关技术还存在晶体管性能较差的问题。
发明内容
第一方面，本公开实施例提供一种半导体结构的制作方法，包括：
提供衬底，在所述衬底中形成凹槽；
在所述凹槽的侧壁上形成阻挡层；
基于所述凹槽的槽底外延生长沟道材料，以在所述凹槽内形成中间结构；
去除部分所述中间结构和部分所述衬底，以形成鳍片结构。
在一种可能的实现方式中，在所述衬底中形成凹槽，包括：
在所述衬底上形成第一牺牲层，蚀刻所述第一牺牲层形成第一开口；
沿所述第一开口蚀刻部分所述衬底，以形成所述凹槽。
在一种可能的实现方式中，在所述凹槽的侧壁上形成阻挡层，包括：
在所述凹槽的侧壁以及槽底形成第二牺牲层；
去除位于所述凹槽的槽底的所述第二牺牲层，位于所述凹槽的侧壁的所述第二牺牲层构成所述阻挡层。
在一种可能的实现方式中，在所述凹槽的侧壁以及槽底形成第二牺牲层，包括：
在所述凹槽的侧壁以及槽底形成第一绝缘层；
在所述第一绝缘层上形成第二绝缘层，所述第一绝缘层和所述第二绝缘层构成所述第二牺牲层。
在一种可能的实现方式中，去除位于所述凹槽的槽底的所述第二牺牲层，包括：
采用各向异性干法蚀刻去除位于所述凹槽的槽底的所述第二绝缘层；
在去除所述第二绝缘层之后，采用清洗液对所述衬底进行清洗，以去除位于所述凹槽的槽底的所述第一绝缘层。
在一种可能的实现方式中，
所述第一牺牲层和所述第二牺牲层还覆盖在所述衬底上；
去除位于所述凹槽的槽底的所述第二牺牲层的同时，去除位于所述衬底上的所述第二牺牲层。
在一种可能的实现方式中，在所述衬底上形成第一牺牲层，包括：在一种可能的实现方式中所述第一牺牲层包括第三绝缘层、第四绝缘层以及第五绝缘层，所述第三绝缘层覆盖在所述衬底表面，所述第四绝缘层位于所述第三绝缘层与所述第五绝缘层之间，所述第五绝缘层覆盖在所述第四绝缘层背离所述衬底的一侧。
在一种可能的实现方式中，基于所述凹槽的槽底外延生长沟道材料，以在所述凹槽内形成中间结构，还包括：
所述沟道材料凸出于所述凹槽；
通过化学机械研磨工艺去除部分所述沟道材料以及位于所述衬底上的所述第五绝缘层，以形成所述中间结构，且所述中间结构的顶表面与所述第四绝缘层齐平。
在一种可能的实现方式中，去除部分所述中间结构和部分所述衬底，包括：
在所述中间结构上形成第三牺牲层，图案化所述第三牺牲层；
以所述第三牺牲层为掩膜蚀刻所述中间结构和所述衬底，以形成所述鳍片结构。
在一种可能的实现方式中，在所述中间结构上形成第三牺牲层，图案化所述第三牺牲层，包括：
在所述第三牺牲层上形成掩膜块，所述掩膜块在所述衬底上的正投影位于所述中间结构内；
在所述第三牺牲层的表面以及所述掩膜块的侧壁和顶表面形成第四牺牲层；
去除位于所述第三牺牲层以及所述掩膜块的顶表面的所述第四牺牲层，以形成牺牲侧壁；
以所述牺牲侧壁为掩膜蚀刻所述第三牺牲层，以形成蚀刻图案。
在一种可能的实现方式中，去除部分所述中间结构和部分所述衬底以后，还包括：
在所述鳍片结构的底部侧壁和所述衬底表面上形成隔离层。
第二方面，本公开实施了还提供一种根据上述的半导体结构的制作方法形成的半导体结构，包括：衬底，以及间隔设置于所述衬底上方的鳍片结构。
在一种可能的实现方式中，每一所述鳍片结构包括上部结构和下部结构，所述上部结构与所述下部结构的材料不同。
在一种可能的实现方式中，所述下部结构的材料包括硅，所述上部结构的材料包括硅锗。
在一种可能的实现方式中，所述半导体结构还包括隔离层，所述隔离层的顶表面高于所述上部结构的底表面，所述隔离层覆盖所述衬底的表面，以及覆盖所述鳍片结构的底部侧面。
本公开实施例提供一种半导体结构的制作方法及半导体结构，半导体结构的制作方法包括：提供衬底，在衬底中形成凹槽；在凹槽的侧壁上形成阻挡层；基于凹槽的槽底外延生长沟道材料，以在凹槽内形成中间结构；去除部分中间结构和部分衬底，以形成鳍片结构。对比于基于凹槽的两个侧壁以及底面生长硅锗，本公开实施例基于凹槽的槽底生长沟道材料，形成的鳍片结构内部晶格排列稳定，有利于提高晶体管的性能。
附图说明
图1为本公开实施例提供的一种半导体结构的制作方法的步骤流程图；
图2为本公开实施例提供的一种半导体结构的制作方法中提供的衬底的结构示意图；
图3为本公开实施例提供的一种半导体结构的制作方法中形成第一开口的结构示意图；
图4为本公开实施例提供的一种半导体结构的制作方法中形成凹槽的结构示意图；
图5为本公开实施例提供的一种半导体结构的制作方法中形成第二牺牲层的结构示意图；
图6为本公开实施例提供的一种半导体结构的制作方法中形成阻挡层的结构示意图；
图7为本公开实施例提供的一种半导体结构的制作方法中填充沟道材料的结构示意图；
图8为本公开实施例提供的一种半导体结构的制作方法中通过化学机械研磨工艺去除部分沟道材料的结构示意图；
图9为本公开实施例提供的一种半导体结构的制作方法中形成第三牺牲层的结构示意图；
图10为本公开实施例提供的一种半导体结构的制作方法中形成第二光刻胶层的结构示意图；
图11为本公开实施例提供的一种半导体结构的制作方法中形成掩膜块的结构示意图；
图12为本公开实施例提供的一种半导体结构的制作方法中形成第四牺牲层的结构示意图；
图13为本公开实施例提供的一种半导体结构的制作方法中形成牺牲侧壁的结构示意图；
图14为本公开实施例提供的一种半导体结构的制作方法中去除掩膜块的结构示意图；
图15为本公开实施例提供的一种半导体结构的制作方法中形成介质块的结构示意图；
图16为本公开实施例提供的一种半导体结构的制作方法中形成鳍片结构的结构示意图；
图17为本公开实施例提供的一种半导体结构的制作方法中形成隔离材料的结构示意图；
图18为本公开实施例提供的一种半导体结构的制作方法中形成隔离层的结构示意图。
具体实施方式
相关技术中，半导体结构中的鳍片结构的制作过程通常分为两种：Gate-first(先栅极)工艺流派和Gate-last(后栅极)工艺流派。其中，Gate-first(先栅极)工艺流派具有制作步骤相对简单，制作成本较低，制作的半导体结构的耐热性较好等优点，因而被广泛应用于DRAM(动态随机存取存储器，Dynamic Random Access Memory)中的鳍片结构的制作中。
使用Gate-first工艺制作鳍片结构的步骤包括：在衬底上形成凹槽后，基于凹槽的两个侧壁以及底面生长硅锗，后续去除部分衬底和部分硅锗以形成鳍片结构。然而，本申请的发明人在实际研究过程中发现，基于上述三个面生长形成的硅锗的晶格结构较为混乱，进而导致形成的晶体管的性能不佳。
有鉴于此，本公开实施例提供一种半导体结构的制作方法及半导体结构。半导体结构的制作方法包括：提供衬底，在衬底中形成凹槽；在凹槽的侧壁上形成阻挡层；基于凹槽的槽底外延生长沟道材料，以在凹槽内形成中间结构；去除部分中间结构和部分衬底，以形成鳍片结构。对比于相关技术中基于凹槽的两个侧壁以及底面生长硅锗，本公开实施例基于凹槽的槽底生长沟道材料，形成的鳍片结构内部晶格排列稳定，有利于提高晶体管的性能。
为使本公开的目的、技术方案和优点更加清楚，下面将结合本公开的优选实施例中的附图，对本公开实施例中的技术方案进行更加详细的描述。在附图中，自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。所描述的实施例是本公开一部分实施例，而不是全部的实施例。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理 解为对本公开的限制。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。下面结合附图对本公开的实施例进行详细说明。
值得说明的是，本公开实施例提供的半导体结构可以应用于PMOS场效晶体管以及由其与NMOS场效晶体管所集成形成的芯片等电子器件内。参照图1，本公开实施例提供的半导体结构的制作方法包括以下步骤：
S101、提供衬底，在衬底中形成凹槽。
参照图2，半导体结构包括衬底10。衬底10可以为后续结构和工艺提供结构基础，该衬底10的材料可以包括硅、锗、硅锗、碳化硅，绝缘体上硅衬底10以及绝缘体上锗衬底10中任一者或多者。本实施例中，衬底10的材质可以为硅。
参照图3和图4，在衬底10中形成凹槽101的步骤，包括：在衬底10上形成第一牺牲层20，蚀刻第一牺牲层20形成第一开口201。
本实施例中，在衬底10上形成第一牺牲层20，包括：第一牺牲层20包括第三绝缘层21、第四绝缘层22以及第五绝缘层23，其中，第三绝缘层21覆盖在衬底10表面，第四绝缘层22位于第三绝缘层21与第五绝缘层23之间，第五绝缘层23覆盖在第四绝缘层22背离衬底10的一侧。在一种具体的实现方式中，第一牺牲层20的材质可以包括氮化硅、氧化硅以及氮氧化硅中的一种或者多种，例如，第三绝缘层21和第五绝缘层23的材质可以为氧化硅，第四绝缘层22的材质可以为氮化硅。通过氮化硅和氧化硅依次层叠设置，有利于提高第一牺牲层20的绝缘效果。
当然，在一些其他实施例中，第一牺牲层20还可以包括其他绝缘结构，本公开实施例在此不进行具体限定。
参照图3，蚀刻第一牺牲层20形成第一开口201的步骤包括：在第一牺牲层20上形成第一光刻胶层301，第一光刻胶层301具有第一光刻图形，以第一光刻胶层301为掩膜蚀刻第一牺牲层20，以形成第一开口201。
参照图4，在形成第一牺牲层20以后，在衬底10中形成凹槽101的步骤还包括：沿第一开口201蚀刻部分衬底10，以形成凹槽101。在一种具体的实施方式中，可以采用湿法蚀刻或者干法蚀刻工艺以第一牺牲层20为掩膜去除部分衬底10，形成的凹槽101为后续的结构和工艺提供结构基础。
本实施例中，在衬底10中形成凹槽101以后，还包括：
S102、在凹槽的侧壁上形成阻挡层。
参照图5，在凹槽101的侧壁上形成阻挡层401的步骤，包括：在凹槽101的侧壁以及槽底形成第二牺牲层40。
本实施例中，在凹槽101的侧壁以及槽底形成第二牺牲层40，包括：在凹槽101的侧壁以及槽底形成第一绝缘层41；在第一绝缘层41上形成第二绝缘层42，第一绝缘层41和第二绝缘层42构成第二牺牲层40。在一种具体的实现方式中，第二牺牲层40材质可以包括氮化硅、氧化硅以及氮氧化硅中的一种或者多种，例如，第一绝缘层41的材质可以为氮化硅，第二绝缘层42的材质可以为氧化硅。通过氮化硅和氧化硅层叠设置，有利于提高第二牺牲层40的绝缘效果。
当然，在一些其他实施例中，第二牺牲层40还可以包括其他绝缘结构，本公开实施例在此不进行具体限定。
参照图6，在凹槽101的侧壁以及槽底形成第二牺牲层40以后，在凹槽101的侧壁上形成阻挡层401的步骤还包括：去除位于凹槽101的槽底的第二牺牲层40，位于凹槽101的侧壁的第二牺牲层40构成阻挡层401。
示例性地，去除位于凹槽101的槽底的第二牺牲层40的同时，保留位于凹槽101的侧壁的第二牺牲层40，位于凹槽101的侧壁的第二牺牲层40即为阻挡层401。通过设置阻挡层401，有利于避免凹槽101的侧壁暴露出来，进而避免后续凹槽101内形成的结构与凹槽101的侧壁接触。
本实施例中，去除位于凹槽101的槽底的第二牺牲层40的步骤，包括：采用各向异性干法蚀刻去除位于凹槽101的槽底的第二绝缘层42。通过各向异性干法蚀刻工艺，防止在蚀刻的过程中出现回蚀，进而避免覆盖在侧壁上的第二绝缘层42被蚀刻掉。在去除第二绝缘层42之后，可以采用清洗液对衬底10进行清洗，以去除位于凹槽101的槽底的第一绝缘层41。通过清洗液去除第一绝缘层41，可以避免刻蚀的过程中对衬底10的表面造成损伤，避免影响后续在凹槽101的槽底生长沟道材料，有利于进一步提高形成的晶体管的性能。
在一种具体的实施方式中，清洗液例如可以为磷酸，有利于在保证对第一绝缘层41的去除效果的同时，减小去除过程中对衬底10表面的影响，有利于进一步提高晶体管的性能。
当然，在一些其他的实施例中，去除位于凹槽101的槽底的第二牺牲层40的步骤，还包括：采用干法蚀刻直接去除第一绝缘层41和第二绝缘层42，有利于简化半导体结构的制作步骤，提高半导体结构的制作效率。
继续参照图6，值的说明的是，第一牺牲层20还覆盖在衬底10上，在凹槽101的侧壁以及槽底形成第二牺牲层40的同时，第二牺牲层40还覆盖在位于衬底10上的第一牺牲层20上。本实施例中，去除位于凹槽101的槽底的第二牺牲层40的同时，还包括：去除位于衬底10上的第二牺牲层40，有利于简化半导体结构的制作步骤，提高半导体结构的制作效率。进一步地，去除位于衬底10上的第二牺牲层40以后，使第一牺牲层20的顶表面与保留的第二牺牲层40的顶表面平齐，有利于提高半导体结构的规整性。
本实施例中，在凹槽101的侧壁上形成阻挡层401以后，还包括：
S103、基于凹槽的槽底外延生长沟道材料，以在凹槽内形成中间结构。
参照图7，由于凹槽101的侧壁覆盖有阻挡层401，沟道材料501只能基于凹槽101的槽底沿一定方向进行外延生长，使得沟道材料501内部的晶格排列稳定，进而有利于提高形成的中间结构50的稳定性，有利于提高形成的晶体管的性能。
本实施例中，沟道材料501可以为硅锗，由于沟道材料501中含有锗元素，可以提高形成的中间结构50的空穴迁移率，进而降低中间结构50的电阻，有利于进一步提高形成的晶体管的性能。进一步地，由于锗元素与硅元素形成的晶格常数不同，所以在凹槽101内生长、形成锗元素与硅元素的晶格时，有利于提高形成的中间结构50的内应力，进而提高中间结构50的电学性能。进一步地，沟道材料501为硅锗，还有利于提高半导体结构的耐热性能。
继续参照图7，形成中间结构50的步骤，还包括：沟道材料501凸出于凹槽101。在凹槽101内填充沟道材料501时，使沟道材料501凸出于凹槽101，避免凹槽101内出现空隙。
参照图8，在形成沟道材料501以后，形成中间结构50的步骤还包括：通过化学机械研磨工艺去除部分沟道材料501以及位于衬底10上的第五绝缘层23，以形成中间结构50，且中间结构50的顶表面与第四绝缘层22齐平。示例性地，在进行化学机械研磨时，同时研磨中间结构 50的顶端与位于衬底10上的第五绝缘层23。
本实施例中，由于第一牺牲层20中第五绝缘层23和第四绝缘层22的材质不同，有利于化学机械研磨设备识别并研磨至第四绝缘层22时停止研磨，保证研磨的精度。进一步地，使用化学机械研磨工艺，还有利于保证形成的中间结构50的顶表面的平整度，有利于提高后续形成的晶体管的性能。
本实施例中，在形成中间结构50以后，还包括：
S104、去除部分中间结构和部分衬底，以形成鳍片结构。
参照图9至图16，去除部分中间结构50和部分衬底10的步骤，包括：在中间结构50上形成第三牺牲层60，图案化第三牺牲层60。
示例性地，参照图9，第三牺牲层60包括第六绝缘层61、第七绝缘层62以及第八绝缘层63，其中，第六绝缘层61覆盖在中间结构50和第四绝缘层22的顶表面，第七绝缘层62位于第六绝缘层61与第八绝缘层63之间，第八绝缘层63覆盖在第七绝缘层62背离衬底10的一侧。在一种具体的实现方式中，第三牺牲层60的材质可以包括氮化硅、氧化硅以及氮氧化硅中的一种或者多种，例如，第六绝缘层61和第八绝缘层63的材质可以为氧化硅，第七绝缘层62的材质可以为氮化硅。通过氮化硅和氧化硅依次层叠设置，有利于提高第三牺牲层60的绝缘效果。
当然，在一些其他实施例中，第三牺牲层60还可以包括其他绝缘结构，本公开实施例在此不进行具体限定。
继续参照图9，本实施例中，第三牺牲层60还可以包括硬掩模层64，硬掩模层64位于第八绝缘层63背离衬底10的一侧，硬掩模层64的材质例如可以为多晶硅。
本实施例中，在形成第三牺牲层60以后，图案化第三牺牲层60的步骤包括：在第三牺牲层60上形成掩膜块801，掩膜块801在衬底10上的正投影位于中间结构50内。
参照图10和图11，在第三牺牲层60上形成掩膜块801的步骤包括：在第三掩膜层81上形成掩膜层81，在掩膜层81背离衬底10的一侧形成抗反射层82。在一种具体的实现方式中，掩膜层81的材质可以包括氮化硅、氮氧化硅中的一种；抗反射层82的材质例如可以为有机硅氧烷(organosiloxane)或者碳涂层(Spin-On-Carbon，SOC)。在抗反射层82背离衬底10的一侧形成第二光刻胶层302，第二光刻胶层302具有第二光刻图形。在形成第二光刻胶层302以后，通过光刻工艺去除部分抗反射层82和部分掩膜层81，以形成抗反射块802和掩膜块801。值得说明的是，通过设置抗反射层82，有利于吸收光刻工艺中的光刻反射光，进而提高光刻工艺的光刻精度。
参照图12，在第三研磨层上形成掩膜块801以后，图案化第三牺牲层60的步骤还包括：在第三牺牲层60的表面以及掩膜块801的侧壁和顶表面形成第四牺牲层90。本实施例中，第四牺牲层90的材质可以为氧化物，第四牺牲层90还覆盖在抗反射块802的侧壁和顶表面。
参照图13，在形成第四牺牲层90以后，图案化第三牺牲层60的步骤还包括：去除位于第三牺牲层60以及掩膜块801的顶表面的第四牺牲层90，以形成牺牲侧壁91。示例性地，去除位于第三牺牲层60以及掩膜块801的顶表面的第四牺牲层90的同时，保留位于掩膜块801侧壁的第四牺牲层90，位于掩膜块801侧壁的第四牺牲层90即为牺牲侧壁91。本实施例中，牺牲侧壁91还覆盖在抗反射块802的侧壁上。
值得说明的是，形成的牺牲侧壁91在衬底10上的正投影位于中间结构50中，以便后续保留牺牲侧壁91正投影内的部分中间结构50，以形成鳍片结构。
参照图14，本实施例中，在形成牺牲侧壁91以后，图案化第三牺牲层60的步骤还包括：去除抗反射块802和掩膜块801，以避免影响后续工艺制程。
参照图15，在形成牺牲侧壁91以后，图案化第三牺牲层60的步骤还包括：以牺牲侧壁91为掩膜蚀刻第三牺牲层60，以形成蚀刻图案。本实施例中，以牺牲侧壁91为掩膜蚀刻第三牺牲层60包括：以牺牲侧壁91为掩膜蚀刻硬掩模层64，以形成硬掩模块641。参照图16，在形成硬掩模块641以后，以硬掩模块641为掩膜依次蚀刻第八绝缘层63、第七绝缘层62以及第六绝缘层61，以形成蚀刻图案。
本实施例中，在图案化第三牺牲层60以后，形成鳍片结构的步骤还包括：以第三牺牲层60为掩膜蚀刻中间结构50和衬底10，以形成鳍片结构。示例性的，以第三牺牲层60为掩膜蚀刻衬底10以后，形成凸出于衬底10的下部结构102，第三牺牲层60为掩膜蚀刻中间结构50以后，形成覆盖在下部结构102顶表面的上部结构502,下部结构102和上部结构502共同构成鳍片结构。
值得说明的是，可以通过调节形成的掩膜块801的尺寸，调节形成的牺牲侧壁91之间的间距，进而调节形成的鳍片结构之间的间距。此处，“间距”是指在平行于衬底10的方向上，相邻的鳍片结构之间距离。本实施例中，可以通过调节形成的掩膜块801的尺寸，将鳍片结构之间的间距控制在合理范围，进而有利于降低相邻的鳍片结构所形成的场效晶体管之间间隔的距离，保证了半导体器件的集成度，同时，还有利于降低形成的相邻的晶体管之间的干扰。
进一步地，还可以通过调节沉积的第四牺牲层90的厚度，调节形成的牺牲侧壁91的宽度，进而调节形成的鳍片结构的宽度。此处，“宽度”是指在平行于衬底10的方向上，鳍片结构在垂直于其延伸方向上的距离。其中，上部结构502中含有锗元素，由于半导体结构的表面上难免存在一定表面缺陷或杂质，因此在表面的锗元素也难免存在晶格缺陷等缺陷，在通电后表现的电学性能会受到一定影响。上部结构502的宽度过窄，会造成大部分锗元素均有可能受到表面缺陷的影响。而上部结构502的宽度相对较宽，可使位于其宽度方向上的锗元素尽可能不受到表面缺陷的影响。本实施例中，可以通过调节沉积的第四牺牲层90的厚度，调节形成的鳍片结构的宽度，进而改善形成的晶体管的电学性能。
本公开实施例提供一种半导体结构的制作方法，包括：提供衬底10，在衬底10中形成凹槽101；在凹槽101的侧壁上形成阻挡层401；基于凹槽101的槽底外延生长沟道材料501，以在凹槽101内形成中间结构50；去除部分中间结构50和部分衬底10，以形成鳍片结构。对比于相关技术中基于凹槽101的两个侧壁以及底面生长硅锗，本公开实施例基于凹槽101的槽底生长沟道材料501，形成的鳍片结构内部晶格排列稳定，有利于提高晶体管的性能。
本实施例中，在形成鳍片结构之后，还包括：在鳍片结构的底部侧壁和衬底10表面上形成隔离层701。参照图17可以在衬底10表面、鳍片结构的侧壁以及顶表面形成隔离材料70。参照图18，在形成隔离材料70以后，去除覆盖在鳍片结构的顶表面以及部分侧壁的隔离材料70，以形成隔离层701。在一种具体的实现方式中，隔离材料70可以为氧化物、氮化物等绝缘材料。
示例性地，隔离层701的顶表面高于上部结构502的底表面，以使后续形成的栅极结构围绕上部结构502设置，进而使得形成的沟道区位于上部结构502内，避免在下部结构102内形成寄生沟道，提高形成的晶体管的性能。
值得说明的是，隔离层701的顶表面高于上部结构502的底表面，还有利于提高鳍片结构的机械结构稳定性，保证鳍片结构的高度，降低鳍片结构在热处理以及实际使用中坍塌失效的风险。此处，“高度”是指从上部结构502的顶表面到隔离层701的顶表面的距离。进一步地，通过调 节蚀刻后形成的隔离层701的厚度，可以调节鳍片结构的高度，防止鳍片结构从隔离层701上伸出的高度过高，上部结构502产生晶格缺陷，进而避免形成的半导体的电学性能降低。
本公开实施例还提供一种半导体结构，该半导体结构的制作方法包括：提供衬底10，在衬底10中形成凹槽101；在凹槽101的侧壁上形成阻挡层401；基于凹槽101的槽底外延生长沟道材料501，以在凹槽101内形成中间结构50；去除部分中间结构50和部分衬底10，以形成鳍片结构。对比于相关技术中基于凹槽101的两个侧壁以及底面生长硅锗，本公开实施例中的半导体结构在制作过程中，基于凹槽101的槽底生长沟道材料501，形成的鳍片结构内部晶格排列稳定，有利于提高晶体管的性能。
参照图18，半导体结构包括：衬底10，以及间隔设置于衬底10上方的鳍片结构。其中，每一鳍片结构包括上部结构502和下部结构102，上部结构502与下部结构102的材料不同。由于上部结构502与下部结构102的材料不同，避免在下部结构102内形成寄生沟道，提高形成的晶体管的性能。
进一步地，下部结构102的材料可以包括硅，上部结构502的材料可以包括硅锗。值得说明的是，由于上部结构502的材料中含有锗元素，可以提高形成的鳍片结构的空穴迁移率，进而降低鳍片结构的电阻，有利于进一步提高形成的晶体管的性能。进一步地，由于锗元素与硅元素形成的晶格常数不同，所以在凹槽101内生长、形成锗元素与硅元素的晶格时，有利于提高形成的鳍片结构的内应力，进而提高中间结构50的电学性能。进一步地，上部结构502的材料为硅锗，还有利于提高半导体结构的耐热性能。
本实施例中，半导体结构还包括隔离层701，隔离层701的顶表面高于上部结构502的底表面，隔离层701覆盖衬底10的表面，以及覆盖鳍片结构的底部侧面。在一种具体的实现方式中，隔离层701的材质可以为氧化物、氮化物等绝缘材料。以使后续形成的栅极结构围绕上部结构502设置，进而使得形成的沟道区位于上部结构502内，避免在下部结构102内形成寄生沟道，进一步提高形成的晶体管的性能。
值得说明的是，隔离层701的顶表面高于上部结构502的底表面，还有利于提高鳍片结构的机械结构稳定性，保证鳍片结构的高度，降低半导体结构在热处理以及实际使用中坍塌失效的风险。此处，“高度”是指从上部结构502的顶表面到隔离层701的顶表面的距离。
上述的描述中，需要理解的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应作广义理解，例如，可以使固定连接，也可以是通过中间媒介间接相连，可以是两个元件内部的连通或者两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。术语“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或者位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或者暗示所指的装置或者元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。在本公开的描述中，“多个”的含义是两个或两个以上，除非是另有精确具体地规定。
本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本公开的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于 清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制作方法，包括：
    提供衬底，在所述衬底中形成凹槽；
    在所述凹槽的侧壁上形成阻挡层；
    基于所述凹槽的槽底外延生长沟道材料，以在所述凹槽内形成中间结构；
    去除部分所述中间结构和部分所述衬底，以形成鳍片结构。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，在所述衬底中形成凹槽，包括：
    在所述衬底上形成第一牺牲层，蚀刻所述第一牺牲层形成第一开口；
    沿所述第一开口蚀刻部分所述衬底，以形成所述凹槽。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，在所述凹槽的侧壁上形成阻挡层，包括：
    在所述凹槽的侧壁以及槽底形成第二牺牲层；
    去除位于所述凹槽的槽底的所述第二牺牲层，位于所述凹槽的侧壁的所述第二牺牲层构成所述阻挡层。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，在所述凹槽的侧壁以及槽底形成第二牺牲层，包括：
    在所述凹槽的侧壁以及槽底形成第一绝缘层；
    在所述第一绝缘层上形成第二绝缘层，所述第一绝缘层和所述第二绝缘层构成所述第二牺牲层。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，去除位于所述凹槽的槽底的所述第二牺牲层，包括：
    采用各向异性干法蚀刻去除位于所述凹槽的槽底的所述第二绝缘层；
    在去除所述第二绝缘层之后，采用清洗液对所述衬底进行清洗，以去除位于所述凹槽的槽底的所述第一绝缘层。
  6. 根据权利要求3所述的半导体结构的制作方法，其中，
    所述第一牺牲层和所述第二牺牲层还覆盖在所述衬底上；
    去除位于所述凹槽的槽底的所述第二牺牲层的同时，去除位于所述衬底上的所述第二牺牲层。
  7. 根据权利要求2所述的半导体结构的制作方法，其中，在所述衬底上形成第一牺牲层，包括：
    所述第一牺牲层包括第三绝缘层、第四绝缘层以及第五绝缘层，所述第三绝缘层覆盖在所述衬底表面，所述第四绝缘层位于所述第三绝缘层与所述第五绝缘层之间，所述第五绝缘层覆盖在所述第四绝缘层背离所述衬底的一侧。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，基于所述凹槽的槽底外延生长沟道材料，以在所述凹槽内形成中间结构，还包括：
    所述沟道材料凸出于所述凹槽；
    通过化学机械研磨工艺去除部分所述沟道材料以及位于所述衬底上的所述第五绝缘层，以形成所述中间结构，且所述中间结构的顶表面与所述第四绝缘层齐平。
  9. 根据权利要求1-8任一项所述的半导体结构的制作方法，其中，去除部分所述中间结构和部分所述衬底，包括：
    在所述中间结构上形成第三牺牲层，图案化所述第三牺牲层；
    以所述第三牺牲层为掩膜蚀刻所述中间结构和所述衬底，以形成所述鳍片结构。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，在所述中间结构上形成第三牺牲层，图案化所述第三牺牲层，包括：
    在所述第三牺牲层上形成掩膜块，所述掩膜块在所述衬底上的正投影位于所述中间结构内；
    在所述第三牺牲层的表面以及所述掩膜块的侧壁和顶表面形成第四牺牲层；
    去除位于所述第三牺牲层以及所述掩膜块的顶表面的所述第四牺牲层，以形成牺牲侧壁；
    以所述牺牲侧壁为掩膜蚀刻所述第三牺牲层，以形成蚀刻图案。
  11. 根据权利要求1-8任一项所述的半导体结构的制作方法，其中，去除部分所述中间结构和部分所述衬底以后，还包括：
    在所述鳍片结构的底部侧壁和所述衬底表面上形成隔离层。
  12. 一种根据权利要求1-11任一所述的半导体结构的制作方法形成的半导体结构，包括：衬底，以及间隔设置于所述衬底上方的鳍片结构。
  13. 根据权利要求12所述的半导体结构，其中，每一所述鳍片结构包括上部结构和下部结构，所述上部结构与所述下部结构的材料不同。
  14. 根据权利要求13所述的半导体结构，其中，所述下部结构的材料包括硅，所述上部结构的材料包括硅锗。
  15. 根据权利要求13所述的半导体结构，其中，所述半导体结构还包括隔离层，所述隔离层的顶表面高于所述上部结构的底表面，所述隔离层覆盖所述衬底的表面，以及覆盖所述鳍片结构的底部侧面。
PCT/CN2022/108097 2022-06-13 2022-07-27 半导体结构的制作方法及半导体结构 Ceased WO2023240752A1 (zh)

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