WO2023240684A1 - 光掩膜组件及半导体结构的制备方法 - Google Patents
光掩膜组件及半导体结构的制备方法 Download PDFInfo
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- WO2023240684A1 WO2023240684A1 PCT/CN2022/101957 CN2022101957W WO2023240684A1 WO 2023240684 A1 WO2023240684 A1 WO 2023240684A1 CN 2022101957 W CN2022101957 W CN 2022101957W WO 2023240684 A1 WO2023240684 A1 WO 2023240684A1
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- Prior art keywords
- layer
- photomask
- opening
- mask layer
- patterned
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000005530 etching Methods 0.000 claims description 62
- 239000003990 capacitor Substances 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 229910052799 carbon Inorganic materials 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 303
- 230000008569 process Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910017107 AlOx Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910019897 RuOx Inorganic materials 0.000 description 1
- 229910003134 ZrOx Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- the present application relates to the field of integrated circuit technology, and in particular to a photomask component and a method for preparing a semiconductor structure.
- DRAM Dynamic Random Access Memory
- DRAM Dynamic Random Access Memory
- a patterned mask layer is formed on the stacked structure based on a photomask.
- this application provides a photomask assembly, including:
- a first photomask the first photomask has a plurality of first photomask patterns, and the plurality of first photomask patterns are arranged at intervals in multiple rows and columns;
- the second photomask has a plurality of second photomask patterns in the second photomask, and the plurality of second photomask patterns are arranged in multiple rows and columns at intervals; the second photomask patterns in each column are The orthographic projection pattern of the mask pattern on the surface of the first photomask is located between two adjacent columns of the first photomask pattern; the first photomask pattern and the orthographic projection are located in the same row.
- the patterns are alternately arranged along the first direction, and the first photomask patterns located in the same column and the orthographic projection graphics located in the same column are arranged at intervals along the second direction.
- the first photomask pattern and the orthographic projection pattern located in the same row have a first offset pitch along the second direction.
- the width of the first photomask pattern is the same as the width of the second photomask pattern
- the first offset pitch is the width of the first photomask pattern or the width of the second photomask pattern. 1/6 to 1/3 of the width of the second photomask pattern.
- This application also provides a method for preparing a semiconductor structure, including:
- a patterned etching mask layer is formed on the stacked structure, and a plurality of spaced rows and columns are formed in the patterned etching mask layer.
- the etched opening patterns of the cloth are arranged at intervals along the first direction in the same row, the etched opening patterns in the same column are arranged at intervals along the second direction, and the etched opening patterns in two adjacent columns are arranged at intervals along the second direction.
- the etching opening pattern has a second offset pitch along the second direction;
- An opening is formed in the stacked structure based on the patterned etching mask layer, the opening exposes the sacrificial layer, and the sacrificial layer is removed based on the opening.
- forming a capacitor hole in the stacked structure includes:
- a first patterned mask layer is formed on the upper surface of the stacked structure.
- a plurality of first opening patterns are formed in the first patterned mask layer.
- the first opening pattern defines the capacitor hole. shape and position;
- the first patterned mask layer is removed.
- forming a patterned etching mask layer on the stacked structure based on the photomask assembly includes:
- the second mask layer is photolithographically etched based on the first photomask to form a second patterned mask layer, and a layer formed in the second patterned mask layer that is consistent with the first photomask is formed.
- the second opening pattern corresponding to the mask pattern
- the third mask layer is photolithographically etched based on the second photomask to form a third patterned mask layer.
- the third patterned mask layer is formed with the second photon layer.
- the third opening pattern corresponding to the mask pattern;
- the first mask layer is etched based on the third patterned mask layer and the second patterned mask layer to obtain the patterned etching mask layer.
- the method before forming the second mask layer on the first mask layer, the method includes:
- a first silicon oxynitride layer is formed on the first amorphous carbon layer.
- the method before etching the second mask layer based on the first photomask, the method includes:
- a second silicon oxynitride layer is formed on the first spin-coated carbon layer.
- the process before forming the third mask layer on the second patterned mask layer, the process includes:
- a third silicon oxynitride layer is formed on the second spin-coated carbon layer.
- forming a stacked structure in which support layers and sacrificial layers are alternately stacked on the upper surface of the substrate includes:
- a third support layer is formed on the upper surface of the second sacrificial layer.
- the first support layer, the second support layer and the third support layer each include a silicon nitride layer or a silicon carbonitride layer, and the first sacrificial layer and the third support layer Both sacrificial layers include silicon oxide layers.
- an opening is formed in the stacked structure based on the patterned etching mask layer, the opening exposes the sacrificial layer, and the sacrificial layer is removed based on the opening, include:
- a first opening is formed in the third support layer based on the patterned etching mask layer, and the first opening exposes the second sacrificial layer;
- a second opening is formed in the second support layer based on the patterned etching mask layer, and the second opening exposes the first sacrificial layer;
- the first sacrificial layer is removed based on the second opening.
- each of the first openings exposes three adjacent capacitor holes.
- the center of each first opening coincides with the center of the area where the three adjacent capacitor holes exposed by the first opening are located.
- the shape of the first opening and the shape of the second opening are both circular.
- the thickness of the third support layer is greater than the thickness of the first support layer and the thickness of the second support layer.
- the method further includes:
- An upper electrode is formed on the surface of the capacitive dielectric layer.
- the upper electrode and the lower electrode both include titanium nitride electrodes; the capacitive dielectric layer includes a high-k dielectric layer.
- Figure 1 is a schematic structural diagram of a photomask assembly provided in an embodiment
- Figure 2 is a schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment
- Figure 3 is a schematic three-dimensional structural diagram of the structure obtained in step S201 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 4 is a flow chart of step S202 in a method for manufacturing a semiconductor structure provided in an embodiment
- Figure 5 is a schematic three-dimensional structural diagram of the structure obtained in step S2021 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 6 is a schematic three-dimensional structural diagram of the structure obtained in step S2022 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 7 is a schematic three-dimensional structural diagram of the structure obtained in step S2023 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 8 is a schematic three-dimensional structural diagram of the structure obtained in step S2024 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 9 is a schematic three-dimensional structural diagram of the structure obtained in step S2025 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 10 is a schematic flowchart of step S203 in the method for manufacturing a semiconductor structure provided in an embodiment
- Figure 11 is a schematic three-dimensional structural diagram of the structure obtained in step S203 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 12 is a schematic three-dimensional structural diagram of the structure obtained in step S204 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 13 is a schematic flowchart of step S205 in the method for manufacturing a semiconductor structure provided in an embodiment
- Figure 14 is a schematic three-dimensional structural diagram of the structure obtained in step S2051 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 15 is a schematic three-dimensional structural diagram of the structure obtained in step S2052 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 16 is a schematic three-dimensional structural diagram of the structure obtained in step S2053 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 17 is a schematic three-dimensional structural diagram of the structure obtained in step S2054 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 18 is a schematic three-dimensional structural diagram of the structure obtained in step S2055 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 19 is a schematic three-dimensional structural diagram of the structure obtained in step S2056 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 20 is a schematic top view of the structure obtained in step S2056 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 21 is a schematic flowchart of step S206 in the method for manufacturing a semiconductor structure provided in an embodiment
- Figure 22 is a schematic cross-sectional view of the structure obtained in step S2061 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 23 is a schematic cross-sectional view of the structure obtained in step S2062 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 24 is a schematic cross-sectional view of the structure obtained in step S2063 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 25 is a schematic cross-sectional view of the structure obtained in step S2064 of the method for preparing a semiconductor structure provided in an embodiment
- Figure 26 is a schematic cross-sectional view of the structure obtained in step S207 of the method for preparing a semiconductor structure provided in an embodiment
- FIG. 27 is a schematic cross-sectional view of the structure obtained in step S208 of the method for preparing a semiconductor structure provided in an embodiment.
- first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the application; for example, a first element, component, region, layer, doping type or section could be termed
- the first doping type becomes the second doping type, and similarly, the second doping type can become the first doping type; the first doping type and the second doping type are different doping types, for example,
- the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
- Spatial relational terms such as “under”, “under”, “under”, “under”, “on”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “under” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” may include both upper and lower orientations. Additionally, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
- Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown are contemplated due, for example, to manufacturing techniques and/or tolerances.
- embodiments of the present application should not be limited to the specific shapes of the regions shown herein but include deviations in shapes due, for example, to manufacturing techniques.
- an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region.
- a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant occurs. Therefore, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.
- This embodiment provides a method for preparing a semiconductor structure.
- DRAM Dynamic Random Access Memory
- DRAM Dynamic Random Access Memory
- a patterned mask layer is formed on the stacked structure based on a photomask.
- the photomask assembly includes: a first photomask and a second photomask (not shown);
- a photomask has a plurality of first photomask patterns 100, and the plurality of first photomask patterns 100 are arranged in multiple rows and columns at intervals;
- a second photomask has a plurality of second photomask patterns, A plurality of second photomask patterns are arranged at intervals in multiple rows and columns;
- the orthographic projection pattern 200 of each column of the second photomask pattern on the surface of the first photomask is located in two adjacent columns of the first photomask pattern 100 between;
- the first photomask patterns 100 and the orthographic projection patterns 200 located in the same row are alternately arranged along the first direction, and the first photomask patterns 100 located in the same column and the orthographic projection patterns 200 located in the same column are arranged along the first direction.
- arranged at intervals in the second direction are arranged at intervals in the second direction.
- the orthographic projection pattern of each column of the second photomask pattern on the surface of the first photomask is located between two adjacent columns of first photomask patterns 100, and is located on the first photomask pattern of the same row.
- the photomask patterns 100 and the orthographic projection patterns 200 are alternately arranged along the first direction, and the first photomask patterns 100 in the same column and the orthographic projection patterns in the same column are arranged at intervals along the second direction, that is, during adjustment The second photomask pattern will not block the first photomask pattern 100.
- the center of the formed opening can be made to coincide with the center of the area between the three capacitor holes, which can significantly increase the opening ratio in the support layer, making the Maximizing the opening can reduce the risk of insufficient etching when removing the sacrificial layer below the support layer, thereby improving the performance of the memory device.
- the first photomask pattern 100 and the orthographic projection pattern 200 located in the same row have a first offset pitch along the second direction.
- the width of the first photomask pattern 100 may be the same as the width of the second photomask pattern, and the first offset pitch is the width of the first photomask pattern 100 or the width of the second photomask pattern. 1/6 ⁇ 1/3.
- the first offset pitch may be 1/6, 1/5, 1/4 or 1/3 of the width of the first photomask pattern 100; it may also be any other distance located at the width of the first photomask pattern 100. Any width from 1/6 to 1/3 is not limited by the above-mentioned embodiments.
- the first photomask pattern 100 and the orthographic projection pattern 200 located in the same row can also be aligned along the second direction.
- This application also provides a method for preparing a semiconductor structure. As shown in Figure 2, the method for preparing a semiconductor structure may include the following steps:
- S202 Form a stacked structure in which support layers and sacrificial layers are alternately stacked on the upper surface of the substrate;
- S203 Form a capacitor hole in the stacked structure; the capacitor hole penetrates the support layer and the sacrificial layer;
- the photomask component based on any of the above solutions forms a patterned etching mask layer on the stacked structure, and a plurality of etching holes arranged at intervals in multiple rows and columns are formed in the patterned etching mask layer. Opening patterns, the etching opening patterns located in the same row are arranged at intervals along the first direction, the etching opening patterns located in the same column are arranged at intervals along the second direction, and the etching opening patterns in two adjacent columns have second opening patterns along the second direction. Dislocation spacing;
- S206 Form an opening in the stacked structure based on the patterned etching mask layer, expose the sacrificial layer through the opening, and remove the sacrificial layer based on the opening.
- the photomask component of any of the above solutions is used to form a patterned etching mask layer on the stacked structure, and a plurality of patterns in multiple rows are formed in the patterned etching mask layer.
- Etching opening patterns arranged in multiple columns at intervals.
- the etching opening patterns located in the same row are arranged at intervals along the first direction.
- the etching opening patterns located in the same column are arranged at intervals along the second direction.
- the etching opening patterns in two adjacent columns are arranged at intervals along the first direction.
- the pattern has a second dislocation pitch along the second direction; after the capacitor hole is formed in the stacked structure including the support layer and the sacrificial layer alternately stacked and the lower electrode is formed in the capacitor hole, when the opening is formed in the support layer based on the photomask component, Through flexible adjustment, the center of the formed opening can be made to coincide with the center of the area between the three capacitor holes, which can significantly increase the opening ratio in the support layer and maximize the opening formed in the support layer. When the sacrificial layer beneath the support layer is removed, the risk of under-etching is reduced, thereby improving memory device performance.
- step S201 please refer to step S201 in Fig. 2 and Fig. 3 to provide a substrate 1.
- the substrate 1 may include but is not limited to a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or the like.
- device structures such as buried gate word lines and bit lines may be formed in the substrate 1 .
- the above device structures are not shown in FIG. 3 .
- step S202 please refer to step S202 in Figure 2 and Figures 4 to 9, a stacked structure in which support layers and sacrificial layers are alternately stacked is formed on the upper surface of the substrate 1.
- forming a stacked structure in which support layers and sacrificial layers are alternately stacked on the upper surface of the substrate 1 may include the following steps:
- the first support layer 21 , the second support layer 22 and the third support layer 23 may each include, but are not limited to, a single-layer structure of a silicon nitride layer or a silicon carbonitride layer, or may have a single-layer structure including, but not limited to, a silicon nitride layer or a silicon carbonitride layer. It is limited to a double-layer structure or a multi-layer structure in which silicon nitride layers and silicon carbonitride layers are stacked in sequence.
- Both the first sacrificial layer 31 and the second sacrificial layer 32 may include, but are not limited to, silicon oxide layers.
- a physical vapor deposition process, a chemical vapor deposition process or an atomic deposition process may be used to form the first support layer 21 , the second support layer 22 , the third support layer 23 , and the first support layer 23 .
- the thickness of the third support layer 23 may be greater than the thickness of the first support layer 21 and the thickness of the second support layer 22 .
- the thickness of the third support layer 23 may be 180nm ⁇ 300nm. Specifically, the thickness of the third support layer 23 may be 180nm, 200nm, 250nm or 300nm, etc.; the thickness of the second support layer 22 may be 8nm ⁇ 50nm, specifically. , the thickness of the second support layer 22 can be 8nm, 10nm, 20nm, 30nm, 40nm or 50nm, etc.; the thickness of the first support layer 21 can be 6nm ⁇ 20nm, specifically, the thickness of the first support layer 21 can be 6nm. , 10nm, 15nm or 20nm; the thickness of the first sacrificial layer 31 can be 200nm ⁇ 500nm.
- the thickness of the first sacrificial layer 31 can be 200nm, 300nm, 400nm or 500nm, etc.; the thickness of the second sacrificial layer 32 can be It is 400nm ⁇ 500nm. Specifically, the thickness of the second sacrificial layer 32 can be 400nm, 450nm or 500nm, etc.
- step S203 please refer to step S203 in Figure 2 and Figures 10 to 11 to form a capacitor hole 4 in the stacked structure; the capacitor hole 4 penetrates the support layer and the sacrificial layer.
- forming a capacitor hole in the stacked structure may include the following steps:
- S2031 Form a first patterned mask layer (not shown) on the upper surface of the stacked structure.
- a plurality of first opening patterns are formed in the first patterned mask layer.
- the first opening pattern is defined The shape and location of the capacitor hole;
- a hard mask layer (such as a silicon nitride layer, etc.) may be formed on the upper surface of the stacked structure; and then a photoresist layer is formed on the upper surface of the hard mask layer; Then the photoresist layer is exposed and developed to obtain a patterned photoresist layer; and then the hard mask layer is etched based on the patterned photoresist layer to obtain a patterned hard mask layer.
- the mask layer is the first patterned mask layer; finally, the patterned photoresist layer is removed.
- a dry etching process may be used to etch the stacked structure based on the first patterned mask layer.
- step S2033 a chemical mechanical polishing process or an etching process may be used to remove the first patterned mask layer.
- step S204 please refer to step S204 in FIG. 2 and FIG. 12, a lower electrode 41 is formed on the side wall and bottom of the capacitor hole 4.
- the lower electrode 41 may include, but is not limited to, a titanium nitride electrode.
- the lower electrode 41 can be formed on the sidewall and bottom of the capacitor hole 4 using, but not limited to, an electroplating process or a deposition process.
- the thickness of the lower electrode 41 should be less than half the radius of the capacitor hole 4, or even smaller, so that after the deposition of the lower electrode 41, there is still enough space in the capacitor hole 4 to subsequently form the capacitor dielectric layer and the upper electrode.
- step S205 please refer to step S205 in Figure 2 and Figures 13 to 20.
- the photomask assembly based on any of the above solutions forms a patterned etching mask layer 5 on the stacked structure.
- Patterned etching A plurality of etching opening patterns 51 arranged in multiple rows and columns are formed in the mask layer 5 .
- the etching opening patterns 51 located in the same row are arranged at intervals along the first direction.
- the etching opening patterns 51 located in the same column are arranged at intervals.
- two adjacent columns of etching opening patterns 51 have a second offset pitch along the second direction.
- the second offset pitch may be 1/6, 1/5, 1/4 or 1/3 of the width of the etching opening pattern 51; it may also be 1/6 to 1/6 of the width of the etching opening pattern 51. Any width of 1/3 is not limited by the above examples.
- forming a patterned etching mask layer on the stacked structure based on the photomask assembly of any of the above solutions may include the following steps:
- S2051 Form the first mask layer 54 on the upper surface of the stacked structure; specifically, the first mask layer 54 can be formed on the upper surface of the third support layer 23, as shown in Figure 14;
- S2052 Form the second mask layer 55 on the first mask layer 54, as shown in Figure 15;
- S2053 Etch the second mask layer 55 based on the first photomask to form a second patterned mask layer 56.
- a pattern corresponding to the first photomask pattern is formed in the second patterned mask layer 56.
- the second opening pattern 561 is shown in Figure 16;
- S2055 Etch the third mask layer 57 based on the second photomask to form a third patterned mask layer 58.
- a pattern corresponding to the second photomask pattern is formed in the third patterned mask layer 58.
- the third opening pattern 581 is shown in Figure 18;
- S2056 Etch the first mask layer 54 based on the third patterned mask layer 58 and the second patterned mask layer 57 to obtain the patterned etching mask layer 5, as shown in Figures 19 and 20.
- a first mask layer 54 can be formed on the upper surface of the stacked structure using, but not limited to, a physical vapor deposition process or a chemical vapor deposition process.
- the first mask layer 54 may include, but is not limited to, a silicon nitride layer.
- the second mask layer 55 may be formed on the first mask layer 54 using, but not limited to, a physical vapor deposition process or a chemical vapor deposition process.
- the second mask layer 55 may include, but is not limited to, a silicon oxide layer.
- a dry etching process may be used to etch the second mask layer 55 based on the first photomask to form the second patterned mask layer 56. .
- a third mask layer 57 may be formed on the second patterned mask layer 56 using, but not limited to, a physical vapor deposition process or a chemical vapor deposition process.
- the third mask layer 57 may include, but is not limited to, a silicon oxynitride layer.
- a dry etching process may be used to etch the third mask layer 57 based on the second photomask to form the third patterned mask layer 58. .
- the following steps may also be included:
- ACL amorphous carbon layer
- a first silicon oxynitride layer (not shown) is formed on the first amorphous carbon layer.
- the following steps may also be included:
- a second silicon oxynitride layer (not shown) is formed on the first spin-coated carbon layer.
- the following steps may also be included:
- a third silicon oxynitride layer (not shown) is formed on the second spin-coated carbon layer.
- step S206 please refer to step S206 in Figure 2 and Figures 21 to 25.
- An opening is formed in the stacked structure based on the patterned etching mask layer 5, and the opening exposes the sacrificial layer; and the sacrificial layer is removed based on the opening.
- an opening is formed in the stacked structure based on the patterned etching mask layer 5, the opening exposes the sacrificial layer, and the sacrificial layer is removed based on the opening, which may include the following steps:
- S2061 Form the first opening 6 in the third support layer 23 based on the patterned etching mask layer 5, and the first opening exposes the second sacrificial layer 32, as shown in Figure 22;
- S2063 Form a second opening (not shown) in the second support layer 22 based on the patterned etching mask layer 5, and the second opening exposes the first sacrificial layer 31, as shown in Figure 24;
- first opening 6 corresponds to the etching opening pattern 51
- the shape and position of the etching opening pattern 51 marked in FIG. 20 are the shape and position of the first opening 6. Location. Each first opening 6 exposes three adjacent capacitor holes 4 .
- the center of each first opening 6 can coincide with the center of the area where the first opening 6 exposes three adjacent capacitor holes, so as to obtain the maximum opening ratio, so that the third support layer 23 can form The number of the first openings 6 is maximized, which is beneficial to reducing the problem of insufficient etching.
- the shape of the first opening 6 and the shape of the second opening may include but are not limited to a circular shape; specifically, a circular shape facilitates the realization that the center of the first opening 6 is adjacent to the exposed portion of the first opening 6 The centers of the areas where the three capacitor holes are located coincide with each other, and the center of the second opening coincides with the centers of the areas where the three adjacent capacitor holes exposed by the second opening are located.
- a wet etching process can be used to remove the first sacrificial layer 31 and the second sacrificial layer 32 .
- the following steps may also be included:
- S208 Form the upper electrode 43 on the surface of the capacitive dielectric layer 42, as shown in FIG. 27.
- the upper electrode 43 may include, but is not limited to, a titanium nitride electrode.
- the upper electrode 43 may be formed using, but is not limited to, electroplating or deposition processes.
- the capacitive dielectric layer 42 may include, but is not limited to, a high-k dielectric layer to increase the capacitance value of the capacitor per unit area; specifically, the capacitive dielectric layer 42 may include, but is not limited to, a ZrOx (zirconia) layer, HfOx ( Hafnium oxide) layer, RuOx (ruthenium oxide) layer and AlOx (aluminum oxide) layer formed by one or more than two kinds.
- the capacitive dielectric layer 42 may be formed using, but is not limited to, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.
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Abstract
本申请涉及一种光掩膜组件及半导体结构的制备方法。光掩膜组件包括:第一光掩膜,第一光掩膜内具有多个第一光掩膜图形100,多个第一光掩膜图形100呈多行多列间隔排布;第二光掩膜,第二光掩膜内具有多个第二光掩膜图形,多个第二光掩膜图形呈多行多列间隔排布;各列第二光掩膜图形在第一光掩膜的表面的正投影图形200位于相邻两列第一光掩膜图形100之间;位于同一行的第一光掩膜图形100及正投影图形200沿第一方向交替间隔排布,位于同一列的第一光掩膜图形100及位于同一列的正投影图形200均沿第二方向间隔排布。
Description
相关申请的交叉引用
本申请要求于2022年06月15日提交中国专利局、申请号为2022106744467、申请名称为“光掩膜组件及半导体结构的制备方法”的中国专利申请的优先权,所述专利申请的全部内容通过引用结合在本申请中。
本申请涉及集成电路技术领域,特别是涉及一种光掩膜组件及半导体结构的制备方法。
DRAM(Dynamic Random Access Memory,动态随机存储器)是计算机中常用的半导体存储器件,由许多重复的存储单元组成。DRAM以在电容器上存储电荷的形式存储数据,需要在每几个毫秒的间隔内将电容器作规则性的充电放电。
在DRAM器件的制备过程中,在包括由下至上依次叠置的支撑层及牺牲层的叠层结构内形成电容孔及下电极后,基于光掩模在叠层结构上形成图形化掩膜层用于在支撑层内形成开口时,由于存在套刻(OVL,Overlay)偏差,会使得在支撑层内形成的开口较少,从而在基于开口去除位于支撑层下方的牺牲层时,很容易出现刻蚀不足(under etch)而导致牺牲层的残留,从而影响DRAM器件的性能。
发明内容
基于此,有必要针对上述问题,提供一种光掩膜组件及半导体结构的制备方法。
为了实现上述目的,一方面,本申请提供了一种光掩膜组件,包括:
第一光掩膜,所述第一光掩膜内具有多个第一光掩膜图形,多个所述第一光掩膜图形呈多行多列间隔排布;
第二光掩膜,所述第二光掩膜内具有多个第二光掩膜图形,多个所述第二光掩膜图形呈多行多列间隔排布;各列所述第二光掩膜图形在所述第一光掩膜的表面的正投影图形位于相邻两列所述第一光掩膜图形之间;位于同一行的所述第一光掩膜图形及所述正投影图形沿第一方向交替间隔排布,位于同一列的所述第一光掩膜图形及位于同一列的所述正投影图形均沿第二方向间隔排布。
在其中一个实施例中,所述第一光掩膜图形与位于同一行的所述正投影图形沿第二方向具有第一错位间距。
在其中一个实施例中,所述第一光掩膜图形的宽度与所述第二光掩膜图形的宽度相同,所述第一错位间距为所述第一光掩膜图形的宽度或所述第二光掩膜图形的宽度的1/6~1/3。
本申请还提供一种半导体结构的制备方法,包括:
提供衬底;
于所述衬底的上表面形成支撑层及牺牲层交替层叠的叠层结构;
于所述叠层结构内形成电容孔;所述电容孔贯穿所述支撑层及所述牺牲层;
于所述电容孔的侧壁及底部形成下电极;
基于上述任一项方案所述的光掩膜组件于所述叠层结构上形成图形化刻蚀掩膜层,所述图形化刻蚀掩膜层内形成有多个呈多行多列间隔排布的刻蚀开口图形,位于同一行的所述刻蚀开口图形沿第一方向间隔 排布,位于同一列的所述刻蚀开口图形沿第二方向间隔排布,相邻两列所述刻蚀开口图形沿第二方向具有第二错位间距;
基于所述图形化刻蚀掩膜层于所述叠层结构内形成开口,所述开口暴露出所述牺牲层,并基于所述开口去除所述牺牲层。
在其中一个实施例中,所述于所述叠层结构内形成电容孔包括:
于所述叠层结构的上表面形成第一图形化掩膜层,所述第一图形化掩膜层内形成有多个第一开口图形,所述第一开口图形定义出所述电容孔的形状及位置;
基于所述第一图形化掩膜层刻蚀所述叠层结构,以于所述叠层结构内形成所述电容孔;
去除所述第一图形化掩膜层。
在其中一个实施例中,所述基于上述任一项方案所述的光掩膜组件于所述叠层结构上形成图形化刻蚀掩膜层包括:
于所述叠层结构的上表面形成第一掩膜层;
于所述第一掩膜层上形成第二掩膜层;
基于所述第一光掩膜对所述第二掩膜层进行光刻刻蚀,以形成第二图形化掩膜层,所述第二图形化掩膜层内形成有与所述第一光掩膜图形对应的第二开口图形;
于所述第二图形化掩膜层上形成第三掩膜层;
基于所述第二光掩膜对所述第三掩膜层进行光刻刻蚀,以形成第三图形化掩膜层,所述第三图形化掩膜层内形成有与所述第二光掩膜图形对应的第三开口图形;
基于所述第三图形化掩膜层及所述第二图形化掩膜层刻蚀所述第一掩膜层,以得到所述图形化刻蚀掩膜层。
在其中一个实施例中,所述于所述第一掩膜层上形成第二掩膜层之前,包括:
于所述第一掩膜层上形成第一非晶碳层;
于所述第一非晶碳层上形成第一氮氧化硅层。
在其中一个实施例中,所述基于所述第一光掩膜对所述第二掩膜层进行刻蚀之前,包括:
于所述第二掩膜层上形成第一旋涂碳层;
于所述第一旋涂碳层上形成第二氮氧化硅层。
在其中一个实施例中,所述于所述第二图形化掩膜层上形成第三掩膜层之前,包括:
于所述第二图形化掩膜层上及所述第二开口图形内形成第二旋涂碳层;
于所述第二旋涂碳层上形成第三氮氧化硅层。
在其中一个实施例中,所述于所述衬底的上表面形成支撑层及牺牲层交替层叠的叠层结构包括:
于所述衬底的上表面形成第一支撑层;
于所述第一支撑层的上表面形成第一牺牲层;
于所述第一牺牲层的上表面形成第二支撑层;
于所述第二支撑层的上表面形成第二牺牲层;
于所述第二牺牲层的上表面形成第三支撑层。
在其中一个实施例中,所述第一支撑层、所述第二支撑层及所述第三支撑层均包括氮化硅层或碳氮化硅层,所述第一牺牲层及所述第二牺牲层均包括氧化硅层。
在其中一个实施例中,所述基于所述图形化刻蚀掩膜层于所述叠层结构内形成开口,所述开口暴露出所述牺牲层,并基于所述开口去除所述牺牲层,包括:
基于所述图形化刻蚀掩膜层于所述第三支撑层内形成第一开口,所述第一开口暴露出所述第二牺牲 层;
基于所述第一开口去除所述第二牺牲层;
基于所述图形化刻蚀掩膜层于所述第二支撑层内形成第二开口,所述第二开口暴露出所述第一牺牲层;
基于所述第二开口去除所述第一牺牲层。
在其中一个实施例中,各所述第一开口均暴露出相邻的三个所述电容孔。
在其中一个实施例中,各所述第一开口的中心与所述第一开口暴露出的相邻的三个所述电容孔所在区域的中心相重合。
在其中一个实施例中,所述第一开口的形状及所述第二开口的形状均为圆形。
在其中一个实施例中,所述第三支撑层的厚度大于所述第一支撑层的厚度及所述第二支撑层的厚度。
在其中一个实施例中,所述基于所述开口去除所述牺牲层之后,还包括:
于所述下电极的表面形成电容介质层;
于所述电容介质层的表面形成上电极。
在其中一个实施例中,所述上电极及所述下电极均包括氮化钛电极;所述电容介质层包括高k介质层。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
为了更清楚地说明本申请实施例或传统技术中的技术方案,下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
为了更好地描述和说明这里公开的那些的实施例和/或示例,可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为一实施例中提供的光掩膜组件的结构示意图;
图2为一实施例中提供的半导体结构的制备方法的流程示意图;
图3为一实施例中提供的半导体结构的制备方法中步骤S201所得结构的立体结构示意图;
图4为一实施例中提供的半导体结构的制备方法中步骤S202的流程图;
图5为一实施例中提供的半导体结构的制备方法中步骤S2021所得结构的立体结构示意图;
图6为一实施例中提供的半导体结构的制备方法中步骤S2022所得结构的立体结构示意图;
图7为一实施例中提供的半导体结构的制备方法中步骤S2023所得结构的立体结构示意图;
图8为一实施例中提供的半导体结构的制备方法中步骤S2024所得结构的立体结构示意图;
图9为一实施例中提供的半导体结构的制备方法中步骤S2025所得结构的立体结构示意图;
图10为一实施例中提供的半导体结构的制备方法中步骤S203的流程示意图;
图11为一实施例中提供的半导体结构的制备方法中步骤S203所得结构的立体结构示意图;
图12为一实施例中提供的半导体结构的制备方法中步骤S204所得结构的立体结构示意图;
图13为一实施例中提供的半导体结构的制备方法中步骤S205的流程示意图;
图14为一实施例中提供的半导体结构的制备方法中步骤S2051所得结构的立体结构示意图;
图15为一实施例中提供的半导体结构的制备方法中步骤S2052所得结构的立体结构示意图;
图16为一实施例中提供的半导体结构的制备方法中步骤S2053所得结构的立体结构示意图;
图17为一实施例中提供的半导体结构的制备方法中步骤S2054所得结构的立体结构示意图;
图18为一实施例中提供的半导体结构的制备方法中步骤S2055所得结构的立体结构示意图;
图19为一实施例中提供的半导体结构的制备方法中步骤S2056所得结构的立体结构示意图;
图20为一实施例中提供的半导体结构的制备方法中步骤S2056所得结构的俯视结构示意图;
图21为一实施例中提供的半导体结构的制备方法中步骤S206的流程示意图;
图22为一实施例中提供的半导体结构的制备方法中步骤S2061所得结构的截面结构示意图;
图23为一实施例中提供的半导体结构的制备方法中步骤S2062所得结构的截面结构示意图;
图24为一实施例中提供的半导体结构的制备方法中步骤S2063所得结构的截面结构示意图;
图25为一实施例中提供的半导体结构的制备方法中步骤S2064所得结构的截面结构示意图;
图26为一实施例中提供的半导体结构的制备方法中步骤S207所得结构的截面结构示意图;
图27为一实施例中提供的半导体结构的制备方法中步骤S208所得结构的截面结构示意图。
附图标记说明:
100、第一光掩膜图形;200、正投影图形;1、衬底;21、第一支撑层;22、第二支撑层;23、第三支撑层;31、第一牺牲层;32、第二牺牲层;4、电容孔;41、下电极;42、电容介质层;43、上电极;5、图形化刻蚀掩膜层;51、刻蚀开口图形;54、第一掩膜层;55、第二掩膜层;56、第二图形化掩膜层;561、第二开口图形;57、第三掩膜层;58、第三图形化掩膜层;581、第三开口图形;6、第一开口。
为了便于理解本申请,下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是,本申请可以以许多不同的形式来实现,并不限于本文所描述的实施例。相反地,提供这些实施例的目的是使对本申请的公开内容更加透彻全面。除非另有定义,本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本申请。
应当明白,当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时,其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分,这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此,在不脱离本申请教导之下,下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分;举例来说,可以将第一掺杂类型成为第二掺杂类型,且类似地,可以将第二掺杂类型成为第一掺杂类型;第一掺杂类型与第二掺杂类型为不同的掺杂类型,譬如,第一掺杂类型可以为P型且第二掺杂类型可以为N型,或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等,在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白,除了图中所示的取向以外,空间关系术语还包括使用和操作中的器件的不同取向。例如,如果附图中的器件翻转,描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此,示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外,器件也可以包括另外地取向(譬如,旋转90度或其它取向),并且在此使用的空间描述语相应地被解释。
在此使用时,单数形式的“一”、“一个”和“所述/该”也可以包括复数形式,除非上下文清楚指出另 外的方式。还应明白,当术语“组成”和/或“包括”在该说明书中使用时,可以确定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时,在此使用时,术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述本申请的实施例,这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此,本申请的实施例不应当局限于在此所示的区的特定形状,而是包括由于例如制造技术导致的形状偏差。例如,显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度,而不是从注入区到非注入区的二元改变。同样,通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此,图中显示的区实质上是示意性的,它们的形状并不表示器件的区的实际形状,且并不限定本申请的范围。
本实施例提供了一种半导体结构的制备方法,DRAM(Dynamic Random Access Memory,动态随机存储器)是常用的半导体存储器件,由许多重复的存储单元组成。DRAM以在电容器上存储电荷的形式存储数据,需要在每几个毫秒的间隔内将电容器作规则性的充电放电。在DRAM器件的制备过程中,在包括由下至上依次叠置的支撑层及牺牲层的叠层结构内形成电容孔及下电极后,基于光掩模在叠层结构上形成图形化掩膜层用于在支撑层内形成开口时,由于存在套刻(OVL,Overlay)偏差,会使得在支撑层内形成的开口较少,从而在基于开口去除位于支撑层下方的牺牲层时,很容易出现刻蚀不足(under etch)而导致牺牲层的残留,从而影响DRAM器件的性能。
基于此,有必要针对上述问题,提供一种光掩膜组件及半导体结构的制备方法。
为了实现上述目的,本申请的实施例提供了一种光掩膜组件,如图1所示,光掩膜组件包括:第一光掩膜及第二光掩膜(图未示出);第一光掩膜内具有多个第一光掩膜图形100,多个第一光掩膜图形100呈多行多列间隔排布;第二光掩膜内具有多个第二光掩膜图形,多个第二光掩膜图形呈多行多列间隔排布;各列第二光掩膜图形在第一光掩膜的表面的正投影图形200位于相邻两列第一光掩膜图形100之间;位于同一行的第一光掩膜图形100及正投影图形200沿第一方向交替间隔排布,位于同一列的第一光掩膜图形100及位于同一列的正投影图形200均沿第二方向间隔排布。
上述实施例的光掩膜组件,各列第二光掩膜图形在第一光掩膜的表面的正投影图形位于相邻两列第一光掩膜图形100之间,位于同一行的第一光掩膜图形100及正投影图形200沿第一方向交替间隔排布,位于同一列的第一光掩膜图形100及位于同一列的正投影图形均沿第二方向间隔排布,即在调整第二光掩膜图形时不会遮挡第一光掩膜图形100,在包括支撑层及牺牲层交替层叠的叠层结构内形成电容孔并在电容孔内形成下电极后,基于光掩膜组件在支撑层内形成开口时,通过灵活的调整,可以使得形成的开口的中心与三个电容孔之间的区域中心相重合,可以显著增大支撑层内的开口率,使得支撑层内形成的开口最大化,在基于支撑层去除支撑层下方的牺牲层时,可以降低蚀刻不足的风险,从而提升存储器件的性能。
在一个实施例中,参阅图1,第一光掩膜图形100与位于同一行的正投影图形200沿第二方向具有第一错位间距。
在一个实施例中,第一光掩膜图形100的宽度可以与第二光掩膜图形的宽度相同,第一错位间距为第一光掩膜图形100的宽度或第二光掩膜图形的宽度的1/6~1/3。
具体地,第一错位间距可以是第一光掩膜图形100的宽度的1/6、1/5、1/4或1/3;也可以是其他位于第一光掩膜图形100的宽度的1/6~1/3的任意宽度,不受上述实施例例举所限制。
当然,在其他示例中,第一光掩膜图形100与位于同一行的正投影图形200也可以沿第二方向对齐。
本申请还提供一种半导体结构的制备方法,如图2所示,半导体结构的制备方法可以包括如下步骤:
S201:提供衬底;
S202:于衬底的上表面形成支撑层及牺牲层交替层叠的叠层结构;
S203:于叠层结构内形成电容孔;电容孔贯穿支撑层及牺牲层;
S204:于电容孔的侧壁及底部形成下电极;
S205:基于上述任一项方案的光掩膜组件于叠层结构上形成图形化刻蚀掩膜层,图形化刻蚀掩膜层内形成有多个呈多行多列间隔排布的刻蚀开口图形,位于同一行的刻蚀开口图形沿第一方向间隔排布,位于同一列的刻蚀开口图形沿第二方向间隔排布,相邻两列刻蚀开口图形沿第二方向具有第二错位间距;
S206:基于图形化刻蚀掩膜层于叠层结构内形成开口,开口暴露出牺牲层,并基于开口去除牺牲层。
上述实施例的半导体结构的制备方法,采用上述任一项方案的光掩膜组件于叠层结构上形成图形化刻蚀掩膜层,图形化刻蚀掩膜层内形成有多个呈多行多列间隔排布的刻蚀开口图形,位于同一行的刻蚀开口图形沿第一方向间隔排布,位于同一列的刻蚀开口图形沿第二方向间隔排布,相邻两列刻蚀开口图形沿第二方向具有第二错位间距;包括支撑层及牺牲层交替层叠的叠层结构内形成电容孔并在电容孔内形成下电极后,基于光掩膜组件在支撑层内形成开口时,通过灵活的调整,可以使得形成的开口的中心与三个电容孔之间的区域中心相重合,可以显著增大支撑层内的开口率,使得支撑层内形成的开口最大化,在基于支撑层去除支撑层下方的牺牲层时,可以降低蚀刻不足的风险,从而提升存储器件的性能。
在步骤S201中,请参阅图2中的S201步骤及图3,提供衬底1。
在一个示例中,衬底1可以包括但不仅限于硅衬底、碳化硅衬底或氮化镓衬底等等。
在另一个示例中,衬底1内可以形成有埋入式栅极字线及位线等器件结构,图3中并未示出上述器件结构。
在步骤S202中,请参阅图2中的S202步骤及图4至图9,于衬底1的上表面形成支撑层及牺牲层交替层叠的叠层结构。
在一个实施例中,如图4所示,S202中,于衬底1的上表面形成支撑层及牺牲层交替层叠的叠层结构可以包括如下步骤:
S2021:于衬底1的上表面形成第一支撑层21,如图5所示;
S2022:于第一支撑层21的上表面形成第一牺牲层31,如图6所示;
S2023:于第一牺牲层31的上表面形成第二支撑层22,如图7所示;
S2024:于第二支撑层22的上表面形成第二牺牲层32,如图8所示;
S2025:于第二牺牲层32的上表面形成第三支撑层23,如图9所示。
在一个实施例中,第一支撑层21、第二支撑层22及第三支撑层23均可以包括但不仅限于氮化硅层或碳氮化硅层的单层结构,也可以为包括但不仅限于氮化硅层和碳氮化硅层依次叠置的双层结构或多层结构。第一牺牲层31及第二牺牲层32均可以包括但不仅限于氧化硅层。
在一个实施例中,上述各步骤中,可以采用但不仅限于物理气相沉积工艺、化学气相沉积工艺或原子沉积工艺形成第一支撑层21、第二支撑层22、第三支撑层23、第一牺牲层31及第二牺牲层32。
在一个实施例中,第三支撑层23的厚度可以大于第一支撑层21的厚度及第二支撑层22的厚度。
第三支撑层23的厚度可以是180nm~300nm,具体的,第三支撑层23的厚度可以为180nm、200nm、250nm或300nm等等;第二支撑层22的厚度可以是8nm~50nm,具体的,第二支撑层22的厚度可以为8nm、10nm、20nm、30nm、40nm或50nm等等;第一支撑层21的厚度可以是6nm~20nm,具体的,第一支撑层21的厚度可以为6nm、10nm、15nm或20nm;第一牺牲层31的厚度可以是200nm~500nm,具体的,第一牺牲层31的厚度可以为200nm、300nm、400nm或500nm等等;第二牺牲层32的厚度可以是400nm~500nm,具体的,第二牺牲层32的厚度可以为400nm、450nm或500nm等等。
在步骤S203中,请参阅图2中的S203步骤及图10至图11,于叠层结构内形成电容孔4;电容孔4贯穿支撑层及牺牲层。
在一个实施例中,如图10所示,S203中,于叠层结构内形成电容孔可以包括如下步骤:
S2031:于叠层结构的上表面形成第一图形化掩膜层(未示出),第一图形化掩膜层内形成有多个第一开口图形(未示出),第一开口图形定义出电容孔的形状及位置;
S2032:基于第一图形化掩膜层刻蚀叠层结构,以于叠层结构内形成电容孔4,如图11所示;
S2033:去除第一图形化掩膜层;去除第一图形化掩膜层后的结构如图11所示。
在一个实施例中,在步骤S2031中,可以先于叠层结构的上表面形成硬掩膜层(譬如氮化硅层等等);然后在硬掩膜层的上表面形成光刻胶层;接着将光刻胶层曝光显影以得到图形化的光刻胶层;接着再基于图形化的光刻胶层刻蚀硬掩膜层,即可得到图形化的硬掩膜层,图形化的硬掩膜层即为第一图形化掩膜层;最后去除图形化的光刻胶层。
在一个实施例中,步骤S2032中,可以采用干法刻蚀工艺基于第一图形化掩膜层刻蚀叠层结构。
在一个实施例中,步骤S2033中,可以采用化学机械研磨工艺或刻蚀工艺去除第一图形化掩膜层。
在步骤S204中,请参阅图2中的S204步骤及图12,于电容孔4的侧壁及底部形成下电极41。
在一个示例中,下电极41可以包括但不仅限于氮化钛电极。
在一个实施例中,可以采用但不仅限于电镀工艺或沉积工艺于电容孔4的侧壁及底部形成下电极41。
需要说明的是,下电极41的厚度要小于电容孔4半径的一半,甚至更小,以在下电极41沉积之后,使得电容孔4内还具有足够的空间在后续形成电容介质层及上电极。
在步骤S205中,请参阅图2中的S205步骤及图13至图20,基于上述任一项方案的光掩膜组件于叠层结构上形成图形化刻蚀掩膜层5,图形化刻蚀掩膜层5内形成有多个呈多行多列间隔排布的刻蚀开口图形51,位于同一行的刻蚀开口图形51沿第一方向间隔排布,位于同一列的刻蚀开口图形51沿第二方向间隔排布,相邻两列刻蚀开口图形51沿第二方向具有第二错位间距。
具体地,第二错位间距可以是刻蚀开口图形51的宽度的1/6、1/5、1/4或1/3;也可以是其他位于刻蚀开口图形51的宽度的1/6~1/3的任意宽度,不受上述实施例例举所限制。
在一个实施例中,如图13所示,S205中,基于上述任一项方案的光掩膜组件于叠层结构上形成图形化刻蚀掩膜层可以包括如下步骤:
S2051:于叠层结构的上表面形成第一掩膜层54;具体的,可以于第三支撑层23的上表面形成第一掩膜层54,如图14所示;
S2052:于第一掩膜层54上形成第二掩膜层55,如图15所示;
S2053:基于第一光掩膜对第二掩膜层55进行刻蚀,以形成第二图形化掩膜层56,第二图形化掩膜层56内形成有与第一光掩膜图形对应的第二开口图形561,如图16所示;
S2054:于第二图形化掩膜层56上形成第三掩膜层57,如图17所示;
S2055:基于第二光掩膜对第三掩膜层57进行刻蚀,以形成第三图形化掩膜层58,第三图形化掩膜层58内形成有与第二光掩膜图形对应的第三开口图形581,如图18所示;
S2056:基于第三图形化掩膜层58及第二图形化掩膜层57刻蚀第一掩膜层54,以得到图形化刻蚀掩膜层5,如图19及图20所示。
在一个实施例中,在步骤S2051中,请参阅图14,可以采用但不仅限于物理气相沉积工艺或化学气相沉积工艺于叠层结构的上表面形成第一掩膜层54。第一掩膜层54可以包括但不仅限于氮化硅层。
在一个实施例中,在步骤S2052中,请参阅图15,可以采用但不仅限于物理气相沉积工艺或化学气相沉积工艺于第一掩膜层54上形成第二掩膜层55。第二掩膜层55可以包括但不仅限氧化硅层。
在一个实施例中,在步骤S2053中,请参阅图16,可以采用干法刻蚀工艺基于第一光掩膜对第二掩膜层55进行刻蚀,以形成第二图形化掩膜层56。
在一个实施例中,在步骤S2054中,请参阅图17,可以采用但不仅限于物理气相沉积工艺或化学气相沉积工艺于第二图形化掩膜层56上形成第三掩膜层57。第三掩膜层57可以包括但不仅限于氮氧化硅层。
在一个实施例中,在步骤S2055中,请参阅图18,可以采用干法刻蚀工艺基于第二光掩膜对第三掩膜层57进行刻蚀,以形成第三图形化掩膜层58。
在一个实施例中,于第一掩膜层54上形成第二掩膜层55之前,还可以包括如下步骤:
于第一掩膜层54上形成第一非晶碳层(amorphous carbon,ACL)(未示出);
于第一非晶碳层上形成第一氮氧化硅层(未示出)。
在一个实施例中,基于第一光掩膜对第二掩膜层55进行刻蚀之前,还可以包括如下步骤:
于第二掩膜层55上形成第一旋涂碳层(未示出);
于第一旋涂碳层上形成第二氮氧化硅层(未示出)。
在一个实施例中,于第二图形化掩膜层56上形成第三掩膜层57之前,还可以包括如下步骤:
于第二图形化掩膜层56上及第二开口图形561内形成第二旋涂碳层(未示出);
于第二旋涂碳层上形成第三氮氧化硅层(未示出)。
在步骤S206中,请参阅图2中的S206步骤及图21至图25,基于图形化刻蚀掩膜层5于叠层结构内形成开口,开口暴露出牺牲层;并基于开口去除牺牲层。
在一个实施例中,如图21所示,S206中,基于图形化刻蚀掩膜层5于叠层结构内形成开口,开口暴露出牺牲层,并基于开口去除牺牲层,可以包括如下步骤:
S2061:基于图形化刻蚀掩膜层5于第三支撑层23内形成第一开口6,第一开口暴露出第二牺牲层32,如图22所示;
S2062:基于第一开口6去除第二牺牲层32,如图23所示;
S2063:基于图形化刻蚀掩膜层5于第二支撑层22内形成第二开口(图未示出),第二开口暴露出第一牺牲层31,如图24所示;
S2064:基于第二开口去除第一牺牲层31,如图25所示。
在一个实施例中,由于第一开口6与刻蚀开口图形51相对应,请继续参阅图20,图20中标识出的刻蚀开口图形51的形状及位置即为第一开口6的形状及位置。各第一开口6均暴露出相邻的三个电容孔4。
在一个实施例中,各第一开口6的中心可以与第一开口6暴露出相邻的三个电容孔所在区域的中心相重合,可以获得最大的开口率,使得第三支撑层23内形成的第一开口6的数量达到最大化,有利于减少蚀刻不足的问题。
在一个实施例中,第一开口6的形状及第二开口的形状均可以包括但不仅限于圆形;具体地,圆形便于实现第一开口6的中心与第一开口6暴露出的相邻的三个电容孔所在区域的中心重合,及第二开口的中心与第二开口暴露出的相邻的三个电容孔所在区域的中心重合。
在一个实施例中,可以采用湿法刻蚀工艺去除第一牺牲层31及第二牺牲层32。
在一个实施例中,基于开口去除牺牲层之后,还可以包括如下步骤:
S207:于下电极41的表面形成电容介质层42,如图26所示;
S208:于电容介质层42的表面形成上电极43,如图27所示。
在一个实施例中,上电极43可以包括但不仅限于氮化钛电极。可以采用但不仅限于电镀或沉积工艺形成上电极43。
在一个实施例中,电容介质层42可以包括但不仅限于高k介质层,以提高单位面积电容器的电容值;具体地,电容介质层42可以包括但不仅限于ZrOx(氧化锆)层、HfOx(氧化铪)层、RuOx(氧化钌)层和AlOx(氧化铝)中的一种或两种以上所形成的叠层。可以采用但不仅限于物理气相沉积工艺、化学 气相沉积工艺或原子层沉积工艺形成电容介质层42。
应该理解的是,虽然如上的各实施例所涉及的流程图中的各个步骤按照箭头的指示依次显示,但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明,这些步骤的执行并没有严格的顺序限制,这些步骤可以以其它的顺序执行。而且,如上的各实施例所涉及的流程图中的至少一部分步骤可以包括多个步骤或者多个阶段,这些步骤或者阶段并不必然是在同一时刻执行完成,而是可以在不同的时刻执行,这些步骤或者阶段的执行顺序也不必然是依次进行,而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
以上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对申请专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本申请构思的前提下,还可以做出若干变形和改进,这些都属于本申请的保护范围。因此,本申请专利的保护范围应以所附权利要求为准。
Claims (18)
- 一种光掩膜组件,包括:第一光掩膜,所述第一光掩膜内具有多个第一光掩膜图形,多个所述第一光掩膜图形呈多行多列间隔排布;第二光掩膜,所述第二光掩膜内具有多个第二光掩膜图形,多个所述第二光掩膜图形呈多行多列间隔排布;各列所述第二光掩膜图形在所述第一光掩膜的表面的正投影图形位于相邻两列所述第一光掩膜图形之间;位于同一行的所述第一光掩膜图形及所述正投影图形沿第一方向交替间隔排布,位于同一列的所述第一光掩膜图形及位于同一列的所述正投影图形均沿第二方向间隔排布。
- 根据权利要求1所述的光掩膜组件,其中,所述第一光掩膜图形与位于同一行的所述正投影图形沿第二方向具有第一错位间距。
- 根据权利要求2所述的光掩膜组件,其中,所述第一光掩膜图形的宽度与所述第二光掩膜图形的宽度相同,所述第一错位间距为所述第一光掩膜图形的宽度或所述第二光掩膜图形的宽度的1/6~1/3。
- 一种半导体结构的制备方法,包括:提供衬底;于所述衬底的上表面形成支撑层及牺牲层交替层叠的叠层结构;于所述叠层结构内形成电容孔;所述电容孔贯穿所述支撑层及所述牺牲层;于所述电容孔的侧壁及底部形成下电极;基于如权利要求1至3中任一项所述的光掩膜组件于所述叠层结构上形成图形化刻蚀掩膜层,所述图形化刻蚀掩膜层内形成有多个呈多行多列间隔排布的刻蚀开口图形,位于同一行的所述刻蚀开口图形沿第一方向间隔排布,位于同一列的所述刻蚀开口图形沿第二方向间隔排布,相邻两列所述刻蚀开口图形沿第二方向具有第二错位间距;以及基于所述图形化刻蚀掩膜层于所述叠层结构内形成开口,所述开口暴露出所述牺牲层,并基于所述开口去除所述牺牲层。
- 根据权利要求4所述的半导体结构的制备方法,其中,所述于所述叠层结构内形成电容孔包括:于所述叠层结构的上表面形成第一图形化掩膜层,所述第一图形化掩膜层内形成有多个第一开口图形,所述第一开口图形定义出所述电容孔的形状及位置;基于所述第一图形化掩膜层刻蚀所述叠层结构,以于所述叠层结构内形成所述电容孔;以及去除所述第一图形化掩膜层。
- 根据权利要求5所述的半导体结构的制备方法,其中,所述基于如权利要求1至3中任一项所述的光掩膜组件于所述叠层结构上形成图形化刻蚀掩膜层包括:于所述叠层结构的上表面形成第一掩膜层;于所述第一掩膜层上形成第二掩膜层;基于所述第一光掩膜对所述第二掩膜层进行光刻刻蚀,以形成第二图形化掩膜层,所述第二图形化掩膜层内形成有与所述第一光掩膜图形对应的第二开口图形;于所述第二图形化掩膜层上形成第三掩膜层;基于所述第二光掩膜对所述第三掩膜层进行光刻刻蚀,以形成第三图形化掩膜层,所述第三图形化掩膜层内形成有与所述第二光掩膜图形对应的第三开口图形;以及基于所述第三图形化掩膜层及所述第二图形化掩膜层刻蚀所述第一掩膜层,以得到所述图形化刻蚀掩膜层。
- 根据权利要求6所述的半导体结构的制备方法,其中,所述于所述第一掩膜层上形成第二掩膜层 之前,包括:于所述第一掩膜层上形成第一非晶碳层;以及于所述第一非晶碳层上形成第一氮氧化硅层。
- 根据权利要求6所述的半导体结构的制备方法,其中,所述基于所述第一光掩膜对所述第二掩膜层进行刻蚀之前,包括:于所述第二掩膜层上形成第一旋涂碳层;以及于所述第一旋涂碳层上形成第二氮氧化硅层。
- 根据权利要求6所述的半导体结构的制备方法,其中,所述于所述第二图形化掩膜层上形成第三掩膜层之前,包括:于所述第二图形化掩膜层上及所述第二开口图形内形成第二旋涂碳层;以及于所述第二旋涂碳层上形成第三氮氧化硅层。
- 根据权利要求4所述的半导体结构的制备方法,其中,所述于所述衬底的上表面形成支撑层及牺牲层交替层叠的叠层结构包括:于所述衬底的上表面形成第一支撑层;于所述第一支撑层的上表面形成第一牺牲层;于所述第一牺牲层的上表面形成第二支撑层;于所述第二支撑层的上表面形成第二牺牲层;以及于所述第二牺牲层的上表面形成第三支撑层。
- 根据权利要求10所述的半导体结构的制备方法,其中,所述第一支撑层、所述第二支撑层及所述第三支撑层均包括氮化硅层或碳氮化硅层,所述第一牺牲层及所述第二牺牲层均包括氧化硅层。
- 根据权利要求10所述的半导体结构的制备方法,其中,所述基于所述图形化刻蚀掩膜层于所述叠层结构内形成开口,所述开口暴露出所述牺牲层,并基于所述开口去除所述牺牲层,包括:基于所述图形化刻蚀掩膜层于所述第三支撑层内形成第一开口,所述第一开口暴露出所述第二牺牲层;基于所述第一开口去除所述第二牺牲层;基于所述图形化刻蚀掩膜层于所述第二支撑层内形成第二开口,所述第二开口暴露出所述第一牺牲层;以及基于所述第二开口去除所述第一牺牲层。
- 根据权利要求12所述的半导体结构的制备方法,其中,各所述第一开口均暴露出相邻的三个所述电容孔。
- 根据权利要求13所述的半导体结构的制备方法,其中,各所述第一开口的中心与所述第一开口暴露出的相邻的三个所述电容孔所在区域的中心相重合。
- 根据权利要求12所述的半导体结构的制备方法,其中,所述第一开口的形状及所述第二开口的形状均为圆形。
- 根据权利要求10所述的半导体结构的制备方法,其中,所述第三支撑层的厚度大于所述第一支撑层的厚度及所述第二支撑层的厚度。
- 根据权利要求4至16中任一项所述的半导体结构的制备方法,其中,所述基于所述开口去除所述牺牲层之后,还包括:于所述下电极的表面形成电容介质层;以及于所述电容介质层的表面形成上电极。
- 根据权利要求17所述的半导体结构的制备方法,其中,所述上电极及所述下电极均包括氮化钛电极;所述电容介质层包括高k介质层。
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CN113206074A (zh) * | 2021-04-30 | 2021-08-03 | 福建省晋华集成电路有限公司 | 半导体器件及其制备方法 |
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