WO2023236245A1 - 逻辑分析解码方法及装置 - Google Patents

逻辑分析解码方法及装置 Download PDF

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Publication number
WO2023236245A1
WO2023236245A1 PCT/CN2022/099838 CN2022099838W WO2023236245A1 WO 2023236245 A1 WO2023236245 A1 WO 2023236245A1 CN 2022099838 W CN2022099838 W CN 2022099838W WO 2023236245 A1 WO2023236245 A1 WO 2023236245A1
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Prior art keywords
sampling
clock frequency
memory circuit
circuit block
chip select
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PCT/CN2022/099838
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English (en)
French (fr)
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王鹏
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Definitions

  • the present disclosure relates to the field of semiconductor testing technology, and in particular, to a logic analysis and decoding method and device.
  • Logic analysis is a method of analyzing the behavior pattern of a circuit and an important testing method for testing the electrical performance of a circuit.
  • the logic analysis of the circuit is mainly carried out using a logic analyzer, that is, the circuit is sampled by the logic analyzer, and the behavior pattern of the circuit is obtained by decoding the sampling results.
  • the decoding of the logic analyzer is almost always based on the decoding of the sampling results of the circuit at a fixed clock frequency.
  • the traditional logic analysis decoding method ensures the accuracy of decoding by synchronizing the sampling frequency of the logic analyzer with the fixed clock frequency of the circuit. sex.
  • circuits perform more and more variable-frequency operations, and traditional logic analysis and decoding methods cannot be applied to the behavior of circuits in variable-frequency application environments.
  • the logic analysis and decoding methods and devices provided by some embodiments of the present disclosure are used to solve the problem of being unable to perform logic analysis and decoding on memory circuit blocks in a variable frequency environment, so as to expand the application field of logic analysis.
  • the present disclosure provides a logical analysis decoding method, including the following steps:
  • sampling file includes a plurality of sampling results, and each of the sampling results includes a sampling point and the sampling point corresponding to the sampling point.
  • the pin status of the memory circuit block, the instruction sequence file includes a plurality of test instructions applied to the memory circuit block;
  • the specific steps of obtaining the sampling file of the memory circuit block include:
  • a logic analyzer is used to obtain sampling files of memory circuit blocks at a fixed sampling frequency.
  • the specific step of determining whether the memory circuit block triggers frequency conversion based on the aligned multiple test instructions and multiple sampling results further includes:
  • the first loop steps include:
  • the pin state includes a first state and a second state; the specific steps of calculating the first current clock frequency of the memory circuit block based on the preset number of sampling results include:
  • Each group of the first sub-sampling results includes a plurality of continuously distributed first states, and a plurality of continuously distributed first states.
  • the trigger threshold is 300 MHz.
  • the specific steps of calculating the switching clock frequency of the memory circuit block based on the plurality of sampling results include:
  • the second loop step includes:
  • the test instructions include a chip select signal and an address signal; the specific steps of aligning multiple test instructions and multiple sampling results according to the switching clock frequency include:
  • the address signal and the pin state in the sampling result are aligned according to the switching clock frequency.
  • the sampling file includes a plurality of record lines arranged in chronological order, each of the record lines records one of the sampling results; the chip select signal and the chip select signal are aligned according to the switching clock frequency.
  • the specific steps for sampling the pin status in the result include:
  • the difference between the first chip select time and the second chip select time is calculated as the configuration time of the chip select signal.
  • the specific steps of aligning the address signal and the pin state in the sampling result according to the switching clock frequency include:
  • the switching clock frequency select the recording row in which the pin state changes from the first state to the second state after applying the address signal to the memory circuit block as the current address row;
  • the difference between the first address time and the second address time is calculated as the configuration time of the address signal.
  • the configuration time of the chip select signal and the configuration time of the address signal are used as decoding instructions, and the configuration in which the decoding instructions are aligned with the fixed sampling frequency is used to continue decoding the sampling result.
  • the present disclosure also provides a logic analysis and decoding device, including a processor, and further including:
  • a memory connected to the processor, is used to store a sampling file of the memory circuit block and generate an instruction sequence file of the memory circuit block.
  • the sampling file includes a plurality of sampling results, and each sampling result includes a sampling point, And the pin status of the memory circuit block corresponding to the sampling point, the instruction sequence file includes a plurality of test instructions applied to the memory circuit block;
  • a first alignment circuit connected to the processor, used to align a plurality of the test instructions and a plurality of the sampling results according to the initial clock frequency;
  • a judgment circuit connected to the processor, is used to judge whether the memory circuit block triggers frequency conversion according to the aligned multiple test instructions and the multiple sampling results. If so, calculate the frequency conversion based on the multiple sampling results.
  • a second alignment circuit is connected to the processor and used to align a plurality of test instructions and a plurality of sampling results according to the switching clock frequency.
  • it also includes:
  • the access port is connected to the memory and is used to receive the sampling file of the memory circuit block obtained by the logic analyzer at a fixed sampling frequency.
  • the plurality of sampling results in the memory are arranged in sequence according to the time order of sampling;
  • the judgment circuit includes a first loop circuit, and the first loop circuit is used to perform the following first loop at least once Steps, until the first current clock frequency of the memory circuit block is greater than the trigger threshold, the first loop step includes:
  • the pin state includes a first state and a second state
  • the first loop circuit is also used to separate the preset number of sampling results arranged in time sequence into multiple groups of first sub-sampling results, and each group of the first sub-sampling results includes a plurality of continuously distributed a first state, and a number of continuously distributed second states adjacent to a number of continuously distributed first states; the first loop circuit is also used to calculate the frequency of each group of the first subsampling results respectively. , as the first sub-clock frequency; the first loop circuit is also used to calculate an average of multiple first sub-clock frequencies as the first current clock frequency.
  • the trigger threshold is 300 MHz.
  • the judgment circuit further includes a second loop circuit configured to use the first initial position corresponding to the first current clock frequency greater than the trigger threshold as the third Second initial position, perform the following second loop step at least once until the second current clock frequency calculated in at least two adjacent second loop steps is the same, and use the same second current clock frequency as the The switching clock frequency of the memory circuit block; the second cycle step includes:
  • the test instructions include a chip select signal and an address signal; the second alignment circuit is also used to align the chip select signal with the pin in the sampling result according to the switching clock frequency. state, and align the address signal with the pin state in the sampling result according to the switching clock frequency.
  • the sampling file includes a plurality of record lines arranged in chronological order, and each of the record lines records one of the sampling results;
  • the second alignment circuit includes a chip select signal alignment circuit.
  • the chip select signal alignment circuit is configured to apply the chip select signal to the memory circuit block according to the switching clock frequency. After the pin status is determined by the The record line whose first state changes to the second state is used as the current line of chip select; the chip select signal alignment circuit is also used to obtain the two record lines adjacent to the current line of chip select. The time interval between is used as the first chip select time, and the pin state in the sampling result before the current row of the chip select is obtained from the first state to the second state. The time interval between the record line and the current line of the chip select is used as the second chip select time; the chip select signal alignment circuit is also used to calculate the time between the first chip select time and the second chip select time. The difference is used as the configuration time of the chip select signal.
  • the second alignment circuit further includes an address signal alignment circuit configured to select the pin after applying the address signal to the memory circuit block according to the switching clock frequency.
  • the record line whose state changes from the first state to the second state is used as the current line of address, and the time interval between the two record lines adjacent to the current line of address is obtained as the third An address time; the address signal alignment circuit is also used to calculate the difference between the first address time and the second address time as the configuration time of the address signal.
  • the processor is configured to use the configuration time of the chip select signal and the configuration time of the address signal as decoding instructions, and continue to use the configuration of the decoding instructions to be aligned with the fixed sampling frequency. The sampling results are decoded.
  • the switching clock frequency of the memory circuit block is calculated based on the sampling results of the logic analysis, and the switching clock frequency is aligned according to the switching clock frequency.
  • a plurality of the test instructions and a plurality of the sampling results enable the test instructions of the memory circuit block in a variable frequency environment to be aligned with the sampling results of the logical analysis, thereby realizing logical analysis of the memory circuit block in a variable frequency environment. Analyze and decode, thereby expanding the application scope of logical analysis.
  • Figure 1 is a flow chart of a logical analysis and decoding method in a specific embodiment of the present disclosure
  • Figure 2 is a structural block diagram of a logic analysis and decoding device in a specific embodiment of the present disclosure.
  • FIG. 1 is a flow chart of the logical analysis and decoding method in the specific implementation mode of this disclosure. As shown in Figure 1, the logical analysis and decoding method includes the following steps:
  • Step S11 obtain the sampling file of the memory circuit block, and generate the instruction sequence file of the memory circuit block.
  • the sampling file includes multiple sampling results, and each sampling result includes a sampling point and a sample corresponding to the sampling point.
  • pin status of the memory circuit block, and the instruction sequence file includes a plurality of test instructions applied to the memory circuit block.
  • the specific steps of obtaining the sampling file of the memory circuit block include:
  • a logic analyzer is used to obtain sampling files of memory circuit blocks at a fixed sampling frequency.
  • the memory circuit block described in this specific embodiment may be, but is not limited to, DRAM.
  • the sampling file of the memory circuit block is obtained through the logic analyzer.
  • the logic analyzer samples the memory circuit block in a sampling mode with a fixed sampling frequency to obtain the sampling file.
  • the sampling frequency of the logic analyzer is more than 4 times the sampling frequency to ensure that the pins of the memory circuit block can complete Switching between the first state and the second state, and both the first state and the second state can have two sampling point verification states.
  • the sampling frequency of the logic analyzer is 4 times the sampling frequency, the logic analyzer can acquire 4 sampling points in each sampling period.
  • the first state may be a low voltage state lower than a threshold voltage (eg, state 0), and the second state may be a high voltage state higher than the threshold voltage (eg, state 1).
  • the sampling depth of the logic analyzer can be set according to actual needs, and this is not limited in this specific implementation. The greater the sampling depth of the logic analyzer, the longer the sequence collected.
  • the sampling file may be a sampling file in CSV format.
  • the sampling file in CSV format is a plain text file.
  • the sampling file describes a plurality of sampling results, and each sampling result includes a plurality of sampling points and a plurality of pin states of the memory circuit block corresponding to the plurality of sampling points.
  • the sampling point is the time point of sampling.
  • the pin status is the collected status of the pin in the memory circuit block.
  • the pin state includes the first state and the second state.
  • Step S12 Align multiple test instructions and multiple sampling results.
  • the test instruction refers to a control instruction sent by the controller of the memory circuit block.
  • the control command includes one or a combination of two or more of a write command (Write), a read command (Read), a precharge command (Precharge), and an activation command (ACT).
  • Aligning multiple test instructions and multiple sampling results means changing the pin state of the sampling point in the sampling result and the clock of the memory circuit block from the first state to the edge alignment of the second state. For example, in a sampling period at 4 times the sampling frequency, the pin status collected at the second sampling point of the logic analyzer is the first state, and the pin status collected at the third sampling point is the second state. , it is considered that the pin status collected at the third sampling point is the result after alignment.
  • Step S13 Determine whether the memory circuit block triggers frequency conversion based on the aligned test instructions and the sampling results. If so, calculate the switching clock frequency of the memory circuit block based on the sampling results. .
  • the specific step of determining whether the memory circuit block triggers frequency conversion based on the aligned multiple test instructions and multiple sampling results further includes:
  • the first loop steps include:
  • the trigger threshold is 300 MHz.
  • a list including the preset number of elements may be declared, and the list is used to dynamically store the preset number of sampling results.
  • the elements in this specific implementation are variables.
  • the element is a storage space used to store the sampling results.
  • the plurality of sampling results in the sampling file are arranged in order of sampling time from first to last, and then the first loop step is performed multiple times.
  • the following description takes the preset number of 160 and the trigger threshold of 300 MHz as an example. Those skilled in the art may also select other preset numbers and other trigger thresholds according to actual needs.
  • the 160 elements in the list respectively store the sampling results from the 1st to the 160th position, and the calculation is based on the 160 sampling results stored in the list.
  • the first current clock frequency of the memory circuit block that is, the initial clock frequency of the memory circuit block
  • determine whether the calculated first current clock frequency is greater than 300 MHz. If not, perform all the steps for the second time. Describe the first cycle steps.
  • the 160 elements in the list respectively store the sampling results from the 2nd to the 161st position, and the calculation is based on the 160 sampling results stored in the list.
  • the first current clock frequency of the memory circuit block is determined, and whether the calculated first current clock frequency is greater than 300 MHz is determined. If not, the first loop step is performed for a third time.
  • the 160 elements in the list respectively store the sampling results from the 3rd to the 162nd bits, and the calculation is based on the 160 sampling results stored in the list.
  • the first current clock frequency of the memory circuit block is determined, and whether the calculated first current clock frequency is greater than 300 MHz is determined. If not, the first loop step is performed for the fourth time.
  • the memory circuit block triggers frequency conversion.
  • the sampling point of the memory circuit block that triggers the frequency conversion operation and the sampling result corresponding to the sampling point that triggers the frequency conversion operation can be learned in a timely and accurate manner. Whether to perform a frequency conversion decoding operation is determined by determining whether the memory circuit block triggers frequency conversion, so as to improve the flexibility of decoding the sampling file.
  • the pin state includes a first state and a second state; the memory circuit block is calculated according to the preset number of the sampling results.
  • the specific steps for the first current clock frequency include:
  • Each group of the first sub-sampling results includes a plurality of continuously distributed first states, and a plurality of continuously distributed first states.
  • the pin state of the memory circuit block includes a continuous second state (for example, state 1), and is adjacent to a continuous second state.
  • the first continuous state at one end (for example, state 0).
  • the reciprocal of the clock cycle of the memory circuit block is the clock frequency of the memory circuit block. Therefore, by dividing and calculating the preset number of sampling results in the list, multiple first sub-clock frequencies of the memory circuit block can be obtained, and multiple first sub-clock frequencies can be calculated.
  • the average frequency is used as the first current clock frequency.
  • the specific steps of calculating the switching clock frequency of the memory circuit block based on the plurality of sampling results include:
  • the second loop step includes:
  • the first initial position in the last first cycle step is used as the second initial position in the second cycle step, that is, the first current clock that triggers frequency conversion is used.
  • the first initial position corresponding to the frequency is used as the second initial position for the first time of the second cycle step.
  • the 160 elements in the list respectively store the sampling results from the nth bit to the 159+nth bit.
  • the second current clock frequency of the memory circuit block is calculated based on the sampling results.
  • the 160 elements in the list respectively store the sampling results from the n+1th bit to the 160+nth bit.
  • the sampling result is used to calculate the second current clock frequency of the memory circuit block, and the second current clock frequency calculated in the second cycle step of the second time is determined to be the same as the second current clock frequency calculated in the second cycle step of the first time. Whether the obtained second current clock frequency is the same, if not, perform the third second loop step.
  • the 160 elements in the list respectively store the sampling results from the n+2nd to the 161+nth bits.
  • the sampling result is used to calculate the second current clock frequency of the memory circuit block, and the second current clock frequency calculated in the third second loop step is determined to be the same as the second current clock frequency calculated in the second second loop step.
  • the obtained second current clock frequency is the same, if not, perform the fourth second loop step.
  • the second current clock frequency calculated in two adjacent second cycle steps is the same, it is confirmed that the clock frequency change of the memory circuit block has stabilized, and the second current clock frequency when stable is used.
  • the clock frequency serves as the switching clock frequency of the memory circuit block.
  • Step S14 Align multiple test instructions and multiple sampling results according to the switching clock frequency.
  • the test instructions include a chip select signal (i.e., CS signal) and an address signal (i.e., CA signal); and multiple test instructions and multiple sampling results are aligned according to the switching clock frequency. Steps include:
  • the address signal and the pin state in the sampling result are aligned according to the switching clock frequency.
  • the sampling file includes a plurality of record lines arranged in chronological order, each of the record lines records one of the sampling results; the chip select signal and the chip select signal are aligned according to the switching clock frequency.
  • the specific steps for sampling the pin status in the result include:
  • the difference between the first chip select time and the second chip select time is calculated as the configuration time of the chip select signal.
  • the sampling file is a sampling file in CSV format, which includes a plurality of record lines arranged in chronological order, and each record line records one of the sampling results.
  • finding the tube state after applying the chip select signal to the memory circuit block from the sampling file The record line whose pin state changes from the first state to the second state is used as the current line of chip selection.
  • Obtaining the time interval between the two record lines adjacent to the current line of the chip selection means obtaining the previous line adjacent to the current line of the chip selection and the previous line adjacent to the current line of the chip selection. The time interval between subsequent rows.
  • the specific steps of aligning the address signal and the pin state in the sampling result according to the switching clock frequency include:
  • the switching clock frequency select the recording row in which the pin state changes from the first state to the second state after applying the address signal to the memory circuit block as the current address row;
  • the difference between the first address time and the second address time is calculated as the configuration time of the address signal.
  • the chip select signal will be sent synchronously with the test instruction of the memory circuit block. If the chip select signal is detected, it is determined that the memory circuit block is accepting the test instruction.
  • the address signal is a specific instruction combination accepted by the memory circuit block synchronously with the chip select signal.
  • the chip select signal and the address signal are the main signals for logical analysis and decoding. By respectively aligning the chip select signal with the sampling result, and the address signal with the sampling result, the logic analysis and decoding can be further ensured. accuracy.
  • the configuration time of the chip select signal and the configuration time of the address signal are used as decoding instructions, and the configuration in which the decoding instructions are aligned with the fixed sampling frequency is used to continue decoding the sampling result.
  • FIG. 2 is a structural block diagram of the logic analysis and decoding device in the specific embodiment of this disclosure.
  • the logical analysis and decoding device provided in this specific embodiment can perform decoding using the logical analysis and decoding method as shown in Figure 1 .
  • the logic analysis and decoding device includes a processor 21 and also includes:
  • the memory 20 is connected to the processor 21 and is used to store the sampling file of the memory circuit block and generate the instruction sequence file of the memory circuit block.
  • the sampling file includes multiple sampling results, and each sampling result includes a sample. points, and the pin status of the memory circuit block corresponding to the sampling point, the instruction sequence file includes a plurality of test instructions applied to the memory circuit block;
  • the first alignment circuit 22 is connected to the processor 21 and is used to align a plurality of the test instructions and a plurality of the sampling results according to the initial clock frequency;
  • the judgment circuit 23 is connected to the processor 21 and is used to judge whether the memory circuit block triggers frequency conversion according to the plurality of aligned test instructions and the plurality of sampling results. If so, based on the plurality of sampling results Calculate the switching clock frequency of the memory circuit block;
  • the second alignment circuit 24 is connected to the processor 21 and is used to align a plurality of test instructions and a plurality of sampling results according to the switching clock frequency.
  • the logic analysis and decoding device further includes:
  • the access port 25 is connected to the memory 20 and is used to receive the sampling file of the memory circuit block acquired by the logic analyzer at a fixed sampling frequency.
  • the plurality of sampling results in the memory 20 are arranged in sequence according to the time order of sampling; the judgment circuit 23 includes a first loop circuit 231, and the first loop circuit 231 is used for rows at least once The following first loop steps, until the first current clock frequency of the memory circuit block is greater than the trigger threshold, include:
  • the pin state includes a first state and a second state
  • the first loop circuit 231 is also used to separate the preset number of sampling results arranged in time sequence into multiple groups of first sub-sampling results, each group of the first sub-sampling results including a number of continuously distributed The first state, and a plurality of continuously distributed second states adjacent to a plurality of continuously distributed first states; the first loop circuit 231 is also used to calculate each group of the first sub-sampling results respectively. frequency as the first sub-clock frequency; the first loop circuit 231 is also used to calculate an average of multiple first sub-clock frequencies as the first current clock frequency.
  • the trigger threshold is 300 MHz.
  • the judgment circuit 23 further includes a second loop circuit 232, the second loop circuit 232 is used to adjust the first initial clock frequency corresponding to the first current clock frequency greater than the trigger threshold.
  • the position is used as the second initial position, and the following second loop steps are performed at least once until the second current clock frequency calculated in at least two adjacent second loop steps is the same, and the same second current clock frequency is used.
  • the second cycle step includes:
  • the test instructions include a chip select signal and an address signal; the second alignment circuit 24 is also used to align the chip select signal with the tube in the sampling result according to the switching clock frequency. pin status, and align the address signal and the pin status in the sampling result according to the switching clock frequency.
  • the sampling file includes a plurality of record lines arranged in chronological order, and each of the record lines records one of the sampling results;
  • the second alignment circuit 24 includes a chip select signal alignment circuit 241.
  • the chip select signal alignment circuit 241 is used to select the pin state after applying the chip select signal to the memory circuit block according to the switching clock frequency.
  • the record line that changes from the first state to the second state is used as the current line of chip selection; the chip select signal alignment circuit 241 is also used to obtain the two adjacent lines adjacent to the current line of chip selection.
  • the time interval between the record lines is used as the first chip select time, and the state of the pin in the sampling result before the current line of the chip select is obtained from the first state to the second state.
  • the time interval between the record row and the current chip select row is used as the second chip select time; the chip select signal alignment circuit 241 is also used to calculate the first chip select time and the second chip select time. The difference between the chip select times is used as the configuration time of the chip select signal.
  • the second alignment circuit 24 further includes an address signal alignment circuit 242, which is configured to select the address signal after applying the address signal to the memory circuit block according to the switching clock frequency.
  • the record line whose pin state changes from the first state to the second state is used as the current line of address, and the time interval between the two record lines adjacent to the current line of address is obtained.
  • the address signal alignment circuit 242 is also used to calculate the difference between the first address time and the second address time, as the configuration time of the address signal.
  • the processor 21 is configured to use the configuration time of the chip select signal and the configuration time of the address signal as decoding instructions, and continue with the configuration of aligning the decoding instructions with the fixed sampling frequency. Decode the sampling results.
  • the logic analysis decoding method and device provided by some embodiments of this specific implementation mode, after confirming that the memory circuit block to be tested triggers frequency conversion, calculates the switching clock frequency of the memory circuit block based on the sampling results of the logic analysis, and calculates the switching clock frequency according to the switching clock Frequency alignment of multiple test instructions and multiple sampling results enables the test instructions of the memory circuit block in a variable frequency environment to be aligned with the sampling results of the logical analysis, thereby realizing the control of the memory circuit block in a variable frequency environment. Perform logical analysis and decoding to expand the application scope of logical analysis.

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Abstract

本公开提供的逻辑分析解码方法包括如下步骤：获取存储器电路块的采样文件，并生成存储器电路块的指令序列文件，采样文件包括多个采样结果，每个采样结果包括采样点、以及与采样点对应的存储器电路块的管脚状态，指令序列文件中包括多个施加至存储器电路块中的测试指令；对齐多个测试指令与多个采样结果；根据对齐后的多个测试指令与多个采样结果判断存储器电路块是否触发变频，若是，则根据多个采样结果计算存储器电路块的切换时钟频率；根据切换时钟频率对齐多个测试指令与多个采样结果。本公开实现了对处于变频环境下的存储器电路块进行逻辑分析解码。

Description

逻辑分析解码方法及装置
相关申请引用说明
本申请要求于2022年06月06日递交的中国专利申请号202210630574.1、申请名为“逻辑分析解码方法及装置”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体测试技术领域，尤其涉及一种逻辑分析解码方法及装置。
背景技术
随着半导体技术的飞速发展，以及各行业对电路的要求不断提升，对电路的性能进行测试，显得尤为重要。逻辑分析是对电路的行为模式进行分析的方法，是检验电路电学性能的一个重要测试手段。
对电路的逻辑分析主要采用逻辑分析仪进行，即通过逻辑分析仪对电路进行采样，结合对采样结果的解码来获知电路的行为模式。逻辑分析仪的解码几乎都是基于所述电路处于固定时钟频率下的采样结果的解码，传统的逻辑分析解码方法是通过将逻辑分析仪的采样频率与电路的固定时钟频率同步来保证解码的准确性。但是，在多种应用环境中，为了节省功耗，电路的变频操作越来越多，传统的逻辑分析解码方法无法应用于电路在变频应用环境下的行为。
因此，如何对处于变频环境下的电路进行逻辑分析解码，从而扩展逻辑分析的应用范围，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的逻辑分析解码方法及装置，用于解决无法对变频环境下的存储器电路块进行逻辑分析解码的问题，以扩展逻辑分析的应用领域。
根据一些实施例，本公开提供了一种逻辑分析解码方法，包括如下步骤：
获取存储器电路块的采样文件，并生成所述存储器电路块的指令序列文件，所述采样文件包括多个采样结果，每个所述采样结果包括采样点、以及与所述采样点对应的所述存储器电路块的管脚状态，所述指令序列文件中包括多个施加至所述存储器电路块中的测试指令；
对齐多个所述测试指令与多个所述采样结果；
根据对齐后的多个所述测试指令与多个所述采样结果判断所述存储器电路块是否触发变频，若是，则根据多个所述采样结果计算所述存储器电路块的切换时钟频率；
根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果。
在一些实施例中，获取存储器电路块的采样文件的具体步骤包括：
采用逻辑分析仪在固定采样频率下获取存储器电路块的采样文件。
在一些实施例中，根据对齐后的多个所述测试指令与多个所述采样结果判断所述存储器电路块是否触发变频的具体步骤还包括：
对多个所述采样结果按照采样的时间顺序依次排列，并进行至少一次如下第一循环步骤，直至所述存储器电路块的第一当前时钟频率大于触发阈值，所述第一循环步骤包括：
自第一初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
根据所述预设数量的所述采样结果计算所述存储器电路块的第一当前时钟频率；
判断所述第一当前频率是否大于触发阈值，若否，则以与所述第一初始位置相邻的下一位置的所述采样结果作为第一初始位置的采样结果进行下一次第一循环步骤。
在一些实施例中，所述管脚状态包括第一状态和第二状态；根据所述预设数量的所述采样结果计算所述存储器电路块的第一当前时钟频率的具体步骤包括：
分隔依时间顺序排列的所述预设数量的所述采样结果为多组第一子采样结果，每组所述第一子采样结果包括连续分布的若干所述第一状态、以及与连续分布的若干所述第一状态相邻的连续分布的若干所述第二状态；
分别计算每组所述第一子采样结果的频率，作为第一子时钟频率；
计算多个所述第一子时钟频率的平均值，作为所述第一当前时钟频率。
在一些实施例中，所述触发阈值为300MHz。
在一些实施例中，根据多个所述采样结果计算所述存储器电路块的切换时钟频率的具体步骤包括：
以与大于所述触发阈值的所述第一当前时钟频率对应的所述第一初始位置作为第二初始位置，进行至少一次如下第二循环步骤，直至至少相邻的两次所述第二循环步骤计算得到的第二当前时钟频率相同，并以相同的所述第二当前时钟频率作为所述存储器电路块的切换时钟频率；所述第二循环步骤包括：
自第二初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
根据所述预设数量的所述采样结果计算所述存储器电路块的第二当前时钟频率；
判断所述第二当前时钟频率是否与上一次所述第二循环步骤计算得到的所述第二当前时钟频率相同，若否，以与所述第二初始位置相邻的下一位置的所述采样结果作为第二初 始位置的采样结果进行下一次第二循环步骤。
在一些实施例中，所述测试指令包括片选信号和地址信号；根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果的具体步骤包括：
根据所述切换时钟频率对齐所述片选信号与所述采样结果中的所述管脚状态；
根据所述切换时钟频率对齐所述地址信号与所述采样结果中的所述管脚状态。
在一些实施例中，所述采样文件包括按时间顺序排布的多个记录行，每个所述记录行记录一个所述采样结果；根据所述切换时钟频率对齐所述片选信号与所述采样结果中的所述管脚状态的具体步骤包括：
根据所述切换时钟频率选取向所述存储器电路块施加所述片选信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为片选当前行；
获取与所述片选当前行相邻的前后两个所述记录行之间的时间间隔，作为第一片选时间；
获取所述片选当前行之前的所述采样结果中所述管脚状态由所述第一状态变为所述第二状态所在的所述记录行与所述片选当前行之间的时间间隔，作为第二片选时间；
计算所述第一片选时间与所述第二片选时间之间的差值，作为所述片选信号的配置时间。
在一些实施例中，根据所述切换时钟频率对齐所述地址信号与所述采样结果中的所述管脚状态的具体步骤包括：
根据所述切换时钟频率选取向所述存储器电路块施加所述地址信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为地址当前行；
获取与所述地址当前行相邻的前后两个所述记录行之间的时间间隔，作为第一地址时间；
计算所述第一地址时间与所述第二地址时间之间的差值，作为所述地址信号的配置时间。
在一些实施例中，根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果之后，还包括如下步骤：
将所述片选信号的配置时间与所述地址信号的配置时间作为解码指令，并采用所述解码指令与所述固定采样频率对齐的配置继续对所述采样结果进行解码。
根据另一些实施例，本公开还提供了一种逻辑分析解码装置，包括处理器，还包括：
存储器，连接所述处理器，用于存储存储器电路块的采样文件，并生成所述存储器电路块的指令序列文件，所述采样文件包括多个采样结果，每个所述采样结果包括采样点、以及与所述采样点对应的所述存储器电路块的管脚状态，所述指令序列文件中包括多个施加至所述存储器电路块中的测试指令；
第一对齐电路，连接所述处理器，用于根据所述初始时钟频率分别对齐多个所述测试指令与多个所述采样结果；
判断电路，连接所述处理器，用于根据对齐后的多个所述测试指令与多个所述采样结果判断所述存储器电路块是否触发变频，若是，则根据多个所述采样结果计算所述存储器电路块的切换时钟频率；
第二对齐电路，连接所述处理器，用于根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果。
在一些实施例中，还包括：
接入端口，连接所述存储器，用于接收逻辑分析仪在固定采样频率下获取存储器电路块的采样文件。
在一些实施例中，所述存储器中的多个所述采样结果按照采样的时间顺序依次排列；所述判断电路包括第一循环电路，所述第一循环电路用于行至少一次如下第一循环步骤，直至所述存储器电路块的第一当前时钟频率大于触发阈值，所述第一循环步骤包括：
自第一初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
根据所述预设数量的所述采样结果计算所述存储器电路块的第一当前时钟频率；
判断所述第一当前频率是否大于触发阈值，若否，则以与所述第一初始位置相邻的下一位置的所述采样结果作为第一初始位置的采样结果进行下一次第一循环步骤。
在一些实施例中，管脚状态包括第一状态和第二状态；
所述第一循环电路还用于分隔依时间顺序排列的所述预设数量的所述采样结果为多组第一子采样结果，每组所述第一子采样结果包括连续分布的若干所述第一状态、以及与连续分布的若干所述第一状态相邻的连续分布的若干所述第二状态；所述第一循环电路还用于分别计算每组所述第一子采样结果的频率，作为第一子时钟频率；所述第一循环电路还用于计算多个所述第一子时钟频率的平均值，作为所述第一当前时钟频率。
在一些实施例中，所述触发阈值为300MHz。
在一些实施例中，所述判断电路还包括第二循环电路，所述第二循环电路用于以与大 于所述触发阈值的所述第一当前时钟频率对应的所述第一初始位置作为第二初始位置，进行至少一次如下第二循环步骤，直至至少相邻的两次所述第二循环步骤计算得到的第二当前时钟频率相同，并以相同的所述第二当前时钟频率作为所述存储器电路块的切换时钟频率；所述第二循环步骤包括：
自第二初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
根据所述预设数量的所述采样结果计算所述存储器电路块的第二当前时钟频率；
判断所述第二当前时钟频率是否与上一次所述第二循环步骤计算得到的所述第二当前时钟频率相同，若否，以与所述第二初始位置相邻的下一位置的所述采样结果作为第二初始位置的采样结果进行下一次第二循环步骤。
在一些实施例中，所述测试指令包括片选信号和地址信号；所述第二对齐电路还用于根据所述切换时钟频率对齐所述片选信号与所述采样结果中的所述管脚状态，并根据所述切换时钟频率对齐所述地址信号与所述采样结果中的所述管脚状态。
在一些实施例中，所述采样文件包括按时间顺序排布的多个记录行，每个所述记录行记录一个所述采样结果；
所述第二对齐电路包括片选信号对齐电路，所述片选信号对齐电路用于根据所述切换时钟频率选取向所述存储器电路块施加所述片选信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为片选当前行；所述片选信号对齐电路还用于获取与所述片选当前行相邻的前后两个所述记录行之间的时间间隔，作为第一片选时间，并获取所述片选当前行之前的所述采样结果中所述管脚状态由所述第一状态变为所述第二状态所在的所述记录行与所述片选当前行之间的时间间隔，作为第二片选时间；所述片选信号对齐电路还用于计算所述第一片选时间与所述第二片选时间之间的差值，作为所述片选信号的配置时间。
在一些实施例中，所述第二对齐电路还包括地址信号对齐电路，所述地址信号对齐电路用于根据所述切换时钟频率选取向所述存储器电路块施加所述地址信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为地址当前行，获取与所述地址当前行相邻的前后两个所述记录行之间的时间间隔，作为第一地址时间；所述地址信号对齐电路还用于计算所述第一地址时间与所述第二地址时间之间的差值，作为所述地址信号的配置时间。
在一些实施例中，所述处理器用于将所述片选信号的配置时间与所述地址信号的配置 时间作为解码指令，并采用所述解码指令与所述固定采样频率对齐的配置继续对所述采样结果进行解码。
本公开一些实施例提供的逻辑分析解码方法及装置，在确认待测试的存储器电路块触发变频之后，则根据逻辑分析的采样结果计算存储器电路块的切换时钟频率，并根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果，从而能够将所述存储器电路块在变频环境下的测试指令与逻辑分析的采样结果对齐，实现了对处于变频环境下的存储器电路块进行逻辑分析解码，从而扩展逻辑分析的应用范围。
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附图1是本公开具体实施方式中逻辑分析解码方法的流程图；
附图2是本公开具体实施方式中逻辑分析解码装置的结构框图。
具体实施方式
下面结合附图对本公开提供的逻辑分析解码方法及装置的具体实施方式做详细说明。
本具体实施方式提供了一种逻辑分析解码方法，附图1是本公开具体实施方式中逻辑分析解码方法的流程图。如图1所示，所述逻辑分析解码方法，包括如下步骤：
步骤S11，获取存储器电路块的采样文件，并生成所述存储器电路块的指令序列文件，所述采样文件包括多个采样结果，每个所述采样结果包括采样点、以及与所述采样点对应的所述存储器电路块的管脚状态，所述指令序列文件中包括多个施加至所述存储器电路块中的测试指令。
在一些实施例中，获取存储器电路块的采样文件的具体步骤包括：
采用逻辑分析仪在固定采样频率下获取存储器电路块的采样文件。
本具体实施方式中所述的存储器电路块可以是但不限于DRAM。本具体实施方式通过所述逻辑分析仪获取所述存储器电路块的所述采样文件。举例来说，所述逻辑分析仪在固定采样频率的采样模式下对所述存储器电路块进行采样，获取所述采样文件。在采用所述逻辑分析仪以固定采样频率对所述存储器电路块进行采样的过程中，所述逻辑分析仪的采样频率为4倍采样频率以上，以确保所述存储器电路块的管脚能够完成第一状态与第二状态之间的切换，且所述第一状态和所述第二状态均能够有两个采样点校验状态。举例来说，所述逻辑分析仪的采样频率为4倍采样频率时，所述逻辑分析仪在每个采样周期可以获取4个采样点。其中，所述第一状态可以为低于阈值电压的低电压状态(例如为状态0)，所述第二状态可以为高于阈值电压的高电压状态(例如状态1)。所述逻辑分析仪的采样深度可 以根据实际需要进行设置，本具体实施方式对此不做限定。所述逻辑分析仪的采样深度越大，采集到的序列(sequence)越长。
在一实施例中，所述采样文件可以为CSV格式的采样文件。CSV格式的所述采样文件为纯文本文件。所述采样文件描述了多个所述采样结果，每个所述采样结果包括多个所述采样点、以及与多个所述采样点一一对应的所述存储器电路块的多个管脚状态。所述采样点为采样的时间点。所述管脚状态为采集到的所述存储器电路块中的管脚的状态。所述管脚状态包括所述第一状态和所述第二状态。
步骤S12，对齐多个所述测试指令与多个所述采样结果。
所述测试指令是指所述存储器电路块的控制器发送的控制指令。在一实施例中，所述控制指令包括写入指令(Write)、读取指令(Read)、预充电指令(Precharge)、激活指令(ACT)中的一种或者两种以上的组合。对齐多个所述测试指令与多个所述采样结果是指，将所述采样结果中所述采样点的所述管脚状态与所述存储器电路块的时钟由所述第一状态变为所述第二状态的沿对齐。举例来说，在4倍采样频率下的一个采样周期中，所述逻辑分析仪第二采样点采集到的管脚状态为第一状态，第三采样点采集到的管脚状态为第二状态，则认为第三采样点采集到的管脚状态为对齐之后的结果。
步骤S13，根据对齐后的多个所述测试指令与多个所述采样结果判断所述存储器电路块是否触发变频，若是，则根据多个所述采样结果计算所述存储器电路块的切换时钟频率。
在一些实施例中，根据对齐后的多个所述测试指令与多个所述采样结果判断所述存储器电路块是否触发变频的具体步骤还包括：
对多个所述采样结果按照采样的时间顺序依次排列，并进行至少一次如下第一循环步骤，直至所述存储器电路块的第一当前时钟频率大于触发阈值，所述第一循环步骤包括：
自第一初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
根据所述预设数量的所述采样结果计算所述存储器电路块的第一当前时钟频率；
判断所述第一当前频率是否大于触发阈值，若否，则以与所述第一初始位置相邻的下一位置的所述采样结果作为第一初始位置的采样结果进行下一次第一循环步骤。
在一些实施例中，所述触发阈值为300MHz。
举例来说，可以声明一个包括所述预设数量的元素的列表，所述列表用于动态存储所述预设数量的所述采样结果。本具体实施方式中的元素为变量。在一实施例中，所述元素为用于存储所述采样结果的存储空间。
对所述采样文件中的多个所述采样结果按照采样时间由先到后的顺序依次排列，之后进行多次所述第一循环步骤。以下以所述预设数量为160、所述触发阈值为300MHz为例进行说明，本领域技术人员也可以根据实际需要选择其他的预设数量和其他的触发阈值。在第一次的所述第一循环步骤中，所述列表中的160个元素分别存储第1位到第160位的所述采样结果，根据所述列表中存储的160个所述采样结果计算所述存储器电路块的第一当前时钟频率(即所述存储器电路块的初始时钟频率)，并判断计算得到的所述第一当前时钟频率是否大于300MHz，若否，则进行第二次的所述第一循环步骤。在第二次的所述第一循环步骤中，所述列表中的160个元素分别存储第2位到第161位的所述采样结果，根据所述列表中存储的160个所述采样结果计算所述存储器电路块的第一当前时钟频率，并判断计算得到的所述第一当前时钟频率是否大于300MHz，若否，则进行第三次的所述第一循环步骤。在第三次的所述第一循环步骤中，所述列表中的160个元素分别存储第3位到第162位的所述采样结果，根据所述列表中存储的160个所述采样结果计算所述存储器电路块的第一当前时钟频率，并判断计算得到的所述第一当前时钟频率是否大于300MHz，若否，则进行第四次的所述第一循环步骤。以此类推，直至所述第一当前时钟频率大于或者等于300MHz，此时，则认为所述存储器电路块触发变频。通过对所述存储器电路块的触发变频的变频点进行监控，从而可以及时、准确的获知所述存储器电路块触发变频操作的采样点、以及与触发变频操作的采样点对应的采样结果。通过判断所述存储器电路块是否触发变频来确定是否进行变频解码操作，以提高对所述采样文件解码的灵活性。
为了简化所述第一当前时钟频率的计算操作，在一些实施例中，所述管脚状态包括第一状态和第二状态；根据所述预设数量的所述采样结果计算所述存储器电路块的第一当前时钟频率的具体步骤包括：
分隔依时间顺序排列的所述预设数量的所述采样结果为多组第一子采样结果，每组所述第一子采样结果包括连续分布的若干所述第一状态、以及与连续分布的若干所述第一状态相邻的连续分布的若干所述第二状态；
分别计算每组所述第一子采样结果的频率，作为第一子时钟频率；
计算多个所述第一子时钟频率的平均值，作为所述第一当前时钟频率。
具体来说，在所述存储器电路块的一个时钟周期内，所述存储器电路块的管脚状态包括一段连续的第二状态(例如状态1)、以及与一段连续的所述第二状态相邻的一端连续的第一状态(例如状态0)。所述存储器电路块的所述时钟周期的倒数即为所述存储器电路块 的时钟频率。因此，对所述列表中的所述预设数量的所述采样结果进行划分和计算，可以得到所述存储器电路块的多个所述第一子时钟频率，计算多个所述第一子时钟频率的平均值，作为所述第一当前时钟频率。
在一些实施例中，根据多个所述采样结果计算所述存储器电路块的切换时钟频率的具体步骤包括：
以与大于所述触发阈值的所述第一当前时钟频率对应的所述第一初始位置作为第二初始位置，进行至少一次如下第二循环步骤，直至至少相邻的两次所述第二循环步骤计算得到的第二当前时钟频率相同，并以相同的所述第二当前时钟频率作为所述存储器电路块的切换时钟频率；所述第二循环步骤包括：
自第二初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
根据所述预设数量的所述采样结果计算所述存储器电路块的第二当前时钟频率；
判断所述第二当前时钟频率是否与上一次所述第二循环步骤计算得到的所述第二当前时钟频率相同，若否，以与所述第二初始位置相邻的下一位置的所述采样结果作为第二初始位置的采样结果进行下一次第二循环步骤。
具体来说，以最后一次所述第一循环步骤中的所述第一初始位置作为第一次所述第二循环步骤的所述第二初始位置，即以触发变频的所述第一当前时钟频率对应的所述第一初始位置作为第一次所述第二循环步骤的所述第二初始位置。举例来说，在第一次的所述第二循环步骤中，所述列表中的160个元素分别存储第n位到第159+n位的所述采样结果，根据所述列表中存储的160个所述采样结果计算所述存储器电路块的第二当前时钟频率。在第二次的所述第二循环步骤中，所述列表中的160个元素分别存储第n+1位到第160+n位的所述采样结果，根据所述列表中存储的160个所述采样结果计算所述存储器电路块的第二当前时钟频率，并判断第二次的所述第二循环步骤计算得到的所述第二当前时钟频率与第一次的所述第二循环步骤计算得到的所述第二当前时钟频率是否相同，若否，则进行第三次的所述第二循环步骤。在第三次的所述第二循环步骤中，所述列表中的160个元素分别存储第n+2位到第161+n位的所述采样结果，根据所述列表中存储的160个所述采样结果计算所述存储器电路块的第二当前时钟频率，并判断第三次的所述第二循环步骤计算得到的所述第二当前时钟频率与第二次的所述第二循环步骤计算得到的所述第二当前时钟频率是否相同，若否，则进行第四次的所述第二循环步骤。以此类推，直至相邻的两次所述第二循环步骤计算得到的第二当前时钟频率相同，则确认所述存储器电路块的时钟频率 变化已稳定，并以稳定时的所述第二当前时钟频率作为所述存储器电路块的切换时钟频率。
步骤S14，根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果。
具体来说，根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果之后，从而确定了例如所述逻辑分析仪采集到的采样结果与所述存储器电路块的时钟之间的对应关系，进而确保了逻辑分析解码的准确性。
在一些实施例中，所述测试指令包括片选信号(即CS信号)和地址信号(即CA信号)；根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果的具体步骤包括：
根据所述切换时钟频率对齐所述片选信号与所述采样结果中的所述管脚状态；
根据所述切换时钟频率对齐所述地址信号与所述采样结果中的所述管脚状态。
在一些实施例中，所述采样文件包括按时间顺序排布的多个记录行，每个所述记录行记录一个所述采样结果；根据所述切换时钟频率对齐所述片选信号与所述采样结果中的所述管脚状态的具体步骤包括：
根据所述切换时钟频率选取向所述存储器电路块施加所述片选信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为片选当前行；
获取与所述片选当前行相邻的前后两个所述记录行之间的时间间隔，作为第一片选时间；
获取所述片选当前行之前的所述采样结果中所述管脚状态由所述第一状态变为所述第二状态所在的所述记录行与所述片选当前行之间的时间间隔，作为第二片选时间；
计算所述第一片选时间与所述第二片选时间之间的差值，作为所述片选信号的配置时间。
举例来说，所述采样文件为CSV格式的采样文件，其包括按时间顺序排布的多个记录行，每个所述记录行记录一个所述采样结果。在根据所述切换时钟频率对齐所述片选信号与所述采样结果中的所述管脚状态时，从所述采样文件中寻找向所述存储器电路块施加所述片选信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为片选当前行。获取与所述片选当前行相邻的前后两个所述记录行之间的时间间隔是指，获取与所述片选当前行相邻的前一行和与所述片选当前行相邻的后一行之间的时间间隔。
在一些实施例中，根据所述切换时钟频率对齐所述地址信号与所述采样结果中的所述管脚状态的具体步骤包括：
根据所述切换时钟频率选取向所述存储器电路块施加所述地址信号之后所述管脚状态 由所述第一状态变为所述第二状态的所述记录行，作为地址当前行；
获取与所述地址当前行相邻的前后两个所述记录行之间的时间间隔，作为第一地址时间；
计算所述第一地址时间与所述第二地址时间之间的差值，作为所述地址信号的配置时间。
具体来说，所述片选信号一定会伴随所述存储器电路块的测试指令同步发出，若检测到所述片选信号，则确定所述存储器电路块正在接受所述测试指令。所述地址信号是和所述片选信号同步被所述存储器电路块接受的具体指令组合。所述片选信号和所述地址信号是进行逻辑分析解码的主要信号，通过分别对齐所述片选信号与所述采样结果、以及所述地址信号与所述采样结果，能够进一步确保逻辑分析解码的精准度。
在一些实施例中，根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果之后，还包括如下步骤：
将所述片选信号的配置时间与所述地址信号的配置时间作为解码指令，并采用所述解码指令与所述固定采样频率对齐的配置继续对所述采样结果进行解码。
本具体实施方式还提供了一种逻辑分析解码装置，附图2是本公开具体实施方式中逻辑分析解码装置的结构框图。本具体实施方式提供的逻辑分析解码装置可以采用如图1所示的逻辑分析解码方法进行解码。如图2所示，所述逻辑分析解码装置，包括处理器21，还包括：
存储器20，连接所述处理器21，用于存储存储器电路块的采样文件，并生成所述存储器电路块的指令序列文件，所述采样文件包括多个采样结果，每个所述采样结果包括采样点、以及与所述采样点对应的所述存储器电路块的管脚状态，所述指令序列文件中包括多个施加至所述存储器电路块中的测试指令；
第一对齐电路22，连接所述处理器21，用于根据所述初始时钟频率分别对齐多个所述测试指令与多个所述采样结果；
判断电路23，连接所述处理器21，用于根据对齐后的多个所述测试指令与多个所述采样结果判断所述存储器电路块是否触发变频，若是，则根据多个所述采样结果计算所述存储器电路块的切换时钟频率；
第二对齐电路24，连接所述处理器21，用于根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果。
在一些实施例中，所述逻辑分析解码装置还包括：
接入端口25，连接所述存储器20，用于接收逻辑分析仪在固定采样频率下获取存储器电路块的采样文件。
在一些实施例中，所述存储器20中的多个所述采样结果按照采样的时间顺序依次排列；所述判断电路23包括第一循环电路231，所述第一循环电路231用于行至少一次如下第一循环步骤，直至所述存储器电路块的第一当前时钟频率大于触发阈值，所述第一循环步骤包括：
自第一初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
根据所述预设数量的所述采样结果计算所述存储器电路块的第一当前时钟频率；
判断所述第一当前频率是否大于触发阈值，若否，则以与所述第一初始位置相邻的下一位置的所述采样结果作为第一初始位置的采样结果进行下一次第一循环步骤。
在一些实施例中，管脚状态包括第一状态和第二状态；
所述第一循环电路231还用于分隔依时间顺序排列的所述预设数量的所述采样结果为多组第一子采样结果，每组所述第一子采样结果包括连续分布的若干所述第一状态、以及与连续分布的若干所述第一状态相邻的连续分布的若干所述第二状态；所述第一循环电路231还用于分别计算每组所述第一子采样结果的频率，作为第一子时钟频率；所述第一循环电路231还用于计算多个所述第一子时钟频率的平均值，作为所述第一当前时钟频率。
在一些实施例中，所述触发阈值为300MHz。
在一些实施例中，所述判断电路23还包括第二循环电路232，所述第二循环电路232用于以与大于所述触发阈值的所述第一当前时钟频率对应的所述第一初始位置作为第二初始位置，进行至少一次如下第二循环步骤，直至至少相邻的两次所述第二循环步骤计算得到的第二当前时钟频率相同，并以相同的所述第二当前时钟频率作为所述存储器电路块的切换时钟频率；所述第二循环步骤包括：
自第二初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
根据所述预设数量的所述采样结果计算所述存储器电路块的第二当前时钟频率；
判断所述第二当前时钟频率是否与上一次所述第二循环步骤计算得到的所述第二当前时钟频率相同，若否，以与所述第二初始位置相邻的下一位置的所述采样结果作为第二初始位置的采样结果进行下一次第二循环步骤。
在一些实施例中，所述测试指令包括片选信号和地址信号；所述第二对齐电路24还用 于根据所述切换时钟频率对齐所述片选信号与所述采样结果中的所述管脚状态，并根据所述切换时钟频率对齐所述地址信号与所述采样结果中的所述管脚状态。
在一些实施例中，所述采样文件包括按时间顺序排布的多个记录行，每个所述记录行记录一个所述采样结果；
所述第二对齐电路24包括片选信号对齐电路241，所述片选信号对齐电路241用于根据所述切换时钟频率选取向所述存储器电路块施加所述片选信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为片选当前行；所述片选信号对齐电路241还用于获取与所述片选当前行相邻的前后两个所述记录行之间的时间间隔，作为第一片选时间，并获取所述片选当前行之前的所述采样结果中所述管脚状态由所述第一状态变为所述第二状态所在的所述记录行与所述片选当前行之间的时间间隔，作为第二片选时间；所述片选信号对齐电路241还用于计算所述第一片选时间与所述第二片选时间之间的差值，作为所述片选信号的配置时间。
在一些实施例中，所述第二对齐电路24还包括地址信号对齐电路242，所述地址信号对齐电路242用于根据所述切换时钟频率选取向所述存储器电路块施加所述地址信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为地址当前行，获取与所述地址当前行相邻的前后两个所述记录行之间的时间间隔，作为第一地址时间；所述地址信号对齐电路242还用于计算所述第一地址时间与所述第二地址时间之间的差值，作为所述地址信号的配置时间。
在一些实施例中，所述处理器21用于将所述片选信号的配置时间与所述地址信号的配置时间作为解码指令，并采用所述解码指令与所述固定采样频率对齐的配置继续对所述采样结果进行解码。
本具体实施方式一些实施例提供的逻辑分析解码方法及装置，在确认待测试的存储器电路块触发变频之后，则根据逻辑分析的采样结果计算存储器电路块的切换时钟频率，并根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果，从而能够将所述存储器电路块在变频环境下的测试指令与逻辑分析的采样结果对齐，实现了对处于变频环境下的存储器电路块进行逻辑分析解码，从而扩展逻辑分析的应用范围。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种逻辑分析解码方法，包括如下步骤：
    获取存储器电路块的采样文件，并生成所述存储器电路块的指令序列文件，所述采样文件包括多个采样结果，每个所述采样结果包括采样点、以及与所述采样点对应的所述存储器电路块的管脚状态，所述指令序列文件中包括多个施加至所述存储器电路块中的测试指令；
    对齐多个所述测试指令与多个所述采样结果；
    根据对齐后的多个所述测试指令与多个所述采样结果判断所述存储器电路块是否触发变频，若是，则根据多个所述采样结果计算所述存储器电路块的切换时钟频率；
    根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果。
  2. 根据权利要求1所述的逻辑分析解码方法，其中，获取存储器电路块的采样文件的具体步骤包括：
    采用逻辑分析仪在固定采样频率下获取存储器电路块的采样文件。
  3. 根据权利要求2所述的逻辑分析解码方法，其中，根据对齐后的多个所述测试指令与多个所述采样结果判断所述存储器电路块是否触发变频的具体步骤还包括：
    对多个所述采样结果按照采样的时间顺序依次排列，并进行至少一次如下第一循环步骤，直至所述存储器电路块的第一当前时钟频率大于触发阈值，所述第一循环步骤包括：
    自第一初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
    根据所述预设数量的所述采样结果计算所述存储器电路块的第一当前时钟频率；
    判断所述第一当前频率是否大于触发阈值，若否，则以与所述第一初始位置相邻的下一位置的所述采样结果作为第一初始位置的采样结果进行下一次第一循环步骤。
  4. 根据权利要求3所述的逻辑分析解码方法，其中，所述管脚状态包括第一状态和第二状态；根据所述预设数量的所述采样结果计算所述存储器电路块的第一当前时钟频率的具体步骤包括：
    分隔依时间顺序排列的所述预设数量的所述采样结果为多组第一子采样结果，每组所述第一子采样结果包括连续分布的若干所述第一状态、以及与连续分布的若干所述第一状态相邻的连续分布的若干所述第二状态；
    分别计算每组所述第一子采样结果的频率，作为第一子时钟频率；
    计算多个所述第一子时钟频率的平均值，作为所述第一当前时钟频率。
  5. 根据权利要求3所述的逻辑分析解码方法，其中，所述触发阈值为300MHz。
  6. 根据权利要求3所述的逻辑分析解码方法，其中，根据多个所述采样结果计算所述存储器电路块的切换时钟频率的具体步骤包括：
    以与大于所述触发阈值的所述第一当前时钟频率对应的所述第一初始位置作为第二初始位置，进行至少一次如下第二循环步骤，直至至少相邻的两次所述第二循环步骤计算得到的第二当前时钟频率相同，并以相同的所述第二当前时钟频率作为所述存储器电路块的切换时钟频率；所述第二循环步骤包括：
    自第二初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
    根据所述预设数量的所述采样结果计算所述存储器电路块的第二当前时钟频率；
    判断所述第二当前时钟频率是否与上一次所述第二循环步骤计算得到的所述第二当前时钟频率相同，若否，以与所述第二初始位置相邻的下一位置的所述采样结果作为第二初始位置的采样结果进行下一次第二循环步骤。
  7. 根据权利要求3所述的逻辑分析解码方法，其中，所述测试指令包括片选信号和地址信号；根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果的具体步骤包括：
    根据所述切换时钟频率对齐所述片选信号与所述采样结果中的所述管脚状态；
    根据所述切换时钟频率对齐所述地址信号与所述采样结果中的所述管脚状态。
  8. 根据权利要求7所述的逻辑分析解码方法，其中，所述采样文件包括按时间顺序排布的多个记录行，每个所述记录行记录一个所述采样结果；根据所述切换时钟频率对齐所述片选信号与所述采样结果中的所述管脚状态的具体步骤包括：
    根据所述切换时钟频率选取向所述存储器电路块施加所述片选信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为片选当前行；
    获取与所述片选当前行相邻的前后两个所述记录行之间的时间间隔，作为第一片选时间；
    获取所述片选当前行之前的所述采样结果中所述管脚状态由所述第一状态变为所述第二状态所在的所述记录行与所述片选当前行之间的时间间隔，作为第二片选时间；
    计算所述第一片选时间与所述第二片选时间之间的差值，作为所述片选信号的配置时 间。
  9. 根据权利要求8所述的逻辑分析解码方法，其中，根据所述切换时钟频率对齐所述地址信号与所述采样结果中的所述管脚状态的具体步骤包括：
    根据所述切换时钟频率选取向所述存储器电路块施加所述地址信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为地址当前行；
    获取与所述地址当前行相邻的前后两个所述记录行之间的时间间隔，作为第一地址时间；
    计算所述第一地址时间与所述第二地址时间之间的差值，作为所述地址信号的配置时间。
  10. 根据权利要求9所述的逻辑分析解码方法，其中，根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果之后，还包括如下步骤：
    将所述片选信号的配置时间与所述地址信号的配置时间作为解码指令，并采用所述解码指令与所述固定采样频率对齐的配置继续对所述采样结果进行解码。
  11. 一种逻辑分析解码装置，包括处理器，还包括：
    存储器，连接所述处理器，用于存储存储器电路块的采样文件，并生成所述存储器电路块的指令序列文件，所述采样文件包括多个采样结果，每个所述采样结果包括采样点、以及与所述采样点对应的所述存储器电路块的管脚状态，所述指令序列文件中包括多个施加至所述存储器电路块中的测试指令；
    第一对齐电路，连接所述处理器，用于根据所述初始时钟频率分别对齐多个所述测试指令与多个所述采样结果；
    判断电路，连接所述处理器，用于根据对齐后的多个所述测试指令与多个所述采样结果判断所述存储器电路块是否触发变频，若是，则根据多个所述采样结果计算所述存储器电路块的切换时钟频率；
    第二对齐电路，连接所述处理器，用于根据所述切换时钟频率对齐多个所述测试指令与多个所述采样结果。
  12. 根据权利要求11所述的逻辑分析解码装置，还包括：
    接入端口，连接所述存储器，用于接收逻辑分析仪在固定采样频率下获取存储器电路块的采样文件。
  13. 根据权利要求12所述的逻辑分析解码装置，其中，所述存储器中的多个所述采样结果按照采样的时间顺序依次排列；所述判断电路包括第一循环电路，所述第一循环电路用于行至少一次如下第一循环步骤，直至所述存储器电路块的第一当前时钟频率大于触发阈值，所述第一循环步骤包括：
    自第一初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
    根据所述预设数量的所述采样结果计算所述存储器电路块的第一当前时钟频率；
    判断所述第一当前频率是否大于触发阈值，若否，则以与所述第一初始位置相邻的下一位置的所述采样结果作为第一初始位置的采样结果进行下一次第一循环步骤。
  14. 根据权利要求13所述的逻辑分析解码装置，其中，管脚状态包括第一状态和第二状态；
    所述第一循环电路还用于分隔依时间顺序排列的所述预设数量的所述采样结果为多组第一子采样结果，每组所述第一子采样结果包括连续分布的若干所述第一状态、以及与连续分布的若干所述第一状态相邻的连续分布的若干所述第二状态；所述第一循环电路还用于分别计算每组所述第一子采样结果的频率，作为第一子时钟频率；所述第一循环电路还用于计算多个所述第一子时钟频率的平均值，作为所述第一当前时钟频率。
  15. 根据权利要求13所述的逻辑分析解码装置，其中，所述触发阈值为300MHz。
  16. 根据权利要求13所述的逻辑分析解码装置，其中，所述判断电路还包括第二循环电路，所述第二循环电路用于以与大于所述触发阈值的所述第一当前时钟频率对应的所述第一初始位置作为第二初始位置，进行至少一次如下第二循环步骤，直至至少相邻的两次所述第二循环步骤计算得到的第二当前时钟频率相同，并以相同的所述第二当前时钟频率作为所述存储器电路块的切换时钟频率；所述第二循环步骤包括：
    自第二初始位置的所述采样结果开始、依序提取预设数量的所述采样结果；
    根据所述预设数量的所述采样结果计算所述存储器电路块的第二当前时钟频率；
    判断所述第二当前时钟频率是否与上一次所述第二循环步骤计算得到的所述第二当前时钟频率相同，若否，以与所述第二初始位置相邻的下一位置的所述采样结果作为第二初始位置的采样结果进行下一次第二循环步骤。
  17. 根据权利要求13所述的逻辑分析解码装置，其中，所述测试指令包括片选信号和地址信号；所述第二对齐电路还用于根据所述切换时钟频率对齐所述片选信号与所述采样结果中的所述管脚状态，并根据所述切换时钟频率对齐所述地址信号与所述采样结果中的 所述管脚状态。
  18. 根据权利要求17所述的逻辑分析解码装置，其中，所述采样文件包括按时间顺序排布的多个记录行，每个所述记录行记录一个所述采样结果；
    所述第二对齐电路包括片选信号对齐电路，所述片选信号对齐电路用于根据所述切换时钟频率选取向所述存储器电路块施加所述片选信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为片选当前行；所述片选信号对齐电路还用于获取与所述片选当前行相邻的前后两个所述记录行之间的时间间隔，作为第一片选时间，并获取所述片选当前行之前的所述采样结果中所述管脚状态由所述第一状态变为所述第二状态所在的所述记录行与所述片选当前行之间的时间间隔，作为第二片选时间；所述片选信号对齐电路还用于计算所述第一片选时间与所述第二片选时间之间的差值，作为所述片选信号的配置时间。
  19. 根据权利要求18所述的逻辑分析解码装置，其中，所述第二对齐电路还包括地址信号对齐电路，所述地址信号对齐电路用于根据所述切换时钟频率选取向所述存储器电路块施加所述地址信号之后所述管脚状态由所述第一状态变为所述第二状态的所述记录行，作为地址当前行，获取与所述地址当前行相邻的前后两个所述记录行之间的时间间隔，作为第一地址时间；所述地址信号对齐电路还用于计算所述第一地址时间与所述第二地址时间之间的差值，作为所述地址信号的配置时间。
  20. 根据权利要求19所述的逻辑分析解码装置，其中，所述处理器用于将所述片选信号的配置时间与所述地址信号的配置时间作为解码指令，并采用所述解码指令与所述固定采样频率对齐的配置继续对所述采样结果进行解码。
PCT/CN2022/099838 2022-06-06 2022-06-20 逻辑分析解码方法及装置 WO2023236245A1 (zh)

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