WO2023231177A1 - 接收电路以及存储器 - Google Patents

接收电路以及存储器 Download PDF

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Publication number
WO2023231177A1
WO2023231177A1 PCT/CN2022/111185 CN2022111185W WO2023231177A1 WO 2023231177 A1 WO2023231177 A1 WO 2023231177A1 CN 2022111185 W CN2022111185 W CN 2022111185W WO 2023231177 A1 WO2023231177 A1 WO 2023231177A1
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WIPO (PCT)
Prior art keywords
signal
node
mode
receiving circuit
pmos transistor
Prior art date
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PCT/CN2022/111185
Other languages
English (en)
French (fr)
Inventor
林峰
Original Assignee
长鑫存储技术有限公司
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Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to KR1020237013120A priority Critical patent/KR20230168173A/ko
Priority to EP22830120.6A priority patent/EP4307302A4/en
Priority to US18/150,921 priority patent/US20230395106A1/en
Publication of WO2023231177A1 publication Critical patent/WO2023231177A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Definitions

  • the present disclosure relates to, but is not limited to, a receiving circuit and a memory.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then passes through the bit line. Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • DRAM can include double-rate dynamic random access memory (Double Data Rate, DDR), GDDR (Graphics Double Data Rate) dynamic random access memory, and low-power double-rate dynamic random access memory (Low Power Double Data Rate, LPDDR).
  • DDR double-rate dynamic random access memory
  • GDDR Graphics Double Data Rate
  • LPDDR Low Power Double Data Rate
  • the present disclosure provides a receiving circuit and a memory.
  • a first aspect of the present disclosure provides a receiving circuit, including: an input buffer configured to receive a first input signal and a second input signal and compare the first input signal and the second input signal to output A first output signal and a second output signal, wherein in differential mode the first input signal and the second input signal are respectively a first signal and a second signal, and in single-ended mode the first input signal is one of the first signal and the second signal, the second input signal is a reference voltage signal, the first signal and the second signal are complementary; the conversion module is configured to receive the The first output signal and the second output signal are amplified and the voltage difference between the first output signal and the second output signal is amplified to output a first internal signal and a second internal signal.
  • the receiving circuit further includes: a selection module, which receives the original first signal, the original second signal and the original reference voltage signal, and is configured to provide the first input to the input buffer in response to the mode selection signal. signal and the second input signal, wherein the mode selection signal is used to characterize the single-ended mode or the differential mode, the first signal corresponds to the original first signal, and the second signal corresponds to The original second signal corresponds to the original reference voltage signal and the reference voltage signal corresponds to the original second signal.
  • a selection module which receives the original first signal, the original second signal and the original reference voltage signal, and is configured to provide the first input to the input buffer in response to the mode selection signal.
  • the mode selection signal is used to characterize the single-ended mode or the differential mode
  • the first signal corresponds to the original first signal
  • the second signal corresponds to
  • the original second signal corresponds to the original reference voltage signal and the reference voltage signal corresponds to the original second signal.
  • the selection module includes: a first selection unit and a second selection unit, one of the first selection unit and the second selection unit receives the original first signal and the original reference voltage signal, The other receives the original second signal and the original reference voltage signal; in the single-ended mode, one of the first selection unit and the second selection unit responds to the mode selection signal Output the first signal or the second signal, and the other outputs the reference voltage signal in response to the mode selection signal; in the differential mode, the first selection unit and the second selection unit One of them outputs the first signal in response to the mode selection signal, and the other outputs the second signal in response to the mode selection signal.
  • the input buffer includes: a current control module configured to provide current to the first node in response to a bias voltage signal; an input module and a load module connected to the input module, the input module and the The first node is connected, and the input module is connected to the load module via a second node and a third node; wherein the input module receives the first input signal and the second input signal, and the second node The first output signal is output, and the third node outputs the second output signal.
  • a current control module configured to provide current to the first node in response to a bias voltage signal
  • an input module and a load module connected to the input module, the input module and the The first node is connected, and the input module is connected to the load module via a second node and a third node; wherein the input module receives the first input signal and the second input signal, and the second node The first output signal is output, and the third node outputs the second output signal.
  • the current control mode is configured to adjust the current provided to the first node in response to the bias voltage signal, so that the current provided to the first node in the single-ended mode is less than The current provided to the first node in the differential mode.
  • the current control module includes: a first control unit connected to the first node and configured to conduct in response to the bias voltage signal to provide a first current to the first node; a second A control unit, connected to the first node, is configured to conduct in response to the control signal and the bias voltage signal to provide a second current to the first node; wherein, in the single-ended mode, The first control unit is turned on and the second control unit is not turned on. In the differential mode, the first control unit and the second control unit are both turned on.
  • the first control unit includes: a first PMOS transistor, a gate of the first PMOS transistor receives an enable signal, and a source of the first PMOS transistor is connected to the power supply voltage; a second PMOS transistor and a third PMOS transistor. tube, the source of the second PMOS tube and the source of the third PMOS tube are both connected to the drain of the first PMOS tube, and the drain of the second PMOS tube and the third PMOS tube The drains of both are connected to the first node, and the gates of the second PMOS transistor and the gates of the third PMOS transistor receive the bias voltage signal.
  • the second control unit includes: a fourth PMOS tube, a gate of the fourth PMOS tube receives the control signal, and a source of the fourth PMOS tube is connected to the power supply voltage; a fifth PMOS tube and a sixth PMOS tube.
  • PMOS tube, the source of the fifth PMOS tube and the source of the sixth PMOS tube are both connected to the drain of the fourth PMOS tube, and the drain of the fifth PMOS tube and the sixth PMOS
  • the drains of the tubes are both connected to the first node, and the gates of the fifth PMOS tube and the sixth PMOS tube both receive the bias voltage signal.
  • the input module includes: a seventh PMOS transistor, a gate of the seventh PMOS transistor receives the first input signal, a source of the seventh PMOS transistor is connected to the first node, and the seventh PMOS transistor has a gate that receives the first input signal.
  • the drain of the PMOS tube is connected to the second node; an eighth PMOS tube, the gate of the eighth PMOS tube receives the second input signal, and the source of the eighth PMOS tube is connected to the first node, The drain of the eighth PMOS transistor is connected to the third node.
  • the load module includes: a first load unit, connected between the second node and the ground terminal, configured such that in the single-ended mode, the equivalent resistance value of the first load unit is greater than The equivalent resistance value of the first load unit in the differential mode; the second load unit, connected between the third node and the ground terminal, is configured such that the second load unit in the single-ended mode The equivalent resistance value of the load unit is greater than the equivalent resistance value of the second load unit in the differential mode.
  • the first load unit includes: a first resistor, connected between the second node and the fourth node; a first adjustable load, connected between the fourth node and the ground, being It is configured to adjust the equivalent resistance value of the first adjustable load in response to the adjustment signal, and the equivalent resistance value of the first adjustable load in the single-ended mode is greater than the first adjustable load in the differential mode.
  • the equivalent resistance value of the adjustable load; the second load unit includes: a second resistor connected between the third node and the fifth node; a second adjustable load connected between the fifth node and the fifth node. between the ground terminals, is configured to adjust the equivalent resistance value of the second adjustable load in response to the adjustment signal, and the equivalent resistance value of the second adjustable load in the single-ended mode is greater than the equivalent resistance value of the second adjustable load in the differential mode.
  • the first adjustable load includes: a third resistor, connected between the fourth node and the ground terminal; a first MOS tube, the first end of the first MOS tube is connected to the fourth node, The second end of the first MOS tube is connected to the ground end, and the control end of the first MOS tube receives the adjustment signal.
  • the first MOS tube responds to the The adjustment signal is turned off, and in the differential mode, the first MOS transistor is turned on in response to the adjustment signal.
  • the second adjustable load includes: a fourth resistor, connected between the fifth node and the ground terminal; a second MOS tube, the first end of the second MOS tube is connected to the fifth node, the second end of the second MOS tube is connected to the ground end, and the control end of the second MOS tube receives the adjustment signal, wherein in the single-ended mode, the second MOS tube responds When the adjustment signal is cut off, in the differential mode, the second MOS transistor is turned on in response to the adjustment signal.
  • the conversion module includes: an amplification unit configured to amplify the voltage difference between the first output signal and the second output signal; a conversion unit configured to amplify the voltage difference after amplification by the amplification unit.
  • the first output signal and the second output signal perform level logic conversion, and the first internal signal and the second internal signal are output.
  • the amplification unit is further configured to adjust the first operating current of the amplification unit in response to the first bias signal, so that the first operating current in the single-ended mode is smaller than the differential mode. the first operating current.
  • the conversion unit is further configured to adjust the second operating current of the conversion unit in response to a second bias signal, so that the second operating current in the single-ended mode is smaller than the differential mode. the second operating current.
  • a second aspect of the present disclosure provides a memory including the receiving circuit as described in the first aspect.
  • the input buffer can use both the first signal and the second signal to operate in the differential mode, and can also use the reference voltage signal and the first signal and the second signal.
  • One can be used in single-ended mode that is, the same input buffer can be used in differential mode or single-ended mode, which is beneficial to reducing the complexity of the receiving circuit and reducing the layout area of the receiving circuit.
  • the input buffer only receives one of the first signal and the second signal, and the other received signal is a reference voltage signal, which can reduce the operating current in the receiving circuit, thus helping to reduce the power consumption of the receiving circuit. power consumption.
  • Figure 1 is a functional block diagram of a receiving circuit provided by an embodiment of the present disclosure
  • Figure 2 is a functional block diagram of the receiving circuit
  • Figures 3 to 6 are four other functional block diagrams of a receiving circuit provided by an embodiment of the present disclosure.
  • FIGS 7 and 8 are schematic diagrams of two circuit structures of the input buffer in the receiving circuit provided by an embodiment of the present disclosure
  • 9 to 11 are schematic diagrams of three circuit structures of the load module in the receiving circuit provided by an embodiment of the present disclosure.
  • the receiving circuit will work in differential mode or single-ended mode according to actual needs. However, the receiving circuit will create separate clock paths for differential mode and single-ended mode. That is, the clock signal received by the receiving circuit in differential mode is different from the clock signal received by the receiving circuit in differential mode. In differential mode, the clock signal received by the receiving circuit uses different clock paths.
  • FIG 2 is a functional block diagram of a receiving circuit.
  • the receiving circuit includes two input buffers, a differential input buffer 11, a single-ended input buffer 12, and a conversion module 13.
  • the differential input buffer 11 When the receiving circuit works in the differential mode, the differential input buffer 11 is in the working state. At this time, the single-ended input buffer 12 is in the non-working state.
  • the differential input buffer 11 receives the first input signal Dqs_t and the first input signal Dqs_t through the first clock path.
  • the second input signal Dqs_c is output to the conversion module 13, and the first internal signal Dqst and the second internal signal Dqsc are output through the conversion module 13; when the receiving circuit operates in the single-ended mode, the single-ended input buffer 12 is in the working state, At this time, the differential input buffer 11 is in a non-working state, and the single-ended input buffer 12 receives one of the first input signal Dqs_t or the second input signal Dqs_c through the second clock path, and receives the reference voltage signal vref, and outputs it to The conversion module 13 outputs the first internal signal Dqst and the second internal signal Dqsc through the conversion module 13 .
  • the differential input buffer 11 uses the first clock path when receiving the first input signal Dqs_t and the second input signal Dqs_c, and the single-ended input buffer 12 receives one of the first input signal Dqs_t or the second input signal Dqs_c.
  • the first clock path is different from the second clock path.
  • the receiving circuit switches between differential mode and single-ended mode, there will be interference between the first clock path and the second clock path.
  • causing the first input signal Dqs_t and/or the second input signal Dqs_c received by the input buffer to generate glitches, reducing the accuracy of the first internal signal Dqst and the second internal signal Dqsc output by the conversion module 13 .
  • designing two input buffers in the receiving circuit is not conducive to simplifying the layout of the receiving circuit, increases the complexity of the receiving circuit, and is not conducive to saving the overall power consumption of the receiving circuit.
  • Embodiments of the present disclosure provide a receiving circuit and a memory.
  • the input buffer can use both the first signal and the second signal to operate in a differential mode, or can also use the reference voltage signal and the first signal and the second signal.
  • One of the signals can work in single-ended mode, that is, the same input buffer can be used in differential mode or single-ended mode, which is beneficial to reducing the complexity of the receiving circuit and reducing the layout of the receiving circuit. area.
  • the input buffer only receives one of the first signal and the second signal, and the other received signal is a reference voltage signal, which can reduce the operating current in the receiving circuit, thus helping to reduce the power consumption of the receiving circuit. power consumption.
  • FIG. 1 An embodiment of the present disclosure provides a receiving circuit.
  • the receiving circuit provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • Figures 1, 3 to 6 are five functional block diagrams of a receiving circuit provided by an embodiment of the present disclosure;
  • Figures 7 and 8 are two circuit structural schematic diagrams of an input buffer in a receiving circuit provided by an embodiment of the present disclosure;
  • 9 to 11 are schematic diagrams of three circuit structures of the load module in the receiving circuit provided by an embodiment of the present disclosure.
  • the receiving circuit includes: an input buffer 101 configured to receive a first input signal input1 and a second input signal input2, compare the first input signal input1 and the second input signal input2, and output a first The output signal out1_p and the second output signal out1_n, where in the differential mode the first input signal input1 and the second input signal input2 are the first signal In1 and the second signal In2 respectively, and in the single-ended mode the first input signal input1 is One of the first signal In1 and the second signal In2, the second input signal input2 is the reference voltage signal vref, the first signal In1 and the second signal In2 are complementary; the conversion module 102 is configured to receive the first output signal out1_p and a second output signal out1_n and amplifying the voltage difference between the first output signal out1_p and the second output signal out1_n to output the first internal signal out2_p and the second internal signal out2_n.
  • the input buffer 101 receives the first input signal input1 and the second input signal input2 through the same transmission path in differential mode and single-ended mode, which is beneficial to reducing the switching between the differential mode and the single-ended mode of the receiving circuit.
  • the first input signal input1 and the second input signal input2 are interfered, the accuracy of the first internal signal out2_p and the second internal signal out2_n output by the conversion module 102 is improved.
  • the complexity of the receiving circuit is simplified, only Using an input buffer 101 is beneficial to reducing the operating current of the receiving circuit, thereby reducing the overall power consumption of the receiving circuit.
  • the first signal In1 and the second signal In2 may be a clock signal and a complementary clock signal respectively.
  • the receiving circuit works in differential mode, it is usually used to receive higher frequency signals for better performance; when the receiving circuit works in single-ended mode, it only receives one clock signal, which has a lower frequency, and receives a reference Voltage signal vref, used for lower frequency operation to save power consumption.
  • the input buffer 101 may include: a current control module 111 configured to provide a current to the first node net1 in response to the bias voltage signal bias0; an input module 112 and connected to the input module 112 The load module 113, the input module 112 is connected to the first node net1, and the input module 112 is connected to the load module 113 via the second node net2 and the third node net3; wherein the input module 112 receives the first input signal input1 and the second input signal input2, the second node net2 outputs the first output signal out1_p (refer to Figure 1), and the third node net3 outputs the second output signal out1_n (refer to Figure 1).
  • the current control module 111 may be configured to adjust the current provided to the first node net1 in response to the bias voltage signal bias0, so that the current provided to the first node net1 in the single-ended mode The current is less than the current provided to the first node net1 in differential mode. In this way, it is beneficial to reduce the operating current in the single-ended mode in the receiving circuit, thereby reducing the overall power consumption of the receiving circuit.
  • the current control module 111 may include: a first PMOS transistor MP1, the gate of the first PMOS transistor MP1 receives the enable signal EnN, and the source of the first PMOS transistor MP1 is connected to the power supply voltage Vccl;
  • the second PMOS transistor MP2 and the third PMOS transistor MP3 have the source electrode of the second PMOS transistor MP2 and the third PMOS transistor MP3 connected to the drain electrode of the first PMOS transistor MP1.
  • the drains of the three PMOS transistors MP3 are all connected to the first node net1, and the gates of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 receive the bias voltage signal bias0.
  • control enable signal EnN can be used as a master switch for whether the input buffer 101 works. For example, when the control enable signal EnN is low level, the first PMOS transistor MP1 is turned on, so that the input buffer 101 can work; the control enable signal EnN When the energy signal EnN is high level, the first PMOS transistor MP1 is turned off. At this time, no matter the bias voltage signal bias0 is high level or low level, there is no current path in the input buffer 101, that is, the input buffer 101 will not perform Work.
  • the current control module 111 by controlling the level value of the bias voltage signal bias0 to adjust the conduction degree of the second PMOS transistor MP2 and the third PMOS transistor MP3, it is beneficial for the current control module 111 to provide the first node net1 in the single-ended mode. The current is less than the current provided to the first node net1 in differential mode.
  • the bias voltage signal bias0 in differential mode, the bias voltage signal bias0 is controlled to be at a first level value, and in single-ended mode, the bias voltage signal bias0 is controlled to be at a second level value, and the second level value is greater than the first level value, In this way, the conduction degree of the second PMOS transistor MP2 and the third PMOS transistor MP3 in the differential mode is greater than that in the single-ended mode, so that the current at the first node net1 in the differential mode is greater than the first node net1 in the single-ended mode. Current at node net1.
  • the current control module 111 may include: a first control unit 1111 connected to the first node net1 and configured to be turned on in response to the bias voltage signal bias0 to provide the first node net1 with The first current; the second control unit 1112, connected to the first node net1, is configured to be turned on in response to the control signal SeEn and the bias voltage signal bias0 to provide the second current to the first node net1; wherein, in the single-ended In the differential mode, the first control unit 1111 is turned on and the second control unit 1112 is not turned on. In the differential mode, the first control unit 1111 and the second control unit 1112 are both turned on.
  • the first control unit 1111 may include: a first PMOS transistor MP1 , the gate of the first PMOS transistor MP1 receives the enable signal EnN, and the source of the first PMOS transistor MP1 is connected to the power supply voltage. Vccl; the second PMOS transistor MP2 and the third PMOS transistor MP3, the source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3 are connected to the drain of the first PMOS transistor MP1, and the drain of the second PMOS transistor MP2 The gate electrode of the second PMOS transistor MP2 and the gate electrode of the third PMOS transistor MP3 both receive the bias voltage signal bias0.
  • the control enable signal EnN can be used as a master switch for whether the first control unit 1111 works. For example, when the control enable signal EnN is low level, the first PMOS transistor MP1 is turned on, so that the first control unit 1111 can work; When the control enable signal EnN is high level, the first PMOS transistor MP1 is turned off. At this time, no matter the bias voltage signal bias0 is high level or low level, there is no current path in the first control unit 1111, that is, the first control unit 1111 won't do the work.
  • the second control unit 1112 may include: a fourth PMOS transistor MP4, the gate of the fourth PMOS transistor MP4 receives the control signal SeEn, and the source of the fourth PMOS transistor MP4 is connected to the power supply voltage Vccl; a fifth PMOS The source of the transistor MP5 and the sixth PMOS transistor MP6 is connected to the drain of the fourth PMOS transistor MP4. The source of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6 are connected to the drain of the fourth PMOS transistor MP4. The drains of the transistor MP6 are both connected to the first node net1, and the gates of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 both receive the bias voltage signal bias0.
  • the enable signal EnN is low level, causing the first PMOS transistor MP1 to be turned on, and the bias voltage signal bias0 is at a level that can cause the second PMOS transistor MP2 and the third PMOS transistor MP3 to be turned on.
  • the conduction degree of the second PMOS transistor MP2 and the third PMOS transistor MP3 can be controlled by adjusting the level value of the bias voltage signal bias0 to control the flow through the second PMOS transistor MP2 and the third PMOS transistor MP3
  • the magnitude of the current, the control signal SeEn is high level, so that the fourth PMOS transistor MP4 is in the off state, no matter what the level value of the bias voltage signal bias0 is, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6
  • the enable signal EnN is low level, causing the first PMOS transistor MP1 to conduct.
  • the bias voltage signal bias0 When the bias voltage signal bias0 is turned on, the bias voltage signal bias0 is at a level value that can cause the second PMOS transistor MP2 and the third PMOS transistor MP3 to turn on, and the second PMOS transistor MP2 and the third PMOS transistor MP2 can be controlled by adjusting the level value of the bias voltage signal bias0.
  • the degree of conduction of the third PMOS transistor MP3 is used to control the magnitude of the current flowing through the second PMOS transistor MP2 and the third PMOS transistor MP3, and the control signal SeEn is also at a low level, causing the fourth PMOS transistor MP4 to be conductive and biased.
  • the voltage signal bias0 is also at a level value that can turn on the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6, and the fifth PMOS transistor MP5 and the sixth PMOS transistor MP5 can be controlled by adjusting the level value of the bias voltage signal bias0.
  • the degree of conduction of tube MP6 is used to control the magnitude of the current flowing through the fifth PMOS tube MP5 and the sixth PMOS tube MP6. That is, the first control unit 1111 and the second control unit 1112 are both turned on, and the current at the first node net1 is the sum of the first current and the second current.
  • the input module 112 may include: a seventh PMOS transistor MP7, the gate of the seventh PMOS transistor MP7 receives the first input signal input1, and the source of the seventh PMOS transistor MP7 is connected to the first input signal input1.
  • a seventh PMOS transistor MP7 receives the first input signal input1, and the source of the seventh PMOS transistor MP7 is connected to the first input signal input1.
  • One node net1, the drain of the seventh PMOS tube MP7 is connected to the second node net2; the eighth PMOS tube MP8, the gate of the eighth PMOS tube MP8 receives the second input signal input2, and the source of the eighth PMOS tube MP8 is connected to the first node net1.
  • Node net1, the drain of the eighth PMOS transistor is connected to the third node net3.
  • the level values of the first input signal input1 and the second input signal input2 change out of synchronization, so that the turn-on moment of the seventh PMOS transistor MP7 that receives the first input signal input1 is different from that of the seventh PMOS transistor MP7 that receives the second input signal input2.
  • the conduction time of the eighth PMOS transistor MP8, and at the same time, the conduction degree of the seventh PMOS transistor MP7 is different from the conduction degree of the eighth PMOS transistor MP8. It can be understood that since the conduction degree of the seventh PMOS transistor MP7 is different from the conduction degree of the eighth PMOS transistor MP8, the shunting capabilities of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 to the current at the first node net1 are also different. Different, so that the voltage at the second node net2 is different from the voltage at the third node 3.
  • the conduction degree of the eighth PMOS transistor MP8 is greater than the conduction degree of the seventh PMOS transistor MP7, so that the first More current at node net1 flows into the path where the eighth PMOS transistor MP8 is located, so that the current at the third node net3 is greater than the current at the second node net2, and the voltage at the third node net3 is higher than the voltage at the second node net2.
  • the load module 113 may include: a first load unit 1131, connected between the second node net2 and the ground, configured as the first load unit in single-ended mode
  • the equivalent resistance value of 1131 is greater than the equivalent resistance value of the first load unit 1131 in the differential mode
  • the second load unit 1132 is connected between the third node net3 and the ground terminal, and is configured to be the first load unit 1131 in the single-ended mode.
  • the equivalent resistance value of the second load unit 1132 is greater than the equivalent resistance value of the second load unit 1132 in the differential mode. It can be seen that whether it is the first load unit 1131 or the second load unit 1132, the equivalent resistance value in the single-ended mode is greater than the equivalent resistance value in the differential mode.
  • the difference between the current at the second node net2 and the current at the third node net3 in the single-ended mode is The absolute value is the first difference.
  • the absolute value of the difference between the current at the second node net2 and the current at the third node net3 is the second difference. The first difference is smaller than the second difference.
  • the product of the equivalent resistance of the first load unit 1131 and the current flowing through the second node net2 is the first product
  • the equivalent resistance of the second load unit 1132 and the current flowing through the third node net3 are The product is the second product
  • the difference between the voltage at the second node net2 and the voltage at the third node net3 is the difference between the first product and the second product.
  • the equivalent resistance of the first load unit 1131 is equal to the equivalent resistance of the second load unit 1132
  • the difference between the voltage at the second node net2 and the voltage at the third node net3 is the equivalent resistance and the current
  • the first load unit 1131 may include a first sub-resistance R1 and a second sub-resistance R2 connected in series, and a third sub-resistor R3 and a fourth sub-resistance R4 connected in parallel, wherein, One end of the first sub-resistor R1 is connected to the second node net2, the other end of the first sub-resistor R1 is connected to one end of the second sub-resistor R2, and the other end of the second sub-resistor R2 is simultaneously connected to one end of the third sub-resistor R3 and One end of the fourth sub-resistor R4 is connected, and the other end of the third sub-resistor R3 is connected to the other end of the fourth sub-resistor R4; the second load unit 1132 may include a fifth sub-resistor R5 and a sixth sub-resistor R6 connected in series, and a seventh sub-resistor
  • the number of sub-resistors connected in series is two and the number of sub-resistors connected in parallel is two as an example in Figure 9.
  • the number of series sub-resistors and the number of parallel sub-resistors can be reasonably designed, or only Design several sub-resistors connected in series to form the first load unit 1131 and/or the second load unit 1132, or only design several sub-resistors connected in parallel to form the first load unit 1131 and/or the second load unit 1132, or design Several sub-resistance groups that have formed a parallel circuit constitute the first load unit 1131 and/or the second load unit 1132.
  • the first load unit 1131 may include: a first resistor 1133 connected between the second node net2 and the fourth node net4; a first adjustable load 1134 connected between the second node net2 and the fourth node net4; Between the four nodes net4 and the ground terminal, it is configured to adjust the equivalent resistance value of the first adjustable load 1134 in response to the adjustment signal SeEnN, and the equivalent resistance value of the first adjustable load 1134 in the single-ended mode is greater than that in the differential mode.
  • the equivalent resistance value of the first adjustable load 1134 is as follows; the second load unit 1132 may include: a second resistor 1135, connected between the third node net3 and the fifth node net5; a second adjustable load 1136, connected between the third node net3 and the fifth node net5; Between the five nodes net5 and the ground terminal, it is configured to adjust the equivalent resistance value of the second adjustable load 1136 in response to the adjustment signal SeEnN, and in the single-ended mode, the equivalent resistance value of the second adjustable load 1136 is greater than the differential The equivalent resistance value of the second adjustable load 1136 in mode.
  • the equivalent resistance value of the first adjustable load 1134 in the single-ended mode is greater than the equivalent resistance value of the first adjustable load 1134 in the differential mode
  • the resistance value is greater than the equivalent resistance value of the first load unit 1131 in the differential mode; by controlling the equivalent resistance value of the second adjustable load 1136 in the single-ended mode to be greater than the equivalent resistance value of the second adjustable load 1136 in the differential mode.
  • the equivalent resistance value of the second load unit 1132 in the single-ended mode is greater than the equivalent resistance value of the second load unit 1132 in the differential mode.
  • the resistance values of the first resistor 1133 and the second resistor 1135 are 0, that is, there is only an adjustable load part in the load module 113, and the second node net2 and the fourth node net4 have the same potential. Nodes, the third node net3 and the fifth node net5 are nodes with the same potential.
  • the first adjustable load 1134 may include: a third resistor 1137 connected between the fourth node net4 and the ground; a first MOS transistor M1, a first resistor of the first MOS transistor M1; The terminal is connected to the fourth node net4, the second terminal of the first MOS tube M1 is connected to the ground terminal, and the control terminal of the first MOS tube M1 receives the adjustment signal SeEnN.
  • the first MOS tube M1 responds to the adjustment signal SeEnN is turned off, and in the differential mode, the first MOS transistor M1 is turned on in response to the adjustment signal SeEnN.
  • the third resistor 1137 is in a parallel relationship with the first MOS transistor M1.
  • the first adjustable load 1134 is composed of the third resistor 1137.
  • the first adjustable load 1134 is composed of a third resistor 1137 and the first MOS transistor M1 connected in parallel.
  • the resistance of the third resistor 1137 is greater than the parallel connection.
  • the total resistance of the third resistor 1137 and the first MOS transistor M1 realizes that the equivalent resistance value of the first adjustable load 1134 in the single-ended mode is greater than the equivalent resistance value of the first adjustable load 1134 in the differential mode.
  • the third resistor 1137 includes four ninth sub-resistance R9, tenth sub-resistor R10, eleventh sub-resistor R11 and twelfth sub-resistance R12 connected in series as an example.
  • the number of sub-resistors connected in series can be reasonably designed, or several sub-resistors connected in parallel can be designed to form the third resistor 1137, or several sub-resistors have been formed.
  • the third resistor 1137 is designed to have both series-connected sub-resistors and parallel-connected sub-resistances.
  • the first MOS tube M1 is an NMOS tube as an example. In the single-ended mode, the adjustment signal SeEnN is low level, the first MOS tube M1 is in the disconnected state, and in the differential mode, the adjustment signal SeEnN is high.
  • the first MOS tube M1 is turned on; in practical applications, the first MOS tube M1 can also be a PMOS tube, then in the single-ended mode, the adjustment signal SeEnN is high level, and the first MOS tube M1 is in the off state , in differential mode, the adjustment signal SeEnN is low level, and the first MOS transistor M1 is turned on.
  • the second adjustable load 1136 may include: a fourth resistor 1138, connected between the fifth node net5 and the ground terminal; a second MOS tube M2, the first end of the second MOS tube M2 is connected to the Five-node net5, the second end of the second MOS tube M2 is connected to the ground end, and the control end of the second MOS tube M2 receives the adjustment signal SeEnN.
  • the second MOS tube M2 In the single-ended mode, the second MOS tube M2 is turned off in response to the adjustment signal SeEnN. In the differential mode, the second MOS transistor M2 is turned on in response to the adjustment signal SeEnN.
  • the fourth resistor 1138 and the second MOS transistor M2 are connected in parallel.
  • the second adjustable load 1136 is composed of the fourth resistor 1138
  • the second adjustable load 1136 is composed of a fourth resistor 1138 and the second MOS transistor M2 connected in parallel.
  • the resistance of the fourth resistor 1138 is greater than the parallel connection.
  • the total resistance of the fourth resistor 1138 and the second MOS transistor M2 realizes that the equivalent resistance value of the second adjustable load 1136 in the single-ended mode is greater than the equivalent resistance value of the second adjustable load 1136 in the differential mode.
  • the fourth resistor 1138 includes four serially connected thirteenth sub-resistor R13 , fourteenth sub-resistor R14 , fifteenth sub-resistor R15 and sixteenth sub-resistor R16 as an example.
  • the number of sub-resistors connected in series can be reasonably designed, or several sub-resistors connected in parallel can be designed to form the fourth resistor 1138, or several sub-resistors connected in parallel can be designed.
  • the sub-resistance group that has formed a parallel circuit constitutes the fourth resistor 1138, or the fourth resistor 1138 is designed to have both series-connected sub-resistors and parallel-connected sub-resistances.
  • the second MOS transistor M2 is an NMOS transistor as an example. In the single-ended mode, the adjustment signal SeEnN is low level, the second MOS transistor M2 is in the disconnected state, and in the differential mode, the adjustment signal SeEnN is high. level, the second MOS tube M2 is turned on; in practical applications, the second MOS tube M2 can also be a PMOS tube, then in the single-ended mode, the adjustment signal SeEnN is high level, and the second MOS tube M2 is in a disconnected state. , in differential mode, the adjustment signal SeEnN is low level, and the second MOS transistor M2 is turned on.
  • the first resistor 1133 may include: a first sub-resistance R1 and a second sub-resistance R2 connected in series, and a third sub-resistance R3 and a fourth sub-resistance R4 connected in parallel, where , one end of the first sub-resistor R1 is connected to the second node net2, the other end of the first sub-resistor R1 is connected to one end of the second sub-resistor R2, and the other end of the second sub-resistor R2 is simultaneously connected to one end of the third sub-resistor R3 It is connected to one end of the fourth sub-resistor R4, and the other end of the third sub-resistor R3 is connected to the other end of the fourth sub-resistor R4.
  • the second resistor 1135 may include a fifth sub-resistance R5 and a sixth sub-resistance R6 connected in series, and a seventh sub-resistance R7 and an eighth sub-resistance R8 connected in parallel, wherein one end of the fifth sub-resistor R5 is connected to the third node.
  • net3 is connected, the other end of the fifth sub-resistor R5 is connected to one end of the sixth sub-resistor R6, the other end of the sixth sub-resistor R6 is simultaneously connected to one end of the seventh sub-resistor R7 and one end of the eighth sub-resistor R8, the seventh The other end of the sub-resistor R7 is connected to the other end of the eighth sub-resistor R8.
  • the receiving circuit may further include: a selection module 103, which receives the original first signal In1, the original second signal In2 and the original reference voltage signal vref, and is configured to respond to the mode select signal mode select , providing the first input signal input1 and the second input signal input2 to the input buffer 101, where the mode selection signal mode select is used to represent the single-ended mode or the differential mode, the first signal In1 corresponds to the original first signal In1, and the second The signal In2 corresponds to the original second signal In2, and the original reference voltage signal vref corresponds to the reference voltage signal vref.
  • a selection module 103 which receives the original first signal In1, the original second signal In2 and the original reference voltage signal vref, and is configured to respond to the mode select signal mode select , providing the first input signal input1 and the second input signal input2 to the input buffer 101, where the mode selection signal mode select is used to represent the single-ended mode or the differential mode, the first signal In1 corresponds to the original first signal In1, and the second The signal In2 correspond
  • the receiving circuit can use the selection module 103 to control the signal received by the receiving circuit to be the original first signal In1 and the original second signal In2, so that the signals received by the input buffer 101 are the first signal In1 and the second signal In2.
  • the signal received by the control receiving circuit is one of the original first signal In1 and the original second signal In2 and the original reference voltage signal vref, so that the signal received by the input buffer 101 is the first signal In1 and the original reference voltage signal vref.
  • One of the second signals In2 and the reference voltage signal vref are used to operate in the single-ended mode.
  • the mode select signal mode select may include: a first mode select signal (not shown in the figure) used to characterize the single-ended mode, and a second mode select signal (not shown in the figure) used to characterize the differential mode. out).
  • the mode select signal mode select received by the selection module 103 is the first mode selection signal
  • the selection module 103 controls the receiving circuit to receive the original first signal In1 and the original second signal In2, so that the input buffer 101 receives the signal are the first signal In1 and the second signal In2
  • the mode selection signal mode select received by the selection module 103 is the second mode selection signal
  • the selection module 103 controls the receiving circuit to receive the original first signal In1 and the original second signal In2.
  • One of the first signal In1 and the second signal In2 and the original reference voltage signal vref so that the signal received by the input buffer 101 is one of the first signal In1 and the second signal In2 and the reference voltage signal vref.
  • the selection module 103 can also control the receiving circuit to operate in the differential mode or the single-ended mode based on the two states of the mode select signal mode select. For example, when the mode select signal mode select received by the selection module 103 is high level, the signals received by the control selection module 103 are the original first signal In1 and the original second signal In2, so that the signal received by the input buffer 101 is the first signal. In1 and the second signal In2; when the mode select signal mode select received by the selection module 103 is low level, the signal received by the control selection module 103 is one of the original first signal In1 and the original second signal In2 and the original reference voltage.
  • the signal vref is such that the signal received by the input buffer 101 is one of the first signal In1 and the second signal In2 and the reference voltage signal vref.
  • the selection module 103 may include: a first selection unit 123 and a second selection unit 133 , one of the first selection unit 123 and the second selection unit 133 receiving the original first signal In1 and The original reference voltage signal vref, the other receives the original second signal In2 and the original reference voltage signal vref; in the single-ended mode, one of the first selection unit 123 and the second selection unit 133 responds to the mode select signal mode select The first signal In1 or the second signal In2 is output, and the other responds to the mode select signal mode select to output the reference voltage signal vref; in the differential mode, one of the first selection unit 123 and the second selection unit 133 responds to the mode The selection signal mode select outputs the first signal In1, and the other outputs the second signal In2 in response to the mode selection signal mode select.
  • the first selection unit 123 receives the original first signal In1 and the original reference voltage signal vref
  • the second selection unit 133 receives the original second signal In2 and the original reference voltage signal vref.
  • the first selection unit 123 In the single-ended mode, the first selection unit 123 outputs the first signal In1 in response to the mode selection signal mode select, and the second selection unit 133 outputs the reference voltage signal vref in response to the mode selection signal mode select, or the first selection unit 123
  • the reference voltage signal vref is output in response to the mode select signal mode select, and the second selection unit 133 outputs the second signal In2 in response to the mode select signal mode select, so that the signals received by the input buffer 101 are the first signal In1 and the second signal One of In2 and the reference voltage signal vref.
  • the first selection unit 123 outputs the first signal In1 in response to the mode select signal mode select, and the second selection unit 133 outputs the second signal In2 in response to the mode select signal mode select to realize the signal received by the input buffer 101 are the first signal In1 and the second signal In2.
  • the conversion module 102 may include: an amplification unit 122 configured to amplify the voltage difference between the first output signal out1_p and the second output signal out1_n; the conversion unit 132 configured to, The level logic conversion is performed on the first output signal and the second output signal amplified by the amplification unit 122, and the first internal signal out2_p and the second internal signal out2_n are output.
  • performing level logic conversion on the first output signal and the second output signal amplified by the amplification unit 122 refers to: converting the first output signal out1_p output by the second node net2 and the output signal output by the third node net3
  • the second output signal out1_n is converted from an analog level to a digital level, that is, the high level state of the first internal signal out2_p and/or the second internal signal out2_n output by the conversion module 102 is infinitely close to the power supply voltage.
  • the first internal signal The low-level state of out2_p and/or the second internal signal out2_n is infinitely close to the ground terminal voltage to facilitate subsequent logic circuit processing.
  • the amplifying unit 122 may be further configured to adjust the first operating current of the amplifying unit 122 in response to the first bias signal Bias1 so that the first operating current in the single-ended mode Less than the first operating current in differential mode. In this way, it is helpful to further ensure that the operating current of the receiving circuit in the single-ended mode is smaller than the operating current in the differential mode, thereby helping to reduce the overall power consumption of the receiving circuit.
  • the conversion unit 132 may be further configured to adjust the second operating current of the conversion unit 132 in response to the second bias signal Bias2 so that the second operating current in the single-ended mode Less than the second operating current in differential mode. In this way, it is helpful to further ensure that the operating current of the receiving circuit in the single-ended mode is smaller than the operating current in the differential mode, thereby helping to reduce the overall power consumption of the receiving circuit.
  • first bias signal bias1 and the second bias signal bias2 may be the same bias signal, which is beneficial to reducing the complexity of the receiving circuit.
  • the enable signal EnN is low level
  • the first PMOS transistor MP1 is turned on
  • the bias voltage signal bias0 is at a level value that causes the second PMOS transistor MP2 and the third PMOS transistor MP3 to be turned on.
  • the control signal SeEn is high level, so that the fourth PMOS transistor MP4 is in a disconnected state.
  • the enable signal EnN is low level
  • the first PMOS transistor MP1 is turned on
  • the bias voltage signal bias0 is at a level value that causes the second PMOS transistor MP2 and the third PMOS transistor MP3 to be turned on
  • the control signal SeEn is also low level
  • the fourth PMOS transistor MP4 is turned on
  • the bias voltage signal bias0 is also at a level value that causes the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 to be turned on, and by adjusting the voltage of the bias voltage signal bias0
  • the flat value controls the conduction degree of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6.
  • the level value of the first input signal input1 when the level value of the first input signal input1 is higher than the level value of the second input signal input2, the level value of the second output signal out1_n output by the third node net3 will be high, and the level value of the second node net2 will be high.
  • the level value of the output first output signal out1_p is low.
  • the level value of the first input signal input1 is lower than the level value of the second input signal input2
  • the level value of the second output signal out1_n output by the third node net3 will be low, and the first output signal output by the second node net2 will be low.
  • out1_p level value is high.
  • the equivalent resistance value of the load module 113 in the single-ended mode is greater than the equivalent resistance value of the load module 113 in the differential mode, so that the difference between the current at the second node net2 and the current at the third node net3 in the single-ended mode
  • the difference between the voltage at the second node net2 and the voltage at the third node net3 can be large, even in single-ended mode there is still a large voltage between the second node net2 and the third node net3. swing.
  • the input The buffer 101 receives the first input signal input1 and the second input signal input2 through the same transmission path in the differential mode and the single-ended mode, which is beneficial to reducing the first input signal input1 and the second input signal input2 when the receiving circuit switches between the differential mode and the single-ended mode.
  • the second input signal input2 is subject to interference to improve the accuracy of the first internal signal out2_p and the second internal signal out2_n output by the conversion module 102.
  • Another embodiment of the present disclosure also provides a memory, including the aforementioned receiving circuit.
  • the memory can selectively receive the first signal In1, the second signal In2 and the reference voltage signal vref to selectively operate in the differential mode or the single-ended mode.
  • the first signal In1 and the second signal In2 received by the memory can be two complementary clock signals, and the frequencies of the first signal In1 and the second signal In2 are higher, which is beneficial to improving the processing speed and operation of the memory.
  • Performance In single-ended mode, the memory only receives one of the first signal In1 and the second signal In2, that is, it only receives one clock signal and operates at a lower frequency, which is beneficial to saving power consumption.
  • the first signal In1 and the second signal In2 received by the memory can be shared in differential mode and single-ended mode, and can be reduced by adjusting the enable signal EnN, the bias voltage signal bias0, the control signal SeEn and the load module 113, etc.
  • the operating current of the memory in single-ended mode to reduce the overall power consumption of the memory.
  • the memory may be DDR memory, such as DDR5 memory.
  • the input buffer can use both the first signal and the second signal to operate in the differential mode, and can also use the reference voltage signal and the first signal and the second signal.
  • One of them can be used in single-ended mode, that is, the same input buffer can be used in differential mode or single-ended mode, which is beneficial to reducing the complexity of the receiving circuit and reducing the layout area of the receiving circuit.
  • the input buffer only receives one of the first signal and the second signal, and the other received signal is a reference voltage signal, which can reduce the operating current in the receiving circuit, thus helping to reduce the power consumption of the receiving circuit. power consumption.

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Abstract

本公开提供一种一种接收电路以及存储器，接收电路包括：输入缓冲器，被配置为，接收第一输入信号和第二输入信号并比较第一输入信号与第二输入信号，输出第一输出信号和第二输出信号，其中，在差分模式下第一输入信号和第二输入信号分别为第一信号和第二信号，在单端模式下第一输入信号为第一信号与第二信号中的一者，第二输入信号为参考电压信号，第一信号和第二信号互补；转换模块，被配置为，接收第一输出信号以及第二输出信号并对第一输出信号与第二输出信号的电压差进行放大，以输出第一内部信号以及第二内部信号。

Description

接收电路以及存储器
本公开基于申请号为202210623097.6、申请日为2022年06月01日、申请名称为“接收电路以及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种接收电路以及存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
DRAM可以包括双倍速率动态随机存储器(Double Data Rate，DDR)、GDDR(Graphics Double Data Rate)动态随机存储器、低功耗双倍速率动态随机存储器(Low Power Double Data Rate，LPDDR)。随着DRAM应用的领域越来越多，如DRAM越来越多的应用于移动领域，用户对于DRAM功耗指标的要求越来越高。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种接收电路以及存储器。
本公开的第一方面提供了一种接收电路，包括：输入缓冲器，被配置为，接收第一输入信号和第二输入信号并比较所述第一输入信号与所述第二输入信号，输出第一输出信号和第二输出信号，其中，在差分模式下所述第一输入信号和所述第二输入信号分别为第一信号和第二信号，在单端模式下所述第一输入信号为所述第一信号与所述第二信号中的一者，所述第二输入信号为参考电压信号，所述第一信号和所述第二信号互补；转换模块，被配置为，接收所述第一输出信号以及所述第二输出信号并对所述第一输出信号与所述第二输出信号的电压差进行放大，以输出第一内部信号以及第二内部信号。
其中，所述接收电路还包括：选择模块，接收原始第一信号、原始第二信号以及原始参考电压信号，被配置为，响应于模式选择信号，向所述输入缓冲器提供所述第一输入信号以及所述第二输入信号，其中，所述模式选择信号用于表征所述单端模式或者所述差分模式，所述第一信号与所述原始第一信号对应，所述第二信号与所述原始第二信号对应，所述原始参考电压信号与所述参考电压信号对应。
其中，所述选择模块包括：第一选择单元以及第二选择单元，所述第一选择单元与所述第二选择单元中的一者接收所述原始第一信号以及所述原始参考电压信号，另一者接收所述原始第二信号以及所述原始参考电压信号；在所述单端模式下，所述第一选择单元与所述第二选择单元中的一者响应于所述模式选择信号输出所述第一信号或者所述第二信号，另一者响应于所述模式选择信号输出所述参考电压信号；在所述差分模式下，所述第一选择单元与所述第二选择单元中的一者响应于所述模式选择信号输出所述第一信号，另一者响应于所述模式选择信号输出所述第二信号。
其中，所述输入缓冲器包括：电流控制模块，被配置为，响应于偏置电压信号向第一节点提供电流；输入模块以及与所述输入模块连接的负载模块，所述输入模块与所述第一节点连接，所述输入模块经由第二节点和第三节点与所述负载模块连接；其中，所 述输入模块接收所述第一输入信号以及所述第二输入信号，所述第二节点输出所述第一输出信号，所述第三节点输出所述第二输出信号。
其中，所述电流控制模被配置为，响应于所述偏置电压信号以调整提供给所述第一节点的电流，以使所述单端模式下提供给所述第一节点的电流小于所述差分模式下提供给所述第一节点的电流。
其中，所述电流控制模块包括：第一控制单元，与所述第一节点连接，被配置为，响应于所述偏置电压信号导通以向所述第一节点提供第一电流；第二控制单元，与所述第一节点连接，被配置为，响应于控制信号以及所述偏置电压信号导通以向所述第一节点提供第二电流；其中，在所述单端模式下所述第一控制单元导通且所述第二控制单元不导通，在所述差分模式下所述第一控制单元以及所述第二控制单元均导通。
其中，所述第一控制单元包括：第一PMOS管，所述第一PMOS管的栅极接收使能信号，所述第一PMOS管的源极连接电源电压；第二PMOS管以及第三PMOS管，所述第二PMOS管的源极以及所述第三PMOS管的源极均与所述第一PMOS管的漏极连接，所述第二PMOS管的漏极以及所述第三PMOS管的漏极均连接所述第一节点，所述第二PMOS管的栅极以及所述第三PMOS管的栅极均接收所述偏置电压信号。
其中，所述第二控制单元包括：第四PMOS管，所述第四PMOS管的栅极接收所述控制信号，所述第四PMOS管的源极连接电源电压；第五PMOS管以及第六PMOS管，所述第五PMOS管的源极以及所述第六PMOS管的源极均与所述第四PMOS管的漏极连接，所述第五PMOS管的漏极以及所述第六PMOS管的漏极均连接所述第一节点，所述第五PMOS管的栅极与所述第六PMOS管的栅极均接收所述偏置电压信号。
其中，所述输入模块包括：第七PMOS管，所述第七PMOS管的栅极接收所述第一输入信号，所述第七PMOS管的源极连接所述第一节点，所述第七PMOS管的漏极连接所述第二节点；第八PMOS管，所述第八PMOS管的栅极接收所述第二输入信号，所述第八PMOS管的源极连接所述第一节点，所述第八PMOS管的漏极连接所述第三节点。
其中，所述负载模块包括：第一负载单元，连接在所述第二节点与地端之间，被配置为，在所述单端模式下所述第一负载单元的等效电阻值大于在所述差分模式下所述第一负载单元的等效电阻值；第二负载单元，连接在所述第三节点与地端之间，被配置为，在所述单端模式下所述第二负载单元的等效电阻值大于在所述差分模式下所述第二负载单元的等效电阻值。
其中，所述第一负载单元包括：第一电阻，连接在所述第二节点与第四节点之间；第一可调负载，连接在所述第四节点与所述地端之间，被配置为，响应于调节信号调整所述第一可调负载的等效电阻值，且所述单端模式下所述第一可调负载的等效电阻值大于所述差分模式下所述第一可调负载的等效电阻值；所述第二负载单元包括：第二电阻，连接在所述第三节点与第五节点之间；第二可调负载，连接在所述第五节点与所述地端之间，被配置为，响应于所述调节信号调整所述第二可调负载的等效电阻值，且在所述单端模式下所述第二可调负载的等效电阻值大于所述差分模式下所述第二可调负载的等效电阻值。
其中，所述第一可调负载包括：第三电阻，连接在所述第四节点与地端之间；第一MOS管，所述第一MOS管的第一端连接所述第四节点，所述第一MOS管的第二端连接所述地端，所述第一MOS管的控制端接收所述调节信号，其中，在所述单端模式下，所述第一MOS管响应于所述调节信号截止，在所述差分模式下，所述第一MOS管响应于所述调节信号导通。
其中，所述第二可调负载包括：第四电阻，连接在所述第五节点与所述地端之间；第二MOS管，所述第二MOS管的第一端连接所述第五节点，所述第二MOS管的第二端连接所述地端，所述第二MOS管的控制端接收所述调节信号，其中，在所述单端模式 下，所述第二MOS管响应于所述调节信号截止，在所述差分模式下，所述第二MOS管响应于所述调节信号导通。
其中，所述转换模块包括：放大单元，被配置为，对所述第一输出信号与所述第二输出信号的电压差进行放大；转换单元，被配置为，对经所述放大单元放大后的所述第一输出信号以及所述第二输出信号进行电平逻辑转换，并输出所述第一内部信号以及所述第二内部信号。
其中，所述放大单元还被配置为，响应于第一偏置信号以调整所述放大单元的第一工作电流，以使所述单端模式下的所述第一工作电流小于所述差分模式下的第一工作电流。
其中，所述转换单元还被配置为，响应于第二偏置信号以调整所述转换单元的第二工作电流，以使所述单端模式下的所述第二工作电流小于所述差分模式下的第二工作电流。
本公开的第二方面提供了一种存储器，包括如第一方面所述的接收电路。
本公开实施例所提供的接收电路以及存储器中，输入缓冲器可以利用第一信号和第二信号两者以运用在差分模式下，也可以利用参考电压信号以及第一信号和第二信号中的一者以运用在单端模式下，即同一输入缓冲器既可以运用在差分模式中，也可以运用在单端模式中，有利于降低接收电路的复杂度，以及降低接收电路的布局面积。此外，在单端模式下，输入缓冲器仅接收第一信号和第二信号中的一者，另外接收的信号为参考电压信号，可以降低接收电路中的工作电流，从而有利于降低接收电路的功耗。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的接收电路的一种功能框图；
图2为接收电路的一种功能框图；
图3至图6为本公开一实施例提供的接收电路的另外四种功能框图；
图7和图8为本公开一实施例提供的接收电路中输入缓冲器的两种电路结构示意图；
图9至图11为本本公开一实施例提供的接收电路中负载模块的三种电路结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
经分析发现，接收电路会根据实际需要工作于差分模式或者单端模式下，但是，接收电路会针对差分模式和单端模式各自创建单独的时钟路径，即差分模式下接收电路接收的时钟信号与差分模式下接收电路接收的时钟信号使用不同的时钟路径。
参考图2，图2为接收电路的一种功能框图，接收电路包括两个输入缓冲器，一个为差分输入缓冲器11，一个为单端输入缓冲器12，以及一个转换模块13。当接收电路工作于差分模式下时，差分输入缓冲器11处于工作状态，此时单端输入缓冲器12处于非工作 状态，差分输入缓冲器11通过第一时钟路径接收第一输入信号Dqs_t和第二输入信号Dqs_c，并输出给转换模块13，通过转换模块13输出第一内部信号Dqst和第二内部信号Dqsc；当接收电路工作于单端模式下时，单端输入缓冲器12处于工作状态，此时差分输入缓冲器11处于非工作状态，单端输入缓冲器12通过第二时钟路径接收第一输入信号Dqs_t或第二输入信号Dqs_c中的一者，以及接收参考电压信号vref，并输出给转换模块13，通过转换模块13输出第一内部信号Dqst和第二内部信号Dqsc。
可见，差分输入缓冲器11接收第一输入信号Dqs_t和第二输入信号Dqs_c时采用的是第一时钟路径，单端输入缓冲器12接收第一输入信号Dqs_t或第二输入信号Dqs_c中的一者时采用的是第二时钟路径，第一时钟路径与第二时钟路径不同，如此，接收电路在差分模式和单端模式之间切换时，第一时钟路径与第二时钟路径之间会存在干扰，使得输入缓冲器接收的第一输入信号Dqs_t和/或第二输入信号Dqs_c信号产生毛刺，降低转换模块13输出的第一内部信号Dqst和第二内部信号Dqsc的准确性。此外，在接收电路中设计两种输入缓冲器，不利于简化接收电路的布局，而且会增加接收电路的复杂度，也不利于节省接收电路整体的功耗。
本公开实施例提供一种接收电路以及存储器，接收电路中，输入缓冲器可以利用第一信号和第二信号两者以工作在差分模式下，也可以利用参考电压信号以及第一信号和第二信号中的一者以工作在单端模式下，即同一输入缓冲器既可以运用在差分模式中，也可以运用在单端模式中，有利于降低接收电路的复杂度，以及降低接收电路的布局面积。此外，在单端模式下，输入缓冲器仅接收第一信号和第二信号中的一者，另外接收的信号为参考电压信号，可以降低接收电路中的工作电流，从而有利于降低接收电路的功耗。
本公开一实施例提供一种接收电路，以下将结合附图对本公开一实施例提供的接收电路进行详细说明。图1、图3至图6为本公开一实施例提供的接收电路的五种功能框图；图7和图8为本公开一实施例提供的接收电路中输入缓冲器的两种电路结构示意图；图9至图11为本公开一实施例提供的接收电路中负载模块的三种电路结构示意图。
结合参考图1和图3，接收电路包括：输入缓冲器101，被配置为，接收第一输入信号input1和第二输入信号input2并比较第一输入信号input1和第二输入信号input2，输出第一输出信号out1_p和第二输出信号out1_n，其中，在差分模式下第一输入信号input1和第二输入信号input2分别为第一信号In1和第二信号In2，在单端模式下第一输入信号input1为第一信号In1与第二信号In2中的一者，第二输入信号input2为参考电压信号vref，第一信号In1和第二信号In2互补；转换模块102，被配置为，接收第一输出信号out1_p以及第二输出信号out1_n并对第一输出信号out1_p与第二输出信号out1_n的电压差进行放大，以输出第一内部信号out2_p以及第二内部信号out2_n。
可见，本公开实施例提供的接收电路中，设计一个既可以运用于差分模式也可以运用于单端模式的输入缓冲器101，一方面，有利于降低接收电路的复杂度以及降低接收电路的布局面积，另一方面，输入缓冲器101在差分模式和单端模式下通过同一传输路径接收第一输入信号input1和第二输入信号input2，有利于降低接收电路在差分模式和单端模式之间切换时第一输入信号input1和第二输入信号input2受到的干扰，以提高转换模块102输出的第一内部信号out2_p以及第二内部信号out2_n的准确性，再一方面，简化接收电路的复杂度，仅使用一个输入缓冲器101有利于降低接收电路的工作电流，从而有利于降低接收电路整体的功耗。
在一些实施例中，第一信号In1和第二信号In2分别可以为时钟信号和互补时钟信号。接收电路工作于差分模式时，通常用于接收频率更高的信号以获得更好的性能；接收电路工作于单端模式时，仅接收一个时钟信号，该时钟信号的频率较低，并接收参考电压信号vref，用于较低频率的操作以节省功耗。
在一些实施例中，参考图5，输入缓冲器101可以包括：电流控制模块111，被配置 为，响应于偏置电压信号bias0向第一节点net1提供电流；输入模块112以及与输入模块112连接的负载模块113，输入模块112与第一节点net1连接，输入模块112经由第二节点net2和第三节点net3与负载模块113连接；其中，输入模块112接收第一输入信号input1以及第二输入信号input2，第二节点net2输出第一输出信号out1_p(参考图1)，第三节点net3输出第二输出信号out1_n(参考图1)。
在一些实施例中，继续参考图5，电流控制模块111可以被配置为，响应于偏置电压信号bias0以调整提供给第一节点net1的电流，以使单端模式下提供给第一节点net1的电流小于差分模式下提供给第一节点net1的电流。如此，有利于降低接收电路中单端模式下的工作电流，以降低接收电路整体的功耗。
在一个例子中，参考图7，电流控制模块111可以包括：第一PMOS管MP1，第一PMOS管MP1的栅极接收使能信号EnN，第一PMOS管MP1的源极连接电源电压Vccl；第二PMOS管MP2以及第三PMOS管MP3，第二PMOS管MP2的源极以及第三PMOS管MP3的源极均与第一PMOS管MP1的漏极连接，第二PMOS管MP2的漏极以及第三PMOS管MP3的漏极均连接第一节点net1，第二PMOS管MP2的栅极以及第三PMOS管MP3的栅极均接收偏置电压信号bias0。如此，控制使能信号EnN可以作为输入缓冲器101是否工作的总开关，例如，控制使能信号EnN为低电平时，第一PMOS管MP1导通，使得输入缓冲器101可以进行工作；控制使能信号EnN为高电平时，第一PMOS管MP1截止，此时无论偏置电压信号bias0为高电平还是低电平，输入缓冲器101中均没有电流通路，即输入缓冲器101不会进行工作。
此外，通过控制偏置电压信号bias0的电平值以调整第二PMOS管MP2以及第三PMOS管MP3的导通程度，从而有利于使得电流控制模块111在单端模式下提供给第一节点net1的电流小于差分模式下提供给第一节点net1的电流。譬如，差分模式下，控制偏置电压信号bias0处于第一电平值，单端模式下，控制偏置电压信号bias0处于第二电平值，且第二电平值大于第一电平值，如此，第二PMOS管MP2和第三PMOS管MP3在差分模式下的导通程度大于在单端模式下的导通程度，使得差分模式下第一节点net1处的电流大于单端模式下第一节点net1处的电流。
在一些实施例中，参考图8，电流控制模块111可以包括：第一控制单元1111，与第一节点net1连接，被配置为，响应于偏置电压信号bias0导通以向第一节点net1提供第一电流；第二控制单元1112，与第一节点net1连接，被配置为，响应于控制信号SeEn以及偏置电压信号bias0导通以向第一节点net1提供第二电流；其中，在单端模式下第一控制单元1111导通且第二控制单元1112不导通，在差分模式下第一控制单元1111以及第二控制单元1112均导通。可见，单端模式下，仅有第一控制单元1111一条电流通路导通以向第一节点net1提供电流，即第一节点net1处的电流为第一电流，差分模式下，存在第一控制单元1111和第二控制单元1112两条并联的电流通路导通以向第一节点net1提供电流，即第一节点net1处的电流为第一电流和第二电流之和，使得单端模式下第一节点net1处的电流小于差分模式下第一节点net1处的电流。
在一些实施例中，继续参考图8，第一控制单元1111可以包括：第一PMOS管MP1，第一PMOS管MP1的栅极接收使能信号EnN，第一PMOS管MP1的源极连接电源电压Vccl；第二PMOS管MP2以及第三PMOS管MP3，第二PMOS管MP2的源极以及第三PMOS管MP3的源极均与第一PMOS管MP1的漏极连接，第二PMOS管MP2的漏极以及第三PMOS管MP3的漏极均连接第一节点net1，第二PMOS管MP2的栅极以及第三PMOS管MP3的栅极均接收偏置电压信号bias0。其中，控制使能信号EnN可以作为第一控制单元1111是否工作的总开关，例如，控制使能信号EnN为低电平时，第一PMOS管MP1导通，使得第一控制单元1111可以进行工作；控制使能信号EnN为高电平时，第一PMOS管MP1截止，此时无论偏置电压信号bias0为高电平还是低电平，第一控制单元 1111中均没有电流通路，即第一控制单元1111不会进行工作。
其中，继续参考图8，第二控制单元1112可以包括：第四PMOS管MP4，第四PMOS管MP4的栅极接收控制信号SeEn，第四PMOS管MP4的源极连接电源电压Vccl；第五PMOS管MP5以及第六PMOS管MP6，第五PMOS管MP5的源极以及第六PMOS管MP6的源极均与第四PMOS管MP4的漏极连接，第五PMOS管MP5的漏极以及第六PMOS管MP6的漏极均连接第一节点net1，第五PMOS管MP5的栅极与第六PMOS管MP6的栅极均接收偏置电压信号bias0。
在一个例子中，单端模式下，使能信号EnN为低电平，使得第一PMOS管MP1导通，偏置电压信号bias0处于可以使得第二PMOS管MP2以及第三PMOS管MP3导通的电平值，且可以通过调节偏置电压信号bias0的电平值大小控制第二PMOS管MP2以及第三PMOS管MP3的导通程度，以控制流过第二PMOS管MP2以及第三PMOS管MP3的电流的大小，控制信号SeEn为高电平，使得第四PMOS管MP4处于断开状态，则无论偏置电压信号bias0的电平值为多少，第五PMOS管MP5以及第六PMOS管MP6中没有电流通过，即第二控制单元1112不导通，第一节点net1处的电流仅由第一控制单元1111提供；差分模式下，使能信号EnN为低电平，使得第一PMOS管MP1导通，偏置电压信号bias0处于可以使得第二PMOS管MP2以及第三PMOS管MP3导通的电平值，且可以用通过调节偏置电压信号bias0的电平值大小控制第二PMOS管MP2以及第三PMOS管MP3的导通程度，以控制流过第二PMOS管MP2以及第三PMOS管MP3的电流的大小，且控制信号SeEn也为低电平，使得第四PMOS管MP4导通，偏置电压信号bias0也处于可以使得第五PMOS管MP5以及第六PMOS管MP6导通的电平值，且可以通过调节偏置电压信号bias0的电平值大小控制第五PMOS管MP5以及第六PMOS管MP6的导通程度，以控制流过第五PMOS管MP5以及第六PMOS管MP6的电流的大小，即第一控制单元1111以及第二控制单元1112均导通，第一节点net1处的电流为第一电流和第二电流之和。
在一些实施例中，参考图7和图8，输入模块112可以包括：第七PMOS管MP7，第七PMOS管MP7的栅极接收第一输入信号input1，第七PMOS管MP7的源极连接第一节点net1，第七PMOS管MP7的漏极连接第二节点net2；第八PMOS管MP8，第八PMOS管MP8的栅极接收第二输入信号input2，第八PMOS管MP8的源极连接第一节点net1，第八PMOS管的漏极连接第三节点net3。
需要说明的是，第一输入信号input1和第二输入信号input2的电平值变化不同步，使得接收第一输入信号input1的第七PMOS管MP7的导通时刻不同于接收第二输入信号input2的第八PMOS管MP8的导通时刻，且同一时刻下，第七PMOS管MP7的导通程度不同于第八PMOS管MP8的导通程度。可以理解的是，基于第七PMOS管MP7的导通程度不同于第八PMOS管MP8的导通程度，第七PMOS管MP7与第八PMOS管MP8对第一节点net1处的电流的分流能力也不同，使得第二节点net2处的电压与第三节点3处的电压不同。
在一个例子中，第一输入信号input1的电平值高于第二输入信号input2的电平值时，第八PMOS管MP8的导通程度大于第七PMOS管MP7的导通程度，使得第一节点net1处的电流更多的流入第八PMOS管MP8所在的通路，使得第三节点net3处的电流大于第二节点net2处的电流，第三节点net3处的电压高于第二节点net2处的电压，从而使得第三节点net3输出的第二输出信号out1_n电平值高，第二节点net2输出的第一输出信号out1_p电平值低，即使得第一输出信号out1_p和第二输出信号out1_n互补。
在一些实施例中，参考图7和图8，负载模块113可以包括：第一负载单元1131，连接在第二节点net2与地端之间，被配置为，在单端模式下第一负载单元1131的等效电阻值大于在差分模式下第一负载单元1131的等效电阻值；第二负载单元1132，连接在第三节点net3与地端之间，被配置为，在单端模式下第二负载单元1132的等效电阻值大于在 差分模式下第二负载单元1132的等效电阻值。可见，无论是第一负载单元1131还是第二负载单元1132，在单端模式下的等效电阻值均大于在差分模式下的等效电阻值。由于单端模式下第一节点net1处的电流小于差分模式下第一节点net1处的电流，且第一节点net1处的电流为第二节点net2处的电流和第三节点net3处的电流的总和，因而，在第八PMOS管MP8的导通程度与第七PMOS管MP7的导通程度不同的前提下，单端模式下第二节点net2处的电流和第三节点net3处的电流之差的绝对值为第一差值，差分模式下第二节点net2处的电流和第三节点net3处的电流之差的绝对值为第二差值，则第一差值比第二差值小。
如此，无论是第一负载单元1131还是第二负载单元1132，在单端模式下的等效电阻值均大于在差分模式下的等效电阻值时，更大的等效电阻可以使得在单端模式下第二节点net2处的电流和第三节点net3处的电流之差较小的情况下，第二节点net2处的电压和第三节点net3处的电压之差可以较大，即使得单端模式下第二节点net2处和第三节点net3处依然有较大的电压摆幅。
可以理解是，第一负载单元1131的等效电阻与流经第二节点net2处的电流的乘积为第一乘积，第二负载单元1132的等效电阻与流经第三节点net3处的电流的乘积为第二乘积，第二节点net2处的电压和第三节点net3处的电压之差为第一乘积与第二乘积之差。在一个例子中，第一负载单元1131的等效电阻等于第二负载单元1132的等效电阻，则第二节点net2处的电压和第三节点net3处的电压之差为该等效电阻与流经第二节点net2处的电流和第三节点net3处的电流之差的乘积。
在一些实施例中，参考图9，第一负载单元1131可以包括相串联的第一子电阻R1和第二子电阻R2，以及相并联的第三子电阻R3和第四子电阻R4，其中，第一子电阻R1的一端与第二节点net2连接，第一子电阻R1的另一端与第二子电阻R2的一端连接，第二子电阻R2的另一端同时与第三子电阻R3的一端和第四子电阻R4的一端连接，第三子电阻R3的另一端与第四子电阻R4的另一端连接；第二负载单元1132可以包括相串联的第五子电阻R5和第六子电阻R6，以及相并联的第七子电阻R7和第八子电阻R8，其中，第五子电阻R5的一端与第三节点net3连接，第五子电阻R5的另一端与第六子电阻R6的一端连接，第六子电阻R6的另一端同时与第七子电阻R7的一端和第八子电阻R8的一端连接，第七子电阻R7的另一端与第八子电阻R8的另一端连接。
需要说明的是，无论是对第一负载单元1131还是对第二负载单元1132而言，图9中仅以串联的子电阻的数量为两个，并联的子电阻的数量为两个为示例，实际应用中，根据接收电路中对第一负载单元1131和/或第二负载单元1132的等效电阻的实际要求，可以合理的设计串联的子电阻的数量以及并联的子电阻的数量，或者仅设计若干个相串联的子电阻构成第一负载单元1131和/或第二负载单元1132，或者仅设计若干个相并联的子电阻构成第一负载单元1131和/或第二负载单元1132，或者设计若干个已经形成并联电路的子电阻组构成第一负载单元1131和/或第二负载单元1132。
在一些实施例中，参考图10和图11，第一负载单元1131可以包括：第一电阻1133，连接在第二节点net2与第四节点net4之间；第一可调负载1134，连接在第四节点net4与地端之间，被配置为，响应于调节信号SeEnN调整第一可调负载1134的等效电阻值，且单端模式下第一可调负载1134的等效电阻值大于差分模式下第一可调负载1134的等效电阻值；第二负载单元1132可以包括：第二电阻1135，连接在第三节点net3与第五节点net5之间；第二可调负载1136，连接在第五节点net5与地端之间，被配置为，响应于调节信号SeEnN调整第二可调负载1136的等效电阻值，且在单端模式下第二可调负载1136的等效电阻值大于差分模式下第二可调负载1136的等效电阻值。如此，通过控制单端模式下第一可调负载1134的等效电阻值大于差分模式下第一可调负载1134的等效电阻值，有利于保证单端模式下第一负载单元1131的等效电阻值大于在差分模式下第一负载单元 1131的等效电阻值；通过控制单端模式下第二可调负载1136的等效电阻值大于差分模式下第二可调负载1136的等效电阻值，有利于保证单端模式下第二负载单元1132的等效电阻值大于在差分模式下第二负载单元1132的等效电阻值。
需要说明的是，在一些实施例中，第一电阻1133和第二电阻1135的阻值为0，即负载模块113中只有可调负载部分，第二节点net2与第四节点net4为电位相同的节点，第三节点net3与第五节点net5为电位相同的节点。
在一些实施例中，参考图11，第一可调负载1134可以包括：第三电阻1137，连接在第四节点net4与地端之间；第一MOS管M1，第一MOS管M1的第一端连接第四节点net4，第一MOS管M1的第二端连接地端，第一MOS管M1的控制端接收调节信号SeEnN，其中，在单端模式下，第一MOS管M1响应于调节信号SeEnN截止，在差分模式下，第一MOS管M1响应于调节信号SeEnN导通。
可以理解的是，第三电阻1137与第一MOS管M1为并联关系，在单端模式下，第一MOS管M1响应于调节信号SeEnN截止时，第一可调负载1134由第三电阻1137构成，在差分模式下，第一MOS管M1响应于调节信号SeEnN导通时，第一可调负载1134由第三电阻1137和第一MOS管M1并联构成，第三电阻1137的阻值大于并联的第三电阻1137和第一MOS管M1的总阻值，从而实现单端模式下第一可调负载1134的等效电阻值大于差分模式下第一可调负载1134的等效电阻值。
需要说明的是，图11中以第三电阻1137包括4个依次串联的第九子电阻R9、第十子电阻R10、第十一子电阻R11以及第十二子电阻R12为示例，在实际应用中，可以根据接收电路中对第三电阻1137的阻值的实际需求，合理设计相串联的子电阻的数量，或者设计若干个相并联的子电阻构成第三电阻1137，或者设计若干个已经形成并联电路的子电阻组构成第三电阻1137，或者设计既存在串联的子电阻也存在并联的子电阻的第三电阻1137。此外，图11中以第一MOS管M1为NMOS管为示例，则单端模式下，调节信号SeEnN为低电平，第一MOS管M1为断开状态，差分模式下，调节信号SeEnN为高电平，第一MOS管M1导通；在实际应用中，第一MOS管M1也可以为PMOS管，则单端模式下，调节信号SeEnN为高电平，第一MOS管M1为断开状态，差分模式下，调节信号SeEnN为低电平，第一MOS管M1导通。
其中，继续参考图11，第二可调负载1136可以包括：第四电阻1138，连接在第五节点net5与地端之间；第二MOS管M2，第二MOS管M2的第一端连接第五节点net5，第二MOS管M2的第二端连接地端，第二MOS管M2的控制端接收调节信号SeEnN，其中，在单端模式下，第二MOS管M2响应于调节信号SeEnN截止，在差分模式下，第二MOS管M2响应于调节信号SeEnN导通。
可以理解的是，第四电阻1138与第二MOS管M2为并联关系，在单端模式下，第二MOS管M2响应于调节信号SeEnN截止时，第二可调负载1136由第四电阻1138构成，在差分模式下，第二MOS管M2响应于调节信号SeEnN导通时，第二可调负载1136由第四电阻1138和第二MOS管M2并联构成，第四电阻1138的阻值大于并联的第四电阻1138和第二MOS管M2的总阻值，从而实现单端模式下第二可调负载1136的等效电阻值大于差分模式下第二可调负载1136的等效电阻值。
需要说明的是，图11中以第四电阻1138包括4个依次串联的第十三子电阻R13、第十四子电阻R14、第十五子电阻R15及第十六子电阻R16为示例，在实际应用中，可以根据接收电路中对第四电阻1138的阻值的实际需求，合理设计相串联的子电阻的数量，或者设计若干个相并联的子电阻构成第四电阻1138，或者设计若干个已经形成并联电路的子电阻组构成第四电阻1138，或者设计既存在串联的子电阻也存在并联的子电阻的第四电阻1138。此外，图11中以第二MOS管M2为NMOS管为示例，则单端模式下，调节信号SeEnN为低电平，第二MOS管M2为断开状态，差分模式下，调节信号SeEnN为高电 平，第二MOS管M2导通；在实际应用中，第二MOS管M2也可以为PMOS管，则单端模式下，调节信号SeEnN为高电平，第二MOS管M2为断开状态，差分模式下，调节信号SeEnN为低电平，第二MOS管M2导通。
继续参考图11，在一些实施例中，第一电阻1133可以包括：相串联的第一子电阻R1和第二子电阻R2，以及相并联的第三子电阻R3和第四子电阻R4，其中，第一子电阻R1的一端与第二节点net2连接，第一子电阻R1的另一端与第二子电阻R2的一端连接，第二子电阻R2的另一端同时与第三子电阻R3的一端和第四子电阻R4的一端连接，第三子电阻R3的另一端与第四子电阻R4的另一端连接。
第二电阻1135可以包括相串联的第五子电阻R5和第六子电阻R6，以及相并联的第七子电阻R7和第八子电阻R8，其中，第五子电阻R5的一端与第三节点net3连接，第五子电阻R5的另一端与第六子电阻R6的一端连接，第六子电阻R6的另一端同时与第七子电阻R7的一端和第八子电阻R8的一端连接，第七子电阻R7的另一端与第八子电阻R8的另一端连接。
在一些实施例中，参考图3，接收电路还可以包括：选择模块103，接收原始第一信号In1、原始第二信号In2以及原始参考电压信号vref，被配置为，响应于模式选择信号mode select，向输入缓冲器101提供第一输入信号input1以及第二输入信号input2，其中，模式选择信号mode select用于表征单端模式或者差分模式，第一信号In1与原始第一信号In1对应，第二信号In2与原始第二信号In2对应，原始参考电压信号vref与参考电压信号vref对应。
如此，接收电路可以借由选择模块103来控制接收电路接收的信号是原始第一信号In1和原始第二信号In2，从而使得输入缓冲器101接收的信号是第一信号In1和第二信号In2以工作于差分模式，还是控制接收电路接收的信号是原始第一信号In1和原始第二信号In2中的一者以及原始参考电压信号vref，从而使得输入缓冲器101接收的信号是第一信号In1和第二信号In2中的一者以及参考电压信号vref，以工作于单端模式。
在一些实施例中，模式选择信号mode select可以包括：用于表征单端模式的第一模式选择信号(图中未示出)，用于表征差分模式的第二模式选择信号(图中未示出)。譬如，选择模块103接收的模式选择信号mode select为第一模式选择信号时，选择模块103控制接收电路接收的信号是原始第一信号In1和原始第二信号In2，使得输入缓冲器101接收的信号是第一信号In1和第二信号In2；选择模块103接收的模式选择信号mode select为第二模式选择信号时，选择模块103控制接收电路接收的信号是原始第一信号In1和原始第二信号In2中的一者以及原始参考电压信号vref，使得输入缓冲器101接收的信号是第一信号In1和第二信号In2中的一者以及参考电压信号vref。
在另一些实施例中，选择模块103也可以基于模式选择信号mode select的两种状态来控制接收电路工作于差分模式还是单端模式。譬如，在选择模块103接收的模式选择信号mode select为高电平时，控制选择模块103接收的信号是原始第一信号In1和原始第二信号In2，使得输入缓冲器101接收的信号是第一信号In1和第二信号In2；在选择模块103接收的模式选择信号mode select为低电平时，控制选择模块103接收的信号是原始第一信号In1和原始第二信号In2中的一者以及原始参考电压信号vref，使得输入缓冲器101接收的信号是第一信号In1和第二信号In2中的一者以及参考电压信号vref。
在一些实施例中，参考图4，选择模块103可以包括：第一选择单元123以及第二选择单元133，第一选择单元123与第二选择单元133中的一者接收原始第一信号In1以及原始参考电压信号vref，另一者接收原始第二信号In2以及原始参考电压信号vref；在单端模式下，第一选择单元123与第二选择单元133中的一者响应于模式选择信号mode select输出第一信号In1或者第二信号In2，另一者响应于模式选择信号mode select输出参考电压信号vref；在差分模式下，第一选择单元123与第二选择单元133中的一者响应于 模式选择信号mode select输出第一信号In1，另一者响应于模式选择信号mode select输出第二信号In2。
在一个例子中，继续参考图4，第一选择单元123接收原始第一信号In1以及原始参考电压信号vref，第二选择单元133接收原始第二信号In2以及原始参考电压信号vref。
在单端模式下，第一选择单元123响应于模式选择信号mode select输出第一信号In1，第二选择单元133中响应于模式选择信号mode select输出参考电压信号vref，或者，第一选择单元123响应于模式选择信号mode select输出参考电压信号vref，第二选择单元133中响应于模式选择信号mode select输出第二信号In2，以实现输入缓冲器101接收的信号是第一信号In1和第二信号In2中的一者以及参考电压信号vref。
在差分模式下，第一选择单元123响应于模式选择信号mode select输出第一信号In1，第二选择单元133响应于模式选择信号mode select输出第二信号In2，以实现输入缓冲器101接收的信号是第一信号In1和第二信号In2。
在一些实施例中，参考图6，转换模块102可以包括：放大单元122，被配置为，对第一输出信号out1_p与第二输出信号out1_n的电压差进行放大；转换单元132，被配置为，对经放大单元122放大后的第一输出信号以及第二输出信号进行电平逻辑转换，并输出第一内部信号out2_p以及第二内部信号out2_n。
需要说明的是，对经放大单元122放大后的第一输出信号以及第二输出信号进行电平逻辑转换指的是：将第二节点net2输出的第一输出信号out1_p和第三节点net3输出的第二输出信号out1_n从模拟电平转换为数字电平，即使得转换模块102输出的第一内部信号out2_p和/或第二内部信号out2_n的高电平状态无限接近于电源电压，第一内部信号out2_p和/或第二内部信号out2_n的低电平状态无限接近于地端电压，以便于后续逻辑电路的处理。
在一些实施例中，继续参考图6，放大单元122还可以被配置为，响应于第一偏置信号Bias1以调整放大单元122的第一工作电流，以使单端模式下的第一工作电流小于差分模式下的第一工作电流。如此，有利于进一步保证接收电路在单端模式下的工作电流小于差分模式下的工作电流，从而有利于降低接收电路整体的功耗。
在一些实施例中，继续参考图6，转换单元132还可以被配置为，响应于第二偏置信号Bias2以调整转换单元132的第二工作电流，以使单端模式下的第二工作电流小于差分模式下的第二工作电流。如此，有利于进一步保证接收电路在单端模式下的工作电流小于差分模式下的工作电流，从而有利于降低接收电路整体的功耗。
需要说明的是，第一偏置信号bias1和第二偏置信号bias2可以是同一偏置信号，有利于降低接收电路的复杂度。
以下以图8所示的接收电路为示例对本公开一实施例提供的接收电路的工作原理进行说明。需要说明的是，前述已对第一控制单元1111、第二控制单元1112、输入模块112以及负载模块113的工作原理进行过简要描述，以下结合图8对接收电路整体的工作原理进行简要描述。
参考图8，单端模式下，使能信号EnN为低电平，第一PMOS管MP1导通，偏置电压信号bias0处于使得第二PMOS管MP2以及第三PMOS管MP3导通的电平值，且通过调节偏置电压信号bias0的电平值大小可以控制第二PMOS管MP2以及第三PMOS管MP3的导通程度；控制信号SeEn为高电平，使得第四PMOS管MP4处于断开状态，第五PMOS管MP5以及第六PMOS管MP6中没有电流通过，即第二控制单元1112不导通。
差分模式下，使能信号EnN为低电平，第一PMOS管MP1导通，偏置电压信号bias0处于使得第二PMOS管MP2以及第三PMOS管MP3导通的电平值，且控制信号SeEn也为低电平，第四PMOS管MP4导通，偏置电压信号bias0也处于使得第五PMOS管MP5以及第六PMOS管MP6导通的电平值，且通过调节偏置电压信号bias0的电平值大小控 制第五PMOS管MP5以及第六PMOS管MP6的导通程度。
上述两种模式下，第一输入信号input1的电平值高于第二输入信号input2的电平值时，会使第三节点net3输出的第二输出信号out1_n电平值高，第二节点net2输出的第一输出信号out1_p电平值低。第一输入信号input1的电平值低于第二输入信号input2的电平值时，会使第三节点net3输出的第二输出信号out1_n电平值低，第二节点net2输出的第一输出信号out1_p电平值高。而且，单端模式下负载模块113的等效电阻值大于在差分模式下负载模块113的等效电阻值，使得单端模式下第二节点net2处的电流和第三节点net3处的电流之差较小的情况下，第二节点net2处的电压和第三节点net3处的电压之差可以较大，即使得单端模式下第二节点net2处和第三节点net3处依然有较大的电压摆幅。
综上所述，设计一个既可以运用于差分模式又可以运用于单端模式的输入缓冲器101，一方面，有利于降低接收电路的复杂度以及降低接收电路的布局面积，另一方面，输入缓冲器101在差分模式和单端模式下通过同一传输路径接收第一输入信号input1和第二输入信号input2，有利于降低接收电路在差分模式和单端模式之间切换时第一输入信号input1和第二输入信号input2受到的干扰，以提高转换模块102输出的第一内部信号out2_p以及第二内部信号out2_n的准确性，再一方面，有利于使得单端模式下接收电路的工作电流小于差分模式下接收电路的工作电流，以降低接收电路在单端模式下的功耗。
本公开另一实施例还提供一种存储器，包括前述的接收电路。如此，存储器可以选择性接收第一信号In1、第二信号In2以及参考电压信号vref以选择性的工作于差分模式或单端模式下。在差分模式下，存储器接收的第一信号In1和第二信号In2可以为互补的两个时钟信号，且第一信号In1和第二信号In2的频率较高，有利于提高存储器的处理速度和工作性能；在单端模式下，存储器仅接收第一信号In1和第二信号In2中的一者，即仅接收一个时钟信号以较低的频率进行工作，有利于节省功耗。此外，存储器接收的第一信号In1和第二信号In2可以在差分模式和单端模式下共享，而且可以通过调整使能信号EnN、偏置电压信号bias0、控制信号SeEn以及负载模块113等，降低存储器在单端模式下的工作电流，以降低存储器整体的功耗。
在一些实施例中，存储器可以为DDR存储器，例如为DDR5存储器。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公 开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的一种接收电路以及存储器中，输入缓冲器可以利用第一信号和第二信号两者以运用在差分模式下，也可以利用参考电压信号以及第一信号和第二信号中的一者以运用在单端模式下，即同一输入缓冲器既可以运用在差分模式中，也可以运用在单端模式中，有利于降低接收电路的复杂度，以及降低接收电路的布局面积。此外，在单端模式下，输入缓冲器仅接收第一信号和第二信号中的一者，另外接收的信号为参考电压信号，可以降低接收电路中的工作电流，从而有利于降低接收电路的功耗。

Claims (17)

  1. 一种接收电路，包括：
    输入缓冲器，被配置为，接收第一输入信号和第二输入信号并比较所述第一输入信号与所述第二输入信号，输出第一输出信号和第二输出信号，其中，在差分模式下所述第一输入信号和所述第二输入信号分别为第一信号和第二信号，在单端模式下所述第一输入信号为所述第一信号与所述第二信号中的一者，所述第二输入信号为参考电压信号，所述第一信号和所述第二信号互补；
    转换模块，被配置为，接收所述第一输出信号以及所述第二输出信号并对所述第一输出信号与所述第二输出信号的电压差进行放大，以输出第一内部信号以及第二内部信号。
  2. 如权利要求1所述的接收电路，其中，还包括：
    选择模块，接收原始第一信号、原始第二信号以及原始参考电压信号，被配置为，
    响应于模式选择信号，向所述输入缓冲器提供所述第一输入信号以及所述第二输入信号，其中，所述模式选择信号用于表征所述单端模式或者所述差分模式，所述第一信号与所述原始第一信号对应，所述第二信号与所述原始第二信号对应，所述原始参考电压信号与所述参考电压信号对应。
  3. 如权利要求2所述的接收电路，其中，所述选择模块包括：
    第一选择单元以及第二选择单元，所述第一选择单元与所述第二选择单元中的一者接收所述原始第一信号以及所述原始参考电压信号，另一者接收所述原始第二信号以及所述原始参考电压信号；
    在所述单端模式下，所述第一选择单元与所述第二选择单元中的一者响应于所述模式选择信号输出所述第一信号或者所述第二信号，另一者响应于所述模式选择信号输出所述参考电压信号；
    在所述差分模式下，所述第一选择单元与所述第二选择单元中的一者响应于所述模式选择信号输出所述第一信号，另一者响应于所述模式选择信号输出所述第二信号。
  4. 如权利要求1所述的接收电路，其中，所述输入缓冲器包括：
    电流控制模块，被配置为，响应于偏置电压信号向第一节点提供电流；
    输入模块以及与所述输入模块连接的负载模块，所述输入模块与所述第一节点连接，所述输入模块经由第二节点和第三节点与所述负载模块连接；
    其中，所述输入模块接收所述第一输入信号以及所述第二输入信号，所述第二节点输出所述第一输出信号，所述第三节点输出所述第二输出信号。
  5. 如权利要求4所述的接收电路，其中，所述电流控制模被配置为，响应于所述偏置电压信号以调整提供给所述第一节点的电流，以使所述单端模式下提供给所述第一节点的电流小于所述差分模式下提供给所述第一节点的电流。
  6. 如权利要求4所述的接收电路，其中，所述电流控制模块包括：
    第一控制单元，与所述第一节点连接，被配置为，响应于所述偏置电压信号导通以向所述第一节点提供第一电流；
    第二控制单元，与所述第一节点连接，被配置为，响应于控制信号以及所述偏置电压 信号导通以向所述第一节点提供第二电流；
    其中，在所述单端模式下所述第一控制单元导通且所述第二控制单元不导通，在所述差分模式下所述第一控制单元以及所述第二控制单元均导通。
  7. 如权利要求6所述的接收电路，其中，所述第一控制单元包括：
    第一PMOS管，所述第一PMOS管的栅极接收使能信号，所述第一PMOS管的源极连接电源电压；
    第二PMOS管以及第三PMOS管，所述第二PMOS管的源极以及所述第三PMOS管的源极均与所述第一PMOS管的漏极连接，所述第二PMOS管的漏极以及所述第三PMOS管的漏极均连接所述第一节点，所述第二PMOS管的栅极以及所述第三PMOS管的栅极均接收所述偏置电压信号。
  8. 如权利要求6所述的接收电路，其中，所述第二控制单元包括：
    第四PMOS管，所述第四PMOS管的栅极接收所述控制信号，所述第四PMOS管的源极连接电源电压；
    第五PMOS管以及第六PMOS管，所述第五PMOS管的源极以及所述第六PMOS管的源极均与所述第四PMOS管的漏极连接，所述第五PMOS管的漏极以及所述第六PMOS管的漏极均连接所述第一节点，所述第五PMOS管的栅极与所述第六PMOS管的栅极均接收所述偏置电压信号。
  9. 如权利要求4所述的接收电路，其中，所述输入模块包括：
    第七PMOS管，所述第七PMOS管的栅极接收所述第一输入信号，所述第七PMOS管的源极连接所述第一节点，所述第七PMOS管的漏极连接所述第二节点；
    第八PMOS管，所述第八PMOS管的栅极接收所述第二输入信号，所述第八PMOS管的源极连接所述第一节点，所述第八PMOS管的漏极连接所述第三节点。
  10. 如权利要求4所述的接收电路，其中，所述负载模块包括：
    第一负载单元，连接在所述第二节点与地端之间，被配置为，在所述单端模式下所述第一负载单元的等效电阻值大于在所述差分模式下所述第一负载单元的等效电阻值；
    第二负载单元，连接在所述第三节点与地端之间，被配置为，在所述单端模式下所述第二负载单元的等效电阻值大于在所述差分模式下所述第二负载单元的等效电阻值。
  11. 如权利要求10所述的接收电路，其中，所述第一负载单元包括：
    第一电阻，连接在所述第二节点与第四节点之间；
    第一可调负载，连接在所述第四节点与所述地端之间，被配置为，响应于调节信号调整所述第一可调负载的等效电阻值，且所述单端模式下所述第一可调负载的等效电阻值大于所述差分模式下所述第一可调负载的等效电阻值；
    所述第二负载单元包括：
    第二电阻，连接在所述第三节点与第五节点之间；
    第二可调负载，连接在所述第五节点与所述地端之间，被配置为，响应于所述调节信号调整所述第二可调负载的等效电阻值，且在所述单端模式下所述第二可调负载的等效电阻值大于所述差分模式下所述第二可调负载的等效电阻值。
  12. 如权利要求11所述的接收电路，其中，所述第一可调负载包括：
    第三电阻，连接在所述第四节点与地端之间；
    第一MOS管，所述第一MOS管的第一端连接所述第四节点，所述第一MOS管的第二端连接所述地端，所述第一MOS管的控制端接收所述调节信号，其中，在所述单端模式下，所述第一MOS管响应于所述调节信号截止，在所述差分模式下，所述第一MOS管响应于所述调节信号导通。
  13. 如权利要求11所述的接收电路，其中，所述第二可调负载包括：
    第四电阻，连接在所述第五节点与所述地端之间；
    第二MOS管，所述第二MOS管的第一端连接所述第五节点，所述第二MOS管的第二端连接所述地端，所述第二MOS管的控制端接收所述调节信号，其中，在所述单端模式下，所述第二MOS管响应于所述调节信号截止，在所述差分模式下，所述第二MOS管响应于所述调节信号导通。
  14. 如权利要求1所述的接收电路，其中，所述转换模块包括：
    放大单元，被配置为，对所述第一输出信号与所述第二输出信号的电压差进行放大；
    转换单元，被配置为，对经所述放大单元放大后的所述第一输出信号以及所述第二输出信号进行电平逻辑转换，并输出所述第一内部信号以及所述第二内部信号。
  15. 如权利要求14所述的接收电路，其中，所述放大单元还被配置为，响应于第一偏置信号以调整所述放大单元的第一工作电流，以使所述单端模式下的所述第一工作电流小于所述差分模式下的第一工作电流。
  16. 如权利要求14所述的接收电路，其中，所述转换单元还被配置为，响应于第二偏置信号以调整所述转换单元的第二工作电流，以使所述单端模式下的所述第二工作电流小于所述差分模式下的第二工作电流。
  17. 一种存储器，包括如权利要求1-16任一项所述的接收电路。
PCT/CN2022/111185 2022-06-01 2022-08-09 接收电路以及存储器 WO2023231177A1 (zh)

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