WO2023230977A1 - 布线基板及其制造方法、发光基板及显示装置 - Google Patents

布线基板及其制造方法、发光基板及显示装置 Download PDF

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Publication number
WO2023230977A1
WO2023230977A1 PCT/CN2022/096785 CN2022096785W WO2023230977A1 WO 2023230977 A1 WO2023230977 A1 WO 2023230977A1 CN 2022096785 W CN2022096785 W CN 2022096785W WO 2023230977 A1 WO2023230977 A1 WO 2023230977A1
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WIPO (PCT)
Prior art keywords
substrate
electrode
conductive layer
orthographic projection
insulating layer
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PCT/CN2022/096785
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English (en)
French (fr)
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WO2023230977A9 (zh
Inventor
王杰
金枝
吴信涛
许邹明
刘欢
丁雷鸣
韩停伟
罗宁雨
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001601.7A priority Critical patent/CN117730637A/zh
Priority to PCT/CN2022/096785 priority patent/WO2023230977A1/zh
Publication of WO2023230977A1 publication Critical patent/WO2023230977A1/zh
Publication of WO2023230977A9 publication Critical patent/WO2023230977A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a wiring substrate, a light-emitting substrate and a display device including the wiring substrate, and a method of manufacturing the wiring substrate.
  • Display devices are generally divided into two categories: liquid crystal display devices and organic light-emitting diode display devices.
  • Liquid crystal display devices are widely used due to their advantages such as thinness, lightness, good shock resistance, wide viewing angle, and high contrast.
  • a liquid crystal display device generally includes a display panel and a backlight source, and the backlight source is usually arranged on the non-display side of the display panel to provide a light source for the display operation of the display panel.
  • Characteristics such as contrast, brightness uniformity, and stability of a liquid crystal display device are related to the structure and performance of the backlight.
  • sub-millimeter light-emitting diodes Mini-LEDs
  • Mini-LEDs sub-millimeter light-emitting diodes
  • a wiring substrate which includes: a substrate including a functional area and a bonding area; a first conductive layer located on the substrate and at least within the functional area; a second conductive layer located on a side of the first conductive layer away from the substrate and at least within the functional area, the second conductive layer being electrically connected to the first conductive layer; and a first insulating layer , located on the side of the second conductive layer away from the substrate and including a main body part and an opening.
  • At least one of the first conductive layer and the second conductive layer includes a plurality of electrodes located in the binding region and extending along a first direction, and each of the plurality of electrodes is included in the first conductive layer. Adjacent to the first end of the functional area in one direction, the orthographic projection of the main body of the first insulating layer on the substrate is at least partially the same as the orthographic projection of the first end of each electrode on the substrate. overlapping.
  • the wiring substrate further includes a second insulating layer located between the first conductive layer and the second conductive layer, and the second conductive layer passes through a pass in the second insulating layer. The hole is in contact with the first conductive layer.
  • the second conductive layer includes a first part and a second part, the first part is located in the functional area, the second part is located in the binding area, and the second part
  • the portion includes a plurality of first electrodes extending along the first direction, and each of the plurality of first electrodes includes the first end.
  • the second conductive layer includes a first surface facing away from the substrate, and a distance from a portion of the first surface located at the first portion to the substrate is greater than a distance from the first surface located at the first portion.
  • the distance from a part of the second part to the substrate, the orthographic projection of the opening of the first insulating layer on the substrate is at least partially equal to the orthogonal projection of the second part on the substrate overlap.
  • the opening of the first insulating layer exposes a remainder of each first electrode except the first end.
  • the orthographic projection of the opening of the first insulating layer on the substrate does not overlap with the orthographic projection of the second insulating layer on the substrate.
  • the first conductive layer is located only within the functional area, and the orthographic projection of the first conductive layer on the substrate is the same as the first portion of the second conductive layer on the substrate.
  • the orthographic projections on the base partially overlap.
  • the first conductive layer in the functional area, includes a second surface facing the second conductive layer and a side surface connected to the second surface and facing the binding area, so The second conductive layer is in direct contact with the side surface of the first conductive layer.
  • the first conductive layer includes a third portion located in the binding area, the third portion includes a plurality of second electrodes extending along the first direction, and the plurality of third electrodes extend along the first direction.
  • An electrode corresponds one-to-one to the plurality of second electrodes, and an orthographic projection of each of the plurality of first electrodes on the substrate is consistent with a corresponding one of the plurality of second electrodes on the substrate. Orthographic projections on the substrate at least partially overlap.
  • Each first electrode and a second electrode corresponding to the first electrode are electrically connected and constitute an electrode, and the electrically connected first electrode and the second electrode each include the first end.
  • the orthographic projection of the first end of the first electrode and the second electrode on the substrate falls on the orthographic projection of the main body of the first insulating layer on the substrate. Inside.
  • the opening of the first insulating layer exposes a remainder of each first electrode except the first end.
  • each second electrode includes a plurality of tooth-like structures extending along the first direction and arranged along a second direction, wherein the second direction intersects the first direction.
  • each of the plurality of tooth-shaped structures includes a second surface facing the second conductive layer and a side surface connected with the second surface, the first electrode and the tooth-shaped structure.
  • the side surfaces of the structure are in direct contact.
  • the first insulating layer in the binding area, includes a plurality of openings, the plurality of openings correspond to the plurality of electrodes, and each of the plurality of openings is in The orthographic projection on the substrate falls within the orthographic projection of the first electrode of an electrode corresponding to the opening on the substrate.
  • the electrode also includes a second end opposite to the first end, and an orthographic projection of the second end of the electrode on the substrate falls on the main body of the first insulating layer on the substrate. within the orthographic projection.
  • the first insulating layer in the binding area, includes a plurality of openings, the plurality of openings correspond to the plurality of electrodes, and each of the plurality of openings is in The orthographic projection on the substrate and the orthographic projection on the substrate of an electrode corresponding to the opening partially overlap.
  • the electrode further includes a second end opposite to the first end, and a portion of the second end is exposed by an opening corresponding to the electrode.
  • the orthographic projection of the second insulating layer on the substrate does not overlap with the orthographic projection of the first electrode and the second electrode on the substrate, and the third electrode of each electrode One electrode is in direct contact with the second electrode.
  • the first insulating layer in the binding area, includes a plurality of openings, the plurality of openings correspond to the plurality of electrodes, and each of the plurality of openings is in The orthographic projection on the substrate falls within the orthographic projection of the first electrode of an electrode corresponding to the opening on the substrate, and the electrode also includes a second end opposite to the first end, so An orthographic projection of the second end of the electrode on the substrate falls within an orthographic projection of the main body of the first insulating layer on the substrate.
  • the orthographic projection of the first electrode on the substrate falls within the orthographic projection of the second electrode on the substrate.
  • the main body portion of the first insulating layer includes a plurality of sub-insulating portions extending along the first direction and spaced apart from each other in a second direction crossing the first direction, the plurality of sub-insulating portions
  • the orthographic projections of two adjacent sub-insulating portions in the portion on the substrate partially overlap with the orthographic projection of one electrode on the substrate, and the orthogonal projections of the first electrode and the second electrode
  • the orthographic projection of the first end on the substrate partially overlaps the orthographic projection of the two adjacent sub-insulating portions on the substrate.
  • the second conductive layer is disposed only in the functional area
  • the first conductive layer includes a third portion disposed in the binding area
  • the third portion includes a A plurality of second electrodes extending in a first direction, each of the plurality of second electrodes including the first end.
  • the second insulating layer includes a plurality of via holes, the plurality of via holes correspond to the plurality of second electrodes, and each of the plurality of via holes is in the The orthographic projection on the substrate falls within the orthographic projection of a second electrode corresponding to the via hole on the substrate.
  • the main body portion of the first insulating layer includes a plurality of sub-insulating portions extending along the first direction and spaced apart from each other in a second direction crossing the first direction, the plurality of sub-insulating portions
  • the orthographic projections of two adjacent sub-insulating portions in the portion on the substrate partially overlap with the orthographic projection of one second electrode on the substrate, and the first end of the second electrode is at The orthographic projection on the substrate partially overlaps the orthographic projection of the two adjacent sub-insulating portions on the substrate.
  • a light-emitting substrate which includes the wiring substrate described in any of the previous embodiments and a plurality of light-emitting elements arranged in the functional area and the binding area. circuit board inside.
  • a display device includes the wiring substrate described in any of the previous embodiments or the light-emitting substrate described in any of the previous embodiments.
  • a method of manufacturing a wiring substrate including: providing a substrate, the substrate including a functional area and a bonding area; applying a first conductive film on the substrate, passing through a first A mask is used to pattern the first conductive film to form a first conductive layer, the first conductive layer is located at least in the functional area; a third conductive layer is applied to a side of the first conductive layer away from the substrate.
  • the second conductive film is patterned through a second mask to form a second conductive layer, the second conductive layer is at least located in the functional area and is electrically connected to the first conductive layer; and
  • a first insulating film is applied on a side of the second conductive layer away from the substrate, and the first insulating film is patterned through a third mask to form a first insulating layer including a main body portion and an opening,
  • At least one of the first conductive layer and the second conductive layer includes a plurality of electrodes located in the binding region and extending along a first direction, and each of the plurality of electrodes is included in the first direction.
  • an orthographic projection of the main body portion of the first insulating layer on the substrate Upwardly adjacent the first end of the functional region, an orthographic projection of the main body portion of the first insulating layer on the substrate at least partially intersects an orthographic projection of the first end of each electrode on the substrate.
  • the step of forming the first conductive layer on the substrate further includes: applying a second insulating film on a side of the first conductive layer away from the substrate, through a fourth mask Patterning the second insulating film to form a second insulating layer; and forming the second conductive layer on a side of the second insulating layer away from the substrate.
  • Figure 1 shows a schematic structural diagram of a wiring substrate in the related art
  • FIG. 2A shows a schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • Figure 2B shows a schematic cross-sectional view taken along line AA' of Figure 2A;
  • Figure 2C shows a simplified schematic diagram of region II of Figure 2A
  • 3A shows an enlarged picture of a partial structure of a wiring substrate in the related art
  • 3B shows an enlarged picture of a partial structure of a wiring substrate in the related art
  • Figure 4 shows a schematic plan view of a wiring substrate in a functional area according to an embodiment of the present disclosure
  • 5A shows a schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • Figure 5B shows a schematic cross-sectional view taken along line BB' of Figure 5A;
  • FIG. 6A shows a schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • Figure 6B shows a schematic cross-sectional view taken along line CC' of Figure 6A;
  • FIG. 7A shows a schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • Figure 7B shows a schematic cross-sectional view taken along line DD' of Figure 7A;
  • FIG. 8A shows a schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • Figure 8B shows a schematic cross-sectional view taken along line EE' of Figure 8A;
  • FIG. 9A shows a schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • Figure 9B shows a schematic cross-sectional view taken along line FF' of Figure 9A;
  • FIG. 10A shows a schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • Figure 10B shows a schematic cross-sectional view taken along line GG' of Figure 10A;
  • 11A shows a schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • Figure 11B shows a schematic cross-sectional view taken along line HH' of Figure 11A;
  • FIG. 12 shows a block diagram of a light emitting substrate according to an embodiment of the present disclosure
  • FIG. 13 shows a block diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 14 shows a flowchart of a method of manufacturing a wiring substrate according to an embodiment of the present disclosure.
  • FIG. 1 shows a wiring substrate 10 in the related art.
  • the wiring substrate 10 includes a substrate 11, a first conductive layer 12, a first sub-insulating layer 141, a second sub-insulating layer 142, a second conductive layer 13, Insulating layer 15 and other structures.
  • anti-oxidation treatment is required, for example, chemical nickel-gold treatment is used to grow the desired nickel-gold layer 17 on the surface, thereby enhancing the second conductive layer. 13 for oxidation resistance and/or connection reliability.
  • the wiring substrate 10 is first pickled, and then the wiring substrate 10 is placed in an activation solution containing Pd 2+ .
  • the metal in the exposed surface area of the second conductive layer 13 undergoes a substitution reaction with Pd 2+ in the activation solution to generate Cu 2+ and Pd (palladium), where Pd is attached to the surface of the second conductive layer 13 facing away from the substrate 11 to form a palladium layer.
  • the wiring substrate 10 is then placed in a solution whose main components are nickel sulfate, sodium hypophosphite (a reducing agent that reduces nickel ions to metallic nickel), and a complexing agent.
  • a layer of phosphorus-nickel alloy layer will be formed on the surface of the pad.
  • the phosphorus-nickel alloy layer will still be oxidized, it is difficult and unreliable to weld the solder to the oxidized phosphorus-nickel alloy layer. Therefore, it is finally necessary to immerse the wiring substrate 10 in a solution containing gold ions to form an immersion gold layer on the surface of the phosphorus-nickel alloy layer.
  • the gold particles in the immersion gold layer can fill the gaps in the nickel-gold layer to reduce the oxidation probability of the phosphorus-nickel alloy layer, thereby weakening the oxidation degree of the exposed area of the second conductive layer 13 .
  • the surface of the exposed area of the second conductive layer 13 has a nickel-gold layer 17 (including the above-mentioned phosphorus-nickel alloy layer and immersion gold layer).
  • the surface of the first conductive layer 12 can be covered to prevent Oxidation occurs.
  • the insulating layer 15 needs to be etched to form a via hole 16 to expose the second conductive layer 13, and the second conductive layer 13 needs to be etched.
  • the surface remote from the substrate 11 is also etched to a certain extent.
  • the etching time will be increased compared to only etching the insulating layer 15 .
  • the thickness of the first sub-insulating layer 141 and the second sub-insulating layer 142 is usually relatively thin.
  • the etching time is increased, the first sub-insulating layer 141 and the second sub-insulating layer 142 will inevitably be over-etched. , thus generating unnecessary via holes 19 in the first sub-insulating layer 141 and the second sub-insulating layer 142 .
  • the via hole 16 in the insulating layer 15 and the undesired via hole 19 in the first sub-insulating layer 141 and the second sub-insulating layer 142 cause the surface of the first conductive layer 12 away from the substrate 11 to be partially exposed, and the first conductive layer 12 is partially exposed.
  • Layer 12 will have abnormal growth of nickel gold layer 18 where the surface is exposed.
  • the abnormally grown nickel-gold layer 18 may cause problems such as short circuits between film layers and damage to the surface flatness of the insulating layer 15 , thereby significantly affecting the reliability of the wiring substrate 10 .
  • Some embodiments of the present disclosure provide an improved wiring substrate that can at least solve the problem of abnormal growth of the nickel-gold layer in the bonding area.
  • FIG. 2A shows a schematic plan view of a partial region of the wiring substrate 100
  • FIG. 2B shows a cross-sectional view taken along line AA' of FIG. 2A
  • the wiring substrate 100 includes: a substrate 101 including a functional area E and a bonding area B; a first conductive layer 102 located on the substrate 101 and at least within the functional area E; The conductive layer 103 is located on the side of the first conductive layer 102 away from the substrate 101 and is located at least in the functional area E.
  • the second conductive layer 103 is electrically connected to the first conductive layer 102; and the first insulating layer 105 is located on the second conductive layer 102.
  • the layer 103 is on a side away from the substrate 101 and includes a body portion 1051 and an opening 1052 .
  • a plurality of electrodes 150 are arranged in the binding area B.
  • the plurality of electrodes 150 respectively extend along the first direction D1 and are spaced apart along the second direction D2 intersecting the first direction D1.
  • the first conductive layer 102 and the second conductive layer 103 At least one of the plurality of electrodes 150 includes a first end P adjacent to the functional region E in the first direction D1, and the main body portion 1051 of the first insulating layer 105 is on the substrate 101
  • the orthographic projection of at least partially overlaps the orthographic projection of the first end P of each electrode 150 on the substrate 101 .
  • the exposed area of the surface of the electrode 150 serves as the binding electrode 107 .
  • first conductive layer 102 the second conductive layer 103 and the first insulating layer 105 is not only applicable to the wiring substrate 100, but also to each wiring substrate described in other embodiments of the present disclosure. This will be described in detail later.
  • main body portion 1051 of the first insulating layer 105" refers to the physical part of the first insulating layer 105, which is made of an appropriate insulating material; the term “the main body portion 1051 of the first insulating layer 105"
  • the opening 1052′′ refers to the hollow via hole of the first insulating layer 105, and the first insulating layer 105 does not have any solid material at the opening 1052.
  • the main body portion 1051 and the opening 1052 constitute the first insulating layer 105 .
  • the term "functional area” refers to the area on the substrate 101 used to arrange functional components (such as light-emitting elements), and the term “binding area” refers to the area on the substrate 101 used to arrange the electrodes 150.
  • the binding area For coupling with the circuit board, if the circuit board has a gold finger structure, the width of each of the plurality of electrodes 150 in the binding area in the second direction is substantially the same, for example, slightly larger than the width of the gold finger structure in the second direction. Width in direction.
  • the inventor of the present application found that abnormal growth of nickel-gold is prone to occur at the first end P of the electrode 150 in the binding region B. Therefore, in the embodiment of the present application, by making the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the substrate 101 and the orthographic projection of the first end P of each electrode 150 on the substrate 101 at least partially. By overlapping, the main body portion 1051 of the first insulating layer 105 can cover at least a portion of the first end P of the electrode 150 .
  • the first end P of the electrode 150 will not be caused.
  • the surface of the terminal P is exposed, so that abnormal growth of nickel-gold at the first terminal P of the electrode 150 can be reduced or even avoided.
  • the first conductive layer 102 of the wiring substrate 100 is only disposed in the functional area E but not in the bonding area B, and the second conductive layer 103 includes a third conductive layer 103 disposed in the functional area E.
  • the second portion 1032 of the second conductive layer 103 includes a plurality of first electrodes 1033 extending along the first direction D1, and the exposed area on the surface of each first electrode 1033 is used as the binding electrode 107.
  • the first electrode 1033 includes a first terminal P.
  • the orthographic projection of the first conductive layer 102 on the substrate 101 does not overlap with the orthographic projection of the first electrode 1033 on the substrate 101 .
  • the length L1 of the first end P of the first electrode 1033 along the first direction D1 is 30-60 microns, and the length L2 of the first electrode 1033 along the first direction D1 is 1050-1100 microns. In some embodiments, the ratio of length L1 to length L2 is between 2% and 6%.
  • FIG. 2C shows a simplified schematic diagram of region II in FIG. 2A , which only shows the relative positional relationship between the first conductive layer 102 and the second conductive layer 103 .
  • the first conductive layer 102 includes a driving voltage signal line VLED, a common voltage signal line 111 (shown in FIG. 4 ), and some other signal lines.
  • the driving voltage signal line VLED and/or the common voltage signal line 111 extends generally along the first direction D1, and one end of the driving voltage signal line VLED and/or the common voltage signal line 111 extends to the functional area E of the wiring substrate 100 away from the bonding area B At any position, the other end is connected to a plurality of first electrodes 1033 extending from the binding area B toward the functional area E.
  • the first conductive layer 102 shown in FIG. 2C may represent a driving voltage signal line VLED or a common voltage signal line 111, which is in direct contact with the first portion 1031 of the second conductive layer 103 in the functional area E. Due to the driving voltage signal
  • the line width of line VLED or a common voltage signal line 111 is much larger than the line width of one first electrode 1033, so the other end of the driving voltage signal line VLED or a common voltage signal line 111 can correspond to multiple first electrodes 1033 and electrically connect.
  • the inventor of the present application found that in the related technology, in the bonding area B, because the surface of the bonding electrode 107 is exposed, and the position where the signal line in the first conductive layer 102 is connected to the electrode is between the bonding electrode 107 With step differences, abnormal growth of nickel and gold is prone to occur.
  • the first conductive layer 102 is only arranged in the functional area E and not in the bonding area B, thus avoiding the driving voltage signal line VLED and the common voltage formed by the first conductive layer 102
  • the signal line 111 has abnormal growth of nickel gold in the binding area B. It can be clearly seen from FIGS.
  • the orthographic projection of the first conductive layer 102 on the substrate 101 partially overlaps the orthographic projection of the first portion 1031 of the second conductive layer 103 on the substrate 101; and the The orthographic projection of a conductive layer 102 on the substrate 101 does not overlap with the orthographic projection of the first electrode 1033 of the second portion 1032 of the second conductive layer 103 on the substrate 101 .
  • the wiring substrate 100 may further include a second insulating layer 104 between the first conductive layer 102 and the second conductive layer 103 , and the first portion 1031 of the second conductive layer 103 passes through the second insulating layer 104
  • the via hole 1043 is electrically connected to the first conductive layer 102.
  • the second insulating layer 104 is only arranged in the functional area E and not in the binding area B. Therefore, the orthographic projection of the second insulating layer 104 on the substrate 101 is the same as the orthogonal projection of the first electrode 1033 on the substrate 101 . Projections do not overlap.
  • the main body portion 1051 of the first insulating layer 105 is on the substrate 101.
  • the orthographic projection does not overlap with the orthographic projection of the main body portion 1044 of the second insulating layer 104 on the substrate 101. This can reduce the distance between the main body portion 1051 of the first insulating layer 105 and the main body portion 1044 of the second insulating layer 104 in the binding area B. Therefore, the peeling-off phenomenon of the first insulating layer 105 and the second insulating layer 104 in the binding area B can be reduced or even avoided.
  • the second conductive layer 103 includes a first portion 1031 located in the functional area E and a second portion 1032 located in the binding area B.
  • the second conductive layer 103 includes a first surface facing away from the substrate 101, and the first surface is step-shaped. Specifically, the part of the first surface located in the first part 1031 may be recorded as surface S11, the part of the first surface located in the second part 1032 may be recorded as surface S13, and the part of the first surface located between surface S11 and surface S13 And the part used to connect the surface S11 and the surface S13 can be recorded as the surface S12.
  • the surface S12 is an inclined surface, so that the distance d1 from the portion S11 of the first surface located at the first portion 1031 to the substrate 101 is greater than the distance d2 from the portion S13 of the first surface located at the second portion 1032 to the substrate 101 .
  • the main body portion 1051 of the first insulating layer 105 is attached to at least the surface S11 , the surface S12 and the portion of the surface S13 of each first electrode 1033 located within the first end P, so as to protect the first portion 1031 of the second conductive layer 103 and The first end P of the first electrode 1033 plays a better covering and protection role.
  • the orthographic projection of the opening 1052 of the first insulating layer 105 on the substrate 101 at least partially overlaps the orthographic projection of the second portion 1032 on the substrate 101 .
  • the orthographic projection of the opening 1052 of the first insulating layer 105 on the substrate 101 does not overlap with the orthographic projection of the second insulating layer 104 on the substrate 101 .
  • the flexible printed circuit board may be bound to an area of the first electrode 1033 other than the first end P, that is, the flexible printed circuit board is bound and connected to the binding electrode.
  • the first conductive layer 102 includes a second surface S21 facing the second conductive layer 103 and a side surface S22 connected to the second surface S21 and facing the binding area B, and the second insulating layer 104 covers the first conductive layer 103 .
  • a part of the second surface S21 of the layer 102 does not cover the side surface S22 of the first conductive layer 102.
  • the second conductive layer 103 is in direct contact with the side surface S22 of the first conductive layer 102 through the via 1043 in the second insulating layer 104.
  • the second insulating layer 104 may be a single film layer or a stacked layer including multiple film layers.
  • the second insulation layer 104 includes a first sub-insulation layer 1041 and a second sub-insulation layer 1042.
  • the thickness of the second insulating layer 104 is generally thin compared to the thickness of the first conductive layer 102 (in one example, the thickness of the first conductive layer 102 is in a direction perpendicular to the substrate 101
  • the thickness of the first sub-insulating layer 1041 in the direction perpendicular to the substrate 101 is 0.24 ⁇ m
  • the thickness of the second sub-insulating layer 1042 in the direction perpendicular to the substrate 101 is 0.15 ⁇ m).
  • the second insulating layer 104 needs to cover the side surface S22 of the first conductive layer 102. Since there is a large step difference between the second surface S21 of the first conductive layer 102 and the surface of the underlying film layer, the second insulating layer 104 needs to cover the side surface S22 of the first conductive layer 102.
  • the layer 104 is prone to breakage at the position where it connects from the second surface S21 to the side surface S22 of the first conductive layer 102, resulting in the second insulating layer 104 being unable to completely cover and protect the first conductive layer 102.
  • the subsequently formed second conductive layer 103 cannot achieve good contact with the underlying film layer at the break position, thereby causing the second conductive layer 103 to fall off. Furthermore, after the second insulating layer 104 is broken, a part of the surface of the first conductive layer 102 will be exposed, thereby oxidizing to generate irregularly shaped metal oxides, reducing the film coherence of the first conductive layer 102 properties and flatness. If the second conductive layer 103 is in direct contact with an area with irregularly shaped oxides in the first conductive layer 102, it will easily cause the second conductive layer 103 to bulge there, thereby causing the second conductive layer 103 to bulge.
  • FIG. 3A shows that in the related art, the second conductive layer 103 and the second insulating layer (PVX1-2) are peeled off at the side surface of the first conductive layer (Cu1), and the second conductive layer (Cu2) and the first conductive layer are separated from each other.
  • FIG. 3B shows that in the related art, the first sub-insulating layer 141 or the second sub-insulating layer 142 is cracked due to the step difference in the first conductive layer 12 , which in turn causes the first conductive layer 12 to be oxidized at the corresponding position. Irregular-shaped (tip) oxides appear, eventually causing the second conductive layer 13 to bulge.
  • the second insulating layer 104 does not cover the side surface S22 of the first conductive layer 102, but the second conductive layer 103 communicates with the second conductive layer 103 via the via 1043 in the second insulating layer 104.
  • the side surface S22 of a conductive layer 102 is in direct contact.
  • the second insulating layer 104 will not break, so that the first electrode 1033 of the second conductive layer 103 will not peel off from the second insulating layer 104 due to contact with the broken second insulating layer 104; further, Since the second insulating layer 104 will not break, the side surface S22 of the first conductive layer 102 will not be oxidized due to surface exposure and have an irregular surface topography, which will not cause the second conductive layer 103 to bulge, thereby causing the second conductive layer 103 to bulge. This will not cause the problem of film peeling between the first electrode 1033 of the second conductive layer 103 and the first conductive layer 102 .
  • the first conductive layer 102 may be a stack of MoNb/Cu/MoNb. In alternative embodiments, first conductive layer 102 may be a stack of Mo/Cu/Mo. In some embodiments, the second conductive layer 103 may be of overlays. In alternative embodiments, second conductive layer 103 may be of overlays. The thickness of the first conductive layer 102 is generally greater than the thickness of the second conductive layer 103 .
  • the wiring substrate 100 may further include a buffer layer 106 between the substrate 101 and the first conductive layer 102 .
  • the buffer layer 106 has a planarizing effect and can improve the adhesion between the first conductive layer 102 and the substrate 101 .
  • FIG. 4 shows the arrangement of the wiring substrate 100 in the functional area E as an example. Way.
  • the functional area of the wiring substrate 100 is provided with a pad group to be bound and connected to tens of thousands of electronic components.
  • the wiring substrate 100 includes in the functional area E: a first pad group 102, located on the substrate 101,
  • the first pad group 102 includes a power supply pad Pwr and an output pad Out.
  • the first pad group 102 is coupled to the micro driver chip 002;
  • the power signal line 103 is located on the substrate with the first pad group 102.
  • the power signal line 103 is coupled to the power supply pad Pwr;
  • the second pad group 104 is located on the same side of the substrate 101 as the first pad group 102.
  • each second pad group 104 is coupled to an electronic component 003.
  • the area of the second conductive layer 103 located in the functional area E and with an exposed surface constitutes the above-mentioned first pad group 102 and second pad group 104 .
  • the first insulating layer 105 includes an opening 1052 in the functional area E, and the opening 1052 exposes a partial area of the second conductive layer 103 for use as a bonding pad.
  • the first pad group 102 can be coupled with the micro driver chip 002 through a reflow soldering process with the assistance of solder
  • the second pad group 104 can be coupled with the light emitting element 003 through a reflow soldering process with the assistance of solder.
  • the part of the second conductive layer 103 exposed by the opening 1052 in the binding area B is used as a binding electrode (for example, the part of the first electrode 1033 except the first end P).
  • the binding electrode is assisted by the anisotropic conductive glue.
  • the bonding connection is realized with the gold finger structure of the circuit board (such as FPC) through the hot pressing process.
  • the substrate 101 includes a plurality of pad areas P.
  • Each pad area P includes a plurality of cascaded first pad groups 102 and a plurality of cascaded first pad groups 102 respectively coupled to the first pad groups 102 .
  • Second pad group 104 Second pad group 104.
  • a plurality of cascaded first pad groups 102 may be arranged in an array along the first direction D1 and/or the second direction D2, which is not limited here.
  • FIG. 4 illustrates schematically an example in which a plurality of cascaded first pad groups 102 in a pad area P are arranged in a row.
  • a power signal line 103 may be coupled to the power supply pads Pwr of a plurality of first pad groups 102 arranged and cascaded along the first direction D1 in a pad area P, thus reducing the power supply.
  • the winding design of the signal line 103 reduces the resistance of the power signal line 103 and thereby reduces the pulse width modulation signal loss on the power signal line 103 .
  • the wiring substrate 100 may also include a first connection lead 106.
  • a power signal line 103 includes a plurality of sub-segments 103'. Two adjacent sub-segments 103' in the first direction D1 may pass through a first connection lead. 106 are connected to each other to realize that the same power signal line 103 supplies power to the power supply pads Pwr of multiple first pad groups 102 arranged and cascaded along the first direction D1 in the same pad area P.
  • the first connection lead 106 and the sub-segment 103' are an integral structure.
  • the first pad group 102 also includes an address pad Di and a ground pad Gnd.
  • the address pad Di and the power supply pad Pwr belonging to the same first pad group 102 are spaced apart in the second direction D2 , and are spaced apart from the output pad Out in the first direction D1, the ground pad Gnd and the power supply pad Pwr are spaced apart from the first direction D1, and are spaced apart from the output pad Out in the second direction D2.
  • the output pad Out is located at the upper left corner of the first pad group 102
  • the address pad Di is located at the lower left corner of the first pad group 102
  • the ground pad Gnd is located at the upper right corner of the first pad group 102.
  • Electrical pad Pwr is located at the lower right corner of the first pad group 102 .
  • Each first pad group 102 may be coupled to one micro driver chip 002
  • each second pad group 104 may be coupled to a plurality of electronic components 003 .
  • the address pad Di can receive an address signal for strobing the micro driver chip 002 of the corresponding address.
  • the power supply pad Pwr can provide the first operating voltage and communication data to the micro driver chip 002, and the communication data can be used to control the luminance of the corresponding light-emitting element.
  • the output pad Out can output a relay signal and a drive signal respectively in different time periods.
  • the relay signal is an address signal provided to the address pad Di in the first pad group 102 of the next level.
  • the drive signal is a drive current.
  • the ground pad Gnd receives the common voltage signal.
  • the power supply pad Pwr, the output pad Out, the ground pad Gnd, and the address pad Di are arranged in the same manner, so that the same pad area P is mutually arranged. There are simple wiring paths between the connected first pad groups 102 to avoid more windings.
  • the wiring substrate 100 may further include an address signal line 108, and one address signal line 108 may be coupled to the address pad Di of the first-level first pad group 102 in one pad area P, so that in In each pad area P, the address signal provided by the address signal line 107 is received through the address pad Di of the first-level first pad group 102 .
  • the wiring substrate 100 may further include a cascade line 109 configured to connect the output pad Out of the n-th level first pad group 102 belonging to the same pad area P and the (n-th +1)
  • the address pad Di, n of the first pad group 102 of the stage is a positive integer, so as to provide the relay signal output by the output pad Out of the n-th stage first pad group 102 to the n-th stage through the cascade line 109.
  • the address pad Di of the first pad group 102 of the (n+1) level may further include a feedback signal line 110 coupled to the output pad Out of the last-stage first pad group 102 in a pad area
  • the panel P forms a loop for transmitting address signals.
  • the wiring substrate 100 may further include a common voltage signal line 111 , and a common voltage signal line 111 is coupled to the ground pads Gnd of all the first pad groups 102 in one pad area P.
  • the wiring substrate 100 may further include a driving voltage signal line VLED, which is used to couple with the electronic component 003 .
  • the first conductive layer 102 is configured to implement the above-mentioned power signal line 103, first connection lead 106, second connection lead 107, address signal line 108, and cascade line. 109.
  • these signal lines are formed by patterning the first conductive layer 102 through one patterning process using the same mask.
  • the first conductive layer 102 is only configured to implement the power signal line 103, the address signal line 108, the feedback signal line 110, and the common voltage signal line. 111 and the driving voltage signal line VLED, and the second conductive layer 103 is configured to realize the first connection lead 106, the second connection lead 107, the cascade line 109, and connect the first pad group and the second pad group and connect the second pad group. The connection line between the second pad group and the second pad group.
  • Fig. 5A shows a schematic plan view of a partial structure of the wiring substrate 200 in the bonding area B and the functional area E
  • Fig. 5B shows a cross-sectional view taken along line BB' of Fig. 5A.
  • the similarities between the wiring substrate 200 and the wiring substrate 100 will not be described, and only the differences between the wiring substrate 200 and the wiring substrate 100 will be described below.
  • the wiring substrate 200 shown in FIG. 5A includes a substrate 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, a second insulating layer 104 and other structures. Different from the wiring substrate 100, the first conductive layer 102 of the wiring substrate 200 is arranged in the functional area E and the bonding area B.
  • the first conductive layer 102 includes a third portion 1022 located in the bonding area B.
  • the third portion 1022 includes A plurality of second electrodes 1023 extending along the first direction D1 and spaced apart along the second direction D2.
  • the second conductive layer 103 includes a first portion 1031 located in the functional area E and a second portion 1032 located in the binding area B.
  • the second portion 1032 includes a plurality of first electrodes 1033 extending along the first direction D1.
  • the plurality of first electrodes 1033 correspond to the plurality of second electrodes 1023 one-to-one, and the orthographic projection of each first electrode 1033 on the substrate 101 falls within the orthographic projection of the corresponding second electrode 1023 on the substrate 101.
  • each first electrode 1033 is electrically connected to a second electrode 1023 corresponding to the first electrode 1033 to form an electrode, and the exposed surface area of the electrode forms the binding electrode 107.
  • Both the first electrode 1033 and the second electrode 1023 include a first end P close to the functional region E.
  • the orthographic projection of the first end P of the first electrode 1033 and the second electrode 1023 on the substrate 101 falls within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the substrate 101 .
  • the opening 1052 of the first insulation layer 105 exposes the remaining area of each first electrode 1033 except the first end P.
  • the driving voltage signal line VLED and the common voltage signal line 111 belonging to the first conductive layer 102 and located in the functional area E are bonded and connected to the electrode at the first end P of the electrode.
  • the driving voltage signal line VLED and the common voltage signal line 111 are prone to abnormal growth of nickel-gold due to their exposed surfaces at the first end P.
  • the electrodes include a second electrode 1023 and a first electrode 1033 located on the side of the second electrode 1023 away from the substrate 101.
  • the first end P of the electrode is on the substrate 101.
  • the orthographic projection falls within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the substrate 101.
  • the first electrode 1033 is spaced between the main body portion 1051 of the first insulating layer 105 and the second electrode 1023.
  • the first electrode 1033 (compared to the thickness of the second insulating layer 104) shields and protects the second electrode 1023, so the first end P of the second electrode 1023 will not be etched, thereby preventing the second electrode 1023 from being etched.
  • the surface of the first terminal P of the two electrodes 1023 is exposed.
  • the first end of the second electrode 1023 of each signal line will not be exposed, so that abnormal growth of nickel gold will not occur.
  • the length L1 of the first end P of the first electrode 1033 along the first direction D1 is 30-60 microns
  • the length L2 of the first electrode 1033 along the first direction D1 is 1050-1100 microns
  • the second electrode The length L3 of 1023 along the first direction D1 is 1066-1116 microns.
  • the ratio of length L1 to length L2 is between 2% and 6%
  • the ratio of length L1 and length L3 is between 2% and 6%.
  • the second insulating layer 104 includes a plurality of via holes 1043 in the bonding area B.
  • the plurality of via holes 1043 correspond to the plurality of electrodes, and each via hole 1043 is located on the front side of the substrate 101 .
  • the projection falls within the orthographic projection of the first electrode 1033 of the corresponding one electrode on the substrate 101 .
  • the second insulating layer 104 extends along the first direction D1 and covers part of the surface of the second electrode 1023 of the first conductive layer 102 located in the binding region B. For example, it can cover and protect the second electrode 1023 in the binding region B.
  • the partial surface of the electrode 1023 close to the first end P of the functional region E, for example, W1 is about 22 ⁇ m.
  • FIG. 5A only shows a schematic structural diagram of the wiring substrate 200 in a partial area, and the schematic diagram does not show the electrical connection relationship between the third part 1022 and various signal lines located in the functional area E.
  • the third part 1022 is connected to various signal lines (such as the power signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111 and the driving signal line) located in the first conductive layer 102.
  • the voltage signal line VLED is electrically connected.
  • FIG. 6A shows a schematic plan view of a partial structure of the wiring substrate 300 in the bonding area B and the functional area E
  • FIG. 6B shows a cross-sectional view taken along line CC' of FIG. 6A.
  • the similarities between the wiring substrate 300 and the wiring substrate 100 will not be described, and only the differences between the wiring substrate 300 and the wiring substrate 100 will be described below.
  • the wiring substrate 300 shown in FIG. 6A includes a substrate 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, a second insulating layer 104 and other structures.
  • the first conductive layer 102 of the wiring substrate 200 is arranged in the functional area E and the bonding area B.
  • the first conductive layer 102 includes a third portion 1022 located in the bonding area B.
  • the third portion 1022 includes A plurality of second electrodes 1023 extending along the first direction D1.
  • the second conductive layer 103 includes a first portion 1031 located in the functional area E and a second portion 1032 located in the binding area B.
  • the second portion 1032 includes a plurality of first electrodes 1033 extending along the first direction D1.
  • the plurality of first electrodes 1033 correspond to the plurality of second electrodes 1023 one-to-one, and the orthographic projection of each second electrode 1023 on the substrate 101 falls within the orthographic projection of the corresponding first electrode 1033 on the substrate 101.
  • each first electrode 1033 is electrically connected to a second electrode 1023 corresponding to the first electrode 1033 to form an electrode, and the exposed area of the electrode surface forms a binding electrode.
  • Both the first electrode 1033 and the second electrode 1023 include a first end P close to the functional region E.
  • the orthographic projection of the first end P of the first electrode 1033 on the substrate 101 falls within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the substrate 101 .
  • the first electrode 1033 can shield and protect the second electrode 1023 during the etching process, so the side surface S32 of the first end P of the second electrode 1023 will not is etched so that side surface S32 is not exposed. That is, the first end of the second electrode 1023 of each signal line will not be exposed, so that abnormal growth of nickel-gold will not occur.
  • each second electrode 1023 includes a plurality of tooth-like structures 1023A extending along the first direction D1 and arranged along the second direction D2 intersecting the first direction D1 .
  • Each second electrode 1023 also includes a connection structure 1023B arranged along the second direction D2. Multiple tooth-like structures 1023A belonging to the same signal line are connected to each other through the connection structure 1023B.
  • the connection structure 1023B can be arranged in the functional area with the signal line.
  • the parts in E have the same line width. Assuming that two metal layers have the same surface area, the one with greater thickness will also have greater surface roughness.
  • the shape of the area of the thicker second electrode 1023 that is in direct contact with the first electrode 1033 is designed into a comb shape, which can increase the size of the second electrode 1023 and the first electrode 1033 to reduce the sliding shear force between the two, increase the adhesion between the second electrode 1023 and the first electrode 1033, and prevent the film from peeling off between the second electrode 1023 and the first electrode 1033. question.
  • Each tooth-shaped structure 1023A includes a second surface S31 facing the second conductive layer 103 and a side surface S32 connected to the second surface S31.
  • the via 1043 of the second insulating layer 104 exposes at least the side surface of each tooth-shaped structure 1023A. S32, causing the first electrode 1033 to directly contact the side surface S32 of the tooth structure 1023A through the via hole 1043 in the second insulation layer 104. In other words, the second insulation layer 104 does not cover the side surface S32 of the tooth structure 1023A.
  • the second insulating layer 104 will not be broken at the side surface S32 of the tooth structure 1023A, so that the first electrode 1033 will not be in contact with the second insulating layer 104 due to contact with the broken second insulating layer 104
  • the film layer peels off; further, because the second insulating layer 104 will not break at the side surface S32 of the tooth structure 1023A, the side surface S32 of the tooth structure 1023A will not be exposed and oxidized to produce oxides, thereby no This will cause the first electrode 1033 to bulge there, which will not cause the film layer to peel off between the first electrode 1033 and the second electrode 1023 .
  • the first insulating layer 105 includes a plurality of openings 1052 , the plurality of openings 1052 correspond to the plurality of first electrodes 1033 one-to-one, and each opening 1052 is on the substrate 101
  • the orthographic projection on the substrate 101 falls within the orthographic projection of a first electrode 1033 corresponding to the opening 1052 on the substrate 101 .
  • Each first electrode 1033 also includes a second terminal Q opposite to the first terminal P.
  • the orthographic projections of the first terminal P and the second terminal Q of each first electrode 1033 on the substrate 101 both fall on the first insulation.
  • the body portion 1051 of the layer 105 is in the orthographic projection on the substrate 101 .
  • both the first end P and the second end Q of the first electrode 1033 can be covered by the main body portion 1051 of the first insulating layer 105, thereby enhancing the bonding electrode 107. Corrosion resistance.
  • FIG. 6A only shows a schematic structural diagram of the wiring substrate 300 in a partial area, and the schematic diagram does not show the electrical connection relationship between the third part 1022 and various signal lines located in the functional area E.
  • the third part 1022 is connected to various signal lines (such as the power supply signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111 and the driving signal line) located in the first conductive layer 102.
  • the voltage signal line VLED is electrically connected.
  • FIG. 7A shows a schematic plan view of a partial structure of the wiring substrate 400 in the bonding area B and the functional area E
  • FIG. 7B shows a cross-sectional view taken along line DD' of FIG. 7A
  • the structure of the wiring substrate 400 is basically the same as that of the wiring substrate 300 except that the opening 1052 of the first insulating layer 105 is different from the wiring substrate 300 .
  • the opening 1052 of the first insulating layer 105 is different from the wiring substrate 300 .
  • the first insulating layer 105 includes a plurality of openings 1052 , the plurality of openings 1052 correspond to the plurality of first electrodes 1033 one-to-one, and each opening 1052 is on the substrate 101
  • the orthographic projection on the substrate 101 partially overlaps with the orthographic projection of a first electrode 1033 corresponding to the opening 1052 on the substrate 101 .
  • Each first electrode 1033 also includes a second end Q opposite to the first end P.
  • the orthographic projection of the first end P of each first electrode 1033 on the substrate 101 falls on the main body portion 1051 of the first insulating layer 105 In the orthographic projection on the substrate 101, the second end Q of each first electrode 1033 is exposed by an opening 1052. With such an arrangement, the main body portion 1051 of the first insulating layer 105 is not disposed at the second end Q of the first electrode 1033 , thereby effectively reducing the problem of film peeling caused by the presence of the first insulating layer 105 .
  • FIG. 7A only shows a schematic structural diagram of the wiring substrate 400 in a partial area, and the schematic diagram does not show the electrical connection relationship between the third part 1022 and various signal lines located in the functional area E.
  • the third part 1022 is connected to various signal lines (such as the power signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111 and the driving signal line) located in the first conductive layer 102.
  • the voltage signal line VLED is electrically connected.
  • FIG. 8A shows a schematic plan view of a partial structure of the wiring substrate 500 in the bonding area B and the functional area E
  • FIG. 8B shows a cross-sectional view taken along line EE' of FIG. 8A .
  • the similarities between the wiring substrate 500 and the wiring substrate 100 will not be described, and only the differences between the wiring substrate 500 and the wiring substrate 100 will be described below.
  • the wiring substrate 500 shown in FIG. 8A includes a substrate 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, a second insulating layer 104 and other structures. Different from the wiring substrate 100, the first conductive layer 102 of the wiring substrate 500 is arranged in the functional area E and the bonding area B.
  • the first conductive layer 102 includes a third portion 1022 located in the bonding area B.
  • the third portion 1022 includes A plurality of second electrodes 1023 extending along the first direction D1.
  • the second conductive layer 103 includes a first portion 1031 located in the functional area E and a second portion 1032 located in the binding area B.
  • the second portion 1032 includes a plurality of first electrodes 1033 extending along the first direction D1.
  • the plurality of first electrodes 1033 correspond to the plurality of second electrodes 1023 one-to-one, and the orthographic projection of each first electrode 1033 on the substrate 101 falls within the orthographic projection of the corresponding second electrode 1023 on the substrate 101.
  • each first electrode 1033 and a second electrode 1023 corresponding to the first electrode 1033 constitute an electrode, and the exposed surface area of the electrode constitutes the binding electrode 107.
  • the electrode includes a first end P close to the functional area E.
  • the orthographic projection of the first end P of the electrode on the substrate 101 falls within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the substrate 101 .
  • the first insulating layer 105 when the first insulating layer 105 is etched, even if the etching time is increased, it may only cause the surface of the first electrode 1033 away from the substrate 101 to be over-etched.
  • the thickness of the second insulating layer 104 is greater than that of the second insulating layer 104.
  • the first electrode 1033 has a shielding and protective effect on the second electrode 1023. Therefore, the first end P of the second electrode 1023 will not be etched, thereby preventing the second electrode 1023 from being etched.
  • the first end P of the electrode 1023 is exposed. That is, the first end of the second electrode 1023 of each signal line will not be exposed, so that abnormal growth of nickel-gold will not occur.
  • FIG. 8A only shows a schematic structural diagram of the wiring substrate 500 in a partial area, and the schematic diagram does not show the electrical connection relationship between the third part 1022 and various signal lines located in the functional area E.
  • the third part 1022 is connected to various signal lines (such as the power signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111 and the driving signal line) located in the first conductive layer 102.
  • the voltage signal line VLED is electrically connected.
  • the second insulating layer 104 is only arranged in the functional area E and not in the binding area B.
  • the orthographic projection of the second insulating layer 104 on the substrate 101 is in the same direction as the first electrode 1033 and the second electrode 1023 .
  • the orthographic projections on the substrate 101 do not overlap, and the first electrode 1033 and the second electrode 1023 constituting each electrode are in direct contact.
  • the first insulating layer 105 includes a plurality of openings 1052 that correspond to the plurality of electrodes one by one, and the orthographic projection of each opening 1052 on the substrate 101 falls corresponding to the opening 1052
  • One of the electrodes is within the orthographic projection on the substrate 101.
  • the electrode formed by each first electrode 1033 and a second electrode 1023 corresponding to the first electrode 1033 also includes a second terminal Q opposite to the first terminal P.
  • the orthographic projections on the substrate 101 all fall within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the substrate 101 . As shown in FIG.
  • the overlapping width W2 of the main body portion 1051 of the first insulating layer 105 and the first electrode 1033 along the second direction D2 is about 30 ⁇ m.
  • FIG. 9A shows a schematic plan view of a partial structure of the wiring substrate 600 in the bonding area B and the functional area E
  • FIG. 9B shows a cross-sectional view taken along line FF' of FIG. 9A .
  • the similarities between the wiring substrate 600 and the wiring substrate 100 will not be described, and only the differences between the wiring substrate 600 and the wiring substrate 100 will be described below.
  • the wiring substrate 600 shown in FIG. 9A includes a substrate 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, a second insulating layer 104 and other structures. Different from the wiring substrate 100, the first conductive layer 102 of the wiring substrate 600 is arranged in the functional area E and the bonding area B. The first conductive layer 102 includes a third portion 1022 located in the bonding area B. The third portion 1022 includes A plurality of second electrodes 1023 extending along the first direction D1. It should be noted that FIG. 9A only shows a schematic structural diagram of the wiring substrate 600 in a partial area, and the schematic diagram does not show the electrical connection relationship between the third part 1022 and various signal lines located in the functional area E.
  • the third part 1022 is connected to various signal lines (such as the power supply signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111 and the driving signal line) located in the first conductive layer 102.
  • the voltage signal line VLED is electrically connected.
  • the second conductive layer 103 includes a first portion 1031 located in the functional area E and a second portion 1032 located in the binding area B.
  • the second portion 1032 includes a plurality of first electrodes 1033 extending along the first direction D1.
  • the plurality of first electrodes 1033 correspond to the plurality of second electrodes 1023 one-to-one, and the orthographic projection of each first electrode 1033 on the substrate 101 falls within the orthographic projection of the corresponding second electrode 1023 on the substrate 101.
  • each first electrode 1033 and a second electrode 1023 corresponding to the first electrode 1033 constitute an electrode, and the exposed surface area of the electrode constitutes the binding electrode 107.
  • the electrode includes a first end P close to the functional area E.
  • the main body portion 1051 of the first insulating layer 105 includes a plurality of sub-insulating portions 1054 extending along the first direction D1 and spaced apart from each other in the second direction D2. Two adjacent sub-insulating portions of the plurality of sub-insulating portions 1054 The orthographic projection of the insulating portion 1054 on the substrate 101 and the orthographic projection of one electrode on the substrate 101 respectively partially overlap.
  • the respective electrodes are spaced apart from each other in the second direction D2, and the respective sub-insulating portions 1054 are also spaced apart from each other in the second direction D2, and each electrode corresponds to two sub-insulating portions 1054, so the spacing area between two adjacent electrodes There must be a part of the area where the sub-insulating part 1054 does not exist. As shown in the area W in FIG. 9A , the sub-insulating part 1054 does not exist in the area W.
  • the stack thickness of the insulating layer in the region W can be reduced, thereby mitigating the problem of film layer peeling caused by excessive thickness of the insulating layer stack.
  • the orthographic projection of the first end P of the electrode composed of each first electrode 1033 and a second electrode 1023 corresponding to the first electrode 1033 on the substrate 101 is in line with the two adjacent electrodes.
  • Orthographic projections of the insulating portion 1054 on the substrate 101 partially overlap, so two adjacent sub-insulating portions 1054 can protect the first end P of the electrode to a certain extent.
  • the first electrode 1033 can at least partially shield and protect the second electrode 1023, and the first end P of the second electrode 1023 is basically not etched, so that the surface of the first end P of the second electrode 1023 Basically no nudity. That is, the first end P of the second electrode 1023 of each signal line is basically not exposed, so that abnormal growth of nickel-gold does not basically occur.
  • the overlapping width W3 of the sub-insulating portion 1054 of the first insulating layer 105 and the first electrode 1033 along the second direction D2 is about 15 ⁇ m, thereby protecting the first electrode 1033 along the first direction D1 Extended sides.
  • the overlapping width W4 of the second insulating layer 104 and the second electrode 1023 along the second direction D2 is about 22 ⁇ m, thereby protecting the two sides of the second electrode 1023 extending along the first direction D1.
  • FIG. 10A shows a schematic plan view of a partial structure of the wiring substrate 700 in the bonding area B and the functional area E
  • FIG. 10B shows a cross-sectional view taken along line GG' of FIG. 10A .
  • the similarities between the wiring substrate 700 and the wiring substrate 100 will not be described, and only the differences between the wiring substrate 700 and the wiring substrate 100 will be described below.
  • the wiring substrate 700 shown in FIG. 10A includes a substrate 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, a second insulating layer 104 and other structures. Different from the wiring substrate 100, the first conductive layer 102 of the wiring substrate 700 is arranged in the functional area E and the bonding area B.
  • the first conductive layer 102 includes a third portion 1022 located in the bonding area B.
  • the third portion 1022 includes A plurality of second electrodes 1023 extending along the first direction D1 and the exposed surface areas of the second electrodes 1023 constitute the binding electrode 107 .
  • the second electrode 1023 includes a first end P close to the functional area E.
  • the second conductive layer 103 of the wiring substrate 700 is arranged only in the functional area E but not in the bonding area B. In an alternative embodiment, the second conductive layer 103 is disposed neither in the functional area E nor in the bonding area B, that is, the wiring substrate 700 only includes the first conductive layer 102 but not the second conductive layer 103 . It should be noted that FIG. 10A only shows a schematic structural diagram of the wiring substrate 700 in a partial area, and the schematic diagram does not show the electrical connection relationship between the third part 1022 and various signal lines located in the functional area E.
  • the third part 1022 is connected to various signal lines (such as the power supply signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111 and the driving signal line) located in the first conductive layer 102.
  • the voltage signal line VLED is electrically connected.
  • the second insulating layer 104 includes a plurality of via holes 1043.
  • the plurality of via holes 1043 correspond to the plurality of second electrodes 1023, and the orthographic projection of each of the plurality of via holes 1043 on the substrate 101 falls on the same plane as the plurality of via holes 1043.
  • a second electrode 1023 corresponding to the via hole 1043 is within the orthographic projection on the substrate 101 .
  • the main body portion 1051 of the first insulating layer 105 includes a plurality of sub-insulating portions 1054 extending along the first direction D1 and spaced apart from each other in the second direction D2.
  • Two adjacent sub-insulating portions of the plurality of sub-insulating portions 1054 The orthographic projection of the insulating portion 1054 on the substrate 101 and the orthographic projection of the second electrode 1023 on the substrate 101 respectively partially overlap, and the orthographic projection of the first end P of the second electrode 1023 on the substrate 101 overlaps with the orthographic projection of the first end P of the second electrode 1023 on the substrate 101.
  • the orthographic projections of two adjacent sub-insulating portions 1054 on the substrate 101 partially overlap.
  • Each second electrode 1023 is spaced apart from each other in the second direction D2, and each sub-insulation portion 1054 is also spaced from each other in the second direction D2.
  • Each second electrode 1023 corresponds to two sub-insulation portions 1054, so two adjacent ones There must be a part of the space between the second electrodes 1023 in which the sub-insulating part 1054 does not exist. As shown in the region W in FIG. 10A , the sub-insulating part 1054 does not exist in the region W.
  • the stack thickness of the insulating layer in the region W can be reduced, thereby mitigating the problem of film layer peeling caused by excessive thickness of the insulating layer stack.
  • the overlapping width of the sub-insulating portion 1054 of the first insulating layer 105 and the second electrode 1023 along the second direction D2 is about 22 ⁇ m, thereby protecting the two sides of the second electrode 1023 extending along the first direction D1.
  • the overlapping width of the second insulating layer 104 and the second electrode 1023 along the second direction D2 is about 15-20 ⁇ m, thereby protecting the two sides of the second electrode 1023 extending along the first direction D1.
  • FIG. 11A shows a schematic plan view of the wiring substrate 800 in the bonding area B
  • FIG. 11B shows a cross-sectional view taken along line HH' of FIG. 11A.
  • the similarities between the wiring substrate 800 and the wiring substrate 100 will not be described, and only the differences between the wiring substrate 800 and the wiring substrate 100 will be described below.
  • the wiring substrate 800 shown in FIG. 11A includes a substrate 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, a second insulating layer 104 and other structures. Different from the wiring substrate 100, the first insulating layer 105 and the second insulating layer 104 of the wiring substrate 800 are only arranged in the functional area E and not in the bonding area B, and the first conductive layer 102 is arranged in the functional area E and the bonding area B. In binding area B.
  • the first conductive layer 102 includes a third portion 1022 located in the binding area B.
  • the third portion 1022 includes a plurality of second electrodes 1023 extending along the first direction D1.
  • the second electrodes 1023 constitute the binding electrode 107.
  • the second conductive layer 103 of the wiring substrate 800 is arranged only in the functional area E but not in the bonding area B. In an alternative embodiment, the second conductive layer 103 is disposed neither in the functional area E nor in the bonding area B, that is, the wiring substrate 800 only includes the first conductive layer 102 but not the second conductive layer 103 . It should be noted that FIG. 11A only shows a schematic structural diagram of the wiring substrate 800 in a partial area, and the schematic diagram does not show the electrical connection relationship between the third part 1022 and various signal lines located in the functional area E.
  • the third part 1022 is connected to various signal lines (such as the power supply signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111 and the driving signal line) located in the first conductive layer 102.
  • the voltage signal line VLED is electrically connected.
  • the wiring substrate 200 shown in FIGS. 5A-5B the wiring substrate 300 shown in FIGS. 6A-6B , the wiring substrate 400 shown in FIGS. 7A-7B , and the wiring substrate 500 shown in FIGS. 8A-8B
  • Various types of signal lines such as the power signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111 and the driving voltage signal line VLED, etc. These signal lines usually have different line widths along the second direction D2.
  • the line width of each of the common voltage signal line 111 and the driving voltage signal line VLED along the second direction D2 is usually larger than the power signal line 103 and the address signal line 108. and the line width of any one of the feedback signal lines 110 along the second direction D2.
  • their respective third portions 1022 include different numbers of second electrodes 1023 .
  • the signal line only includes a second electrode 1023 in the third part 1022 of the binding area B; if a certain signal line (such as the driving voltage signal line VLED and the common voltage signal line 111) is in the functional area E along the second
  • the line width in direction D2 is much larger than the line width of the electrode 150 in the bonding area along the second direction D2, then the signal line includes a plurality of second electrodes 1023 in the third part 1022 of the bonding area B.
  • multiple second electrodes 1023 belonging to the same signal line are connected to each other at the first end.
  • FIG. 12 shows a block diagram of a light-emitting substrate 900.
  • the light-emitting substrate 900 includes the wiring substrate described in any of the previous embodiments and a plurality of circuit boards arranged in the functional area E.
  • each light-emitting element may be a light-emitting diode (LED), a sub-millimeter light-emitting diode (Mini LED), or a micro light-emitting diode (Mirco LED).
  • Mini LED as a light-emitting element, high-dynamic range (HDR) display can be achieved.
  • the circuit board may be a flexible circuit board (FPC), for example.
  • FPC flexible circuit board
  • One end of the FPC is connected to the printed circuit board (PCBA), and the other end of the FPC is connected to the binding electrode 107 on the light-emitting substrate 900 through a chip-on-film (COF), for example.
  • the control signal of the IC on the PCBA is transmitted to the bonding electrode 107 via the FPC.
  • One end of the plurality of signal lines on the light-emitting substrate 900 is bound to the binding electrode 107, and the other end is electrically connected to the light-emitting element. Therefore, the control signal can be transmitted to the light-emitting element via the signal line to control the light-emitting element to emit light.
  • the light-emitting substrate 900 provided by the embodiments of the present disclosure can have substantially the same technical effects as the wiring substrate described in the previous embodiments. Therefore, for the purpose of simplicity, the technical effects of the light-emitting substrate 900 will not be repeated here.
  • FIG. 13 shows a block diagram of a display device 1000 including the wiring substrate or the light-emitting substrate described in any of the previous embodiments.
  • the display device 1000 may be a liquid crystal display device, which includes a liquid crystal panel and a backlight source disposed on the non-display side of the liquid crystal panel.
  • the backlight source includes the wiring substrate described in any of the previous embodiments, for example Can be used to implement HDR dimming for display operations.
  • the liquid crystal display device can have more uniform backlight brightness and better display contrast.
  • the display device 1000 can be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators, e-books, and any other product or component with a display function.
  • the display device 1000 can have substantially the same technical effects as the wiring substrate described in the previous embodiments, for the purpose of brevity, the technical effects of the display device 1000 will not be repeated here.
  • FIG. 14 shows a flow chart of the method 1100.
  • the method 1100 can be applied to the wiring substrate described in any of the previous embodiments.
  • Method 1100 may include the following steps.
  • S1101 Provide a substrate 101, which includes a functional area E and a binding area B.
  • the substrate 101 can be made of flexible or rigid material. Specifically, it can be PEN resin, silicone resin, polyimide, glass, quartz, plastic, etc. The embodiments of the present disclosure do not limit the material of the substrate 101 .
  • S1102 Apply a first conductive film on the substrate 101, and pattern the first conductive film through a first mask to form a first conductive layer 102.
  • the first conductive layer 102 is at least located in the functional area E.
  • a first conductive film is applied on the substrate 101 by a magnetron sputtering method or an electroplating method, and the first conductive film is patterned using a first mask to form a first conductive layer 102.
  • the first conductive layer 102 may include the aforementioned driving voltage signal lines, address selection signal lines, power signal lines, data driving signal lines, common voltage signal lines, feedback signal lines, and optional second electrodes 1023 .
  • the first conductive layer 102 may be a stack of MoNb/Cu/MoNb. In alternative embodiments, first conductive layer 102 may be a stack of Mo/Cu/Mo.
  • S1103 Apply a second conductive film on the side of the first conductive layer 102 away from the substrate 101, and pattern the second conductive film through a second mask to form the second conductive layer 103.
  • the second conductive layer 103 is at least located in the functional area. B and is electrically connected to the first conductive layer 102 .
  • a second conductive film is applied on the side of the first conductive layer 102 away from the substrate 101 by a magnetron sputtering method or an electroplating method, and the second conductive film is patterned using a second mask to form the second conductive layer 103 .
  • the second conductive layer 103 may include the first pad group 102, the second pad group 104 and the optional first electrode 1033 as described above.
  • the first pad group 102 may be used to install the micro driver chip 002.
  • the two pad sets 104 can be used to mount electronic components 003 .
  • the second conductive layer 103 may be formed by the following process: first, forming a thickness of about MoNb layer, and then form a thickness of approximately The Cu layer is finally formed on the Cu layer with a thickness of approximately MoNb layer.
  • the second conductive layer 103 may be formed by the following process: first forming a thickness of about Mo layer, and then form a Mo layer on the Mo layer with a thickness of approximately The Cu layer is finally formed on the Cu layer with a thickness of approximately The Mo layer.
  • S1104 Apply a first insulating film on the side of the second conductive layer 103 away from the substrate 101, and pattern the first insulating film through a third mask to form the first insulating layer 105 including the main body portion 1051 and the opening 1052, wherein , at least one of the first conductive layer 102 and the second conductive layer 103 includes a plurality of electrodes located in the binding region B and extending along the first direction D1, and each of the plurality of electrodes includes adjacent ones in the first direction D1.
  • the orthographic projection of the first end P of the functional region E and the main body portion 1051 of the first insulating layer 105 on the substrate 101 at least partially overlaps with the orthographic projection of the first end P of each electrode on the substrate 101 .
  • the first insulating layer 105 may be formed on a side of the second conductive layer 103 away from the substrate 101 by a magnetron sputtering method. By causing the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the substrate 101 to at least partially overlap the orthographic projection of the first end P of each electrode on the substrate 101, it is possible to prevent Abnormal growth of nickel-gold occurs on signal lines.
  • the material of the first insulating layer 105 may be organic materials, inorganic materials, or a combination of organic materials and inorganic materials.
  • the first insulating layer 105 may be a single film layer, or may include multiple film layers.
  • the first conductive layer 102 and before forming the second conductive layer 103 may also include: applying a third conductive layer on a side of the first conductive layer 102 away from the substrate 101 by magnetron sputtering.
  • the second insulating film is patterned through a fourth mask to form the second insulating layer 104 .
  • the material of the second insulating layer 104 may be organic materials, inorganic materials, or a combination of organic materials and inorganic materials.
  • the second insulating layer 104 may be a single film layer, or may include multiple film layers.
  • the second insulation layer 104 includes a first sub-insulation layer 1041 and a second sub-insulation layer 1042.
  • an OC may also be formed between the first sub-insulating layer 1041 and the second sub-insulating layer 1042 through a fifth mask.
  • the OC layer can be a negative photoresist composed of organic materials.
  • the thickness of the OC layer is greater than that of the first insulating layer 105 and the second insulating layer 104 , and is usually arranged only in the functional region E. In one example, the thickness of the OC layer is 3-4 microns.
  • a thicker OC layer can be used to wrap the particles between the first conductive layer 102 and the second conductive layer 103 to prevent the particles from penetrating the first conductive layer 102 and the second conductive layer 103 and causing a short circuit between them.
  • the OC layer can play a planarizing role.
  • the first conductive layer 102 may further include: forming a buffer layer 106 on the substrate 101, for example, by a magnetron sputtering method.
  • the buffer layer 106 can be used to reduce stress on the substrate 101 during subsequent preparation of the first conductive layer 102 and the second conductive layer 103, thereby preventing bending deformation of the substrate 101.
  • the buffer layer 106 can also prevent impurities in the substrate 101 from adversely affecting the conductive properties of the subsequently formed first conductive layer 102 and the second conductive layer 103 .
  • the buffer layer 112 may be any suitable material, for example, SiN, SiO, or SiON.
  • the method 1100 can use fewer masks (for example, five masks) to prepare the wiring substrate. Compared with the related art that requires at least seven masks to prepare the wiring substrate, the method 1100 provided by the embodiment of the present disclosure It can reduce the number of required masks, simplify the process, and reduce production costs. Other technical effects achieved by the method 1100 may refer to the technical effects of the wiring substrate described in the previous embodiments. Therefore, for the purpose of brevity, the description will not be repeated here.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed above could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the disclosure. Because of this, variations in the shapes illustrated may be expected, for example, as a result of manufacturing techniques and/or tolerances. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure.

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Abstract

一种布线基板及其制造方法、发光基板以及显示装置。布线基板（100）包括：衬底（101）；第一导电层（102），位于衬底上且至少位于功能区（E）内；第二导电层（103），位于第一导电层上且至少位于绑定区（B）内以及与第一导电层电连接；第一绝缘层（105），位于第二导电层远离衬底的一侧且包括主体部（1051）和开口（1052）。第一导电层和第二导电层中的至少一个包括位于绑定区内且沿第一方向（D1）延伸的多个电极（1033），该电极包括在第一方向上邻近功能区的第一端（P），第一绝缘层的主体部与每个电极的第一端在衬底上的正投影至少部分交叠。

Description

布线基板及其制造方法、发光基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种布线基板、包括该布线基板的发光基板和显示装置、以及制造该布线基板的方法。
背景技术
显示装置通常分为液晶显示装置和有机发光二极管显示装置两大类，液晶显示装置由于具有轻薄化、抗震性好、视角广、对比度高等优点而得到广泛应用。液晶显示装置通常包括显示面板和背光源，背光源通常布置在显示面板的非显示侧以为显示面板的显示操作提供光源。液晶显示装置的对比度、亮度均匀性以及稳定性等特性与背光源的结构和性能相关联。近几年，次毫米发光二极管(Mini-LED)由于其优异的性能而得到广泛的关注，并被越来越多地应用到背光源中。
发明内容
根据本公开的一方面，提供了一种布线基板，该布线基板包括：衬底，包括功能区和绑定区；第一导电层，位于所述衬底上且至少位于所述功能区内；第二导电层，位于所述第一导电层远离所述衬底的一侧且至少位于所述功能区内，所述第二导电层与所述第一导电层电连接；以及第一绝缘层，位于所述第二导电层远离所述衬底的一侧且包括主体部和开口。所述第一导电层和所述第二导电层中的至少一个包括位于所述绑定区内且沿第一方向延伸的多个电极，所述多个电极中的每一个包括在所述第一方向上邻近所述功能区的第一端，所述第一绝缘层的主体部在所述衬底上的正投影与每个电极的第一端在所述衬底上的正投影至少部分地交叠。
在一些实施例中，所述布线基板还包括位于所述第一导电层与所述第二导电层之间的第二绝缘层，所述第二导电层经由所述第二绝缘层中的过孔与所述第一导电层接触。
在一些实施例中，所述第二导电层包括第一部和第二部，所述第一部位于所述功能区内，所述第二部位于所述绑定区内，所述第二部包括沿所述第一方向延伸的多个第一电极，所述多个第一电极中的每 一个包括所述第一端。
在一些实施例中，所述第二导电层包括背离所述衬底的第一表面，所述第一表面位于所述第一部的部分到所述衬底的距离大于所述第一表面位于所述第二部的部分到所述衬底的距离，所述第一绝缘层的开口在所述衬底上的正投影与所述第二部在所述衬底上的正投影至少部分地交叠。
在一些实施例中，所述第一绝缘层的开口暴露每个第一电极的除所述第一端之外的其余部分。
在一些实施例中，在所述绑定区，所述第一绝缘层的开口在所述衬底上的正投影与所述第二绝缘层在所述衬底上的正投影不交叠。
在一些实施例中，所述第一导电层仅位于所述功能区内，所述第一导电层在所述衬底上的正投影与所述第二导电层的第一部在所述衬底上的正投影部分地交叠。
在一些实施例中，在所述功能区，所述第一导电层包括面向所述第二导电层的第二表面和与所述第二表面衔接且朝向所述绑定区的侧表面，所述第二导电层与所述第一导电层的侧表面直接接触。
在一些实施例中，所述第一导电层包括位于所述绑定区内的第三部，所述第三部包括沿所述第一方向延伸的多个第二电极，所述多个第一电极与所述多个第二电极一一对应，并且所述多个第一电极中的每一个在所述衬底上的正投影与所述多个第二电极中的相应一个在所述衬底上的正投影至少部分地交叠。每个第一电极和与该第一电极相应的一个第二电极电连接且构成电极，并且电连接的第一电极和第二电极均包括所述第一端。
在一些实施例中，所述第一电极和所述第二电极的第一端在所述衬底上的正投影落在所述第一绝缘层的主体部在所述衬底上的正投影内。
在一些实施例中，所述第一绝缘层的开口暴露每个第一电极的除所述第一端之外的其余部分。
在一些实施例中，每个第二电极包括沿所述第一方向延伸且沿第二方向排布的多个齿状结构，其中所述第二方向与所述第一方向交叉。
在一些实施例中，所述多个齿状结构中的每一个包括面向所述第二导电层的第二表面和与所述第二表面衔接的侧表面所述第一电极与 所述齿状结构的侧表面直接接触。
在一些实施例中，在所述绑定区，所述第一绝缘层包括多个开口，所述多个开口与所述多个电极一一对应，并且所述多个开口中的每一个在所述衬底上的正投影落在与该开口对应的一个电极的第一电极在所述衬底上的正投影内。所述电极还包括与所述第一端相对的第二端，所述电极的第二端在所述衬底上的正投影落在所述第一绝缘层的主体部在所述衬底上的正投影内。
在一些实施例中，在所述绑定区，所述第一绝缘层包括多个开口，所述多个开口与所述多个电极一一对应，并且所述多个开口中的每一个在所述衬底上的正投影和与该开口对应的一个电极在所述衬底上的正投影部分地交叠。所述电极还包括与所述第一端相对的第二端，所述第二端的一部分被与该电极对应的一个开口暴露。
在一些实施例中，所述第二绝缘层在所述衬底上的正投影与所述第一电极和第二电极在所述衬底上的正投影不交叠，并且每个电极的第一电极与第二电极直接接触。
在一些实施例中，在所述绑定区，所述第一绝缘层包括多个开口，所述多个开口与所述多个电极一一对应，并且所述多个开口中的每一个在所述衬底上的正投影落在与该开口对应的一个电极的第一电极在所述衬底上的正投影内，所述电极还包括与所述第一端相对的第二端，所述电极的第二端在所述衬底上的正投影落在所述第一绝缘层的主体部在所述衬底上的正投影内。
在一些实施例中，对于每个电极，所述第一电极在所述衬底上的正投影落在所述第二电极在所述衬底上的正投影内。
在一些实施例中，所述第一绝缘层的主体部包括沿所述第一方向延伸且在与所述第一方向交叉的第二方向上彼此间隔的多个子绝缘部，所述多个子绝缘部中的两个相邻子绝缘部在所述衬底上的正投影与一个电极在所述衬底上的正投影分别部分地交叠，并且所述第一电极和所述第二电极的第一端在所述衬底上的正投影与所述两个相邻子绝缘部在所述衬底上的正投影部分地交叠。
在一些实施例中，所述第二导电层仅布置在所述功能区内，所述第一导电层包括布置在所述绑定区内的第三部，所述第三部包括沿所述第一方向延伸的多个第二电极，所述多个第二电极中的每一个包括 所述第一端。
在一些实施例中，所述第二绝缘层包括多个过孔，所述多个过孔与所述多个第二电极一一对应，并且所述多个过孔中的每一个在所述衬底上的正投影落在与该过孔对应的一个第二电极在所述衬底上的正投影内。
在一些实施例中，所述第一绝缘层的主体部包括沿所述第一方向延伸且在与所述第一方向交叉的第二方向上彼此间隔的多个子绝缘部，所述多个子绝缘部中的两个相邻子绝缘部在所述衬底上的正投影与一个第二电极在所述衬底上的正投影分别部分地交叠，并且所述第二电极的第一端在所述衬底上的正投影与所述两个相邻子绝缘部在所述衬底上的正投影部分地交叠。
根据本公开的另一方面，提供了一种发光基板，该发光基板包括在前面任一个实施例描述的布线基板以及设置在所述功能区内的多个发光元件和设置在所述绑定区内的电路板。
根据本公开的又一方面，提供了一种显示装置，该显示装置包括在前面任一个实施例描述的布线基板或前面任一个实施例描述的发光基板。
根据本公开的再一方面，提供了一种制造布线基板的方法，包括：提供衬底，所述衬底包括功能区和绑定区；在所述衬底上施加第一导电膜，通过第一掩膜对所述第一导电膜进行构图以形成第一导电层，所述第一导电层至少位于所述功能区内；在所述第一导电层远离所述衬底的一侧施加第二导电膜，通过第二掩膜对所述第二导电膜进行构图以形成第二导电层，所述第二导电层至少位于所述功能区内且与所述第一导电层电连接；以及在所述第二导电层远离所述衬底的一侧施加第一绝缘膜，通过第三掩膜对所述第一绝缘膜进行构图以形成包括主体部和开口的第一绝缘层，所述第一导电层和所述第二导电层中的至少一个包括位于所述绑定区内且沿第一方向延伸的多个电极，所述多个电极中的每一个包括在所述第一方向上邻近所述功能区的第一端，所述第一绝缘层的主体部在所述衬底上的正投影与每个电极的第一端在所述衬底上的正投影至少部分地交叠。
在一些实施例中，在所述衬底上形成第一导电层的步骤之后，还包括：在所述第一导电层远离所述衬底的一侧施加第二绝缘膜，通过 第四掩膜对所述第二绝缘膜进行构图以形成第二绝缘层；以及在所述第二绝缘层远离所述衬底的一侧形成所述第二导电层。
附图说明
为了更清楚地描述本公开实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了相关技术中的布线基板的结构示意图；
图2A示出了根据本公开实施例的布线基板的部分结构的平面示意图；
图2B示出了沿着图2A的AA’线截取的剖面示意图；
图2C示出了图2A的区域II的简化示意图；
图3A示出了相关技术中的布线基板的局部结构的放大图片；
图3B示出了相关技术中的布线基板的局部结构的放大图片；
图4示出了根据本公开实施例的布线基板在功能区的平面结构示意图；
图5A示出了根据本公开实施例的布线基板的部分结构的平面示意图；
图5B示出了沿着图5A的BB’线截取的剖面示意图；
图6A示出了根据本公开实施例的布线基板的部分结构的平面示意图；
图6B示出了沿着图6A的CC’线截取的剖面示意图；
图7A示出了根据本公开实施例的布线基板的部分结构的平面示意图；
图7B示出了沿着图7A的DD’线截取的剖面示意图；
图8A示出了根据本公开实施例的布线基板的部分结构的平面示意图；
图8B示出了沿着图8A的EE’线截取的剖面示意图；
图9A示出了根据本公开实施例的布线基板的部分结构的平面示意图；
图9B示出了沿着图9A的FF’线截取的剖面示意图；
图10A示出了根据本公开实施例的布线基板的部分结构的平面示意图；
图10B示出了沿着图10A的GG’线截取的剖面示意图；
图11A示出了根据本公开实施例的布线基板的部分结构的平面示意图；
图11B示出了沿着图11A的HH’线截取的剖面示意图；
图12示出了根据本公开实施例的发光基板的框图；
图13示出了根据本公开实施例的显示装置的框图；以及
图14示出了根据本公开实施例的制造布线基板的方法的流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
图1示出了相关技术中的一种布线基板10，该布线基板10包括衬底11、第一导电层12、第一子绝缘层141、第二子绝缘层142、第二导电层13、绝缘层15等结构。对于第二导电层13远离衬底11且裸露的区域表面，需要进行防氧化处理，例如采用化学镍金方式进行处理，以在该表面上生长期望的镍金层17，从而增强第二导电层13的抗氧化性和/或连接可靠性。具体的，在化学镍金工艺中，首先对布线基板10进行酸洗，然后将布线基板10置于包含Pd 2+的活化溶液中，此时，第二导电层13中表面裸露区域的金属(例如Cu)与活化溶液中的Pd 2+发生置换反应，生成了Cu 2+和Pd(钯)，其中Pd附着在第二导电层13背离衬底11的表面，形成钯层。而后将布线基板10置于主要成分是硫酸镍、次磷酸钠(还原剂，使镍离子还原为金属镍)、络合剂的溶液中，在焊盘的表面会生成一层磷镍合金层，由于磷镍合金层仍然会被氧化，焊料与发生氧化的磷镍合金层焊接困难且不可靠，因此最后还需要将布线基板10浸入含有金离子溶液中，在磷镍合金层表面形成浸金层，浸金层中的金颗粒可填塞化镍金层中的空隙，以降低磷镍合金层的氧化概率，从而可以减弱第二导电层13裸露区域的氧化程度。从 而使得第二导电层13裸露区域表面具有镍金层17(包括上述磷镍合金层和浸金层)。
在图1中的虚线矩形框图出的区域I内，第一子绝缘层141和第二子绝缘层142为没有过孔的连续膜层时，可以覆盖第一导电层12的表面使其免于发生氧化。而为了对在第二导电层13表面形成镍金层17提供较佳的界面，需对绝缘层15进行刻蚀处理以形成过孔16来露出第二导电层13，并对第二导电层13远离衬底11的表面也进行一定程度的刻蚀。由于需要额外刻蚀第二导电层13远离衬底11的表面，因此相比于仅刻蚀绝缘层15而言，会增加刻蚀的时间。而第一子绝缘层141和第二子绝缘层142的厚度通常比较薄，在增加刻蚀时间的情况下，会不可避免地引起第一子绝缘层141和第二子绝缘层142被过刻，从而在第一子绝缘层141和第二子绝缘层142中产生本不需要的过孔19。绝缘层15中的过孔16以及第一子绝缘层141和第二子绝缘层142中的不期望的过孔19使得第一导电层12远离衬底11的表面被部分地暴露，第一导电层12在表面裸露的位置处会异常生长镍金层18。该异常生长的镍金层18会引起诸如膜层之间的短路、绝缘层15的表面平坦性的破坏等问题，从而显著影响布线基板10的可靠性。
本公开的一些实施例提供了改进的布线基板，该布线基板至少能够解决绑定区内异常生长镍金层的问题。
图2A示出了布线基板100的部分区域的平面示意图，图2B示出了沿着图2A的AA’线截取的剖面图。如图2A和图2B所示，该布线基板100包括：衬底101，包括功能区E和绑定区B；第一导电层102，位于衬底101上且至少位于功能区E内；第二导电层103，位于第一导电层102远离衬底101的一侧且至少位于功能区E内，第二导电层103与第一导电层102电连接；以及第一绝缘层105，位于第二导电层103远离衬底101的一侧且包括主体部1051和开口1052。绑定区B布置有多个电极150，该多个电极150分别沿第一方向D1延伸且沿与第一方向D1交叉的第二方向D2间隔设置，第一导电层102和第二导电层103中的至少一个包括该多个电极150，多个电极150中的每一个包括在第一方向D1上邻近功能区E的第一端P，第一绝缘层105的主体部1051在衬底101上的正投影与每个电极150的第一端P在衬底101上的正投影至少部分地交叠。电极150表面裸露的区域用作绑定电极107。需 要指出的是，所描述的第一导电层102、第二导电层103以及第一绝缘层105的相对位置关系不仅适应于布线基板100，还适应于本公开其他实施例描述的各个布线基板，这将在后文详细地描述。
需要说明的是，在本文中，术语“第一绝缘层105的主体部1051”是指第一绝缘层105的实体部分，该实体部分由适当的绝缘材料构成；术语“第一绝缘层105的开口1052”是指第一绝缘层105的镂空的过孔，第一绝缘层105在该开口1052处不具有任何实体的材料。主体部1051和开口1052构成第一绝缘层105。另外，术语“功能区”是指衬底101上用来布置功能元器件(例如发光元件)的区域，术语“绑定区”是指衬底101上用来布置电极150的区域，绑定区用于与电路板耦接，若电路板具有金手指结构，则绑定区中的多个电极150中的每个电极在第二方向上的宽度基本相同，例如略大于金手指结构在第二方向上的宽度。
本申请的发明人发现，绑定区B内的电极150的第一端P处容易发生化镍金的异常生长。因此，在本申请的实施例中，通过使第一绝缘层105的主体部1051在衬底101上的正投影与每个电极150的第一端P在衬底101上的正投影至少部分地交叠，可以使第一绝缘层105的主体部1051覆盖电极150的第一端P的至少一部分。这样，即使在刻蚀第一绝缘层105以形成开口1052时，由于第一绝缘层105的主体部1051对电极150的第一端P具有遮挡和保护作用，因此不会导致电极150的第一端P的表面裸露，从而可以减轻甚至避免电极150的第一端P处发生化镍金的异常生长。
具体地，参考图2A和图2B，布线基板100的第一导电层102仅布置在功能区E内而未布置在绑定区B内，第二导电层103包括布置在功能区E内的第一部1031和布置在绑定区B内的第二部1032。第二导电层103的第二部1032包括沿第一方向D1延伸的多个第一电极1033，每个第一电极1033表面裸露的区域用作绑定电极107。第一电极1033包括第一端P。第一导电层102在衬底101上的正投影与第一电极1033在衬底101上的正投影不交叠。在一些实施例中，第一电极1033的第一端P沿第一方向D1的长度L1为30～60微米，第一电极1033沿第一方向D1的长度L2为1050～1100微米。在一些实施例中，长度L1与长度L2的比值在2％～6％之间。
图2C示出了图2A中的区域II的简化示意图，其仅示出了第一导电层102和第二导电层103的相对位置关系。第一导电层102包括驱动电压信号线VLED、公共电压信号线111(图4中示出)以及其他一些信号线。驱动电压信号线VLED和/或公共电压信号线111大致沿第一方向D1延伸，驱动电压信号线VLED和/或公共电压信号线111的一端延伸到布线基板100的功能区E远离绑定区B的任意位置，另一端与从绑定区B朝向功能区E延伸的多个第一电极1033连接。图2C示出的第一导电层102可以代表一条驱动电压信号线VLED或一条公共电压信号线111，其在功能区E内与第二导电层103的第一部1031直接接触，由于驱动电压信号线VLED或一条公共电压信号线111的线宽远大于一个第一电极1033的线宽，因而驱动电压信号线VLED或一条公共电压信号线111的另一端可以与多个第一电极1033对应且电连接。
本申请的发明人发现，在相关技术中，在绑定区B内，由于绑定电极107的表面裸露，且第一导电层102中的信号线与电极连接的位置与绑定电极107之间具有段差，容易发生异常生长化镍金的现象。但是在本公开的实施例中，第一导电层102仅布置在功能区E内而不布置在绑定区B内，因此避免了由第一导电层102形成的驱动电压信号线VLED和公共电压信号线111在绑定区B内异常生长化镍金。从图2A-2C可以清楚地看出，第一导电层102在衬底101上的正投影与第二导电层103的第一部1031在衬底101上的正投影部分地交叠；而第一导电层102在衬底101上的正投影与第二导电层103的第二部1032的第一电极1033在衬底101上的正投影不交叠。通过使第一导电层102仅布置在功能区E内而未布置在绑定区B内，这样，当对第一绝缘层105进行刻蚀以形成位于绑定区B内的开口1052时，无论刻蚀时间是否增加，都可以避免上述异常生长化镍金现象的发生。
在一些实施例中，布线基板100还可以包括位于第一导电层102与第二导电层103之间的第二绝缘层104，第二导电层103的第一部1031经由第二绝缘层104中的过孔1043与第一导电层102电连接。第二绝缘层104仅布置在功能区E内，而未布置在绑定区B内，因此，第二绝缘层104在衬底101上的正投影与第一电极1033在衬底101上的正投影不交叠。如果在绑定区B内布置多个叠加的绝缘层，由于多 个绝缘层彼此之间的附着力通常比较差，因此容易导致绝缘层发生膜层脱落(Peeling)现象。当多个绝缘层的叠加厚度超过一定的阈值(例如
Figure PCTCN2022096785-appb-000001
)时，出现这种脱落现象的概率会显著增加。为了避免绑定区B内出现膜层脱落问题，在发光基板100中，如图2A所示，在多个第一电极1033中的任意相邻两个第一电极1033之间的区域，没有设置第二绝缘层104的主体部1044，因此，在多个第一电极1033中的任意相邻两个第一电极1033之间的区域，第一绝缘层105的主体部1051在衬底101上的正投影与第二绝缘层104的主体部1044在衬底101上的正投影不重叠，这样可以减少第一绝缘层105的主体部1051与第二绝缘层104的主体部1044在绑定区B内的叠加，从而可以减轻甚至避免第一绝缘层105与第二绝缘层104在绑定区B内出现脱落的现象。
如图2B所示，第二导电层103包括位于功能区E内的第一部1031和位于绑定区B内的第二部1032。第二导电层103包括背离衬底101的第一表面，该第一表面呈现台阶状。具体地，该第一表面位于第一部1031的部分可以记为表面S11，该第一表面位于第二部1032的部分可以记为表面S13，该第一表面的位于表面S11与表面S13之间且用来衔接表面S11与表面S13的部分可以记为表面S12。该表面S12为倾斜的表面，因此使得第一表面位于第一部1031的部分S11到衬底101的距离d1大于第一表面位于第二部1032的部分S13到衬底101的距离d2。第一绝缘层105的主体部1051至少附接到表面S11、表面S12以及每个第一电极1033的表面S13位于第一端P内的部分，以对第二导电层103的第一部1031和第一电极1033的第一端P起到更好的覆盖和保护作用。第一绝缘层105的开口1052在衬底101上的正投影与第二部1032在衬底101上的正投影至少部分地交叠。在一些实施例中，第一绝缘层105的开口1052在衬底101上的正投影与第二绝缘层104在衬底101上的正投影不交叠。柔性印刷电路板可以绑定到第一电极1033的除第一端P以外的区域，即柔性印刷电路板与绑定电极绑定连接。
在一些实施例中，第一导电层102包括面向第二导电层103的第二表面S21和与第二表面S21衔接且朝向绑定区B的侧表面S22，第二绝缘层104覆盖第一导电层102的第二表面S21的一部分但不覆盖第一导电层102的侧表面S22，第二导电层103经由第二绝缘层104 中的过孔1043与第一导电层102的侧表面S22直接接触。第二绝缘层104可以是单个膜层，也可以是包括多个膜层的叠层。在一个示例中，第二绝缘层104包括第一子绝缘层1041和第二子绝缘层1042。在垂直于衬底101的方向上，相比于第一导电层102的厚度，第二绝缘层104的厚度通常比较薄(在一个示例中，第一导电层102在垂直于衬底101的方向上的厚度为1.8μm，第一子绝缘层1041在垂直于衬底101的方向上的厚度为0.24μm，第二子绝缘层1042在垂直于衬底101的方向上的厚度为0.15μm)。在相关技术中，第二绝缘层104需要覆盖第一导电层102的侧表面S22，由于第一导电层102的第二表面S21与下方膜层表面之间具有较大的段差，因此第二绝缘层104从第一导电层102的第二表面S21到侧表面S22衔接的位置处容易出现断裂，导致第二绝缘层104无法对第一导电层102形成完全覆盖和保护。另外，第二绝缘层104出现断裂以后，后续形成的第二导电层103在断裂位置处无法与下方膜层实现良好接触，进而引起第二导电层103出现脱落问题。进一步地，由于第二绝缘层104出现断裂后，会使得第一导电层102的部分区域的表面裸露，从而发生氧化而生成形状不规则的金属氧化物，降低第一导电层102的膜层连贯性和平整性，若第二导电层103与第一导电层102中出现具有不规则形状氧化物的区域直接接触，则容易导致第二导电层103在该处出现鼓包，进而导致第二导电层103出现脱落问题。因此，如果将第二绝缘层104布置在第一导电层102的侧表面S22处，容易引起第二导电层103出现脱落现象。图3A示出了相关技术中第二导电层103与第二绝缘层(PVX1-2)在第一导电层(Cu1)的侧表面处出现脱落，以及第二导电层(Cu2)与第一导电层(Cu1)在第一导电层(Cu1)的侧表面处出现脱落。图3B示出了相关技术中由于第一导电层12存在段差而导致第一子绝缘层141或第二子绝缘层142出现断裂(Crack)，进而使得第一导电层12在对应位置发生氧化而出现不规则形状(Tip)氧化物，最终导致第二导电层13出现鼓包的现象。
在本公开的实施例提供的布线基板100中，第二绝缘层104不覆盖第一导电层102的侧表面S22，而是第二导电层103经由第二绝缘层104中的过孔1043与第一导电层102的侧表面S22直接接触。这样，第二绝缘层104不会发生断裂，从而第二导电层103的第一电极1033 不会由于接触到断裂的第二绝缘层104而与第二绝缘层104发生膜层脱落；进一步地，由于第二绝缘层104不会发生断裂，因此第一导电层102的侧表面S22不会因表面裸露发生氧化而具有不规则的表面形貌，从而不会导致第二导电层103出现鼓包，进而不会导致第二导电层103的第一电极1033与第一导电层102之间出现膜层脱落问题。
在一些实施例中，第一导电层102可以是MoNb/Cu/MoNb的叠层。在替代的实施例中，第一导电层102可以是Mo/Cu/Mo的叠层。在一些实施例中，第二导电层103可以是
Figure PCTCN2022096785-appb-000002
Figure PCTCN2022096785-appb-000003
的叠层。在替代的实施例中，第二导电层103可以是
Figure PCTCN2022096785-appb-000004
的叠层。第一导电层102的厚度通常大于第二导电层103的厚度。
如图2B所示，在一些实施例中，布线基板100还可以包括位于衬底101与第一导电层102之间的缓冲层106。缓冲层106具有平坦化作用，可以提高第一导电层102与衬底101之间的附着力。
图2A-2C主要示出了布线基板100在绑定区B的布置方式，为了使读者更清楚地理解布线基板100的整体布置，图4作为示例示出了布线基板100在功能区E的布置方式。
布线基板100的功能区设置有待与数万个电子元件绑定连接的焊盘组，参考图4，该布线基板100在功能区E包括：第一焊盘组102，位于衬底101之上，第一焊盘组102包括供电焊盘Pwr和输出焊盘Out，可选地，第一焊盘组102与微型驱动芯片002耦接；电源信号线103，与第一焊盘组102位于衬底101的同一侧，电源信号线103与供电焊盘Pwr耦接；第二焊盘组104，与第一焊盘组102位于衬底101的同一侧，可选地，每个第二焊盘组104与一个电子元件003耦接。第二导电层103中位于功能区E且表面裸露的区域构成上述第一焊盘组102和第二焊盘组104。具体地，第一绝缘层105在功能区E包括开口1052，该开口1052暴露出第二导电层103的部分区域以用作焊盘。第一焊盘组102可以在焊料的辅助下通过回流焊工艺与微型驱动芯片002实现耦接，第二焊盘组104可以在焊料的辅助下通过回流焊工艺与发光元件003实现耦接。第二导电层103在绑定区B被开口1052暴露的部分用作绑定电极(例如第一电极1033除第一端P之外的部分)，该绑定电极在异方性导电胶的辅助下通过热压工艺与电路板(例如FPC)的 金手指结构实现绑定连接。在一些实施例中，衬底101包括多个焊盘区P，每个焊盘区P包括多个级联的第一焊盘组102以及分别与各第一焊盘组102耦接的多个第二焊盘组104。可选地，在一个焊盘区P内，多个级联的第一焊盘组102可以沿第一方向D1和/或第二方向D2阵列排布，在此不做限定。图4以一个焊盘区P中多个级联的第一焊盘组102排布成一列为例进行示意说明。在一些实施例中，一条电源信号线103可以与一个焊盘区P中沿第一方向D1排布且级联的多个第一焊盘组102的供电焊盘Pwr耦接，这样可以减少电源信号线103的绕线设计，从而减小电源信号线103的电阻，进而降低电源信号线103上的脉冲宽度调制信号损耗。在一些实施例中，布线基板100还可以包括第一连接引线106，一条电源信号线103包括多个子段103′，在第一方向D1相邻的两个子段103′可以通过一个第一连接引线106相互连接，以实现同一条电源信号线103为同一焊盘区P中沿第一方向D1排布且级联的多个第一焊盘组102的供电焊盘Pwr供电。可选地，第一连接引线106与子段103′为一体结构。在一些实施例中，第一焊盘组102还包括地址焊盘Di和接地焊盘Gnd，属于同一第一焊盘组102的地址焊盘Di与供电焊盘Pwr在第二方向D2上间隔设置、并与输出焊盘Out在第一方向D1上间隔设置，接地焊盘Gnd与供电焊盘Pwr在第一方向D1上间隔设置、并与输出焊盘Out在第二方向D2上间隔设置。示例性地，输出焊盘Out位于第一焊盘组102的左上角，地址焊盘Di位于第一焊盘组102的左下角，接地焊盘Gnd位于第一焊盘组102的右上角，供电焊盘Pwr位于第一焊盘组102的右下角。每个第一焊盘组102可以与一个微型驱动芯片002耦接，每个第二焊盘组104与多个电子元件003耦接。在一些实施例中，地址焊盘Di可接收地址信号，以用于选通相应地址的微型驱动芯片002。供电焊盘Pwr可为微型驱动芯片002提供第一工作电压和通信数据，该通信数据可用于控制相应发光元件的发光亮度。输出焊盘Out可在不同的时段内分别输出中继信号和驱动信号，中继信号为提供给下一级第一焊盘组102中的地址焊盘Di的地址信号，驱动信号为驱动电流，用于驱动与该输出焊盘Out所在第一焊盘组102耦接的发光元件发光。接地焊盘Gnd接收公共电压信号。在一些实施例中，在各第一焊盘组102中，供电焊盘Pwr、输出焊盘Out、接地焊盘Gnd、地址焊盘Di的排列方式相同，以使得同 一焊盘区P内相互级联的第一焊盘组102之间具有简洁的走线路径，避免产生较多的绕线。
在一些实施例中，布线基板100还可以包括地址信号线108，一条地址信号线108可以与一个焊盘区P中的第1级第一焊盘组102的地址焊盘Di耦接，使得在每个焊盘区P内，通过第1级第一焊盘组102的地址焊盘Di接收地址信号线107提供的地址信号。在一些实施例中，布线基板100还可以包括级联线109，级联线109被配置为连接属于同一焊盘区P的第n级第一焊盘组102的输出焊盘Out和第(n+1)级第一焊盘组102的地址焊盘Di，n为正整数，以通过级联线109将第n级第一焊盘组102的输出焊盘Out输出的中继信号提供给第(n+1)级第一焊盘组102的地址焊盘Di。在一些实施例中，布线基板100还可以包括反馈信号线110，一条反馈信号线110与一个焊盘区P中最后一级第一焊盘组102的输出焊盘Out耦接，以在一个焊盘区P形成传输地址信号的回路。在一些实施例中，布线基板100还可以包括公共电压信号线111，一条公共电压信号线111与一个焊盘区P内全部第一焊盘组102的接地焊盘Gnd耦接。在一些实施例中，布线基板100还可以包括驱动电压信号线VLED，驱动电压信号线VLED用来与电子元件003耦接。
以图4为例，在布线基板的功能区E内，第一导电层102被配置为实现上述电源信号线103、第一连接引线106、第二连接引线107、地址信号线108、级联线109、反馈信号线110、公共电压信号线111、驱动电压信号线VLED以及连接第一焊盘组与第二焊盘组以及连接第二焊盘组和第二焊盘组之间的连接线(未示出)。在制备过程中，通过利用同一掩模板经由一次构图工艺对第一导电层102进行构图来形成这些信号线。
可以理解的是，在另一些实施例中，在布线基板的功能区E内，第一导电层102仅被配置为实现电源信号线103、地址信号线108、反馈信号线110、公共电压信号线111和驱动电压信号线VLED，而第二导电层103被配置为实现第一连接引线106、第二连接引线107、级联线109以及连接第一焊盘组与第二焊盘组以及连接第二焊盘组和第二焊盘组之间的连接线。
图5A示出了布线基板200在绑定区B和功能区E内的部分结构 的平面示意图，图5B示出了沿着图5A的BB’线截取的剖面图。为了简洁起见，布线基板200与布线基板100的相同之处不再描述，下文仅描述布线基板200与布线基板100的不同之处。
图5A示出的布线基板200包括衬底101、第一导电层102、第二导电层103、第一绝缘层105以及第二绝缘层104等结构。与布线基板100不同，布线基板200的第一导电层102布置在功能区E和绑定区B内，第一导电层102包括位于绑定区B内的第三部1022，第三部1022包括沿第一方向D1延伸且沿第二方向D2间隔设置的多个第二电极1023。第二导电层103包括位于功能区E内的第一部1031和位于绑定区B内的第二部1032，第二部1032包括沿第一方向D1延伸的多个第一电极1033。多个第一电极1033与多个第二电极1023一一对应，并且每个第一电极1033在衬底101上的正投影落在相应一个第二电极1023在衬底101上的正投影内，并且每个第一电极1033和与该第一电极1033相应的一个第二电极1023电连接以构成电极，该电极的表面裸露区域构成绑定电极107。第一电极1033和第二电极1023均包括靠近功能区E的第一端P。第一电极1033和第二电极1023的第一端P在衬底101上的正投影落在第一绝缘层105的主体部1051在衬底101上的正投影内。在一些实施例中，第一绝缘层105的开口1052暴露每个第一电极1033的除第一端P之外的其余区域。
属于第一导电层102且位于功能区E的驱动电压信号线VLED和公共电压信号线111在电极的第一端P处与电极绑定连接。如前所述，相关技术中，驱动电压信号线VLED和公共电压信号线111由于在第一端P处的表面裸露而容易导致化镍金的异常生长。而在本公开的实施例提供的布线基板200中，电极包括第二电极1023和位于第二电极1023远离衬底101一侧的第一电极1033，电极的第一端P在衬底101上的正投影落在第一绝缘层105的主体部1051在衬底101上的正投影内，也就是说，第一绝缘层105的主体部1051与第二电极1023之间至少间隔有第一电极1033。通过这样的布置方式，在对第一绝缘层105进行刻蚀时，即使刻蚀时间增加，也顶多只是可能导致第一电极1033背离衬底101的表面被过刻，但是由于具有较厚厚度(相比于第二绝缘层104的厚度)的第一电极1033对第二电极1023进行遮挡和保护，因此第二电极1023的第一端P处不会被刻蚀到，从而不会使第二电极 1023的第一端P的表面裸露。相应地，即各个信号线的第二电极1023的第一端不会被暴露，从而不会发生化镍金的异常生长。
在一些实施例中，第一电极1033的第一端P沿第一方向D1的长度L1为30～60微米，第一电极1033沿第一方向D1的长度L2为1050～1100微米，第二电极1023沿第一方向D1的长度L3为1066～1116微米。在一些实施例中，长度L1与长度L2的比值在2％～6％之间，长度L1与长度L3的比值在2％～6％之间。
在一些实施例中，第二绝缘层104在绑定区B内包括多个过孔1043，多个过孔1043与多个电极一一对应，并且每个过孔1043在衬底101上的正投影落在相应的一个电极的第一电极1033在衬底101上的正投影内。如图5B所示，在一个示例中，第二绝缘层104沿第一方向D1延伸并覆盖第一导电层102位于绑定区B的第二电极1023的部分表面，例如可以覆盖并保护第二电极1023的靠近功能区E的第一端P的部分表面，例如W1为22μm左右。
需要说明的是，图5A仅示出了布线基板200在部分区域内的结构示意图，该示意图没有示出第三部1022与位于功能区E的各种信号线的电连接关系。事实上，在布线基板200中，第三部1022与位于第一导电层102中的各种信号线(例如电源信号线103、地址信号线108、反馈信号线110、公共电压信号线111和驱动电压信号线VLED)电连接。
图6A示出了布线基板300在绑定区B和功能区E内的部分结构的平面示意图，图6B示出了沿着图6A的CC’线截取的剖面图。为了简洁起见，布线基板300与布线基板100的相同之处不再描述，下文仅描述布线基板300与布线基板100的不同之处。
图6A示出的布线基板300包括衬底101、第一导电层102、第二导电层103、第一绝缘层105以及第二绝缘层104等结构。与布线基板100不同，布线基板200的第一导电层102布置在功能区E和绑定区B内，第一导电层102包括位于绑定区B内的第三部1022，第三部1022包括沿第一方向D1延伸的多个第二电极1023。第二导电层103包括位于功能区E内的第一部1031和位于绑定区B内的第二部1032，第二部1032包括沿第一方向D1延伸的多个第一电极1033。多个第一电极1033与多个第二电极1023一一对应，并且每个第二电极1023在衬 底101上的正投影落在相应一个第一电极1033在衬底101上的正投影内，并且每个第一电极1033和与该第一电极1033相应的一个第二电极1023电连接以构成电极，电极表面裸露的区域构成绑定电极。第一电极1033和第二电极1023均包括靠近功能区E的第一端P。第一电极1033的第一端P在衬底101上的正投影落在第一绝缘层105的主体部1051在衬底101上的正投影内。通过这样的布置方式，在对第一绝缘层105进行刻蚀时，即使刻蚀时间增加，也顶多只是可能导致第一电极1033背离衬底101的表面被过刻，但是由于第一电极1033相比于第二绝缘层104具有较厚厚度，第一电极1033可以在刻蚀过程中实现对第二电极1023的遮挡和保护，因此第二电极1023的第一端P的侧表面S32不会被刻蚀到，从而不会使侧表面S32裸露。即各个信号线的第二电极1023的第一端不会被暴露，从而不会发生化镍金的异常生长。
如图6A所示，每个第二电极1023包括沿第一方向D1延伸且沿与第一方向D1交叉的第二方向D2排布的多个齿状结构1023A。每个第二电极1023还包括沿第二方向D2布置的连接结构1023B，属于同一个信号线的多个齿状结构1023A通过连接结构1023B相互连接，连接结构1023B可以与该信号线布置在功能区E中的部分具有相同的线宽。假设两个金属层具有相同的表面面积，其中厚度较大者的表面粗糙度也较大。两个金属层在直接接触时容易在接触表面产生横向滑切力，使得两者之间的附着力变差，从而产生膜层脱落问题。在本公开的实施例提供的布线基板300中，将厚度较大的第二电极1023中与第一电极1033直接接触的区域形状设计成梳状，可以增大第二电极1023与第一电极1033之间的接触面积，从而减少两者之间的滑切力，增大第二电极1023与第一电极1033之间的附着力，避免第二电极1023与第一电极1033之间产生膜层脱落问题。
每个齿状结构1023A包括面向第二导电层103的第二表面S31和与第二表面S31衔接的侧表面S32，第二绝缘层104的过孔1043至少暴露每个齿状结构1023A的侧表面S32，使得第一电极1033经由第二绝缘层104中的过孔1043与齿状结构1023A的侧表面S32直接接触。换句话说，第二绝缘层104不覆盖齿状结构1023A的侧表面S32。通过这样的布置方式，第二绝缘层104不会在齿状结构1023A的侧表面 S32处发生断裂，从而第一电极1033不会由于接触到断裂的第二绝缘层104而与第二绝缘层104发生膜层脱落；进一步地，由于第二绝缘层104不会在齿状结构1023A的侧表面S32处断裂，因此齿状结构1023A的侧表面S32不会被暴露发生氧化而产生氧化物，从而不会导致第一电极1033在该处出现鼓包，进而不会导致第一电极1033与第二电极1023之间出现膜层脱落问题。
如图6A和6B所示，在绑定区B内，第一绝缘层105包括多个开口1052，多个开口1052与多个第一电极1033一一对应，并且每个开口1052在衬底101上的正投影落在与该开口1052对应的一个第一电极1033在衬底101上的正投影内。每个第一电极1033还包括与第一端P相对的第二端Q，每个第一电极1033的第一端P和第二端Q在衬底101上的正投影均落在第一绝缘层105的主体部1051在衬底101上的正投影内。通过使开口1052的面积小于第一电极1033的面积，可以使第一电极1033的第一端P和第二端Q均被第一绝缘层105的主体部1051遮盖，从而增强绑定电极107的防腐蚀能力。
需要说明的是，图6A仅示出了布线基板300在部分区域内的结构示意图，该示意图没有示出第三部1022与位于功能区E的各种信号线的电连接关系。事实上，在布线基板300中，第三部1022与位于第一导电层102中的各种信号线(例如电源信号线103、地址信号线108、反馈信号线110、公共电压信号线111和驱动电压信号线VLED)电连接。
图7A示出了布线基板400在绑定区B和功能区E内的部分结构的平面示意图，图7B示出了沿着图7A的DD’线截取的剖面图。除了第一绝缘层105的开口1052与布线基板300不同之外，布线基板400的结构与布线基板300的结构基本相同。为了简洁起见，下文仅描述布线基板400与布线基板300的不同之处。
如图7A和7B所示，在绑定区B内，第一绝缘层105包括多个开口1052，多个开口1052与多个第一电极1033一一对应，并且每个开口1052在衬底101上的正投影与该开口1052对应的一个第一电极1033在衬底101上的正投影部分地交叠。每个第一电极1033还包括与第一端P相对的第二端Q，每个第一电极1033的第一端P在衬底101上的正投影落在第一绝缘层105的主体部1051在衬底101上的正投影内， 每个第一电极1033的第二端Q被一个开口1052暴露。通过这样的布置方式，可以使第一绝缘层105的主体部1051不设置在第一电极1033的第二端Q，从而可以有效减少因第一绝缘层105的存在而产生的膜层脱落问题。
需要说明的是，图7A仅示出了布线基板400在部分区域内的结构示意图，该示意图没有示出第三部1022与位于功能区E的各种信号线的电连接关系。事实上，在布线基板400中，第三部1022与位于第一导电层102中的各种信号线(例如电源信号线103、地址信号线108、反馈信号线110、公共电压信号线111和驱动电压信号线VLED)电连接。
图8A示出了布线基板500在绑定区B和功能区E内的部分结构的平面示意图，图8B示出了沿着图8A的EE’线截取的剖面图。为了简洁起见，布线基板500与布线基板100的相同之处不再描述，下文仅描述布线基板500与布线基板100的不同之处。
图8A示出的布线基板500包括衬底101、第一导电层102、第二导电层103、第一绝缘层105以及第二绝缘层104等结构。与布线基板100不同，布线基板500的第一导电层102布置在功能区E和绑定区B内，第一导电层102包括位于绑定区B内的第三部1022，第三部1022包括沿第一方向D1延伸的多个第二电极1023。第二导电层103包括位于功能区E内的第一部1031和位于绑定区B内的第二部1032，第二部1032包括沿第一方向D1延伸的多个第一电极1033。多个第一电极1033与多个第二电极1023一一对应，并且每个第一电极1033在衬底101上的正投影落在相应一个第二电极1023在衬底101上的正投影内，并且每个第一电极1033和与该第一电极1033相应的一个第二电极1023构成电极，该电极中表面裸露的区域构成绑定电极107。电极包括靠近功能区E的第一端P。电极的第一端P在衬底101上的正投影落在第一绝缘层105的主体部1051在衬底101上的正投影内。通过这样的布置方式，在对第一绝缘层105进行刻蚀时，即使刻蚀时间增加，也顶多只是可能导致第一电极1033背离衬底101的表面被过刻，但是由于第一电极1033的厚度大于第二绝缘层104的厚度，第一电极1033对第二电极1023具有遮挡和保护作用，因此第二电极1023的第一端P处不会被刻蚀到，从而不会使第二电极1023的第一端P被暴露。 即各个信号线的第二电极1023的第一端不会被暴露，从而不会发生化镍金的异常生长。
需要说明的是，图8A仅示出了布线基板500在部分区域内的结构示意图，该示意图没有示出第三部1022与位于功能区E的各种信号线的电连接关系。事实上，在布线基板500中，第三部1022与位于第一导电层102中的各种信号线(例如电源信号线103、地址信号线108、反馈信号线110、公共电压信号线111和驱动电压信号线VLED)电连接。另外，第二绝缘层104仅布置在功能区E内而未布置在绑定区B内，因此，第二绝缘层104在衬底101上的正投影与第一电极1033和第二电极1023在衬底101上的正投影不交叠，构成每个电极的第一电极1033与第二电极1023直接接触。通过不在绑定区B内设置第二绝缘层104，可以有效减少绑定区B内的多个绝缘层叠加引起的膜层脱落问题。
在绑定区B内，第一绝缘层105包括多个开口1052，多个开口1052与多个电极一一对应，并且每个开口1052在衬底101上的正投影落在与该开口1052对应的一个电极在衬底101上的正投影内。每个第一电极1033和与该第一电极1033相应的一个第二电极1023构成的电极还包括与第一端P相对的第二端Q，每个电极的第一端P和第二端Q在衬底101上的正投影均落在第一绝缘层105的主体部1051在衬底101上的正投影内。如图8B所示，在一个示例中，第一绝缘层105的主体部1051与第一电极1033沿第二方向D2的重叠宽度W2为30μm左右。通过使开口1052的面积小于第一电极1033的面积，可以使电极的第一端P和第二端Q均被第一绝缘层105的主体部1051遮盖，从而增强电极的防腐蚀能力。
图9A示出了布线基板600在绑定区B和功能区E内的部分结构的平面示意图，图9B示出了沿着图9A的FF’线截取的剖面图。为了简洁起见，布线基板600与布线基板100的相同之处不再描述，下文仅描述布线基板600与布线基板100的不同之处。
图9A示出的布线基板600包括衬底101、第一导电层102、第二导电层103、第一绝缘层105以及第二绝缘层104等结构。与布线基板100不同，布线基板600的第一导电层102布置在功能区E和绑定区B内，第一导电层102包括位于绑定区B内的第三部1022，第三部1022 包括沿第一方向D1延伸的多个第二电极1023。需要说明的是，图9A仅示出了布线基板600在部分区域内的结构示意图，该示意图没有示出第三部1022与位于功能区E的各种信号线的电连接关系。事实上，在布线基板600中，第三部1022与位于第一导电层102中的各种信号线(例如电源信号线103、地址信号线108、反馈信号线110、公共电压信号线111和驱动电压信号线VLED)电连接。
第二导电层103包括位于功能区E内的第一部1031和位于绑定区B内的第二部1032，第二部1032包括沿第一方向D1延伸的多个第一电极1033。多个第一电极1033与多个第二电极1023一一对应，并且每个第一电极1033在衬底101上的正投影落在相应一个第二电极1023在衬底101上的正投影内，并且每个第一电极1033和与该第一电极1033相应的一个第二电极1023构成电极，该电极中表面裸露的区域构成绑定电极107。电极包括靠近功能区E的第一端P。
如图9A所示，第一绝缘层105的主体部1051包括沿第一方向D1延伸且在第二方向D2上彼此间隔的多个子绝缘部1054，多个子绝缘部1054中的两个相邻子绝缘部1054在衬底101上的正投影与一个电极在衬底101上的正投影分别部分地交叠。各个电极在第二方向D2上彼此间隔布置，各个子绝缘部1054在第二方向D2上也彼此间隔布置，而每个电极对应两个子绝缘部1054，因此相邻两个电极之间的间隔区域内必然有一部分区域是不存在子绝缘部1054的，如图9A中的区域W所示，该区域W处不存在子绝缘部1054。通过不在该区域W布置第一绝缘层105，可以减少该区域W处的绝缘层的堆叠厚度，从而可以减轻由于绝缘层堆叠厚度过大导致的膜层脱落问题。
如图9A所示，由每个第一电极1033和与该第一电极1033相应的一个第二电极1023构成的电极的第一端P在衬底101上的正投影与该两个相邻子绝缘部1054在衬底101上的正投影部分地交叠，因此两个相邻子绝缘部1054可以在一定程度上保护该电极的第一端P。在对第一绝缘层105进行刻蚀时，即使刻蚀时间增加，顶多只是可能导致第一电极1033背离衬底101的表面被过刻，但是由于电极的厚度大于第二绝缘层104的厚度，第一电极1033可以对第二电极1023进行至少部分地遮挡和保护，第二电极1023的第一端P处基本上不会被刻蚀到，从而第二电极1023的第一端P的表面基本不会裸露。即各个信号线的 第二电极1023的第一端P基本不会被暴露，从而基本不会发生化镍金的异常生长。
如图9B所示，在一个示例中，第一绝缘层105的子绝缘部1054与第一电极1033沿第二方向D2的重叠宽度W3为15μm左右，从而保护第一电极1033沿第一方向D1延伸的两个侧边。第二绝缘层104与第二电极1023沿第二方向D2的重叠宽度W4为22μm左右，从而保护第二电极1023沿第一方向D1延伸的两个侧边。
图10A示出了布线基板700在绑定区B和功能区E内的部分结构的平面示意图，图10B示出了沿着图10A的GG’线截取的剖面图。为了简洁起见，布线基板700与布线基板100的相同之处不再描述，下文仅描述布线基板700与布线基板100的不同之处。
图10A示出的布线基板700包括衬底101、第一导电层102、第二导电层103、第一绝缘层105以及第二绝缘层104等结构。与布线基板100不同，布线基板700的第一导电层102布置在功能区E和绑定区B内，第一导电层102包括位于绑定区B内的第三部1022，第三部1022包括沿第一方向D1延伸的多个第二电极1023，第二电极1023的表面裸露的区域构成绑定电极107。第二电极1023包括靠近功能区E的第一端P。在一些实施例中，布线基板700的第二导电层103仅布置在功能区E内，而不布置在绑定区B内。在替代的实施例中，第二导电层103既不设置在功能区E内也不设置在绑定区B内，即布线基板700仅包括第一导电层102而不包括第二导电层103。需要说明的是，图10A仅示出了布线基板700在部分区域内的结构示意图，该示意图没有示出第三部1022与位于功能区E的各种信号线的电连接关系。事实上，在布线基板700中，第三部1022与位于第一导电层102中的各种信号线(例如电源信号线103、地址信号线108、反馈信号线110、公共电压信号线111和驱动电压信号线VLED)电连接。
第二绝缘层104包括多个过孔1043，多个过孔1043与多个第二电极1023一一对应，并且多个过孔1043中的每一个在衬底101上的正投影落在与该过孔1043对应的一个第二电极1023在衬底101上的正投影内。
如图10A所示，第一绝缘层105的主体部1051包括沿第一方向D1延伸且在第二方向D2上彼此间隔的多个子绝缘部1054，多个子绝 缘部1054中的两个相邻子绝缘部1054在衬底101上的正投影与一个第二电极1023在衬底101上的正投影分别部分地交叠，并且第二电极1023的第一端P在衬底101上的正投影与两个相邻子绝缘部1054在衬底101上的正投影部分地交叠。各个第二电极1023在第二方向D2上彼此间隔布置，各个子绝缘部1054在第二方向D2上也彼此间隔布置，而每个第二电极1023对应两个子绝缘部1054，因此相邻两个第二电极1023之间的间隔区域内必然有一部分区域是不存在子绝缘部1054的，如图10A中的区域W所示，该区域W处不存在子绝缘部1054。通过不在该区域W布置第一绝缘层105，可以减少该区域W处的绝缘层的堆叠厚度，从而可以减轻由于绝缘层堆叠厚度过大导致的膜层脱落问题。
在一个示例中，第一绝缘层105的子绝缘部1054与第二电极1023沿第二方向D2的重叠宽度为22μm左右，从而保护第二电极1023沿第一方向D1延伸的两个侧边。第二绝缘层104与第二电极1023沿第二方向D2的重叠宽度为15～20μm左右，从而保护第二电极1023沿第一方向D1延伸的两个侧边。
图11A示出了布线基板800在绑定区B内的平面示意图，图11B示出了沿着图11A的HH’线截取的剖面图。为了简洁起见，布线基板800与布线基板100的相同之处不再描述，下文仅描述布线基板800与布线基板100的不同之处。
图11A示出的布线基板800包括衬底101、第一导电层102、第二导电层103、第一绝缘层105以及第二绝缘层104等结构。与布线基板100不同，布线基板800的第一绝缘层105以及第二绝缘层104仅布置在功能区E内，而不布置在绑定区B内，第一导电层102布置在功能区E和绑定区B内。第一导电层102包括位于绑定区B内的第三部1022，第三部1022包括沿第一方向D1延伸的多个第二电极1023，第二电极1023构成绑定电极107。在一些实施例中，布线基板800的第二导电层103仅布置在功能区E内，而不布置在绑定区B内。在替代的实施例中，第二导电层103既不设置在功能区E内也不设置在绑定区B内，即布线基板800仅包括第一导电层102而不包括第二导电层103。需要说明的是，图11A仅示出了布线基板800在部分区域内的结构示意图，该示意图没有示出第三部1022与位于功能区E的各种信号线的电连接 关系。事实上，在布线基板800中，第三部1022与位于第一导电层102中的各种信号线(例如电源信号线103、地址信号线108、反馈信号线110、公共电压信号线111和驱动电压信号线VLED)电连接。
通过将第一绝缘层105和第二绝缘层104位于绑定区B内的部分全部刻蚀去除，可以避免多个绝缘层在绑定区B内堆叠的情况，从而可以防止由于多个绝缘层堆叠引起的膜层脱落问题。
需要说明的是，对于图5A-5B示出的布线基板200、图6A-6B示出的布线基板300、图7A-7B示出的布线基板400、图8A-8B示出的布线基板500、图9A-9B示出的布线基板600、图10A-10B示出的布线基板700、以及图11A-11B示出的布线基板800，这些布线基板的第一导电层102包括位于功能区E的多种类型的信号线，例如电源信号线103、地址信号线108、反馈信号线110、公共电压信号线111和驱动电压信号线VLED等。这些信号线沿第二方向D2通常具有不同的线宽，例如公共电压信号线111和驱动电压信号线VLED中的每一条沿第二方向D2的线宽通常大于电源信号线103、地址信号线108以及反馈信号线110中的任意一条沿第二方向D2的线宽。对于具有不同线宽的信号线，其各自的第三部1022包括的第二电极1023的个数并不相同。例如，如果某信号线(例如电源信号线103、地址信号线108、反馈信号线110)在功能区E沿第二方向D2的线宽与绑定区中的电极150沿第二方向D2的线宽相当，那么该信号线在绑定区B的第三部1022仅包括一个第二电极1023；如果某信号线(例如驱动电压信号线VLED和公共电压信号线111)在功能区E沿第二方向D2的线宽远大于绑定区中的电极150沿第二方向D2的线宽，那么该信号线在绑定区B的第三部1022包括多个第二电极1023，在一些实施例中，属于同一信号线的多个第二电极1023在第一端相互连接。
根据本公开的另一方面，提供了一种发光基板，图12示出了发光基板900的框图，该发光基板900包括在前面任一个实施例描述的布线基板以及设置在功能区E内的多个发光元件和设置在绑定区B内的电路板。在一些实施例中，每个发光元件可以为发光二极管(LED)、次毫米发光二极管(Mini LED)或微型发光二极管(Mirco LED)。利用Mini LED作为发光元件，可以实现高动态范围(High-Dynamic Range，HDR)显示。当这种发光基板应用于显示装置中时，可以显著提升显示 装置的对比度。电路板例如可以是柔性电路板(FPC)。FPC的一端与印刷电路板(PCBA)连接，FPC的另一端例如通过覆晶薄膜(COF)连接到发光基板900上的绑定电极107。PCBA上的IC的控制信号经由FPC传递到绑定电极107。发光基板900上的多条信号线一端绑定到绑定电极107，另一端与发光元件电连接。因此，控制信号可以经由信号线传递到发光元件以控制发光元件发光。
本公开实施例提供的发光基板900可以与前面各个实施例描述的布线基板具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述发光基板900的技术效果。
根据本公开的又一方面，提供了一种显示装置，图13示出了显示装置1000的框图，该显示装置1000包括在前面任一个实施例中描述的布线基板或发光基板。在一些实施例中，该显示装置1000可以为液晶显示装置，其包括液晶面板和设置在该液晶面板的非显示侧的背光源，背光源包括在前面任一个实施例中描述的布线基板，例如可以用于实现HDR调光以用于显示操作。该液晶显示装置可以具有更均匀的背光亮度，具有更好的显示对比度。显示装置1000可以为任意适当的显示装置，包括但不限于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子书等任何具有显示功能的产品或部件。
由于显示装置1000可以与前面各个实施例描述的布线基板具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述显示装置1000的技术效果。
根据本公开的再一方面，提供了一种制造布线基板的方法，图14示出了该方法1100的流程图，该方法1100可以适用于前面任一实施例描述的布线基板。方法1100可以包括以下步骤。
S1101：提供衬底101，衬底101包括功能区E和绑定区B。
衬底101可以为柔性或刚性材料，具体的，可以为PEN树脂、硅胶树脂、聚酰亚胺、玻璃、石英、塑料等，本公开的实施例对衬底101的材料不作限制。
S1102：在衬底101上施加第一导电膜，通过第一掩膜对第一导电膜进行构图以形成第一导电层102，第一导电层102至少位于功能区E内。
在衬底101上通过磁控溅射方法或电镀方法施加第一导电膜，通 过利用第一掩膜对第一导电膜进行构图以形成第一导电层102。第一导电层102可以包括如前所述的驱动电压信号线、选址信号线、电源信号线、数据驱动信号线、公共电压信号线、反馈信号线以及可选的第二电极1023。在一个示例中，第一导电层102可以是MoNb/Cu/MoNb的叠层。在替代的实施例中，第一导电层102可以是Mo/Cu/Mo的叠层。
S1103：在第一导电层102远离衬底101的一侧施加第二导电膜，通过第二掩膜对第二导电膜进行构图以形成第二导电层103，第二导电层103至少位于功能区B内且与第一导电层102电连接。
在第一导电层102远离衬底101的一侧通过磁控溅射方法或电镀方法施加第二导电膜，通过利用第二掩膜对第二导电膜进行构图以形成第二导电层103。第二导电层103可以包括如前所述的第一焊盘组102、第二焊盘组104以及可选的第一电极1033，第一焊盘组102可以用于安装微型驱动芯片002，第二焊盘组104可以用于安装电子元件003。在一个示例中，第二导电层103可以通过如下工艺来形成：首先在第一导电层102远离衬底101的一侧形成厚度大约为
Figure PCTCN2022096785-appb-000005
的MoNb层，然后在MoNb层上形成厚度大约为
Figure PCTCN2022096785-appb-000006
的Cu层，最后在Cu层上形成厚度大约为
Figure PCTCN2022096785-appb-000007
的MoNb层。在替代的示例中，第二导电层103可以通过如下工艺来形成：首先在第一导电层102远离衬底101的一侧形成厚度大约为
Figure PCTCN2022096785-appb-000008
的Mo层，然后在Mo层上形成厚度大约为
Figure PCTCN2022096785-appb-000009
的Cu层，最后在Cu层上形成厚度大约为
Figure PCTCN2022096785-appb-000010
的Mo层。
S1104：在第二导电层103远离衬底101的一侧施加第一绝缘膜，通过第三掩膜对第一绝缘膜进行构图以形成包括主体部1051和开口1052的第一绝缘层105，其中，第一导电层102和第二导电层103中的至少一个包括位于绑定区B内且沿第一方向D1延伸的多个电极，多个电极中的每一个包括在第一方向D1上邻近功能区E的第一端P，第一绝缘层105的主体部1051在衬底101上的正投影与每个电极的第一端P在衬底101上的正投影至少部分地交叠。
可以在第二导电层103远离衬底101的一侧通过磁控溅射方法形成第一绝缘层105。通过使第一绝缘层105的主体部1051在衬底101上的正投影与每个电极的第一端P在衬底101上的正投影至少部分地 交叠，可以防止第一端P处的信号线发生化镍金的异常生长。第一绝缘层105的材料可以是有机材料、无机材料或者有机材料和无机材料的结合。第一绝缘层105可以是单个膜层，也可以包括多个膜层。
在一些实施例中，在形成第一导电层102之后且在形成第二导电层103之前，还可以包括：在第一导电层102远离衬底101的一侧通过磁控溅射的方法施加第二绝缘膜，通过第四掩膜对第二绝缘膜进行构图以形成第二绝缘层104。第二绝缘层104的材料可以是有机材料、无机材料或者有机材料和无机材料的结合。第二绝缘层104可以是单个膜层，也可以包括多个膜层。在一个示例中，第二绝缘层104包括第一子绝缘层1041和第二子绝缘层1042。
在第二绝缘层104包括第一子绝缘层1041和第二子绝缘层1042的实施例中，还可以通过第五掩膜在第一子绝缘层1041和第二子绝缘层1042之间形成OC(Over Coating)层，该OC层可以是一种由有机材料构成的负性光刻胶。OC层的厚度大于第一绝缘层105和第二绝缘层104的厚度，并且通常仅布置在功能区E。在一个示例中，OC层的厚度在3～4微米。较厚的OC层可以用来包裹第一导电层102和第二导电层103之间的颗粒，防止颗粒刺穿第一导电层102和第二导电层103而导致两者之间发生短路。另外，OC层可以起到平坦化作用。
在一些实施例中，在形成第一导电层102之前，还可以包括：在衬底101上例如通过磁控溅射方法形成缓冲层106。缓冲层106可以用来减小在后续制备第一导电层102和第二导电层103时对衬底101造成的应力，从而可以避免衬底101发生弯曲变形。缓冲层106还可以避免衬底101中的杂质对后续形成的第一导电层102和第二导电层103的导电性能的不利影响。缓冲层112可以是任意适当的材料，例如，可以是SiN、SiO或SiON。
该方法1100可以使用较少的掩膜板(例如五个掩膜板)来制备布线基板，相比于相关技术中至少需要七个掩膜板来制备布线基板，本公开实施例提供的方法1100可以减少所需掩膜板的数量，简化工艺制程，降低生产成本。该方法1100实现的其他技术效果可以参考前面各个实施例描述的布线基板的技术效果，因此，出于简洁的目的，此处不再重复描述。
将理解的是，尽管术语第一、第二、第三等在本文中可以用来描 述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，上面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“行”、“列”、“在...之下”、“在...之上”、“左”、“右”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在...之下”可以涵盖在...之上和在...之下的取向两者。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在...上”或“直接在...上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此。任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种布线基板，包括：
    衬底，包括功能区和绑定区；
    第一导电层，位于所述衬底上且至少位于所述功能区内；
    第二导电层，位于所述第一导电层远离所述衬底的一侧且至少位于所述功能区内，所述第二导电层与所述第一导电层电连接；以及
    第一绝缘层，位于所述第二导电层远离所述衬底的一侧且包括主体部和开口，
    其中，所述第一导电层和所述第二导电层中的至少一个包括位于所述绑定区内且沿第一方向延伸的多个电极，所述多个电极中的每一个包括在所述第一方向上邻近所述功能区的第一端，所述第一绝缘层的主体部在所述衬底上的正投影与每个电极的第一端在所述衬底上的正投影至少部分地交叠。
  2. 根据权利要求1所述的布线基板，还包括位于所述第一导电层与所述第二导电层之间的第二绝缘层，所述第二导电层经由所述第二绝缘层中的过孔与所述第一导电层接触。
  3. 根据权利要求2所述的布线基板，其中，所述第二导电层包括第一部和第二部，所述第一部位于所述功能区内，所述第二部位于所述绑定区内，所述第二部包括沿所述第一方向延伸的多个第一电极，所述多个第一电极中的每一个包括所述第一端。
  4. 根据权利要求3所述的布线基板，其中，所述第二导电层包括背离所述衬底的第一表面，所述第一表面位于所述第一部的部分到所述衬底的距离大于所述第一表面位于所述第二部的部分到所述衬底的距离，所述第一绝缘层的开口在所述衬底上的正投影与所述第二部在所述衬底上的正投影至少部分地交叠。
  5. 根据权利要求4所述的布线基板，其中，所述第一绝缘层的开口暴露每个第一电极的除所述第一端之外的其余部分。
  6. 根据权利要求5所述的布线基板，其中，在所述绑定区，所述第一绝缘层的开口在所述衬底上的正投影与所述第二绝缘层在所述衬底上的正投影不交叠。
  7. 根据权利要求3-6中任一项所述的布线基板，其中，所述第一 导电层仅位于所述功能区内，所述第一导电层在所述衬底上的正投影与所述第二导电层的第一部在所述衬底上的正投影部分地交叠。
  8. 根据权利要求7所述的布线基板，其中，在所述功能区，所述第一导电层包括面向所述第二导电层的第二表面和与所述第二表面衔接且朝向所述绑定区的侧表面，所述第二导电层与所述第一导电层的侧表面直接接触。
  9. 根据权利要求3所述的布线基板，
    其中，所述第一导电层包括位于所述绑定区内的第三部，所述第三部包括沿所述第一方向延伸的多个第二电极，所述多个第一电极与所述多个第二电极一一对应，并且所述多个第一电极中的每一个在所述衬底上的正投影与所述多个第二电极中的相应一个在所述衬底上的正投影至少部分地交叠，并且
    其中，每个第一电极和与该第一电极相应的一个第二电极电连接且构成所述电极，并且电连接的第一电极和第二电极均包括所述第一端。
  10. 根据权利要求9所述的布线基板，其中，所述第一电极和所述第二电极的第一端在所述衬底上的正投影落在所述第一绝缘层的主体部在所述衬底上的正投影内。
  11. 根据权利要求10所述的布线基板，其中，所述第一绝缘层的开口暴露每个第一电极的除所述第一端之外的其余部分。
  12. 根据权利要求10所述的布线基板，其中，每个第二电极包括沿所述第一方向延伸且沿第二方向排布的多个齿状结构，其中所述第二方向与所述第一方向交叉。
  13. 根据权利要求12所述的布线基板，其中，所述多个齿状结构中的每一个包括面向所述第二导电层的第二表面和与所述第二表面衔接的侧表面，所述第一电极与所述齿状结构的侧表面直接接触。
  14. 根据权利要求12或13所述的布线基板，
    其中，在所述绑定区，所述第一绝缘层包括多个开口，所述多个开口与所述多个电极一一对应，并且所述多个开口中的每一个在所述衬底上的正投影落在与该开口对应的一个第一电极在所述衬底上的正投影内，并且
    其中，所述电极还包括与所述第一端相对的第二端，所述电极的 第二端在所述衬底上的正投影落在所述第一绝缘层的主体部在所述衬底上的正投影内。
  15. 根据权利要求12或13所述的布线基板，
    其中，在所述绑定区，所述第一绝缘层包括多个开口，所述多个开口与所述多个电极一一对应，并且所述多个开口中的每一个在所述衬底上的正投影和与该开口对应的一个电极在所述衬底上的正投影部分地交叠，并且
    其中，所述电极还包括与所述第一端相对的第二端，所述第二端的一部分被与该电极对应的一个开口暴露。
  16. 根据权利要求10所述的布线基板，其中，所述第二绝缘层在所述衬底上的正投影与所述第一电极和第二电极在所述衬底上的正投影不交叠，并且每个电极的第一电极与第二电极直接接触。
  17. 根据权利要求16所述的布线基板，
    其中，在所述绑定区，所述第一绝缘层包括多个开口，所述多个开口与所述多个电极一一对应，并且所述多个开口中的每一个在所述衬底上的正投影落在与该开口对应的一个电极的第一电极在所述衬底上的正投影内，并且
    其中，所述电极还包括与所述第一端相对的第二端，所述电极的第二端在所述衬底上的正投影落在所述第一绝缘层的主体部在所述衬底上的正投影内。
  18. 根据权利要求9所述的布线基板，其中，对于每个电极，所述第一电极在所述衬底上的正投影落在所述第二电极在所述衬底上的正投影内。
  19. 根据权利要求18所述的布线基板，其中，所述第一绝缘层的主体部包括沿所述第一方向延伸且在与所述第一方向交叉的第二方向上彼此间隔的多个子绝缘部，所述多个子绝缘部中的两个相邻子绝缘部在所述衬底上的正投影与一个电极在所述衬底上的正投影分别部分地交叠，并且所述第一电极和所述第二电极的第一端在所述衬底上的正投影与所述两个相邻子绝缘部在所述衬底上的正投影部分地交叠。
  20. 根据权利要求2所述的布线基板，其中，所述第二导电层仅布置在所述功能区内，所述第一导电层包括布置在所述绑定区内的第三部，所述第三部包括沿所述第一方向延伸的多个第二电极，所述多个 第二电极中的每一个包括所述第一端。
  21. 根据权利要求20所述的布线基板，其中，所述第二绝缘层包括多个过孔，所述多个过孔与所述多个第二电极一一对应，并且所述多个过孔中的每一个在所述衬底上的正投影落在与该过孔对应的一个第二电极在所述衬底上的正投影内。
  22. 根据权利要求21所述的布线基板，其中，所述第一绝缘层的主体部包括沿所述第一方向延伸且在与所述第一方向交叉的第二方向上彼此间隔的多个子绝缘部，所述多个子绝缘部中的两个相邻子绝缘部在所述衬底上的正投影与一个第二电极在所述衬底上的正投影分别部分地交叠，并且所述第二电极的第一端在所述衬底上的正投影与所述两个相邻子绝缘部在所述衬底上的正投影部分地交叠。
  23. 一种发光基板，包括根据权利要求1-22中任一项所述的布线基板以及设置在所述功能区内的多个发光元件和设置在所述绑定区内的电路板。
  24. 一种显示装置，包括根据权利要求1-22中任一项所述的布线基板或权利要求23所述的发光基板。
  25. 一种制造布线基板的方法，包括：
    提供衬底，所述衬底包括功能区和绑定区；
    在所述衬底上施加第一导电膜，通过第一掩膜对所述第一导电膜进行构图以形成第一导电层，所述第一导电层至少位于所述功能区内；
    在所述第一导电层远离所述衬底的一侧施加第二导电膜，通过第二掩膜对所述第二导电膜进行构图以形成第二导电层，所述第二导电层至少位于所述功能区内且与所述第一导电层电连接；以及
    在所述第二导电层远离所述衬底的一侧施加第一绝缘膜，通过第三掩膜对所述第一绝缘膜进行构图以形成包括主体部和开口的第一绝缘层，
    其中，所述第一导电层和所述第二导电层中的至少一个包括位于所述绑定区内且沿第一方向延伸的多个电极，所述多个电极中的每一个包括在所述第一方向上邻近所述功能区的第一端，所述第一绝缘层的主体部在所述衬底上的正投影与每个电极的第一端在所述衬底上的正投影至少部分地交叠。
  26. 根据权利要求25所述的方法，在所述衬底上形成第一导电层 的步骤之后，还包括：
    在所述第一导电层远离所述衬底的一侧施加第二绝缘膜，通过第四掩膜对所述第二绝缘膜进行构图以形成第二绝缘层；以及
    在所述第二绝缘层远离所述衬底的一侧形成所述第二导电层。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599823A (zh) * 2020-05-29 2020-08-28 京东方科技集团股份有限公司 阵列基板及显示装置
CN111970816A (zh) * 2020-08-27 2020-11-20 合肥鑫晟光电科技有限公司 驱动电路背板、及其制备方法、背光模组
CN113066849A (zh) * 2021-03-31 2021-07-02 京东方科技集团股份有限公司 显示面板和显示装置
CN113782546A (zh) * 2021-08-26 2021-12-10 厦门天马微电子有限公司 显示面板和显示装置

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CN111599823A (zh) * 2020-05-29 2020-08-28 京东方科技集团股份有限公司 阵列基板及显示装置
CN111970816A (zh) * 2020-08-27 2020-11-20 合肥鑫晟光电科技有限公司 驱动电路背板、及其制备方法、背光模组
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CN113782546A (zh) * 2021-08-26 2021-12-10 厦门天马微电子有限公司 显示面板和显示装置

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