CN111599823A - 阵列基板及显示装置 - Google Patents
阵列基板及显示装置 Download PDFInfo
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- CN111599823A CN111599823A CN202010479718.9A CN202010479718A CN111599823A CN 111599823 A CN111599823 A CN 111599823A CN 202010479718 A CN202010479718 A CN 202010479718A CN 111599823 A CN111599823 A CN 111599823A
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Abstract
本公开实施例公开了一种阵列基板及显示装置,涉及显示技术领域,用于避免对源漏导电层造成腐蚀,进而避免应用有该阵列基板的显示装置出现撕膜斜纹不良,改善该显示装置的显示效果。该阵列基板,具有显示区和位于所述显示区的旁侧的绑定区。所述阵列基板包括:衬底、多个第一晶体管、以及多个导电电极。所述多个第一晶体管设置在所述衬底的一侧、且位于所述显示区,第一晶体管包括第一栅极、第一源极和第一漏极。所述多个导电引脚设置在所述衬底的一侧、且位于所述绑定区,所述多个导电引脚与所述第一栅极同层设置。所述多个导电电极分别设置在所述多个导电引脚远离所述衬底一侧表面。本公开提供的阵列基板及显示装置用于实现触控及显示。
Description
技术领域
本公开涉及显示技术领域,尤其涉及一种阵列基板及显示装置。
背景技术
液晶显示装置(Liquid Crystal Display,简称LCD)由于具有功耗小、微型化、轻薄等优点,因而得到广泛地应用。
发明内容
本公开实施例的目的在于提供一种阵列基板及显示装置,用于避免对源漏导电层造成腐蚀,进而避免应用有该阵列基板的显示装置出现撕膜斜纹不良,改善该显示装置的显示效果。
为达到上述目的,本公开实施例提供了如下技术方案:
本公开实施例的第一方面提供了一种阵列基板。所述阵列基板具有显示区和位于所述显示区的旁侧的绑定区。所述阵列基板包括:衬底、多个第一晶体管、以及多个导电电极。所述多个第一晶体管设置在所述衬底的一侧、且位于所述显示区,第一晶体管包括第一栅极、第一源极和第一漏极。所述多个导电引脚设置在所述衬底的一侧、且位于所述绑定区,所述多个导电引脚与所述第一栅极同层设置。所述多个导电电极分别设置在所述多个导电引脚远离所述衬底一侧表面。
本公开的一些实施例所提供的阵列基板,通过绑定区内的导电引脚与第一晶体管中的第一栅极同层设置,并将导电电极直接设置在导电引脚的远离衬底的一侧表面上,而未保留用于形成源漏导电层的薄膜中覆盖导电引脚的部分,这样在制备形成阵列基板的过程中,可以避免对源漏导电层造成腐蚀,进而可以避免应用有上述阵列基板的显示装置出现撕膜斜纹不良,有效改善该显示装置的显示效果。
在一些实施例中,所述阵列基板,还包括:设置在所述衬底一侧、且沿第一方向延伸的多条触控信号线。所述多条触控信号线与所述第一源极、所述第一漏极同层设置。至少一条触控信号线与一个导电引脚电连接。
在一些实施例中,所述的阵列基板,还包括:设置在所述多条触控信号线远离所述衬底一侧的多个触控电极。每个触控电极与至少一条触控信号线电连接。
在一些实施例中,所述阵列基板,还包括:设置在所述多个第一晶体管和所述多个触控电极之间的平坦层。所述平坦层具有多个第一过孔,每条触控信号线通过至少一个第一过孔与一个触控电极电连接。所述平坦层在所述衬底上的正投影与所述多个导电引脚在所述衬底上的正投影无交叠。
在一些实施例中,所述阵列基板,还包括:设置在所述多个触控电极远离或靠近所述衬底一侧的多个像素电极。每个第一晶体管的第一源极和第一漏极中的一者与一个像素电极电连接。所述多个导电电极与所述多个触控电极或所述多个像素电极同层设置。
在一些实施例中,所述阵列基板,还包括:与所述多条触控信号线同层设置、且沿第一方向延伸的多条数据线。每个第一晶体管的第一源极和第一漏极中的另一者与一条数据线电连接。至少一条数据线与一个导电引脚电连接。
在一些实施例中,所述阵列基板,还包括:多个连接部。所述导电引脚通过连接部与所述至少一条触控信号线电连接。
在一些实施例中,在所述阵列基板包括多个触控电极的情况下,所述多个连接部与所述多个触控电极同层设置、且分别与所述多个导电电极为一体结构。或者,在所述阵列基板包括多个像素电极的情况下,所述多个连接部与所述多个像素电极同层设置、且分别与所述多个导电电极为一体结构。所述连接部的一端与所述至少一条触控信号线电连接。
在一些实施例中,所述连接部包括多路复用器。所述多路复用器的输入端与一个导电引脚电连接,输出端与至少两条触控信号线电连接。
在一些实施例中,所述多路复用器包括至少两个第二晶体管,第二晶体管包括第二源极和第二漏极。所述第二源极和所述第二漏极中的一者与所述导电引脚电连接,另一者与所述至少两条触控信号线中的一条触控信号线电连接。
在一些实施例中,所述阵列基板,还包括:设置在所述第一源极和所述第一漏极所在膜层与所述第一栅极之间的绝缘层。所述绝缘层中设置有多个第二过孔,每条触控信号线通过至少一个第二过孔与一个导电引脚电连接。
在一些实施例中,所述多个导电引脚在所述衬底上的正投影,位于所述多个导电电极在所述衬底上的正投影范围内。
在一些实施例中,所述阵列基板,还包括:设置在所述第一源极和所述第一漏极所在膜层与所述第一栅极之间的绝缘层。所述绝缘层在所述衬底上的正投影与所述多个导电引脚在所述衬底上的正投影无交叠。
本公开实施例的另一方面提供了一种显示装置。所述显示装置,包括:如上述一些实施例中所述的阵列基板;与所述阵列基板相对设置的对置基板;以及,设置在所述阵列基板和所述对置基板之间的液晶层。
本公开实施例提供的显示装置所能实现的有益效果,与上述技术方案提供的阵列基板所能达到的有益效果相同,在此不做赘述。
在一些实施例中,所述显示装置,还包括:与所述阵列基板中的多个导电电极绑定的覆晶薄膜。
附图说明
为了更清楚地说明本公开中的技术方案,下面将对本公开一些实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本公开的一些实施例的附图,对于本领域普通技术人员来讲,还可以根据这些附图获得其他的附图。此外,以下描述中的附图可以视作示意图,并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程等的限制。
图1为根据相关技术中的一种触控与显示集成装置的结构图;
图2为根据本公开的一些实施例中的一种阵列基板的结构图;
图3为根据本公开的一些实施例中的另一种阵列基板的结构图;
图4为根据本公开的一些实施例中的又一种阵列基板的结构图;
图5为根据本公开的一些实施例中的又一种阵列基板的结构图;
图6为图3所示阵列基板的一种沿M-M'向的剖视图;
图7为图3所示阵列基板的另一种沿M-M'向的剖视图;
图8为图3所示阵列基板的一种沿N-N'向的剖视图;
图9为图4所示阵列基板的一种沿R-R'向的剖视图;
图10为图5所示阵列基板的一种沿S-S'向的剖视图;
图11为图5所示阵列基板的另一种沿S-S'向的剖视图;
图12为图5所示阵列基板的一种连接部的等效电路图;
图13为根据本公开的一些实施例中的一种阵列基板的制备方法的流程图;
图14为图13所示流程图中S200的一种流程图;
图15为图13所示流程图中S200的另一种流程图;
图16为根据本公开的一些实施例中的一种阵列基板的制备流程图;
图17为根据本公开的一些实施例中的一种显示装置的结构图;
图18为根据本公开的一些实施例中的另一种显示装置的结构图。
具体实施方式
下面将结合附图,对本公开一些实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本公开一部分实施例,而不是全部的实施例。基于本公开所提供的实施例,本领域普通技术人员所获得的所有其他实施例,都属于本公开保护的范围。
除非上下文另有要求,否则,在整个说明书和权利要求书中,术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思,即为“包含,但不限于”。在说明书的描述中,术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外,所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中,除非另有说明,“多个”的含义是两个或两个以上。
在描述一些实施例时,可能使用了“连接”及其衍伸的表达。例如,描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
如本文中所使用,根据上下文,术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地,根据上下文,短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言,其不排除适用于或被配置为执行额外任务或步骤的设备。
另外,“基于”的使用意味着开放和包容性,因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样,“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值,其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即,测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中,为了清楚,放大了层和区域的厚度。因此,可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此,示例性实施方式不应解释为局限于本文示出的区域的形状,而是包括因例如制造而引起的形状偏差。例如,示为矩形的蚀刻区域通常将具有弯曲的特征。因此,附图中所示的区域本质上是示意性的,且它们的形状并非旨在示出设备的区域的实际形状,并且并非旨在限制示例性实施方式的范围。
在相关技术中,LCD中可以设置有触控结构,例如可以构成触控与显示集成(Touchand Display Driver Integration,简称TDDI)装置。这样可以使得该TDDI装置既能够实现画面的显示,又能够具有触控功能。然而,在LCD中设置触控结构后,在进行显示的过程中,容易出现撕膜斜纹不良。
本公开的发明人经过大量地研究,发现了产生上述不良现象的原因。下面以如图1所示的结构为例,对产生上述不良现象的原因进行示意性说明。
在一些实施例中,TDDI装置包括显示区和位于显示区旁侧的绑定区。显示区内设置有多个晶体管(例如为薄膜晶体管),该晶体管包括同层设置的源极1'和漏极2'。触控结构包括位于显示区的多条触控信号线3'以及位于绑定区的多个导电垫4'。其中,源极1'、漏极2'、触控信号线3'与多个导电垫4'同层设置;触控信号线3'与导电垫4'的一侧设置有平坦层5'。
这样在制备上述触控结构的过程中,可以先沉积形成一导电层,然后对该导电层进行刻蚀,形成晶体管的源极1'和漏极2'以及触控结构的触控信号线3'和导电垫4',之后可以再形成平坦层5'。其中,平坦层5'未覆盖导电垫4',并暴露出导电垫4'的侧面,且平坦层5'中具有暴露触控信号线3'的表面以及源极1'和漏极2'中的一者的表面的过孔。
本公开的发明人发现,上述导电层由钛金属层、铝金属层及钛金属层依次层叠构成,在对采用构图工艺(例如为曝光、显影)形成平坦层5'的过程中,导电垫4'的侧面(该侧面的材料包括铝)可以通过显影液,与通过平坦层5'的过孔所暴露出触控信号线3'的表面以及源极1'和漏极2'中的一者的表面(该表面的材料即为钛),发生氧化还原反应(当然,导电垫4'的侧面所包括的铝也可以和导电垫4'的表面所包括的钛通过显影液发生氧化还原反应),进而对导电垫4'、触控信号线3'以及源极1'和漏极2'中的一者造成腐蚀,使得导电垫4'、触控信号线3'以及源极1'和漏极2'中的一者出现卷边现象或者金属屑残留现象,进而导致TDDI装置出现撕膜斜纹不良。
基于此,本公开的一些实施例提供了一种阵列基板100。如图2所示,该阵列基板100具有显示区A(显示区A例如具有多个子像素区域P,该多个子像素区域P可以呈阵列状排布)和位于显示区A旁侧的非显示区C,非显示区C包括绑定区B。其中,显示区A和绑定区B之间可以具有间隙。
在一些示例中,如图2~图11所示,阵列基板100包括:衬底10。
上述衬底10的结构包括多种,具体可以根据实际需要选择设置。例如,衬底10可以为空白的衬底基板。又如,衬底10可以包括空白的衬底基板以及设置在该空白的衬底基板上的功能薄膜(该功能薄膜例如为缓冲层)。
上述空白的衬底基板的类型包括多种,具体可以根据实际需要选择设置。例如,空白的衬底基板可以为PMMA(Polymethyl methacrylate,聚甲基丙烯酸甲酯)衬底基板或者玻璃衬底基板。
在一些示例中,如图2所示,阵列基板100还包括:设置在衬底10的一侧、且位于显示区A的多条数据线DL和多条栅线GL。该多条数据线DL沿第一方向X延伸,该多条栅线GL沿第二方向Y延伸。
上述多条栅线GL和上述多条数据线DL交叉且相互绝缘,限定出上述多个子像素区域P。
在一些示例中,如图2所示,阵列基板100还包括:设置在衬底10的一侧、且位于显示区A的多个第一晶体管11。每个第一晶体管11包括第一栅极111、第一源极112和第一漏极113。
示例性的,每个子像素区域P内可以设置有一个第一晶体管11。如图2所示,可以把沿第一方向X排列成一排的子像素区域P称为同一列子像素区域P,可以把沿第二方向Y排列成一排的子像素区域P称为同一行子像素区域P。同一行子像素区域P的各第一晶体管11例如可以与一条栅线GL电连接,同一列子像素区域P内的各第一晶体管11可以与一条数据线DL电连接。其中,每个第一晶体管11可以通过第一栅极111与相应的栅线GL电连接,并通过第一源极112和第一漏极113中的一者(例如为第一源极112)与相应的数据线DL电连接。
当然,同一行子像素区域P的各第一晶体管11还可以与多条栅线GL电连接,本公开实施例对此不做限定。
在一些示例中,如图3~图11所示,阵列基板100还包括:设置在衬底10的一侧、且位于绑定区B的多个导电引脚12。其中,每相邻的两个导电引脚12之间具有间隙,这样可以确保每相邻的两个导电引脚12之间处于绝缘状态,避免每相邻的两个导电引脚12形成短接。
此处,如图3~图5所示,每个导电引脚12例如可以呈条状,并沿第一方向Y延伸。
如图6、图7、图10和图11所示,上述多个导电引脚12可以与第一栅极111同层设置。这样可以使得该多个导电引脚12具有良好的电学性能。由于第一栅极111与上述栅线GL同层设置,这也就意味着,导电引脚12、第一栅极111以及栅线GL可以同层设置。
需要说明的是,本文中提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层,然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同,一次构图工艺可能包括多次曝光、显影或刻蚀工艺,而形成的层结构中的特定图形可以是连续的也可以是不连续的,这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来,可以同时制备形成导电引脚12、第一栅极111以及栅线GL,有利于简化阵列基板100的制备工艺。
此外,上述第一源极112、第一漏极113以及数据线DL也可以同层设置。这样可以在一次构图工艺中,同时制备形成第一源极112、第一漏极113以及数据线DL,有利于简化阵列基板100的制备工艺。
在一些示例中,如图2所示,至少一条数据线DL与一个电极引脚12电连接。这样可以利用电极引脚12向数据线DL内传输数据电压,进而向与数据线DL电连接的第一晶体管11传输数据电压,使得阵列基板100工作。
此处,数据线DL与电极引脚12之间的关系包括多种,可以根据实际需要选择设置。
例如,如图2所示,数据线DL可以与电极引脚12一一对应的电连接。这样利用电极引脚12独立地向数据线DL传输数据电压,避免数据电压在传输的过程中发生串扰。
又如,多条数据线DL可以与一个电极引脚12电连接。示例性的,一个电极引脚12可以与两条、三条或四条等数据线DL电连接,此时,可以分时段向数据线DL传输数据电压。这样可以减少电极引脚12的数量,增大相邻两个电极引脚12之间的间距,避免相邻两个电极引脚12之间出现短接的情况。
在一些示例中,如图3~图11所示,阵列基板100还包括:分别设置在上述多个导电引脚12远离衬底10一侧表面的多个导电电极13。
此处,多个导电引脚12和多个导电电极13之间的位置关系,例如可以为:多个导电引脚12和多个导电电极13一一对应,也即每个导电引脚12远离衬底10的一侧表面可以设置有一个导电电极13。
导电电极13设置在导电引脚12远离衬底10一侧的表面,也即,导电电极13靠近衬底10一侧的表面和对应的导电引脚12远离衬底10一侧的表面直接接触,两者之间未设置其他薄膜。
需要说明的是,本文中提及的“A设置在(或位于)B远离C的一侧”,既指在空间上的三者的位置关系,又指A相比于B在后制备形成。
下面,可以将导电引脚12、第一栅极111以及栅线GL所在膜层称为栅导电层,可以将第一源极112、第一漏极113以及数据线DL所在膜层称为源漏导电层,可以将导电电极13所在膜层称为电极层。
在一些示例中,第一源极112和第一漏极113设置在第一栅极111远离衬底10的一侧,也即源漏导电层相比栅导电层在后制备形成。
在一些示例中,导电电极13设置在第一源极112和第一漏极113远离衬底10的一侧,也即电极层相比源漏导电层在后制备形成。
由于导电电极13靠近衬底10一侧的表面和对应的导电引脚12远离衬底10一侧的表面直接接触,这也就意味着,在制备形成源漏导电层的过程中,用于形成源漏导电层的薄膜中覆盖导电引脚12的部分被去除,使得源漏导电层在衬底10上的正投影与导电引脚12在衬底10上的正投影无交叠。这也在后续制备阵列基板100的过程中,可以避免对源漏导电层造成腐蚀。
由此,本公开的一些实施例所提供的阵列基板100,通过绑定区B内的导电引脚12与第一晶体管11中的第一栅极111同层设置,并将导电电极13直接设置在导电引脚12的远离衬底10的一侧表面上,而未保留用于形成源漏导电层的薄膜中覆盖导电引脚12的部分,这样在制备形成阵列基板100的过程中,可以避免对源漏导电层造成腐蚀,进而可以避免应用有上述阵列基板100的显示装置出现撕膜斜纹不良,有效改善该显示装置的显示效果。
在一些实施例中,如图3~图5所示,上述多个导电引脚12在衬底10上的正投影,位于上述多个导电电极13在衬底10上的正投影范围内。示例性的,每个导电引脚12在衬底10上的正投影,位于相应的导电电极13在衬底10上的正投影范围内。每个导电电极13覆盖相应的导电引脚12。
这样可以利用导电电极13对相应的导电引脚12形成防刻蚀保护,避免在制备阵列基板100的过程中,对导电引脚12的形貌造成影响。
此处,每相邻的两个导电电极13之间具有间隙,这样可以确保每相邻的两个导电电极13之间处于绝缘状态,避免每相邻的两个导电电极13形成短接,进而避免被导电电极13覆盖的导电引脚12形成短接。
在一些实施例中,如图3~图11所示,上述阵列基板100还包括:设置在衬底10一侧的多条触控信号线14。
在一些示例中,如图6、图7、图10和图11所示,上述多条触控信号线14与第一源极112、第一漏极113以及上述多条数据线DL同层设置。这样可以在一次构图工艺中,同时制备形成触控信号线14、第一源极112、第一漏极113以及数据线DL,有利于简化阵列基板100的制备工艺。此外,还可以避免对上述多条触控信号线14造成腐蚀,进而可以避免应用有上述阵列基板100的显示装置出现撕膜斜纹不良,有效改善该显示装置的显示效果。
在一些示例中,如图3~图5所示,该多条触控信号线14沿第一方向Y延伸,也即,多条触控信号线14的延伸方向与上述多条数据线DL的延伸方向相同或大致相同。这样便于对阵列基板100所包括的图案进行排布、规避,避免触控信号线14和数据线DL形成交叉,进而出现短接的情况。
在一些示例中,如图3~图5所示,触控信号线14与导电引脚12电连接。这样导电引脚12中的信号便可以传输至相应的触控信号线14中,或者触控信号线14中的信号可以传输至相应的导电引脚12中。
此处,导电引脚12和触控信号线14之间的连接关系包括多种,可以根据实际需要选择设置。示例性的,至少一条触控信号线14与一个导电引脚12电连接。
例如,触控信号线14和导电引脚12可以一一对应,也即每条触控信号线14可以与一个导电引脚12电连接。这样利用电极引脚12独立地向触控信号线14传输信号,避免信号在传输的过程中发生串扰。
又如,多条触控信号线14可以与一个导电引脚12电连接。例如,一个导电引脚12与两条触控信号线14电连接;或者,一个导电引脚12与三条触控信号线14电连接;或者,一个导电引脚12与六条触控信号线14电连接。这样可以减少电极引脚12的数量,增大相邻两个电极引脚12之间的间距,避免相邻两个电极引脚12之间出现短接的情况。
在一些示例中,与触控信号线14电连接的电极引脚12以及与数据线DL电连接的电极引脚12不是同一个电极引脚12。也即,一个电极引脚12在电连接有触控信号线14的情况下,则仅与触控信号线14电连接;一个电极引脚12在电连接有数据线DL的情况下,则仅与数据线DL电连接。
需要说明的是,本公开的一些示例中还在阵列基板100中设置有其他信号线(例如为公共电极线),此时,上述多个导电引脚12中还可以包括与公共电极线或栅线GL电连接的导电引脚12。
在一些实施例中,如图3~图5所示,上述阵列基板100还包括:设置在上述多条触控信号线14远离衬底10一侧的多个触控电极15。该多个触控电极15同层设置且相互独立。
在一些示例中,如图3~图5所示,每个触控电极15与至少一条触控信号线14电连接。此时,可以利用该至少一条触控信号线14向该触控电极15输入信号(例如为触控检测信号),或将触控电极15中的信号(例如为电容值信号)输出。
在一些示例中,本公开的一些实施例提供的阵列基板100,可以应用于自电容模式的显示装置中。这样在人体未触碰该显示装置时,各个触控电极15所承受的电容值为一个固定值;而在人体触碰该显示装置时,人体触碰的位置所对应的触控电极15所承受的电容值为固定值叠加人体电容值,之后可以通过导电引脚12和触控信号线14传输各个触控电极15的电容值,检测各个触控电极15的电容值的变化,判断出人体所触碰的位置。
此处,触控电极15与触控信号线14之间的关系包括多种,可以根据实际需要选择设置。
例如,如图3~图5所示,上述多个触控电极15可以分别与该多条触控信号线14一一对应的电连接。这样可以减少触控信号线14的数量,有利于降低触控信号线14在阵列基板100中的空间占比;并且,可以利用每条触控信号线14独立传输对应的触控电极15所承受的电容值,避免该电容值在传输的过程中发生串扰,避免对人体所触碰的位置判断错误,进而可以确保判断人体所触碰的位置的准确性。
又如,如图3和图5所示,每个触控电极15可以与多条触控信号线14电连接。示例性的,如图3和图5所示,每个触控电极15可以与两条触控信号线14电连接。这样在触控电极15与其中一条触控信号线14之间的连接出现异常时,也可以利用另外的触控信号线14与触控电极15进行信号传输,有利于提高触控电极15与触控信号线14电连接的可靠性,以及两者之间信号传输的可靠性。
上述触控电极15的材料包括多种,可以根据实际需要选择设置。示例性的,触控电极15的材料可以为具有较高的光线透过率的导电材料。该导电材料例如可以为氧化铟锡(Indium Tin Oxide,简称ITO)或氧化铟镓锌(Indium Gallium Zinc Oxide,简称IGZO)等。
此处,需要说明的是,一个电极引脚12所电连接的至少一条触控信号线14,与一个触控电极15所电连接的至少一条触控信号线14,可以是相同的,也可以是不同的。示例性的,如图5所示,一个电极引脚12所电连接的多条触控信号线14中,其中的一部分触控信号线14分别与不同的触控电极15电连接。
在一些实施例中,如图6、图7、图10和图11所示,上述阵列基板100还包括:设置在上述多个第一晶体管11和上述多个触控电极15之间的平坦层16。也即,该平坦层16设置在源漏导电层和上述多个触控电极15之间。
通过设置平坦层16,可以使得设置在平坦层16远离衬底10的一侧的多个触控电极15具有较为平整的形貌,避免上述多个触控电极15出现凹凸不平的现象。
在一些示例中,如图6、图7、图10和图11所示,平坦层16具有多个第一过孔K1,每条触控信号线14通过至少一个第一过孔K1与一个触控电极15电连接。
此处,上述多个第一过孔K1暴露上述多条触控信号线14远离衬底10一侧的表面。
示例性的,上述多个第一过孔K1与上述多条触控信号线14一一对应。此时,每条触控信号线14可以通过一个第一过孔K1与一个触控电极15电连接。这样可以减少刻蚀形成第一过孔K1的数量,降低制备形成平坦层16的工艺难度。
示例性的,每条触控信号线14对应有多个第一过孔K1。此时,每条触控信号线14可以通过多个第一过孔K1与一个触控电极15电连接。这样可以增大各触控电极15与相应的触控信号线14的接触面积,确保各触控电极15与相应的触控信号线14之间的良好电连接。
在一些示例中,如图6、图7、图10和图11所示,平坦层16在衬底10上的正投影与上述多个导电引脚12在衬底10上的正投影无交叠。示例性的,平坦层16在衬底10上的正投影与绑定区B的边界无交叠。也即,平坦层16未对位于导电引脚12远离衬底10一侧表面上的导电电极13形成覆盖。
由于平坦层16具有较好的绝缘性能,通过设置平坦层16与上述多个导电引脚12之间的位置关系,可以避免平坦层16对导电电极13与其它结构(例如覆晶薄膜)之间的电连接产生不良影响。此处,关于覆晶薄膜,可以参照下面的一些实施例中的说明。
在一些实施例中,如图7和图11所示,上述阵列基板100还包括:多个像素电极17。
在一些示例中,如图7和图11所示,上述多个像素电极17可以设置在上述多个触控电极15远离衬底10的一侧。当然,上述多个像素电极17还可以设置在上述多个触控电极15靠近衬底10的一侧。本公开对此不做限定。
此处,如图2所示,在每个第一晶体管11通过第一源极112与相应的数据线DL电连接的情况下,每个像素电极17可以与第一晶体管11的第一漏极113电连接。在每个第一晶体管11通过第一漏极113与相应的数据线DL电连接的情况下,每个像素电极17与第一晶体管11的第一源极112电连接。
如图2所示,以每个第一晶体管11通过第一源极112与相应的数据线DL电连接,且每个像素电极17可以与第一晶体管11的第一漏极113电连接为例。在阵列基板100工作的过程中,可以通过栅线GL向第一晶体管11的第一栅极111传输控制信号(例如为控制第一晶体管11导通的控制信号),控制第一晶体管11打开;然后通过数据线GL将数据电压依次经该第一晶体管11的第一源极112、第一漏极113传输至像素电极17,对该像素电极17充电。
上述像素电极17的材料包括多种,可以根据实际需要选择设置。示例性的,像素电极17的材料可以为具有较高的光线透过率的导电材料。该导电材料例如可以为ITO或IGZO等。
在一些示例中,如图6、图7、图10和图11所示,上述多个导电电极13可以与上述多个触控电极15或上述多个像素电极17同层设置。这样可以在一次构图工艺中,同时制备形成该多个导电电极13和多个触控电极15,或者同时制备形成该多个导电电极13和多个像素电极17,有利于简化阵列基板100的制备工艺。
通过将上述多个导电电极13与上述多个触控电极15或上述多个像素电极17同层设置,可以避免额外增加一次构图工艺,降低制备阵列基板100的复杂度,减少材料的使用量,降低阵列基板100的生产成本。
在一些示例中,上述一些实施例中的多个触控电极15被复用为公共电极。这样在应用有上述阵列基板100的显示装置在进行画面显示、而未进行触控检测的情况下,可以在该多个触控电极15中传输公共电压,并在该多个触控电极15和上述多个像素电极17之间产生电场,该电场能够驱动上述显示装置中的液晶分子偏转,使得显示装置实现画面显示。
在本公开实施例中,在上述显示装置进行画面显示时,可以通过导电引脚12、触控信号线14向触控电极15传输公共电压;在进行触控检测的情况下,触控电极15所承受的电压值可以通过触控信号线14、导电引脚12传输。由此,导电引脚12与相应的至少一条触控信号线14之间需要具有较为良好的电连接。
此处,导电引脚12与相应的至少一条触控信号线14之间的连接方式包括多种,可以根据实际需要选择设置。
在一些实施例中,导电引脚12与相应的至少一条触控信号线14之间可以直接电连接。此时,如图3所示,该至少一条触控信号线14可以与同一个触控电极15电连接。
在一些示例中,如图6、图7、图10和图11所示,上述阵列基板100还包括:设置在第一源极112和第一漏极113所在膜层(也即源漏导电层)与第一栅极111之间的绝缘层18。该绝缘层18被配置为对第一源极112和第一漏极113所在膜层和第一栅极111进行绝缘,避免形成短接。
此处,绝缘层18的类型包括多种,其类型与第一晶体管11的结构相关。
示例性的,如图6、图7、图10和图11所示,每个第一晶体管11还包括第一有源层114。
例如,如图6和图7所示,第一有源层114设置在第一栅极111靠近衬底10的一侧。此时,第一晶体管11的结构为顶栅结构。绝缘层18可以称为层间介质层,该绝缘层18可以为由氮化硅薄膜和二氧化硅薄膜叠层构成。
又如,如图10和图11所示,第一有源层114设置在第一栅极111远离衬底10的一侧。此时,第一晶体管11的结构为底栅结构。绝缘层18可以称为栅绝缘层,该绝缘层18可以采用氧化硅、氮化硅或氮氧化硅等材料形成。
在一些示例中,如图8所示,绝缘层18中设置有多个第二过孔K2,每条触控信号线14通过至少一个第二过孔K2与一个导电引脚12电连接。
此时,上述多个导电引脚12被引出绑定区B,上述多个第二过孔K2暴露出被引出绑定区B的部分的远离衬底10一侧的表面,每条触控信号线14通过至少一个第二过孔K2直接与该表面接触,形成电连接。这样有利于简化阵列基板100的结构。
基于此,如图8所示,导电电极13覆盖导电引脚12位于绑定区B的部分,未对导电引脚12被引出绑定区B的部分形成覆盖。
在一些示例中,如图6、图7、图10和图11所示,绝缘层18在衬底10上的正投影与上述多个导电引脚12在衬底10上的正投影无交叠。也即,绝缘层18未对导电引脚12远离衬底10一侧的表面形成覆盖。示例性的,绝缘层18在衬底10上的正投影与绑定区B的边界无交叠。
由于绝缘层18具有较好的绝缘性能,通过设置绝缘层18与上述多个导电引脚12之间的位置关系,可以避免绝缘层18对导电引脚12与其它结构(例如导电电极13)之间的电连接产生不良影响。
在另一些实施例中,导电引脚12与相应的至少一条触控信号线14之间间接电连接。
示例性的,如图4和图5所示,阵列基板100还包括:多个连接部19。其中,至少一条触控信号线14通过连接部19与一个导电引脚12电连接。也即,连接部19的一端与导电引脚12电连接,另一端与该至少一条触控信号线14电连接。其中,连接部19与该至少一条触控信号线14之间连接关系可以为:连接部19与触控信号线14一一对应的电连接,或者,一个连接部19可以与该至少一条触控信号线14电连接。
此处,连接部19的结构包括多种,可以根据实际需要选择设置。
在一些示例中,如图9所示,在上述阵列基板100包括多个触控电极15的情况下,上述多个连接部19与该多个触控电极15同层设置。或者,在阵列基板100包括多个像素电极17的情况下,该多个连接部19与该多个像素电极17同层设置。此时,每个连接部19即为与触控电极15同层且材料相同或与像素电极17同层且材料相同的导电图案。
在此情况下,上述多个连接部19可以分别与上述多个导电电极13为一体结构,连接部19的一端可以通过过孔与至少一条触控信号线14电连接。
基于此,如图4所示,该至少一条触控信号线14可以与同一个触控电极15电连接。
在本示例中,通过将连接部19与触控电极15或像素电极17同层设置,这样可以在一次构图工艺中,同时制备形成连接部19与触控电极15,或者同时制备形成连接部19与像素电极17,有利于简化阵列基板100的制备工艺。
在另一些示例中,如图12所示,连接部19包括多路复用器191(Multiplexer或MUX)。该多路复用器191包括输入端D1和输出端D2,其中,输入端D1与一个导电引脚12电连接,输出端D2与至少两条触控信号线14电连接。示例性的,该输出端D2可以与两条、三条或四条触控信号线14电连接。
通过使得每个多路复用器191的输入端D1与一个导电引脚12电连接,输出端D2与至少两条触控信号线14电连接,可以减少导电引脚12的数量,进而增大相邻两个导电引脚12之间的间距,避免相邻两个导电引脚12出现短接的现象。
上述多路复用器191的结构例如为:包括至少两个第二晶体管1911。每个第二晶体管1911包括第二源极19111和第二漏极19112。
此处,如图10和图11所示,第二源极19111和第二漏极19112中的一者(例如为第二源极19111)可以作为输入端D1,与导电引脚12电连接,另一者(例如为第二漏极19112)可以作为输出端D2,与至少两条触控信号线14中的一条触控信号线14电连接。
这样在应用有阵列基板100的显示装置进行画面显示时,可以将公共电压传输至电极引脚12,之后经过多路复用器191将该公共电压传输至相应的触控信号线14及触控电极15。其中,该触控信号线14可以为多路复用器191所连接的至少两条触控信号线14中的部分触控信号线14。
在此情况下,如图5所示,该至少一条触控信号线14可以与同一个触控电极15电连接,也可以与不同的触控电极15电连接。
此外,需要说明的是,至少一条数据线DL与一个导电引脚12之间,也可以通过连接部19实现电连接。两者之间的连接可以参照上述一些实施例中对至少一条触控信号线14与一个导电引脚12之间的连接的说明,此处不再赘述。
本公开的一些实施例提供了一种阵列基板的制备方法。如图13所示,该阵列基板的制备方法,包括:S100~300。
S100,如图16中(a)所示,提供衬底10。该衬底10具有显示区A和位于显示区A的旁侧的绑定区B。
在一些示例中,衬底10的结构可以参照上述一些实施例中对衬底10的结构的说明,此处不再赘述。
S200,如图16中(f)所示,在衬底10的一侧形成多个第一晶体管11和多个导电引脚12。该多个第一晶体管11位于显示区A,第一晶体管11包括第一栅极111、第一源极112和第一漏极113。该多个导电引脚12位于绑定区B,且与第一栅极111同层设置。
在一些示例中,如图14所示,在上述S200中,形成多个第一晶体管11和多个导电引脚12的步骤,包括:S210~S250。
S210,如图16中(b)所示,在衬底10的一侧形成栅导电薄膜G。
示例性的,可以采用磁控溅射工艺形成上述栅导电薄膜G。该栅导电薄膜G的材料例如可以为铝(Al)、铜(Cu)、钼(Mo)、钛(Ti)或铝钕合金(AlNd)等电阻值较小的金属材料。
S220,如图16中(c)所示,对栅导电薄膜G进行图案化,形成位于显示区A的多个第一晶体管11的第一栅极111,以及位于绑定区B的多个导电引脚12,得到栅导电层。
示例性的,可以采用光刻工艺或湿刻工艺等对栅导电薄膜G进行图案化。
S230,如图16中(d)所示,在栅导电层远离衬底10的一侧形成绝缘层18。
示例性的,可以采用光刻工艺形成上述绝缘层18。
此处,绝缘层18的结构及材料可以参照上述一些实施例中对绝缘层18的结构及材料的说明,此处不再赘述。
S240,如图16中(e)所示,在衬底10的一侧(也即绝缘层18远离衬底10的一侧)形成源漏导电薄膜SD。
示例性的,可以采用磁控溅射工艺形成上述源漏导电薄膜SD。
此处,形成源漏导电薄膜SD的方法例如可以为:在绝缘层18远离衬底10的一侧形成第一钛金属薄膜,然后在该第一钛金属薄膜远离衬底10的一侧形成铝金属薄膜,然后在该铝金属薄膜远离衬底10的一侧形成第二钛金属薄膜,得到上述源漏导电薄膜SD。
S250,如图16中(f)所示,对源漏导电薄膜SD进行图案化,去除源漏导电薄膜SD中位于绑定区B的部分,并在显示区A形成多条触控信号线14以及多个第一晶体管11的第一源极112和第一漏极113,得到源漏导电层。
示例性的,可以采用光刻工艺或湿刻工艺等对源漏导电薄膜SD进行图案化。
通过去除源漏导电薄膜SD中位于绑定区B的部分,可以在后续制备形成阵列基板100的过程中,避免对源漏导电层造成腐蚀,进而可以避免应用有上述阵列基板100的显示装置出现撕膜斜纹不良,有效改善该显示装置的显示效果。
S300,如图16中(i)所示,分别在上述多个导电引脚12远离衬底10一侧的表面形成多个导电电极13。
在一些示例中,在上述S300中,形成多个导电电极13,包括S310~S320。
S310,在上述多个导电引脚12远离衬底10一侧的表面上形成电极薄膜。
示例性的,可以采用溅射工艺形成上述电极薄膜。该电极薄膜的材料例如可以为ITO或IGZO等。
S320,对该电极薄膜进行图案化,得到上述多个导电电极13。
示例性的,可以采用光刻工艺或湿刻工艺等对电极薄膜进行图案化。
此处,在对电极薄膜进行图案化,得到上述多个导电电极13时,还可以得到分别与上述多条触控信号线14电连接的触控电极15,或者还可以得到分别与上述多个第一晶体管11的第一源极112和第一漏极113中的一者电连接的像素电极17。
上述导电引脚12和导电电极13之间的关系可以参照上述一些实施例中的说明,此处不再赘述。
本公开的一些实施例中所提供的阵列基板的制备方法,所能实现额有益效果,与上述一些实施例中所提供的阵列基板所能实现的有益效果相同,此处不再赘述。
在一些实施例中,如图15所示,在上述S300之前,阵列基板的制备方法还包括:S260~S270。
S260,如图16中(g)所示,在上述多条触控信号线14、上述多个第一晶体管11和上述多个电极引脚12远离衬底10的一侧形成平坦薄膜16'。
示例性的,上述平坦薄膜16'可以采用等离子体增强化学气相沉积(PlasmaEnhanced Chemical Vapor Deposition,简称PECVD)工艺制备形成。平坦薄膜16'的材料例如可以为有机树脂。
S270,如图16中(h)所示,对平坦薄膜16'进行图案化,在平坦薄膜16'中形成暴露上述多条触控信号线14的第一过孔K1,并去除平坦薄膜16'中位于绑定区B内的部分,得到平坦层16。平坦层16在衬底10上的正投影与上述多个导电引脚12在衬底10上的正投影无交叠。
示例性的,可以采用光刻工艺对平坦薄膜16'进行图案化。
在上述步骤S320中,在得到多个导电电极13时,还得到多个触控电极15的情况下,每个触控电极15可以通过至少一个第一过孔K1与相应的触控信号线14电连接。
如图17和图18所示,本公开的一些实施例提供了一种显示装置1000。如图17所示,该显示装置1000包括:如上述一些实施例中所述的阵列基板100,与该阵列基板100相对设置的对置基板200以及设置在该阵列基板100和对置基板200之间的液晶层300。
在一些实施例中,由于阵列基板100中的触控电极15可以复用为公共电极,因此,如图17所示,上述对置基板200可以包括:对置衬底20、彩膜层21以及黑矩阵22。
在一些示例中,如图17所示,彩膜层21设置在对置衬底20靠近阵列基板100的一侧。彩膜层21可使得穿过彩膜层21射向外界的光线为所需颜色的光线。
在一些示例中,如图17所示,黑矩阵22设置在对置衬底20靠近阵列基板100的一侧。示例性的,黑矩阵22设置有多个开口,上述彩膜层21设置在该多个开口内。这样可以避免出现光线混色现象。
此外,黑矩阵22可以对阵列基本100中的第一晶体管11、栅线GL、数据线DL以及第二晶体管1911等形成遮挡,对第一晶体管11和第二晶体管1911等形成保护,并避免形成外界光线的反射。
在一些示例中,如图17所示,上述液晶层300包括多个液晶分子。在显示装置1000进行显示的过程中,阵列基板100中的像素电极17和触控电极15之间可以产生电场,以驱动该液晶层300中的液晶分子的偏转,实现画面显示。
本公开的一些实施例中所提供的显示装置1000,所能实现额有益效果,与上述一些实施例中所提供的阵列基板100所能实现的有益效果相同,此处不再赘述。
在一些实施例中,如图17所示,上述显示装置1000还包括:与阵列基板100中的多个导电电极13绑定的覆晶薄膜(Chip On Flex,或,Chip On Film,简称COF)400。
在一些示例中,上述覆晶薄膜400包括柔性电路板40,以及设置在该柔性电路板40一侧的集成电路(Integrated Circuit,简称IC)41。其中,柔性电路板40可以通过各向异性导电胶(Anisotropic Conductive Film,简称ACF)与绑定区B内的多个导电电极13粘合在一起。
示例性的,上述IC 41可以通过柔性电路板40、导电电极13、导电引脚12及触控信号线14向触控电极15中传输公共电压,使得显示装置1000能够实现画面显示。触控电极15所承载的电容值也可以通过触控信号线14、导电引脚12、导电电极13及柔性电路板40传输至IC 41,对触控电极15所承载的电容值的变化进行判断,实现对触控位置的判断。
在一些实施例中,上述显示装置1000为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述,仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。
Claims (15)
1.一种阵列基板,其特征在于,具有显示区和位于所述显示区的旁侧的绑定区;所述阵列基板包括:
衬底;
设置在所述衬底的一侧、且位于所述显示区的多个第一晶体管,第一晶体管包括第一栅极、第一源极和第一漏极;
设置在所述衬底的一侧、且位于所述绑定区的多个导电引脚,所述多个导电引脚与所述第一栅极同层设置;以及,
分别设置在所述多个导电引脚远离所述衬底一侧表面的多个导电电极。
2.根据权利要求1所述的阵列基板,其特征在于,还包括:设置在所述衬底一侧、且沿第一方向延伸的多条触控信号线;
所述多条触控信号线与所述第一源极、所述第一漏极同层设置;
至少一条触控信号线与一个导电引脚电连接。
3.根据权利要求2所述的阵列基板,其特征在于,还包括:设置在所述多条触控信号线远离所述衬底一侧的多个触控电极;
每个触控电极与至少一条触控信号线电连接。
4.根据权利要求3所述的阵列基板,其特征在于,还包括:设置在所述多个第一晶体管和所述多个触控电极之间的平坦层;
所述平坦层具有多个第一过孔,每条触控信号线通过至少一个第一过孔与一个触控电极信号线电连接;
所述平坦层在所述衬底上的正投影与所述多个导电引脚在所述衬底上的正投影无交叠。
5.根据权利要求3所述的阵列基板,其特征在于,还包括:设置在所述多个触控电极远离或靠近所述衬底一侧的多个像素电极;
每个第一晶体管的第一源极和第一漏极中的一者与一个像素电极电连接;
所述多个导电电极与所述多个触控电极或所述多个像素电极同层设置。
6.根据权利要求5所述的阵列基板,其特征在于,还包括:与所述多条触控信号线同层设置、且沿第一方向延伸的多条数据线;
每个第一晶体管的第一源极和第一漏极中的另一者与一条数据线电连接;
至少一条数据线与一个导电引脚电连接。
7.根据权利要求2~6中任一项所述的阵列基板,其特征在于,还包括:多个连接部;
所述导电引脚通过连接部与所述至少一条触控信号线电连接。
8.根据权利要求7所述的阵列基板,其特征在于,在所述阵列基板包括多个触控电极的情况下,所述多个连接部与所述多个触控电极同层设置、且分别与所述多个导电电极为一体结构;或者,
在所述阵列基板包括多个像素电极的情况下,所述多个连接部与所述多个像素电极同层设置、且分别与所述多个导电电极为一体结构;
所述连接部的一端与所述至少一条触控信号线电连接。
9.根据权利要求7所述的阵列基板,其特征在于,所述连接部包括多路复用器;
所述多路复用器的输入端与一个导电引脚电连接,输出端与至少两条触控信号线电连接。
10.根据权利要求9所述的阵列基板,其特征在于,所述多路复用器包括至少两个第二晶体管,第二晶体管包括第二源极和第二漏极;
所述第二源极和所述第二漏极中的一者与所述导电引脚电连接,另一者与所述至少两条触控信号线中的一条触控信号线电连接。
11.根据权利要求2~6中任一项所述的阵列基板,其特征在于,还包括:设置在所述第一源极和所述第一漏极所在膜层与所述第一栅极之间的绝缘层;
所述绝缘层中设置有多个第二过孔,每条触控信号线通过至少一个第二过孔与一个导电引脚电连接。
12.根据权利要求1~6中任一项所述的阵列基板,其特征在于,所述多个导电引脚在所述衬底上的正投影,位于所述多个导电电极在所述衬底上的正投影范围内。
13.根据权利要求1~6中任一项所述的阵列基板,其特征在于,还包括:设置在所述第一源极和所述第一漏极所在膜层与所述第一栅极之间的绝缘层;
所述绝缘层在所述衬底上的正投影与所述多个导电引脚在所述衬底上的正投影无交叠。
14.一种显示装置,其特征在于,包括:
如权利要求1~13中任一项所述的阵列基板;
与所述阵列基板相对设置的对置基板;以及,
设置在所述阵列基板和所述对置基板之间的液晶层。
15.根据权利要求14所述的显示装置,其特征在于,还包括:与所述阵列基板中的多个导电电极绑定的覆晶薄膜。
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WO2021238463A1 (zh) * | 2020-05-29 | 2021-12-02 | 京东方科技集团股份有限公司 | 阵列基板及其制备方法、显示装置 |
US11901375B2 (en) | 2020-05-29 | 2024-02-13 | Ordos Yuansheng Optoelectronics Co., Ltd. | Array substrate and method for manufacturing the same, and display apparatus |
CN113838871A (zh) * | 2021-09-26 | 2021-12-24 | 京东方科技集团股份有限公司 | 显示面板及显示装置 |
WO2023142111A1 (zh) * | 2022-01-30 | 2023-08-03 | 京东方科技集团股份有限公司 | 显示面板和显示装置 |
WO2023230977A1 (zh) * | 2022-06-02 | 2023-12-07 | 京东方科技集团股份有限公司 | 布线基板及其制造方法、发光基板及显示装置 |
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CN111599823B (zh) | 2024-01-05 |
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