WO2023226547A1 - 一种保护low-k介质的有源芯片硅通孔制作方法 - Google Patents

一种保护low-k介质的有源芯片硅通孔制作方法 Download PDF

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WO2023226547A1
WO2023226547A1 PCT/CN2023/081829 CN2023081829W WO2023226547A1 WO 2023226547 A1 WO2023226547 A1 WO 2023226547A1 CN 2023081829 W CN2023081829 W CN 2023081829W WO 2023226547 A1 WO2023226547 A1 WO 2023226547A1
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layer
dielectric
hole
low
silicon
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PCT/CN2023/081829
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French (fr)
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戴风伟
曹立强
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华进半导体封装先导技术研发中心有限公司
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Publication of WO2023226547A1 publication Critical patent/WO2023226547A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Definitions

  • the present invention relates to the technical field of semiconductor packaging, and in particular to a method for making active chip through-silicon vias that protect low-k dielectrics.
  • TSV through silicon vias
  • CMOS process is performed first, then the TSV process is performed, and finally the metal interconnection structure is produced. Since the through silicon hole needs to be wet cleaned after etching, if there is a low-k (low dielectric constant) medium, there will be verified damage to the low-k medium.
  • the through silicon hole production of the medium through hole process route is It is completed before the metal interconnection layer. Therefore, there is no need to consider the low-k dielectric in the metal interconnection structure when making through silicon holes.
  • the process route of medium through-holes can only be carried out in wafer factories, and there are very few wafer factories with through-silicon via technology in the world. Therefore, this process route is greatly restricted.
  • the industry has proposed a through-silicon via process route for front-side back vias, that is, first perform the CMOS process and metal interconnection structure production, and finally perform the through-silicon via production.
  • the through-silicon via production of this process route is carried out after the chip processing is completed, and can be carried out in the packaging and testing factory.
  • the wafer factory processes chips, and the packaging and testing factory produces through-silicon vias. The division of labor is clear, and the above-mentioned restricted problems are solved.
  • the through silicon via is performed after the metal interconnection structure is completed, the through silicon via etching needs to pass through the low-k dielectric, and the through silicon via needs to be wet cleaned. If the low-k structure is not provided with an effective Protection means, low-k media will be subject to verification damage.
  • the task of the present invention is to provide a method for making an active chip through silicon hole that protects low-k dielectric, by making a protective layer to protect the low-k dielectric, completely isolating the low-k dielectric, and avoiding the presence of the low-k dielectric.
  • the through silicon vias are corroded and damaged during the cleaning process.
  • the present invention provides a method for making active chip through silicon holes that protect low-k dielectric, including:
  • an active chip includes a substrate, a metal interconnection layer, and an active layer located between the substrate and the metal interconnection layer, and both the active layer and the metal interconnection layer have through holes.
  • the metal interconnect layer includes a multi-layer dielectric layer, a low-k dielectric between the multi-layer dielectric layers, and a metal wiring located in the dielectric layer and the low-k dielectric;
  • a protective layer is formed on the upper surface of the dielectric layer and the inner wall of the first through hole through plasma enhanced chemical vapor deposition.
  • the material of the protective layer is an inorganic material.
  • the size of the hole pattern is smaller than the size of the first through hole.
  • a through-hole region in the active layer and the substrate located under the hole pattern is etched through a Bosch process to form a through-silicon via.
  • the size of the through silicon hole is smaller than the size of the first through hole.
  • the material of the protective layer is silicon dioxide, silicon nitride and/or aluminum oxide.
  • the present invention at least has the following beneficial effects:
  • the present invention discloses a method for making active chip through-silicon holes that protect low-k media.
  • the low-k medium is protected by making a protective layer, and the low-k medium is completely isolated, which can avoid The low-k dielectric is damaged during the cleaning of through silicon holes; the production process of this protective layer is simple and is compatible with the through silicon hole process; the protective layer has obvious characteristics and is traceable.
  • Figure 1 shows a flow chart of fabricating through silicon vias in an active chip according to one embodiment of the present invention.
  • 2 to 7 illustrate a schematic diagram of the manufacturing process of a through silicon via of an active chip according to an embodiment of the present invention.
  • the quantifiers "a” and “ ⁇ " do not exclude the scenario of multiple elements.
  • the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and does not limit the order of each step. In different embodiments of the present invention, it can be determined according to the adjustment of the process. Adjust the order of steps.
  • the present invention is based on the following insight of the inventor:
  • the through-silicon vias need to be etched through a low-k medium, and the through-silicon vias need to be wet-cleaned after the etching is completed.
  • the cleaning fluid is corrosive. If the low-k medium is not protected, the low-k medium will be damaged during the cleaning process. Moreover, the structure of the low-k medium is loose, and the cleaning fluid will penetrate and corrode the metal interconnection structure. metal wiring.
  • Inorganic materials such as silicon dioxide, silicon nitride, and aluminum oxide will not be corroded by the cleaning solution, so they can be used as a protective layer for low-k media to prevent medium-low-k media from being damaged.
  • Figure 1 shows a flow chart of making a through silicon via in an active chip according to one embodiment of the present invention
  • Figures 2 to 7 show a process of making a through silicon via in an active chip according to one embodiment of the present invention.
  • Step 1 as shown in Figure 2, provide an active chip 100.
  • the active chip includes a substrate 101, an active layer 102, and a metal interconnection layer 103.
  • Active layer 102 is located between substrate 101 and metal interconnect layer 103 .
  • the metal interconnection layer 103 includes a multi-layer dielectric layer 1031, a low-k dielectric 1032 located between the multi-layer dielectric layers, and a metal wiring 1033 located in the dielectric layer and the low-k dielectric.
  • the low-k dielectric 1032 is an insulating material with a low dielectric constant.
  • the active layer 102 includes an active area 1021. Both the active layer 102 and the metal interconnection layer 103 have reserved via areas (blank areas that do not contain active devices and metal wiring). Through holes can be etched in this via area to avoid damaging the metal wiring 1032 and the existing metal wiring.
  • Source device 1021 is reserved via areas (blank areas that do not contain active devices and metal wiring). Through holes can be etched in this via area to avoid damaging
  • Step 2 As shown in FIG. 3 , the dielectric layer 1031 and the low-k dielectric 1032 are etched to form the first through hole 104 .
  • Step 3 As shown in FIG. 4 , a protective layer 105 is formed on the upper surface of the dielectric layer 1031 and the inner wall of the first through hole 104 by plasma enhanced chemical vapor deposition. This protective layer completely isolates the low-k media 1032.
  • the protective layer is made of inorganic materials such as silicon dioxide, silicon nitride, and aluminum oxide.
  • Step 4 as shown in Figure 5, arrange photoresist 106 above the dielectric layer 1031 and in the first through hole, and remove part of the photoresist in the first through hole through photolithography to form a hole pattern 107, and then etch The protective layer 105 is exposed at the bottom of the hole pattern 107 .
  • the size of the hole pattern 107 is smaller than the size of the first through hole 104 .
  • Step 5 as shown in FIG. 6 , the through-hole area in the active layer 102 and the substrate 101 located under the hole pattern 107 are etched through the Bosch process to form a through-silicon via 108 .
  • the size of the through silicon via 108 is smaller than the size of the first through hole 104 .
  • Step 6 as shown in FIG. 7, remove the photoresist 106 and clean the through silicon via 108.
  • the low-k dielectric 1032 is protected from corrosion damage by the protective layer 105 .
  • the protective layer of low-k dielectric has high practicability, simple process and good realizability. It can be applied to any product suitable for making TSV, such as CPU, GPU, ASIC, Memory, FPGA and other computing or storage chips. .
  • the present invention has at least the following beneficial effects: a protective low-k medium disclosed in the present invention
  • the active chip through-silicon via manufacturing method protects the low-k dielectric by making a protective layer, completely isolating the low-k dielectric, and preventing the low-k dielectric from being damaged during the cleaning of the through-silicon via; the protective layer
  • the production process is simple and compatible with the through-silicon via process; the protective layer has obvious features and is traceable.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及一种保护low-k介质的有源芯片硅通孔制作方法，包括：提供有源芯片，其中所述有源芯片包括衬底、金属互连层以及位于衬底与金属互连层之间的有源层，且所述有源层和金属互连层均具有通孔区，所述金属互连层包括多层介质层、位于多层介质层之间的low-k介质以及位于介质层和low-k介质中的金属布线；刻蚀介质层和low-k介质形成第一通孔；在介质层的上表面以及第一通孔的内壁制作保护层；在介质层的上方以及第一通孔内布置光刻胶，并通过光刻去除第一通孔中的部分光刻胶形成孔图形，然后刻蚀孔图形底部暴露出的保护层；刻蚀位于孔图形之下的有源层中的通孔区和衬底形成硅通孔；以及去除光刻胶，并清洗硅通孔。

Description

一种保护low-k介质的有源芯片硅通孔制作方法 技术领域
本发明涉及半导体封装技术领域，尤其涉及一种保护low-k介质的有源芯片硅通孔制作方法。
背景技术
在功能芯片上制作硅通孔(TSV)一般采用中通孔(via-middle TSV)的工艺路线，即先进行CMOS工艺，再进行TSV工艺，最后制作金属互连结构。由于硅通孔刻蚀后需要进行湿法清洗，如果有low-k(低介电常数)介质存在，对low-k介质会有验证的损伤，但是中通孔工艺路线的硅通孔制作是在金属互连层之前完成，因此，硅通孔制作时无需考虑金属互连结构中的low-k介质。然而中通孔的工艺路线只能在晶圆厂进行，而且全球范围内具有硅通孔技术的晶圆厂少之又少，因此，这种工艺路线受到很大的限制。
为了解决上述问题，业界提出正面后通孔的硅通孔工艺路线，即先进行CMOS工艺和金属互连结构制作，最后再进行硅通孔制作。这种工艺路线的硅通孔制作是在芯片加工完成后进行的，而且可以在封测厂进行。晶圆厂加工芯片，封测厂制作硅通孔，分工明确，上述的受限问题得到解决。
但是由于硅通孔是在完成金属互连结构之后进行的，硅通孔刻蚀需要穿过low-k介质，并且需要对硅通孔进行湿法清洗，如果没有对low-k结构提供有效的保护手段，low-k介质将会受到验证损伤。
发明内容
本发明的任务是提供一种保护low-k介质的有源芯片硅通孔制作方法，通过制作保护层来保护low-k介质，将low-k介质完全隔离，能够避免low-k介质的在清洗硅通孔的过程中受到腐蚀和损伤。
在本发明的第一方面，针对现有技术中存在的问题，本发明提供一种保护low-k介质的有源芯片硅通孔制作方法来解决，包括：
提供有源芯片，其中所述有源芯片包括衬底、金属互连层以及位于衬底与金属互连层之间的有源层，且所述有源层和金属互连层均具有通孔区，所述金属互连层包括多层介质层、位于多层介质层之间的low-k介质以及位于介质层和low-k介质中的金属布线；
刻蚀介质层和low-k介质形成第一通孔；
在介质层的上表面以及第一通孔的内壁制作保护层；
在介质层的上方以及第一通孔内布置光刻胶，并通过光刻去除第一通孔中的部分光刻胶形成孔图形，然后刻蚀孔图形底部暴露出的保护层；
刻蚀位于孔图形之下的有源层中的通孔区和衬底形成硅通孔；以及
去除光刻胶，并清洗硅通孔。
进一步地，通过等离子体增强化学气相沉积法在介质层的上表面以及第一通孔的内壁制作保护层。
进一步地，所述保护层的材料为无机材料。
进一步地，所述孔图形的尺寸小于所述第一通孔的尺寸。
进一步地，通过博世工艺刻蚀位于所述孔图形之下的所述有源层中的通孔区和所述衬底形成硅通孔。
进一步地，所述硅通孔的尺寸小于所述第一通孔的尺寸。
进一步地，所述保护层的材料为二氧化硅、氮化硅和/或氧化铝。
本发明至少具有下列有益效果：本发明公开的一种保护low-k介质的有源芯片硅通孔制作方法，通过制作保护层来保护low-k介质，将low-k介质完全隔离，能够避免low-k介质的在清洗硅通孔过程中受到损伤；该保护层的制作工艺简单，能够兼容硅通孔工艺；该保护层特征明显，具有可追溯性。
附图说明
为了进一步阐明本发明的各实施例的以上和其它优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明的典型实施例，因此将不被认为是对其范围的限制。在附图中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。
图1示出了根据本发明一个实施例的在有源芯片中制作硅通孔的流程图；以及
图2至图7示出了根据本发明一个实施例的有源芯片的硅通孔的制作过程示意图。
具体实施方式
应当指出，各附图中的各组件可能为了图解说明而被夸大地示出，而不一定是比例正确的。
在本发明中，各实施例仅仅旨在说明本发明的方案，而不应被理解为限制性的。
在本发明中，除非特别指出，量词“一个”、“一”并未排除多个元素的场景。
在此还应当指出，在本发明的实施例中，为清楚、简单起见，可能示出了仅仅一部分部件或组件，但是本领域的普通技术人员能够理解，在本发明的教导下，可根据具体场景需要添加所需的部件或组件。
在此还应当指出，在本发明的范围内，“相同”、“相等”、“等于”等措辞并不意味着二者数值绝对相等，而是允许一定的合理误差，也就是说，所述措辞也涵盖了“基本上相同”、“基本上相等”、“基本上等于”。
在此还应当指出，在本发明的描述中，术语“中心”、“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是明示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为明示或暗示相对重要性。
另外，本发明的实施例以特定顺序对工艺步骤进行描述，然而这只是为了方便区分各步骤，而并不是限定各步骤的先后顺序，在本发明的不同实施例中，可根据工艺的调节来调整各步骤的先后顺序。
本发明基于发明人的如下洞察：
在有源芯片上制作硅通孔时，硅通孔刻蚀需要穿过low-k介质，并且刻蚀完成后需要对硅通孔进行湿法清洗。清洗液具有腐蚀性，如果不对low-k介质进行保护，清洗的过程中low-k介质将会受到验证损伤，而且low-k介质的结构疏松，清洗液会渗透，从而腐蚀金属互连结构中的金属布线。
二氧化硅、氮化硅、氧化铝等无机材料不会被清洗液耐腐蚀，因此可以作为low-k介质的保护层，避免中low-k介质受到验证损伤。
图1示出了根据本发明一个实施例的在有源芯片中制作硅通孔的流程图；图2至图7示出了根据本发明一个实施例的有源芯片的硅通孔的制作过程示意图。
步骤1，如图2所示，提供有源芯片100。有源芯片包括衬底101、有源层102、金属互连层103。有源层102位于衬底101和金属互连层103之间。金属互连层103包括多层介质层1031、位于多层介质层之间的low-k介质1032以及位于介质层和low-k介质中的金属布线1033。low-k介质1032为低介电常数的绝缘材料。有源层102中包含了有源区1021。有源层102和金属互连层103均具有预留的通孔区(不含有源器件和金属布线的空白区域)，可以在该通孔区刻蚀通孔，从而避免损伤金属布线1032和有源器件1021。
步骤2，如图3所示，刻蚀介质层1031和low-k介质1032形成第一通孔104。
步骤3，如图4所示，通过等离子体增强化学气相沉积法在介质层1031的上表面以及第一通孔104的内壁制作保护层105。该保护层将low-k介质1032完全隔离。在本发明的一个实施例中，保护层的材料为二氧化硅、氮化硅、氧化铝等无机材料。
步骤4，如图5所示，在介质层1031的上方以及第一通孔内布置光刻胶106，并通过光刻去除第一通孔中的部分光刻胶形成孔图形107，然后刻蚀孔图形107底部暴露出的保护层105。孔图形107的尺寸小于第一通孔104的尺寸。
步骤5，如图6所示，通过博世工艺刻蚀位于孔图形107之下的有源层102中的通孔区和衬底101形成硅通孔108。硅通孔108的尺寸小于第一通孔104的尺寸。
步骤6，如图7所示，去除光刻胶106，并清洗硅通孔108。在清洗的过程中low-k介质1032在保护层105的保护下免受腐蚀损伤。
low-k介质的保护层的实用性高，工艺简单，具有良好的可实现性，可应用于任意适合于制作TSV的产品，如CPU、GPU、ASIC、Memory、FPGA等计算类或存储类芯片。
本发明至少具有下列有益效果：本发明公开的一种保护low-k介质 的有源芯片硅通孔制作方法，通过制作保护层来保护low-k介质，将low-k介质完全隔离，能够避免low-k介质的在清洗硅通孔过程中受到损伤；该保护层的制作工艺简单，能够兼容硅通孔工艺；该保护层特征明显，具有可追溯性。
虽然本发明的一些实施方式已经在本申请文件中予以了描述，但是本领域技术人员能够理解，这些实施方式仅仅是作为示例示出的。本领域技术人员在本发明的教导下可以想到众多的变型方案、替代方案和改进方案而不超出本发明的范围。所附权利要求书旨在限定本发明的范围，并藉此涵盖这些权利要求本身及其等同变换的范围内的方法和结构。

Claims (7)

  1. 一种保护low-k介质的有源芯片硅通孔制作方法，包括：
    提供有源芯片，其中所述有源芯片包括衬底、金属互连层以及位于衬底与金属互连层之间的有源层，且所述有源层和金属互连层均具有通孔区，所述金属互连层包括多层介质层、位于多层介质层之间的low-k介质以及位于介质层和low-k介质中的金属布线；
    通过刻蚀介质层和low-k介质形成第一通孔；
    在介质层的上表面以及第一通孔的内壁制作保护层；
    在介质层的上方以及第一通孔内布置光刻胶，并通过光刻去除第一通孔中的部分光刻胶形成孔图形，然后刻蚀孔图形底部暴露出的保护层；
    刻蚀位于孔图形之下的有源层中的通孔区和衬底形成硅通孔；以及
    去除光刻胶，并清洗硅通孔。
  2. 根据权利要求1所述的保护low-k介质的有源芯片硅通孔制作方法，其特征在于，通过等离子体增强化学气相沉积法在介质层的上表面以及第一通孔的内壁制作保护层。
  3. 根据权利要求1所述的保护low-k介质的有源芯片硅通孔制作方法，其特征在于，所述保护层的材料为无机材料。
  4. 根据权利要求1所述的保护low-k介质的有源芯片硅通孔制作方法，其特征在于，所述孔图形的尺寸小于所述第一通孔的尺寸。
  5. 根据权利要求1所述的保护low-k介质的有源芯片硅通孔制作方法，其特征在于，通过博世工艺刻蚀位于所述孔图形之下的所述有源层中的通孔区和所述衬底形成硅通孔。
  6. 根据权利要求1所述的保护low-k介质的有源芯片硅通孔制作方法，其特征在于，所述硅通孔的尺寸小于所述第一通孔的尺寸。
  7. 根据权利要求1所述的保护low-k介质的有源芯片硅通孔制作方法，其特征在于，所述保护层的材料为二氧化硅、氮化硅和/或氧化铝。
PCT/CN2023/081829 2022-05-27 2023-03-16 一种保护low-k介质的有源芯片硅通孔制作方法 WO2023226547A1 (zh)

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CN103918068A (zh) * 2011-11-09 2014-07-09 高通股份有限公司 用于穿过低k布线层来图案化穿板通孔的低k介电保护分隔物
US20150137388A1 (en) * 2013-11-21 2015-05-21 Eun-ji Kim Semiconductor devices
CN113517221A (zh) * 2020-03-26 2021-10-19 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN115000005A (zh) * 2022-05-27 2022-09-02 华进半导体封装先导技术研发中心有限公司 一种保护low-k介质的有源芯片硅通孔制作方法

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CN101355047A (zh) * 2007-07-27 2009-01-28 中芯国际集成电路制造(上海)有限公司 在低介电常数介质层中形成通孔的方法
CN103918068A (zh) * 2011-11-09 2014-07-09 高通股份有限公司 用于穿过低k布线层来图案化穿板通孔的低k介电保护分隔物
US20150137388A1 (en) * 2013-11-21 2015-05-21 Eun-ji Kim Semiconductor devices
CN113517221A (zh) * 2020-03-26 2021-10-19 台湾积体电路制造股份有限公司 半导体结构及其形成方法
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