WO2023226087A1 - 封装基板、电源噪声测试装置及电源噪声测试方法 - Google Patents

封装基板、电源噪声测试装置及电源噪声测试方法 Download PDF

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Publication number
WO2023226087A1
WO2023226087A1 PCT/CN2022/097546 CN2022097546W WO2023226087A1 WO 2023226087 A1 WO2023226087 A1 WO 2023226087A1 CN 2022097546 W CN2022097546 W CN 2022097546W WO 2023226087 A1 WO2023226087 A1 WO 2023226087A1
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Prior art keywords
test
power supply
power
pad
pads
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PCT/CN2022/097546
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English (en)
French (fr)
Inventor
石宏龙
马茂松
刘建斌
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长鑫存储技术有限公司
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Priority to US17/951,625 priority Critical patent/US11959938B2/en
Publication of WO2023226087A1 publication Critical patent/WO2023226087A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/26—Measuring noise figure; Measuring signal-to-noise ratio
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a packaging substrate, a power supply noise testing device and a power supply noise testing method.
  • DDR Double Data Rate
  • the power signal in order to verify the integrity of the power supply, the power signal generally needs to be tested during the operation of the SDRAM chip.
  • the power signal can be brought out through a signal test board to test it, or a power test point can be added to the system motherboard to test it.
  • the pins of the same power supply signal are connected together, which makes it impossible to accurately measure the power supply noise inside the chip during the power signal test.
  • the present disclosure provides a packaging substrate, a power supply noise testing device and a power supply noise testing method, which can not only test the power supply noise inside the chip, but also improve the accuracy of the testing.
  • an embodiment of the present disclosure provides a packaging substrate.
  • the packaging substrate includes a plurality of pad arrays, and each pad array includes at least a power pad; wherein:
  • Power pads belonging to the same power type in multiple pad arrays are divided into test pads and power pad sets; where the power pad set includes other power pads that belong to the same power type except the test pads, And the power pads in the power pad set are all electrically connected together; the test pads are used for noise testing of the internal power supply corresponding to the same power supply type in the chip under test.
  • the packaging substrate includes four pad arrays; wherein the four pad arrays have an up-down and left-right symmetrical structure.
  • the packaging substrate further includes a conductive layer; wherein, in the conductive layer, the power pads in the power pad set are electrically connected using copper laying to form the first power network, and the test pad is independent of the third power network.
  • a power network
  • the surface of the packaging substrate is provided with gold fingers; wherein, in the same power supply type, the distance between the test pad and the gold finger is smaller than the distance between the power pad and the gold finger in the power pad set. .
  • a chip to be tested is also placed on the surface of the packaging substrate, and the chip to be tested includes multiple pin arrays, each pin array includes at least a power pin; wherein, the multiple pin arrays belong to the same
  • the power supply pins of the power type are divided into test pins and power pin sets; among them, the power pins in the power pin set are electrically connected to the power pads in the power pad set, and the test pins are electrically connected to the test pads. Electrical connection, so that the test pad can perform noise testing on the internal power supply corresponding to the same power supply type in the chip under test through the test pin.
  • the package substrate is also provided with metal vias and metal traces; wherein the test pads are electrically connected to the gold fingers through metal traces and metal vias, and gold wires are used between the gold fingers and the test pins. Electrical connection is made in this way to realize that the test pad and the test pin are electrically connected together.
  • each pad array at least includes a VDD1 power pad, a VDD2 power pad, and a VDDQ power pad; wherein the same power source type is any one of the VDD1 power source type, the VDD2 power source type, and the VDDQ power source type. .
  • the power pads belonging to the VDD1 power type in the multiple pad arrays are divided into VDD1 power test pads and a VDD1 power pad set; wherein, all power pads in the VDD1 power pad set are electrically connected To form a VDD1 power supply network, and the VDD1 power supply test pad is independent of the VDD1 power supply network.
  • the VDD1 power supply test pad is used for noise testing of the VDD1 power supply inside the chip under test; the power supply pads belonging to the VDD2 power supply type in multiple pad arrays It is divided into VDD2 power test pad and VDD2 power pad set; among them, the power pads in the VDD2 power pad set are all electrically connected to form a VDD2 power network, and the VDD2 power test pad is independent of the VDD2 power network, and the VDD2 power
  • the test pads are used for noise testing of the VDD2 power supply inside the chip under test; the power pads belonging to the VDDQ power supply type in the multiple pad arrays are divided into VDDQ power supply test pads and VDDQ power supply pad sets; among them, the VDDQ power supply pads All power pads in the pad set are electrically connected to form a VDDQ power network, and the VDDQ power test pad is independent of the VDDQ power network.
  • the VDDQ power test pad is used for noise testing of the VDDQ power supply inside the chip under test.
  • inventions of the present disclosure provide a power supply noise testing device.
  • the power supply noise testing device includes the packaging substrate, a chip under test, and a test board as described in the first aspect; wherein:
  • the test board is provided with a first test point corresponding to the first power supply type
  • the chip under test at least includes power pins corresponding to the first power type, and the power pins are divided into first test pins and a first set of power pins except the first test pins;
  • the packaging substrate at least includes power supply pads corresponding to the first power supply type, and the power supply pads are divided into first test pads and a first set of power supply pads other than the first test pads;
  • the power pins in the first power pin set are electrically connected to the power pads in the first power pad set
  • the first test pin is electrically connected to the first test pad
  • the first test pad is also electrically connected. It is electrically connected to the first test point, so that the first test point can perform noise testing on the internal power supply corresponding to the first power supply type in the chip under test through the first test pad and the first test pin.
  • the chip under test, the packaging substrate and the test board are stacked in sequence.
  • the test board is further provided with multiple solder point arrays corresponding to multiple pad arrays in the packaging substrate, and each solder point array includes at least power supply solder points; wherein, the multiple solder point arrays
  • the power supply solder points belonging to the first power supply type are divided into a first test solder point and a first power supply solder point set.
  • the power supply solder points in the first power supply solder point set correspond to the power supply pads in the first power supply pad set. Electrically connected, and all power supply solder points in the first power supply solder point set are electrically connected together to form a first power supply network; wherein, the first test solder point is independent of the first power supply network.
  • the test board is further provided with a first metal trace; wherein the first test pad is connected to the first test solder point, and the first test solder point is electrically connected to the first test point through the first metal trace. connection to achieve electrical connection between the first test pad and the first test point.
  • the test board is further provided with a first resistance mark, and the first resistance mark includes a first solder point and a second solder point; wherein the first solder point is connected to the first test solder point, and the second solder point Connect to the first power network.
  • the first resistor in the test mode, is not soldered at the first resistance mark, so that the first test soldering point is disconnected from the first power network; in the working mode, the first resistor mark is soldered The first resistor is so that the first test soldering point and the first power network are in an electrical connection state.
  • the resistance of the first resistor is 0 ohms.
  • the first power supply type is any one of VDD1 power supply type, VDD2 power supply type and VDDQ power supply type; wherein, on the test board, different first power supply types are provided with different first test points. and different first resistor identification.
  • embodiments of the present disclosure provide a power supply noise testing method, which is applied to the power supply noise testing device described in the second aspect.
  • the method includes:
  • the test mode perform a noise test on the internal power supply corresponding to the first power supply type in the chip under test through the first test point on the test board; wherein the first test point has a corresponding relationship with the first power supply type, and the first power supply type It is any one of VDD1 power supply type, VDD2 power supply type and VDDQ power supply type.
  • the test board is further provided with multiple solder point arrays corresponding to multiple pad arrays in the packaging substrate, and each solder point array includes at least power supply solder points; wherein, the multiple solder point arrays
  • the power supply solder points belonging to the first power supply type are divided into a first test solder point and a first power supply solder point set.
  • the power supply solder points in the first power supply solder point set correspond to the power supply pads in the first power supply pad set. Electrically connected, and all power supply solder points in the first power supply solder point set are electrically connected together to form a first power supply network; wherein, the first test solder point is independent of the first power supply network.
  • the test board is further provided with a first resistance mark
  • the method further includes: in the working mode, determining and welding a first resistor at the first resistance mark, and controlling the first test soldering point and the first resistance mark through the first resistance.
  • the power network is electrically connected.
  • the method further includes: in the test mode, determining that the first resistor is not soldered at the first resistance mark, so that the first test soldering point is disconnected from the first power network.
  • Embodiments of the present disclosure provide a packaging substrate, a power supply noise testing device and a power supply noise testing method.
  • the packaging substrate includes a plurality of pad arrays, and each pad array includes at least a power pad, Power pads belonging to the same power type in multiple pad arrays are divided into test pads and power pad sets; where the power pad set includes other power pads that belong to the same power type except the test pads, And the power pads in the power pad set are all electrically connected together; the test pads are used for noise testing of the internal power supply corresponding to the same power supply type in the chip under test.
  • the power supply noise testing device includes a packaging substrate, a chip under test and a test board; wherein the test board is provided with a first test point corresponding to the first power supply type; the chip under test at least includes a first power supply type Corresponding power pins, and the power pins are divided into first test pins and a first set of power pins except the first test pin; the packaging substrate at least includes a power pad corresponding to the first power type, and The power pads are divided into a first test pad and a first power pad set except the first test pad; wherein, the power pins in the first power pin set are different from the power pins in the first power pad set.
  • the power pad is electrically connected
  • the first test pin is electrically connected to the first test pad
  • the first test pad is also electrically connected to the first test point, so that the first test point can pass through the first test pad and
  • the first test pin performs noise testing on the internal power supply corresponding to the first power supply type in the chip under test.
  • a pin is independently used as the first test pin on the package substrate, and the first test point is set on the test board, and then the first test pin and the first test point are
  • the connection not only enables the signal used to test the power supply noise to be drawn out through the first test point, but also realizes that the test signal is independent of the first power supply network corresponding to the first power supply type; in this way, the signal used to test the power supply noise is treated by the first test point on the test board. Testing the internal power supply in the chip for noise testing can improve the testing accuracy of power supply noise.
  • Figure 1 is a schematic layout diagram of a packaging substrate
  • Figure 2 is a schematic diagram of the test results of a chip power supply noise
  • Figure 3 is a schematic structural diagram of a packaging substrate according to an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of another packaging substrate according to an embodiment of the present disclosure.
  • Figure 5 is a partially enlarged schematic diagram of a packaging substrate provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of a packaging substrate provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of a power supply noise testing device provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of another power supply noise testing device according to an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of test results of an internal power supply noise provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic flow chart of a power supply noise testing method according to an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • SDRAM Synchronous Dynamic Random Access Memory
  • the power signal can be led out through the SDRAM signal test board and then tested; or a power test point can also be added to the system motherboard to test it.
  • a power test point can also be added to the system motherboard to test it.
  • pins with the same power supply signals are connected together, resulting in the inability to accurately measure the power supply noise inside the chip when testing the power supply.
  • VDD1 power type there can be at least three types of power signals, such as VDD1 power type, VDD2 power type and VDDQ power type, and each power type can have multiple power pins corresponding to it.
  • the chip can be set with multiple VDD1 power pins, multiple VDD2 power pins and multiple VDDQ power pins. These power pins can be connected to the corresponding VDD1 power pads, VDD2 power pads and VDDQ on the packaging substrate. The power pads are electrically connected respectively.
  • FIG. 1 shows a schematic layout diagram of a packaging substrate.
  • two types of power pads can be included: VDD2 power pad and VDDQ power pad.
  • VDD2 power pad and VDDQ power pad.
  • all VDD2 power pads belonging to the VDD2 power type are all connected together to form a VDD2 power network
  • VDDQ power pads belonging to the VDDQ power type are all connected together to form a VDDQ power network.
  • Figure 2 shows a schematic diagram of the test results of chip power supply noise.
  • (a) is the power supply noise test result inside the chip
  • (b) is the power supply noise test result outside the chip.
  • the internal power supply noise refers to the power supply noise actually measured inside the chip
  • the external power supply noise refers to the power supply noise measured outside the chip in a conventional way.
  • the bold solid line box reflects that the power supply noise inside the chip is very serious; but for the corresponding period in (b), there is almost no power supply noise measured outside the chip. Details See bold dashed box.
  • the VDD1 power pad, VDD2 power pad and VDDQ power pad are all connected together on the package substrate, that is, the power pins corresponding to the same power signal are all connected together.
  • the power supply noise test in related technologies cannot distinguish.
  • the external test is the overall noise of a type of power supply signal, so that the external noise measured in the conventional way cannot correctly reflect the actual noise inside the chip, thus As a result, the accurate internal power supply noise of the chip cannot be directly measured when testing the power supply.
  • embodiments of the present disclosure provide a packaging substrate.
  • the packaging substrate includes multiple pad arrays, and each pad array includes at least a power pad.
  • the power pads belonging to the same power type in the multiple pad arrays are The pads are divided into test pads and power pad sets; where the power pad set includes other power pads that belong to the same power type except the test pads, and all power pads in the power pad set are electrically connected Together; the test pad is used for noise testing of the internal power supply corresponding to the same power supply type in the chip under test.
  • Embodiments of the present disclosure also provide a power supply noise testing device and a power supply noise testing method. The method is applied to the power supply noise testing device.
  • the power supply noise testing device includes a packaging substrate, a chip to be tested, and a test board; wherein, the test board is provided with A first test point corresponding to the first power type; the chip under test at least includes a power pin corresponding to the first power type, and the power pin is divided into a first test pin and a first test pin other than the first test pin.
  • a set of power pins the packaging substrate at least includes power pads corresponding to the first power type, and the power pads are divided into a first test pad and a first set of power pads other than the first test pad, and the first
  • the power pins in the power pin set are electrically connected to the power pads in the first power pad set
  • the first test pin is electrically connected to the first test pad
  • the first test pad is also connected to the first test pad.
  • the points are electrically connected, so that the first test point can perform noise testing on the internal power supply corresponding to the first power supply type in the chip under test through the first test pad and the first test pin.
  • a pin is independently used as the first test pin on the package substrate, and the first test point is set on the test board, and then the first test pin and the first test point are
  • the connection not only enables the signal used to test the power supply noise to be drawn out through the first test point, but also realizes that the test signal is independent of the first power supply network corresponding to the first power supply type; in this way, the signal used to test the power supply noise is treated by the first test point on the test board. Testing the internal power supply in the chip for noise testing can improve the testing accuracy of power supply noise.
  • FIG. 3 shows a schematic structural diagram of a packaging substrate provided by an embodiment of the present disclosure.
  • the package substrate 40 may include multiple pad arrays (such as pad array 401 , pad array 402 , pad array 403 , and pad array 404 ), and each pad array includes at least a power supply solder. Disk; among them:
  • the power pads belonging to the same power type in the multiple pad arrays are divided into test pads 411 and a power pad set.
  • the power pad set may include other power pads belonging to the same power type except the test pad 411.
  • Pad 412, and all power pads in the power pad set are electrically connected together;
  • the test pad 411 can be used to perform noise testing on the internal power supply corresponding to the same power supply type in the chip under test.
  • the package substrate (Package Substrate), referred to as SUB, can provide functions such as electrical connection, protection, support, heat dissipation, and assembly for the chip under test to achieve multi-pin and shrink packaging.
  • the packaging substrate is the carrier of the semiconductor chip packaging. It mainly fixes the cut wafer (Die) to the packaging substrate, and uses ultra-fine metal wires or conductive resin to realize the bonding between the Die and the pads on the packaging substrate. Make electrical connections.
  • the chip to be tested may refer to a wafer or a wafer, which is represented by Die.
  • the internal power supply in Die can include multiple power supply types, such as VDD1 power supply type, VDD2 power supply type, VDDQ power supply type, etc.
  • VDDQ can be regarded as the power supply for the input and output buffer circuit (Inputs/Outputs Buffer, IO Buffer);
  • VDD1 and VDD2 can be regarded as the power supply for the chip core, but the voltages of VDD1 and VDD2 are different.
  • the embodiment of the present disclosure can perform the noise test on the internal power supply corresponding to the VDD1 power supply type, or it can also perform the noise test on the internal power supply corresponding to the VDD2 power supply type, or it can also This is a noise test for the internal power supply corresponding to the VDDQ power supply type, and there is no limit to this here.
  • Pad 411 the remaining 19 power pads (such as 412) form a power pad set corresponding to the VDDQ power type, and all power pads in the power pad set are electrically connected together.
  • multiple power supply pads of the same power supply type one of them can be independently selected as a test pad, and then all the remaining power supply pads can be electrically connected together. In this way, using independent test pads to conduct noise tests on the internal power supply in the chip under test can accurately measure the noise of the chip's internal power supply.
  • the packaging substrate 40 may include four pad arrays; wherein the four pad arrays have an up-down and left-right symmetrical structure.
  • the packaging substrate 40 may include a pad array 401 , a pad array 402 , a pad array 403 and a pad array 404 .
  • the four pad arrays can have a left-right symmetrical structure along the horizontal direction or an up-down symmetrical structure along the vertical direction. In this way, in the design of the packaging substrate 40, the distribution of these pad arrays is symmetrical and the overall appearance is good.
  • the packaging substrate 40 may also include a conductive layer 413; wherein, in the conductive layer 413, the power pads in the power pad set adopt The copper laying method is used for electrical connection to form a first power network, and the test pad 411 is independent of the first power network.
  • the packaging substrate 40 may be a multi-layer board, in which each layer may serve as a conductive layer.
  • each layer may serve as a conductive layer.
  • VDD1 power type VDD2 power type
  • VDDQ power type different layers can realize electrical connection of power pads corresponding to different power types respectively, and can also realize the same power supply.
  • Type of large-area copper laying can improve the over-current capability, while reducing the impedance of the power supply, effectively suppressing crosstalk between signals, and also achieving the purpose of conducive to heat dissipation.
  • Figure 1 can be regarded as one conductive layer
  • Figure 4 can be regarded as another conductive layer.
  • the surface of the packaging substrate 40 is provided with gold fingers; wherein, in the same power supply type, the distance between the test pad and the gold finger is smaller than the distance between the power pad and the gold finger in the power pad set. the distance between.
  • the independent test pad can be any power pad of the same power type. In a specific implementation, it can also be in the same power supply type, and the selected test pad needs to be as close as possible to the gold finger on the packaging substrate 40, so that the wiring is as short as possible and the wiring loop is as small as possible.
  • FIG. 5 shows a partially enlarged schematic diagram of a packaging substrate provided by an embodiment of the present disclosure.
  • the arrangement of the golden fingers 414 on the packaging substrate is schematically illustrated.
  • the distance between the finally selected test pad and the gold finger needs to be smaller than the distance between other power supply pads and the gold finger.
  • a chip to be tested (not shown in the figure) is also placed on the surface of the packaging substrate 40 , and the chip to be tested includes multiple pin arrays, each pin array including at least a power pin. ;in:
  • Power pins belonging to the same power type in multiple pin arrays are divided into test pins and power pin sets; among them, the power pins in the power pin set are electrically connected to the power pads in the power pad set. , the test pin is electrically connected to the test pad, so that the test pad can perform noise testing on the internal power supply corresponding to the same power supply type in the chip under test through the test pin.
  • the power supply pads on the packaging substrate need to be divided to separate one power supply pad as a test pad, and then all other power supply pads are connected together; and for the chip under test, correspondingly, the power pin of the chip under test also needs to be divided to separate a power pin as a test pin, so that the test pad can pass the test pin to be tested
  • the internal power supply corresponding to the same power supply type in the chip is tested for noise.
  • the multiple pin arrays of the chip under test there is a corresponding relationship between the multiple pin arrays of the chip under test and the multiple pad arrays of the packaging substrate.
  • Each pin is connected to a pad on the packaging substrate.
  • the multiple pin arrays also have a left-right symmetrical structure along the horizontal direction, and an up-down symmetrical structure along the vertical direction.
  • the test pin is electrically connected to the test pad, and the remaining other power supply pins are connected to the power pads in the power pad set.
  • the external power supply can realize the noise test of the internal power supply corresponding to the same power supply type in the chip under test, and can also improve the test accuracy of the power supply noise.
  • the package substrate 40 is also provided with metal vias and metal traces; wherein, the test pad is electrically connected to the gold finger through the metal trace and metal via hole, and there is a gap between the gold finger and the test pin. Use gold wires for electrical connection to electrically connect the test pads and test pins together.
  • the selected test pad 411 is connected to the gold finger provided on the surface of the packaging substrate 40 through wiring and via holes on the back side of the packaging substrate 40, and then is connected to the gold finger through drilling. Connect the gold wire to the power pin of the chip under test.
  • other power supply pads can also be connected from the back of the package substrate 40 to gold fingers provided on the surface of the package substrate 40 through traces and via holes, and then connected to other power sources of the chip under test through gold wires. pins to achieve electrical connection between the power pads of the packaging substrate 40 and the power pins of the chip under test.
  • FIG. 6 shows a specific structural schematic diagram of a packaging substrate 40 provided by an embodiment of the present disclosure.
  • a packaging substrate 40 may include: gold fingers 414, gold wires 415, chip under test 416 and pad array 417.
  • a pad array 417 is provided on the back of the packaging substrate 40 . Taking the test pads in the pad array 417 as an example, they are connected to the packaging substrate 40 from the back of the packaging substrate 40 through traces and vias. The gold fingers 414 provided on the surface are then connected to the test pins of the chip under test 416 through gold wires 415, thereby achieving electrical connection between the test pads and the test pins.
  • each pad array at least includes a VDD1 power pad, a VDD2 power pad and a VDDQ power pad; wherein the same power type is one of the VDD1 power type, VDD2 power type and VDDQ power type. Any one.
  • the power supply pads here may include at least three types, such as VDD1 power supply pad, VDD2 power supply pad, VDDQ power supply pad, etc.; correspondingly, the same power supply type may be VDD1 power supply pad.
  • Type any one of VDD2 power type and VDDQ power type.
  • the methods of power supply noise testing are similar. Each can separately implement a noise test of the VDD1 power supply in the chip under test, or a noise test of the VDD2 power supply in the chip under test, or Noise test of VDDQ power supply in the chip under test.
  • the power supply pads belonging to the VDD1 power supply type in the multiple pad arrays are divided into VDD1 power supply test pads and VDD1 power supply pad sets; where, the VDD1 power supply pad The power pads in the set are all electrically connected to form a VDD1 power network, and the VDD1 power test pad is independent of the VDD1 power network.
  • the VDD1 power test pad is used for noise testing of the VDD1 power supply inside the chip under test.
  • the power supply pads belonging to the VDD2 power supply type in the multiple pad arrays are divided into VDD2 power supply test pads and VDD2 power supply pad sets; wherein, the VDD2 power supply pads All power pads in the pad set are electrically connected to form a VDD2 power network, and the VDD2 power test pad is independent of the VDD2 power network.
  • the VDD2 power test pad is used for noise testing of the VDD2 power supply inside the chip under test;
  • the power supply pads belonging to the VDDQ power supply type in the multiple pad arrays are divided into VDDQ power supply test pads and VDDQ power supply pad sets; wherein, the VDDQ power supply pad set All power pads in the pad set are electrically connected to form a VDDQ power network, and the VDDQ power test pad is independent of the VDDQ power network.
  • the VDDQ power test pad is used for noise testing of the VDDQ power supply inside the chip under test.
  • these power supply pads can be divided into corresponding test pads and power supply pad sets, as well as the chip under test.
  • the power pins in the power pad set can also be divided into corresponding test pins and power pin sets; then all the power pads in the power pad set are electrically connected together through copper laying to achieve the purpose of eliminating the test pins.
  • the other power supply pins are all electrically connected together.
  • test pad of the VDD1 power supply is independent of the VDD1 power supply network
  • test pad of the VDD2 power supply is independent of the VDD2 power supply network
  • test pad of the VDDQ power supply is independent of the VDDQ power supply network
  • the VDD1 power network, VDD2 power network and VDDQ power network are also independent of each other.
  • test pad is named VDDQ1
  • VDDQ1 the corresponding test pin on the chip under test
  • Embodiments of the present disclosure provide a packaging substrate.
  • the packaging substrate includes multiple pad arrays, and each pad array includes at least power pads. Power pads belonging to the same power type in the multiple pad arrays are divided. It is a set of test pads and power pads; wherein the power pad set includes other power pads that belong to the same power supply type except the test pads, and the power pads in the power pad set are all electrically connected together;
  • the test pad is used for noise testing of the internal power supply corresponding to the same power supply type in the chip under test. In this way, although the power pads in the power pad set are all electrically connected together, the test pads are not electrically connected to them. Using independent test pads to perform noise tests on the internal power supply in the chip under test can accurately measure The internal power supply noise of the chip thus improves the test accuracy of power supply noise.
  • FIG. 7 shows a schematic structural diagram of a power supply noise testing device 80 provided by an embodiment of the present disclosure.
  • the power supply noise testing device 80 may include a packaging substrate 801, a chip under test 802 and a test board 803; where:
  • the test board 803 is provided with a first test point a corresponding to the first power supply type
  • the chip under test 802 at least includes power pins corresponding to the first power type, and the power pins are divided into first test pins and a first set of power pins except the first test pins;
  • the packaging substrate 801 may at least include power supply pads corresponding to the first power supply type, and the power supply pads are divided into first test pads and a first set of power supply pads other than the first test pads.
  • the power pins in the first power pin set are electrically connected to the power pads in the first power pad set
  • the first test pin is electrically connected to the first test pad
  • the first test pad is also electrically connected. It is electrically connected to the first test point, so that the first test point can perform noise testing on the internal power supply corresponding to the first power supply type in the chip under test through the first test pad and the first test pin.
  • the packaging substrate 801 may be the packaging substrate 40 provided in the previous embodiment.
  • the test board 803 can be a signal test board or a system main board, without any limitation here.
  • test points can be set on the test board 803.
  • a corresponding first test point can be set on the test board 803, and then the power signal to be tested can be led out through the first test point, so that internal testing can be performed outside the chip 802 under test. Power supply noise test, and the test accuracy of power supply noise is high.
  • the number of test points on the test board 803 can also be There are multiple test points, and the number of test points is related to the number of power supply types; in other words, different test points are correspondingly set on the test board 803 for different power supply types.
  • the first power supply type may be any one of VDD1 power supply type, VDD2 power supply type and VDDQ power supply type; wherein, on the test board 803, different first power supply types are correspondingly provided with different first power supply types. Test point.
  • a VDD1 test point corresponding to the VDD1 power supply type, a VDD2 test point corresponding to the VDD2 power supply type, and a VDDQ test point corresponding to the VDDQ power supply type can be set; and then the chip under test can be implemented through the VDD1 test point
  • the VDD1 power supply inside the 802 is tested for noise.
  • the VDD2 test point can be used to test the VDD2 power supply inside the chip 802 under test.
  • the VDDQ test point can be used to test the VDDQ power supply inside the chip 802 under test.
  • the chip under test 802 the packaging substrate 801 and the test board 803 are stacked in sequence.
  • the chip under test 802 is disposed above the packaging substrate 801 and the test board 803 is disposed below the packaging substrate 801 , thereby forming a stacked structure.
  • This stacked structure can not only save layout space, but also The overall aesthetics are good.
  • the test board 803 may also be provided with multiple solder point arrays (such as solder point array 831, solder point array 832, solder point arrays) corresponding to multiple pad arrays in the packaging substrate 801. Array 833 and solder point array 834), and each solder point array includes at least power supply solder points; where:
  • the power supply solder points belonging to the first power supply type in the plurality of solder joint arrays are divided into a first test solder point b and a first power supply solder point set.
  • the power supply solder points in the first power supply solder point set are different from the first power supply pad set.
  • the power pads in correspond to electrical connections, and all the power pads in the first power pad set are electrically connected together to form a first power network; where the first test pad a is independent of the first power network.
  • the test board 803 may include a solder point array 831 , a solder point array 832 , a solder point array 833 and a solder point array 834 .
  • the four solder spot arrays can have a left-right symmetrical structure along the X-axis direction, or an up-down symmetrical structure along the Y-axis direction.
  • the power pins in the chip 802 under test also need to be divided to separate one power pin as the first test pin, and then other power pins are electrically connected to the corresponding power pads to achieve All power pins except the first test pin are also electrically connected to the first power network, but the first test pin is not connected to the first power network; correspondingly, the power solder joints in the test board 803 also need to be Similarly, separate a power supply solder point as the first test solder point, and then the first test pin passes through the first test pad, the first test solder point and the first test point in order to be electrically connected, so that the chip under test 802 Externally, the first test point can be used to perform noise testing on the internal power supply corresponding to the first power supply type in the chip under test.
  • the test board 803 is also provided with a first metal trace; wherein the first test pad is connected to the first test solder point, and the first test solder point is connected to the first test solder point through the first metal trace.
  • a test point is electrically connected to realize the electrical connection between the first test pad and the first test point.
  • the thick solid line on the test board 803 represents the first metal trace. It can be clearly seen from Figure 7 that the first test pin is electrically connected to the first test solder point through the first test pad in the package substrate 801, and then on the test board 803, the first test solder point passes through the metal The trace is electrically connected to the first test point a to realize the electrical connection between the first test pin and the first test point; thus, the power signal to be tested can be led to the outside of the chip to be tested 802 to facilitate power supply noise testing. .
  • the test board 803 can also be provided with a first resistance mark R1, and the first resistance mark R1 includes a first solder point and a second solder point; wherein, the first solder point and The first test solder point is connected, and the second solder point is connected to the first power network.
  • the first resistor in the test mode, is not welded at the first resistor mark R1, so that the first test solder point is disconnected from the first power supply network; in the working mode, the first resistor is not welded to the first resistor mark R1.
  • the first resistor is welded at the resistance mark R1, so that the first test soldering point and the first power supply network are in an electrical connection state.
  • the first power supply type is still taken as an example.
  • the test board 803 is provided with a first resistance mark R1 corresponding to the first power supply type.
  • the first resistance mark R1 is used to convert the first
  • the test solder joint is isolated from the first power network.
  • the first test solder point needs to be independent of the first power supply network.
  • the first resistor is not welded at the first resistor mark R1, so that the first test solder point is disconnected from the first power supply network; In the normal operation of the system, that is, in the working mode, the first test solder point also needs power supply.
  • the first resistor needs to be welded at the first resistor mark R1 to electrically connect the first test solder point and the first power supply network. In this way, by using the first resistor to identify whether the first resistor is welded at R1, the connection or disconnection between the first test soldering point and the first power supply network can be achieved.
  • the resistance of the first resistor may be 0 ohms. In this way, when the first resistor with a resistance of 0 ohms is used to realize the electrical connection between the first test solder point and the first power network, energy loss on the first resistor can be avoided.
  • the first power supply type is any one of VDD1 power supply type, VDD2 power supply type and VDDQ power supply type; wherein, on the test board 803, different first power supply types are correspondingly set with different The first test point and the different first resistor identification.
  • the VDDQ test pad in the package substrate 801 and the corresponding VDDQ test pin in the chip under test 802 are separated, and then other VDDQ power supply pins are connected together to form VDDQ power network, and the VDDQ test pin is not connected to the VDDQ power network; however, when the test board 803 is powered, the independent VDDQ test pin and the VDDQ power network still need to be powered together.
  • the VDDQ test pin there are many VDDQ power pins in the chip 802 under test, and the lack of one pin does not affect normal operation; but when not testing, the VDDQ test pin is idle at this time, and can be passed through the first resistor. It supplies power; but it no longer supplies power when testing. At this time, the test VDDQ test pin is only used for noise testing of the VDDQ power supply in the chip 802 under test.
  • the same power supply as the VDDQ power supply network can be provided for the VDDQ test pin; if the first resistor If the first resistor of 0 ohm is not soldered at R1, it is equivalent to no longer supplying power to the VDDQ test pin. At this time, it is just to connect the other VDDQ power pins in the chip 802 under test together, and then pass the VDDQ test pin.
  • FIG. 9 shows a schematic diagram of test results of internal power supply noise provided by an embodiment of the present disclosure. As shown in FIG. 9 , the test result is measured outside the chip 802 under test, specifically at the first test point. That is to say, the test platform is assembled according to the embodiments of the present disclosure, and then the internal power supply in the chip is tested through the first test point, so that the power supply noise of the DIE inside the chip can be tested more accurately.
  • Embodiments of the present disclosure provide a power supply noise testing device.
  • the power supply noise testing device relates to semiconductor memory technology, especially to the testing and verification of SDRAM. Specifically, it uses a special packaging design to be more accurate in the power supply measurement of the chip under test.
  • the packaging substrate is provided with a first test pad that is independent of the first power supply network
  • the chip under test is provided with a corresponding first test pin that is independent of the first power supply network; and then the packaging substrate and the chip under test are packaged To form a semiconductor structure, the semiconductor structure is then placed on the test board.
  • the first test pin that is independent of the first power supply network is electrically connected to the first test point on the test board through the first test pad, so that the semiconductor structure to be tested can be tested through the external first test point. It can test the power supply noise inside the chip and improve the test accuracy of power supply noise.
  • FIG. 10 shows a schematic flow chart of a power supply noise testing method provided by an embodiment of the present disclosure.
  • the method may include:
  • S1001 In the test mode, perform a noise test on the internal power supply corresponding to the first power supply type in the chip under test through the first test point on the test board; where the first test point has a corresponding relationship with the first power supply type, and the first The power supply type is any one of VDD1 power supply type, VDD2 power supply type and VDDQ power supply type.
  • this method is applied to the power supply noise testing device described in the previous embodiment, and it can be regarded as a method of performing noise testing on the internal power supply in the SDRAM chip.
  • the power supply noise testing device here may include a test board, a packaging substrate and a chip to be tested; and the chip to be tested, the packaging substrate and the test board are stacked in sequence.
  • the test board is further provided with multiple solder point arrays corresponding to multiple pad arrays in the packaging substrate, and each solder point array includes at least power supply solder points; wherein, multiple The power supply solder points belonging to the first power supply type in the solder point array are divided into a first test solder point and a first power supply solder point set.
  • the power supply solder points in the first power supply solder point set and the power supply pads in the first power supply pad set are The soldering pads correspond to electrical connections, and all the power supply soldering points in the first power supply soldering point set are electrically connected together to form a first power supply network; wherein the first test soldering point is independent of the first power supply network.
  • each solder point is electrically connected to the corresponding pad.
  • the power pins in the chip under test also need to be divided to separate one power pin as the first test pin, and then the other power pins are electrically connected to the corresponding power pads to achieve in addition to the third All power pins other than the first test pin are also electrically connected to the first power network, but the first test pin is not connected to the first power network.
  • the power solder joints in the test board also need to be divided in the same way.
  • An independent power supply solder point is used as the first test solder point, and then the first test pin is electrically connected through the first test pad, the first test solder point and the first test point, so that outside the chip under test,
  • the first test point enables noise testing of the internal power supply corresponding to the first power supply type in the chip under test.
  • the test board is also provided with a first resistance mark.
  • the method may also include: in the working mode, determining the first resistance mark and welding the first resistor at the first resistance mark, and controlling the first test welding through the first resistance.
  • the point is electrically connected to the first power supply network.
  • the method may further include: in the test mode, determining that the first resistor is not welded at the first resistance mark, so that the first test solder point is disconnected from the first power network.
  • the resistance of the first resistor may be 0 ohms.
  • the first power supply type is only any one of them; then there can be multiple resistor marks that can be set on the test board, and the number of resistor marks is related to the number of power supply types; in other words, different power supply types can also be set with different resistor marks on the test board. .
  • the test board is provided with a first resistance mark corresponding to the first power supply type, and the first resistance mark is used to isolate the first test solder joint from the first power supply network.
  • the first test solder point needs to be independent of the first power supply network.
  • the first resistor is not soldered at the first resistor mark, so that the first test solder point is disconnected from the first power supply network; in When the system is operating normally, that is, in the working mode, the first test solder point also needs to be powered.
  • the first resistor needs to be welded at the first resistor mark to electrically connect the first test solder point and the first power network.
  • the connection or disconnection between the first test solder point and the first power supply network can be realized, so that when in the test mode, the first resistor can be directly connected outside the chip under test. Measure accurate internal power supply noise test results.
  • the embodiment of the present disclosure provides a power supply noise testing method, specifically a method of accurately measuring the internal power supply noise of the chip by modifying the design of the packaging substrate.
  • the network distribution of the power supply pins is modified in the design of the packaging substrate.
  • add the corresponding test points in the test board for example, the system motherboard
  • disconnect the first resistor of 0 ohm in the test mode and then perform the internal power supply noise measurement according to the test points of the corresponding power supply
  • the technical solution provided by the foregoing embodiments can directly measure the accurate power supply noise inside the chip using corresponding test points in the test mode, thereby improving the power supply noise testing accuracy.
  • the embodiment of the present disclosure is based on the power supply noise testing device, by independently setting up a pin on the packaging substrate as the first test pin, and setting the first test point on the test board, and then connecting the first test pin and the first test pin.
  • the test point connection not only enables the signal used to test the power supply noise to be drawn out through the first test point, but also realizes that the test signal is independent of the first power supply network corresponding to the first power supply type; in this way, through the first test on the test board Performing noise tests on the internal power supply in the chip under test can improve the test accuracy of power supply noise.

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Abstract

本公开实施例提供了一种封装基板、电源噪声测试装置及电源噪声测试方法，该封装基板包括多个焊盘阵列，且每一个焊盘阵列中至少包括电源焊盘；多个焊盘阵列中属于同一电源类型的电源焊盘被划分为测试焊盘和电源焊盘集合；其中，电源焊盘集合包括属于同一电源类型且除测试焊盘之外的其他电源焊盘，且电源焊盘集合中的电源焊盘全部电连接在一起；测试焊盘用于对待测芯片中同一电源类型对应的内部电源进行噪声测试。

Description

封装基板、电源噪声测试装置及电源噪声测试方法
相关的交叉引用
本公开基于申请号为202210580267.7、申请日为2022年05月25日、发明名称为“封装基板、电源噪声测试装置及电源噪声测试方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种封装基板、电源噪声测试装置及电源噪声测试方法。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列数据可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
以同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)为例，为了验证电源完整性，SDRAM芯片在运行过程中，一般需要对电源信号进行测试。例如，可以通过信号测试板将电源信号引出以对其进行测试，或者也可以在系统主板上添加电源测试点以对其测试。然而，在SDRAM芯片的封装基板设计中，相同电源信号的引脚都会连接在一起，从而导致电源信号测试时无法准确测量到芯片内部的电源噪声情况。
发明内容
本公开提供了一种封装基板、电源噪声测试装置及电源噪声测试方法，不仅可以实现对芯片内部的电源噪声测试，而且还能够提高测试的准确度。
第一方面，本公开实施例提供了一种封装基板，封装基板包括多个焊盘阵列，且每一个焊盘阵列中至少包括电源焊盘；其中：
多个焊盘阵列中属于同一电源类型的电源焊盘被划分为测试焊盘和电源焊盘集合；其中，电源焊盘集合包括属于同一电源类型且除测试焊盘之外的其他电源焊盘，且电源焊盘集合中的电源焊盘全部电连接在一起；测试焊盘用于对待测芯片中同一电源类型对应的内部电源进行噪声测试。
在一些实施例中，封装基板包括四个焊盘阵列；其中，四个焊盘阵列呈上下对称且左右对称结构。
在一些实施例中，封装基板还包括导电层；其中，在导电层中，电源焊盘集合中的电源焊盘采用铺铜方式进行电连接以形成第一电源网络，且测试焊盘独立于第一电源网络。
在一些实施例中，封装基板的表面设置有金手指；其中，在同一电源类型中，测试焊盘与金手指之间的距离小于电源焊盘集合中的电源焊盘与金手指之间的距离。
在一些实施例中，封装基板的表面还放置有待测芯片，且待测芯片包括多个引脚阵列，每一个引脚阵列中至少包括电源引脚；其中，多个引脚阵列中属于同一电源类型的电源引脚被划分为测试引脚和电源引脚集合；其中，电源引脚集合中的电源引脚与电源焊盘集合中的电源焊盘对应电连接，测试引脚与测试焊盘电连接，以使得测试焊盘能够通过测试引脚对待测芯片中同一电源类型对应的内部电源进行噪声测试。
在一些实施例中，封装基板还设置有金属过孔和金属走线；其中，测试焊盘通过金属走线和金属过孔电连接到金手指，金手指与测试引脚之间采用打金线方式进行电连接，以实现测试焊盘与测试引脚电连接到一起。
在一些实施例中，每一个焊盘阵列至少包括VDD1电源焊盘、VDD2电源焊盘和VDDQ电源焊盘；其中，同一电源类型为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项。
在一些实施例中，多个焊盘阵列中属于VDD1电源类型的电源焊盘被划分为VDD1电源测试焊盘和VDD1电源焊盘集合；其中，VDD1电源焊盘集合中的电源焊盘全部电连接以形成VDD1电源网络，且VDD1电源测试焊盘独立于VDD1电源网络，VDD1电源测试焊盘用于对待测芯片内部的VDD1电源进行噪声测试；多个焊盘阵列中属于VDD2电源类型的电源焊盘被划分为VDD2电源测试焊盘和VDD2电源焊盘集合；其中，VDD2电源焊盘集合中的电源焊盘全部电连接以形成VDD2电源网络，且VDD2电源测试焊盘独立于VDD2电源网络，VDD2电源测试焊盘用于对待测芯片内部的VDD2电源进行噪声测试；多个焊盘阵列中属于VDDQ电源类型的电源焊盘被划分为VDDQ电源测试焊盘和VDDQ电源焊盘集合；其中，VDDQ电源焊盘集合中的电源焊盘全部电连接以形成VDDQ电源网络，且VDDQ电源测试焊盘独立于VDDQ电源网络，VDDQ电源测试焊盘用于对待测芯片内部的VDDQ电源进行噪声测试。
第二方面，本公开实施例提供了一种电源噪声测试装置，该电源噪声测试装置包括如第一方面所述的封装基板、待测芯片和测试板；其中：
测试板设置有第一电源类型对应的第一测试点；
待测芯片至少包括第一电源类型对应的电源引脚，且电源引脚被划分为第一测试引脚和除第一测试引脚之外的第一电源引脚集合；
封装基板至少包括第一电源类型对应的电源焊盘，且电源焊盘被划分为第一测试焊盘和除第一测试焊盘之外的第一电源焊盘集合；
其中，第一电源引脚集合中的电源引脚与第一电源焊盘集合中的电源焊盘对应电连接，第一测试引脚与第一测试焊盘电连接，且第一测试焊盘还与第一测试点电连接，以使得第一测试点能够通过第一测试焊盘和第一测试引脚对待测芯片中第一电源类型对应的内部电源进行噪声测试。
在一些实施例中，待测芯片、封装基板和测试板依次叠放。
在一些实施例中，测试板还设置有与封装基板中的多个焊盘阵列相对应的多个焊点阵列，且每一个焊点阵列中至少包括电源焊点；其中，多个焊点阵列中属于第一电源类型的电源焊点被划分为第一测试焊点和第一电源焊点集合，第一电源焊点集合中的电源焊点与第一电源焊盘集合中的电源焊盘对应电连接，且第一电源焊点集合中的电源焊点全部电连接在一起，以形成第一电源网络；其中，第一测试焊点独立于第一电源网络。
在一些实施例中，测试板还设置有第一金属走线；其中，第一测试焊盘与第一测试焊点连接，且第一测试焊点通过第一金属走线与第一测试点电连接，以实现第一测试焊盘与第一测试点的电连接。
在一些实施例中，测试板还设置有第一电阻标识，且第一电阻标识包括第一焊点和第二焊点；其中，第一焊点与第一测试焊点连接，第二焊点与第一电源网络连接。
在一些实施例中，在测试模式下，第一电阻标识处未焊接第一电阻，以使得第一测试焊点与第一电源网络处于断开状态；在工作模式下，第一电阻标识处焊接第一电阻，以使得第一测试焊点与第一电源网络处于电连接状态。
在一些实施例中，第一电阻的阻值为0欧姆。
在一些实施例中，第一电源类型为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项；其中，在测试板上，不同的第一电源类型对应设置有不同的第一测试点和不同的第一电阻标识。
第三方面，本公开实施例提供了一种电源噪声测试方法，应用于第二方面所述的电源噪声测试装置，该方法包括：
在测试模式下，通过测试板上的第一测试点对待测芯片中第一电源类型对应的内部电源进行噪声测试；其中，第一测试点与第一电源类型具有对应关系，且第一电源类型为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项。
在一些实施例中，测试板还设置有与封装基板中的多个焊盘阵列相对应的多个焊点阵列，且每一个焊点阵列中至少包括电源焊点；其中，多个焊点阵列中属于第一电源类型的电源焊点被划分为第一测试焊点和第一电源焊点集合，第一电源焊点集合中的电源焊点与第一电源焊盘集合中的电源焊盘对应电连接，且第一电源焊点集合中的电源焊点全部电连接在一起，以形成第一电源网络；其中，第一测试焊点独立于第一电源网络。
在一些实施例中，测试板还设置有第一电阻标识，该方法还包括：在 工作模式下，确定第一电阻标识处焊接第一电阻，通过第一电阻控制第一测试焊点与第一电源网络处于电连接状态。
在一些实施例中，该方法还包括：在测试模式下，确定第一电阻标识处未焊接第一电阻，以使得第一测试焊点与第一电源网络处于断开状态。
本公开实施例提供了一种封装基板、电源噪声测试装置及电源噪声测试方法，对于封装基板来说，该封装基板包括多个焊盘阵列，且每一个焊盘阵列中至少包括电源焊盘，多个焊盘阵列中属于同一电源类型的电源焊盘被划分为测试焊盘和电源焊盘集合；其中，电源焊盘集合包括属于同一电源类型且除测试焊盘之外的其他电源焊盘，且电源焊盘集合中的电源焊盘全部电连接在一起；测试焊盘用于对待测芯片中同一电源类型对应的内部电源进行噪声测试。对于电源噪声测试装置来说，该电源噪声测试装置包括封装基板、待测芯片和测试板；其中，测试板设置有第一电源类型对应的第一测试点；待测芯片至少包括第一电源类型对应的电源引脚，且电源引脚被划分为第一测试引脚和除第一测试引脚之外的第一电源引脚集合；封装基板至少包括第一电源类型对应的电源焊盘，且电源焊盘被划分为第一测试焊盘和除第一测试焊盘之外的第一电源焊盘集合；其中，第一电源引脚集合中的电源引脚与第一电源焊盘集合中的电源焊盘对应电连接，第一测试引脚与第一测试焊盘电连接，且第一测试焊盘还与第一测试点电连接，以使得第一测试点能够通过第一测试焊盘和第一测试引脚对待测芯片中第一电源类型对应的内部电源进行噪声测试。这样，基于该电源噪声测试装置，通过在封装基板上独立出一个管脚作为第一测试引脚使用，并且在测试板上设置第一测试点，然后由第一测试引脚与第一测试点连接，不仅能够将用于测试电源噪声的信号通过第一测试点引出，同时实现了该测试信号独立于第一电源类型对应的第一电源网络；如此，通过测试板上的第一测试点对待测芯片中的内部电源进行噪声测试，可以提高电源噪声的测试准确度。
附图说明
图1为一种封装基板的布局示意图；
图2为一种芯片电源噪声的测试结果示意图；
图3为本公开实施例提供一种封装基板的组成结构示意图；
图4为本公开实施例提供另一种封装基板的组成结构示意图；
图5为本公开实施例提供的一种封装基板的局部放大示意图；
图6为本公开实施例提供的一种封装基板的具体结构示意图；
图7为本公开实施例提供一种电源噪声测试装置的组成结构示意图；
图8为本公开实施例提供另一种电源噪声测试装置的组成结构示意图；
图9为本公开实施例提供的一种内部电源噪声的测试结果示意图；
图10为本公开实施例提供一种电源噪声测试方法的流程示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
可以理解，以同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)为例，SDRAM芯片在运行过程中，一般需要对电源信号进行测试以验证电源完整性。
在相关技术中，可以通过SDRAM信号测试版，将电源信号引出，然后对其进行测试；或者，也可以在系统主板上添加电源测试点对其进行测试。然而，在SDRAM芯片的封装基板设计中，相同电源信号的引脚都会连接在一起，从而导致测试电源时无法准确测量到芯片内部的电源噪声情况。
对于SDRAM芯片而言，至少可以包括有三种类型的电源信号，例如VDD1电源类型、VDD2电源类型和VDDQ电源类型，而且每一种电源类型对应的电源引脚可以有多个。具体地，该芯片可以设置多个VDD1电源引脚、多个VDD2电源引脚和多个VDDQ电源引脚，这些电源引脚可以与封装基板上对应的VDD1电源焊盘、VDD2电源焊盘和VDDQ电源焊盘分别电连接。
示例性地，参见图1，其示出了一种封装基板的布局示意图。如图1所示，可以包括两种类型的电源焊盘：VDD2电源焊盘和VDDQ电源焊盘。其中，属于VDD2电源类型的所有VDD2电源焊盘全部连接在一起以形成VDD2电源网络，属于VDDQ电源类型的所有VDDQ电源焊盘全部连接在一起以形成VDDQ电源网络。在这里，由于属于VDD2电源类型的所有VDD2电源焊盘全部连接在一起，即实现了将芯片中VDD2电源类型对应的所有电源引脚全部连接在一起；由于属于VDDQ电源类型的所有VDDQ电源焊盘全部连接在一起，即实现了将芯片中VDDQ电源类型对应的所有 电源引脚全部连接在一起。同理，对于属于VDD1电源类型的VDD1电源焊盘(图中未示出)来说，这些所有的VDD1电源焊盘在封装基板中也将全部连接在一起，使得芯片中VDD1电源类型的所有电源引脚全部连接在一起。
基于图1的封装基板，图2示出了一种芯片电源噪声的测试结果示意图。如图2所示，(a)为芯片内部的电源噪声测试结果，(b)为芯片外部的电源噪声测试结果。其中，内部的电源噪声是指在芯片内部实际测量到的电源噪声，外部的电源噪声是指常规方式下在芯片外部测量到的电源噪声。在图2中，对于(a)来说，加粗实线框内反映了芯片内部的电源噪声非常严重；但是在(b)中的对应时段，此时芯片外部测量的电源噪声几乎没有，详见加粗虚线框。
也就是说，在相关技术中，VDD1电源焊盘、VDD2电源焊盘和VDDQ电源焊盘在封装基板上均是各自连接到一起的，即相同电源信号对应的电源引脚都会连接在一起。由此可见，相关技术中的电源噪声测试是无法进行区分的，这时候外部测试的是一类电源信号的整体噪声，使得常规方式下测量到的外部噪声不能正确反映芯片内部的实际噪声，从而导致在测试电源时无法直接测量到芯片内部电源噪声的准确情况。
基于此，本公开实施例提供了一种封装基板，该封装基板包括多个焊盘阵列，且每一个焊盘阵列中至少包括电源焊盘，多个焊盘阵列中属于同一电源类型的电源焊盘被划分为测试焊盘和电源焊盘集合；其中，电源焊盘集合包括属于同一电源类型且除测试焊盘之外的其他电源焊盘，且电源焊盘集合中的电源焊盘全部电连接在一起；测试焊盘用于对待测芯片中同一电源类型对应的内部电源进行噪声测试。本公开实施例还提供了一种电源噪声测试装置以及电源噪声测试方法，该方法应用于电源噪声测试装置，该电源噪声测试装置包括封装基板、待测芯片和测试板；其中，测试板设置有第一电源类型对应的第一测试点；待测芯片至少包括第一电源类型对应的电源引脚，且电源引脚被划分为第一测试引脚和除第一测试引脚之外的第一电源引脚集合；封装基板至少包括第一电源类型对应的电源焊盘，且电源焊盘被划分为第一测试焊盘和除第一测试焊盘之外的第一电源焊盘集合，第一电源引脚集合中的电源引脚与第一电源焊盘集合中的电源焊盘对应电连接，第一测试引脚与第一测试焊盘电连接，且第一测试焊盘还与第一测试点电连接，以使得第一测试点能够通过第一测试焊盘和第一测试引脚对待测芯片中第一电源类型对应的内部电源进行噪声测试。
这样，基于该电源噪声测试装置，通过在封装基板上独立出一个管脚作为第一测试引脚使用，并且在测试板上设置第一测试点，然后由第一测试引脚与第一测试点连接，不仅能够将用于测试电源噪声的信号通过第一测试点引出，同时实现了该测试信号独立于第一电源类型对应的第一电源网络；如此，通过测试板上的第一测试点对待测芯片中的内部电源进行噪 声测试，可以提高电源噪声的测试准确度。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图3，其示出了本公开实施例提供一种封装基板的组成结构示意图。如图3所示，封装基板40可以包括多个焊盘阵列(如焊盘阵列401、焊盘阵列402、焊盘阵列403和焊盘阵列404)，且每一个焊盘阵列中至少包括电源焊盘；其中：
多个焊盘阵列中属于同一电源类型的电源焊盘被划分为测试焊盘411和电源焊盘集合，该电源焊盘集合可以包括属于同一电源类型且除测试焊盘411之外的其他电源焊盘412，而且该电源焊盘集合中的电源焊盘全部电连接在一起；
测试焊盘411，可以用于对待测芯片中同一电源类型对应的内部电源进行噪声测试。
需要说明的是，在本公开实施例中，封装基板(Package Substrate)，简称SUB，可以为待测芯片提供电连接、保护、支撑、散热、组装等功效，以实现多引脚化，缩小封装产品体积、改善电性能及散热性、超高密度或多芯片模块化的目的。在这里，封装基板是半导体芯片封装的载体，其主要是将切割好的晶片(Die)固定到封装基板上，并且利用利用超细的金属导线或者导电性树脂实现Die与封装基板上的焊盘进行电连接。
还需要说明的是，在本公开实施例中，待测芯片可以是指晶片或晶圆，用Die表示。其中，针对Die中的内部电源可以包括多种电源类型，例如VDD1电源类型、VDD2电源类型和VDDQ电源类型等。在这里，VDDQ可以看作是为输入输出缓冲电路(Inputs/Outputs Buffer，IO Buffer)供电的电源；VDD1和VDD2可以看作是给芯片内核供电的电源，但是VDD1与VDD2的电压大小不同。这样，对于待测芯片的内部电源进行噪声测试，本公开实施例可以是针对VDD1电源类型对应的内部电源进行噪声测试，或者也可以是针对VDD2电源类型对应的内部电源进行噪声测试，或者还可以是针对VDDQ电源类型对应的内部电源进行噪声测试，这里对此并不作任何限定。
示例性地，如图3所示，以VDDQ电源类型为例，属于VDDQ电源类型的电源焊盘有20个(用黑色填充标识)；针对这20个电源焊盘，可以选取其中一个作为测试焊盘411，剩下的19个电源焊盘(如412)组成VDDQ电源类型对应的电源焊盘集合，该电源焊盘集合中的所有电源焊盘全部电连接到一起。
也就是说，在本公开实施例中，同一电源类型的电源焊盘可以有多个，这多个电源焊盘并非是全部电连接到一起的。具体地，针对同一电源类型的多个电源焊盘，可以独立出其中一个作为测试焊盘，然后将剩余的其他电源焊盘全部电连接到一起。这样，利用独立出的测试焊盘对待测芯片中的内部电源进行噪声测试，能够准确测量到芯片内部电源噪声的情况。
在一些实施例中，封装基板40可以包括四个焊盘阵列；其中，四个焊盘阵列呈上下对称且左右对称结构。
还需要说明的是，在本公开实施例中，具体参见图3，封装基板40可以包括焊盘阵列401、焊盘阵列402、焊盘阵列403和焊盘阵列404。对于这四个焊盘阵列既可以沿水平方向呈左右对称结构，又可以沿垂直方向呈上下对称结构。这样，在封装基板40的设计中，这些焊盘阵列的分布对称而且整体美观性好。
在一些实施例中，在图3所示封装基板40的基础上，参见图4，封装基板40还可以包括导电层413；其中，在导电层413中，电源焊盘集合中的电源焊盘采用铺铜方式进行电连接以形成第一电源网络，且测试焊盘411独立于第一电源网络。
需要说明的是，在本公开实施例中，封装基板40可以为多层板，其中，每一层均可以作为导电层。示例性地，对于VDD1电源类型、VDD2电源类型和VDDQ电源类型等三种电源类型而言，不同的层可以实现将不同的电源类型对应的电源焊盘分别进行电连接，而且还可以实现同一电源类型的大面积铺铜，从而能够提高过电流能力，同时降低电源的阻抗，有效地抑制信号之间的串扰，还能够达到利于散热的目的。例如，对于封装基板的多层导电层而言，图1可以看作是一导电层，图4可以看作是另一导电层。
还需要说明的是，在本公开实施例中，如图4所示，以VDDQ电源类型为例，在处于VDDQ电源噪声的测试模式时，除了测试焊盘411之外，剩余的其他电源焊盘全部电连接到一起以形成VDDQ电源网络，但是测试焊盘411与VDDQ电源网络不连接，以方便后续利用测试焊盘411进行VDDQ电源的噪声测试。
进一步地，在一些实施例中，封装基板40的表面设置有金手指；其中，在同一电源类型中，测试焊盘与金手指之间的距离小于电源焊盘集合中的电源焊盘与金手指之间的距离。
需要说明的是，在本公开实施例中，对于独立的测试焊盘而言，可以是同一电源类型中的任意一个电源焊盘。在一种具体的实现方式中，也可以是在同一电源类型中，选取的测试焊盘需要尽量靠近封装基板40上的金手指，使得走线尽量短、走线环路尽量小。
示例性地，参见图5，其示出了本公开实施例提供的一种封装基板的局部放大示意图。在图5中，针对金手指414在封装基板上的设置进行了示意说明。这样，在同一电源类型中，当进行测试焊盘的选取时，最终所选取的测试焊盘与金手指之间的距离需要小于其他电源焊盘与金手指之间的距离。
进一步地，在一些实施例中，封装基板40的表面还放置有待测芯片(图中未示出)，而且待测芯片包括多个引脚阵列，每一个引脚阵列中至少包 括电源引脚；其中：
多个引脚阵列中属于同一电源类型的电源引脚被划分为测试引脚和电源引脚集合；其中，电源引脚集合中的电源引脚与电源焊盘集合中的电源焊盘对应电连接，测试引脚与测试焊盘电连接，以使得测试焊盘能够通过测试引脚对待测芯片中同一电源类型对应的内部电源进行噪声测试。
需要说明的是，在本公开实施例中，针对同一电源类型，不仅封装基板上的电源焊盘需要进行划分，以独立出一个电源焊盘作为测试焊盘，然后将其他的电源焊盘全部连接在一起；而且对于待测芯片而言，对应地，待测芯片的电源引脚也需要进行划分，以独立出一个电源引脚作为测试引脚，以使得测试焊盘能够通过测试引脚对待测芯片中同一电源类型对应的内部电源进行噪声测试。
还需要说明的是，在本公开实施例中，待测芯片的多个引脚阵列与封装基板的多个焊盘阵列之间是具有对应关系的，每一个引脚与封装基板上的焊盘对应连接。在这里，对于待测芯片而言，多个引脚阵列也是沿水平方向呈左右对称结构，以及沿垂直方向呈上下对称结构。
示例性地，仍以同一电源类型为例，在独立出一个测试引脚之后，该测试引脚与测试焊盘对应电连接，剩余的其他电源引脚与电源焊盘集合中的电源焊盘一一对应电连接，以使得剩余的其他电源引脚也全部电连接在一起；而独立出的测试引脚通过测试焊盘连接到待测芯片的外部，从而通过该测试引脚，在待测芯片的外部即可实现对待测芯片中同一电源类型对应的内部电源进行噪声测试，还能够提高电源噪声的测试准确度。
进一步地，在一些实施例中，封装基板40还设置有金属过孔和金属走线；其中，测试焊盘通过金属走线和金属过孔电连接到金手指，金手指与测试引脚之间采用打金线方式进行电连接，以实现测试焊盘与测试引脚电连接到一起。
需要说明的是，在本公开实施例中，对于所选取的测试焊盘411，在封装基板40的背面会通过走线和过孔连接到封装基板40的表面设置的金手指，然后再通过打金线方式连接到待测芯片的电源引脚上。另外，对于其他电源焊盘，也可以是从封装基板40的背面通过走线和过孔连接到封装基板40的表面设置的金手指，然后再通过打金线方式连接到待测芯片的其他电源引脚上，以便实现封装基板40的电源焊盘与待测芯片的电源引脚之间的电连接。
示例性地，参见图6，其示出了本公开实施例提供的一种封装基板40的具体结构示意图。如图6所示，这里可以包括：金手指414、金线415、待测芯片416和焊盘阵列417。由图6可以看出，在封装基板40的背面设置有焊盘阵列417，以焊盘阵列417中的测试焊盘为例，从封装基板40的背面通过走线和过孔连接到封装基板40的表面设置的金手指414，然后再通过金线415连接到待测芯片416的测试引脚上，从而实现测试焊盘与测 试引脚之间的电连接。
进一步地，在一些实施例中，每一个焊盘阵列至少包括VDD1电源焊盘、VDD2电源焊盘和VDDQ电源焊盘；其中，同一电源类型为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项。
需要说明的是，在本公开实施例中，这里的电源焊盘可以包括至少三种，例如VDD1电源焊盘、VDD2电源焊盘和VDDQ电源焊盘等；对应地，同一电源类型可以为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项。对于这三种电源类型，其进行电源噪声测试的方法类似，均可以通过独立出一个测试引脚来分别实现对待测芯片中VDD1电源的噪声测试、或者对待测芯片中VDD2电源的噪声测试、或者对待测芯片中VDDQ电源的噪声测试。
在一种具体的实施例中，对于VDD1电源来说，多个焊盘阵列中属于VDD1电源类型的电源焊盘被划分为VDD1电源测试焊盘和VDD1电源焊盘集合；其中，VDD1电源焊盘集合中的电源焊盘全部电连接以形成VDD1电源网络，且VDD1电源测试焊盘独立于VDD1电源网络，VDD1电源测试焊盘用于对待测芯片内部的VDD1电源进行噪声测试。
在另一种具体的实施例中，对于VDD2电源来说，多个焊盘阵列中属于VDD2电源类型的电源焊盘被划分为VDD2电源测试焊盘和VDD2电源焊盘集合；其中，VDD2电源焊盘集合中的电源焊盘全部电连接以形成VDD2电源网络，且VDD2电源测试焊盘独立于VDD2电源网络，VDD2电源测试焊盘用于对待测芯片内部的VDD2电源进行噪声测试；
在又一种具体的实施例中，对于VDDQ电源来说，多个焊盘阵列中属于VDDQ电源类型的电源焊盘被划分为VDDQ电源测试焊盘和VDDQ电源焊盘集合；其中，VDDQ电源焊盘集合中的电源焊盘全部电连接以形成VDDQ电源网络，且VDDQ电源测试焊盘独立于VDDQ电源网络，VDDQ电源测试焊盘用于对待测芯片内部的VDDQ电源进行噪声测试。
需要说明的是，如果封装基板40存在有多种电源类型，那么针对每一种电源类型来说，这些电源焊盘均可被划分为对应的测试焊盘和电源焊盘集合，以及待测芯片中的电源引脚也可被划分为对应的测试引脚和电源引脚集合；然后将该电源焊盘集合中的电源焊盘通过铺铜方式全部电连接到一起，以实现除测试引脚之前的其他电源引脚全部电连接到一起，这时候通过将测试引脚引出到待测芯片的外部，不仅能够实现对待测芯片中的该电源类型进行电源噪声测试，还能够提高电源噪声的测试准确度。
还需要说明的是，在本公开实施例中，VDD1电源的测试焊盘独立于VDD1电源网络，VDD2电源的测试焊盘独立于VDD2电源网络，VDDQ电源的测试焊盘独立于VDDQ电源网络；而且VDD1电源网络、VDD2电源网络和VDDQ电源网络之间也相互独立。
还需要说明的是，在本公开实施例中，以VDDQ电源为例，如果测试 焊盘命名为VDDQ1，那么待测芯片上对应的测试引脚也可命名为VDDQ1，以便更好地实现该测试引脚与封装基板上的测试焊盘的电连接。
本公开实施例提供了一种封装基板，该封装基板包括多个焊盘阵列，且每一个焊盘阵列中至少包括电源焊盘，多个焊盘阵列中属于同一电源类型的电源焊盘被划分为测试焊盘和电源焊盘集合；其中，电源焊盘集合包括属于同一电源类型且除测试焊盘之外的其他电源焊盘，且电源焊盘集合中的电源焊盘全部电连接在一起；测试焊盘用于对待测芯片中同一电源类型对应的内部电源进行噪声测试。这样，虽然电源焊盘集合中的电源焊盘全部电连接在一起，但是测试焊盘并不与其电连接，利用独立出的测试焊盘对待测芯片中的内部电源进行噪声测试，能够准确测量到芯片内部电源噪声的情况，从而提高了电源噪声的测试准确度。
在本公开的另一实施例中，参见图7，其示出了本公开实施例提供一种电源噪声测试装置80的组成结构示意图。如图7所示，电源噪声测试装置80可以包括封装基板801、待测芯片802和测试板803；其中：
测试板803设置有第一电源类型对应的第一测试点a；
待测芯片802至少包括第一电源类型对应的电源引脚，且电源引脚被划分为第一测试引脚和除第一测试引脚之外的第一电源引脚集合；
封装基板801至少可以包括第一电源类型对应的电源焊盘，且电源焊盘被划分为第一测试焊盘和除第一测试焊盘之外的第一电源焊盘集合。
其中，第一电源引脚集合中的电源引脚与第一电源焊盘集合中的电源焊盘对应电连接，第一测试引脚与第一测试焊盘电连接，而且第一测试焊盘还与第一测试点电连接，以使得第一测试点能够通过第一测试焊盘和第一测试引脚对待测芯片中第一电源类型对应的内部电源进行噪声测试。
需要说明的是，在本公开实施例中，封装基板801可以是如前述实施例提供的封装基板40。另外，测试板803可以是信号测试单板或者系统主板，这里不作任何限定。
还需要说明的是，在本公开实施例中，为了方便在芯片外部进行电源噪声测试，可以在测试板803上设置测试点。在这里，以第一电源类型为例，可以在测试板803上设置对应的第一测试点，然后通过第一测试点将待测试的电源信号引出，从而能够在待测芯片802的外部进行内部电源噪声测试，而且电源噪声的测试准确度高。
可以理解地，在本公开实施例中，由于待测芯片802对应的电源类型可以有多个，而第一电源类型仅是其中的任意一项；那么测试板803上测试点的数量也可以有多个，而且测试点的数量与电源类型的数量具有关联关系；换句话说，不同的电源类型在测试板803上对应设置有不同的测试点。
在一些实施例中，第一电源类型可以为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项；其中，在测试板803上，不同的第 一电源类型对应设置有不同的第一测试点。
具体来说，在测试板803上，可以设置有VDD1电源类型对应的VDD1测试点、VDD2电源类型对应的VDD2测试点和VDDQ电源类型对应的VDDQ测试点；然后通过VDD1测试点能够实现对待测芯片802内部的VDD1电源进行噪声测试，通过VDD2测试点能够实现对待测芯片802内部的VDD2电源进行噪声测试，通过VDDQ测试点能够实现对待测芯片802内部的VDDQ电源进行噪声测试。
在一些实施例中，在电源噪声测试装置80中，待测芯片802、封装基板801和测试板803依次叠放。
需要说明的是，具体参见图7，待测芯片802设置于封装基板801的上方，测试板803设置于封装基板801的下方，从而形成叠层结构，该叠层结构不仅可以节省布局空间，而且整体美观度好。
在一些实施例中，参见图8，测试板803还可以设置有与封装基板801中的多个焊盘阵列相对应的多个焊点阵列(如焊点阵列831、焊点阵列832、焊点阵列833和焊点阵列834)，且每一个焊点阵列中至少包括电源焊点；其中：
多个焊点阵列中属于第一电源类型的电源焊点被划分为第一测试焊点b和第一电源焊点集合，第一电源焊点集合中的电源焊点与第一电源焊盘集合中的电源焊盘对应电连接，且第一电源焊点集合中的电源焊点全部电连接在一起，以形成第一电源网络；其中，第一测试焊点a独立于第一电源网络。
需要说明的是，在本公开实施例中，具体参见图8，测试板803可以包括焊点阵列831、焊点阵列832、焊点阵列833和焊点阵列834。对于这四个焊点阵列既可以沿X轴方向呈左右对称结构，又可以沿Y轴方向呈上下对称结构。
还需要说明的是，在本公开实施例中，测试板803中的四个焊点阵列与封装基板801中的四个焊盘阵列之间具有对应关系，每一个焊点分别与对应焊盘进行电连接。这样，以第一电源类型为例，不仅封装基板801中的电源焊盘需要进行划分，以独立出一个电源焊盘作为第一测试焊盘，然后将其他的电源焊盘全部连接以形成第一电源网络；对应地，待测芯片802中的电源引脚也需要进行划分，以独立出一个电源引脚作为第一测试引脚，然后其他电源引脚与对应的电源焊盘电连接，以实现除了第一测试引脚之外的电源引脚也全部电连接到第一电源网络，但是第一测试引脚与第一电源网络未连接；对应地，测试板803中的电源焊点也需要进行同样划分，以独立出一个电源焊点作为第一测试焊点，然后第一测试引脚依次经过第一测试焊盘、第一测试焊点与第一测试点电连接，使得在待测芯片802的外部，通过第一测试点能够实现对待测芯片中第一电源类型对应的内部电源进行噪声测试。
进一步地，在一些实施例中，测试板803还设置有第一金属走线；其中，第一测试焊盘与第一测试焊点连接，且第一测试焊点通过第一金属走线与第一测试点电连接，以实现第一测试焊盘与第一测试点的电连接。
需要说明的是，在本公开实施例中，具体参见图7，测试板803上的加粗实线表示第一金属走线。从图7中可以明显看出，第一测试引脚通过封装基板801中的第一测试焊盘与第一测试焊点进行电连接，然后在测试板803上，第一测试焊点再经过金属走线与第一测试点a电连接，以实现第一测试引脚与第一测试点的电连接；从而能够将待测试的电源信号引出到待测芯片802的外部，以方便进行电源噪声测试。
进一步地，在一些实施例中，参见图8，测试板803还可以设置有第一电阻标识R1，且第一电阻标识R1包括第一焊点和第二焊点；其中，第一焊点与第一测试焊点连接，第二焊点与第一电源网络连接。
在一种具体的实现方式中，在测试模式下，第一电阻标识R1处未焊接第一电阻，以使得第一测试焊点与第一电源网络处于断开状态；在工作模式下，第一电阻标识R1处焊接第一电阻，以使得第一测试焊点与第一电源网络处于电连接状态。
需要说明的是，在本公开实施例中，仍以第一电源类型为例，测试板803上设置有第一电源类型对应的第一电阻标识R1，该第一电阻标识R1用于将第一测试焊点与第一电源网络隔开。其中，在测试模式下，第一测试焊点需要独立于第一电源网络，这时候第一电阻标识R1处未焊接第一电阻，以使得第一测试焊点与第一电源网络之间断开；在系统正常运行即工作模式下，第一测试焊点也需要供电，这时候第一电阻标识R1处需要焊接第一电阻，以使得第一测试焊点与第一电源网络之间电连接。这样，通过第一电阻标识R1处是否焊接第一电阻，从而能够实现第一测试焊点与第一电源网络之间的连接或断开。
还需要说明的是，在本公开实施例中，第一电阻的阻值可以为0欧姆。这样，利用阻值为0欧姆的第一电阻来实现第一测试焊点与第一电源网络之间的电连接时，可以避免第一电阻上的能量损失。
进一步地，在一些实施例中，第一电源类型为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项；其中，在测试板803上，不同的第一电源类型对应设置有不同的第一测试点和不同的第一电阻标识。
在本公开实施例中，由于待测芯片802对应的电源类型可以有多个，而第一电源类型仅是其中的任意一项；那么在测试板803上可以设置的电阻标识也可以有多个，而且电阻标识的数量与电源类型的数量具有关联关系；换句话说，不同的电源类型在测试板803上也可以对应设置有不同的电阻标识。
示例性地，以VDDQ电源类型为例，虽然将封装基板801中的VDDQ测试焊盘和待测芯片802中对应的VDDQ测试引脚独立出来，然后将其他 的VDDQ电源引脚连接到一起形成VDDQ电源网络，而且VDDQ测试引脚未与VDDQ电源网络连接；但是在测试板803供电时，还是需要给独立出的VDDQ测试引脚和VDDQ电源网络一起供电。理论上，待测芯片802中的VDDQ电源引脚有很多个，缺少一个引脚并不影响正常工作；但是在不做测试时，这时候VDDQ测试引脚处于闲置状态，可以通过第一电阻为其供电；而在进行测试时不再为其供电，这时候的测试VDDQ测试引脚仅用于待测芯片802中的VDDQ电源的噪声测试。
也就是说，在本公开实施例中，如果第一电阻标识R1处焊接有0欧姆的第一电阻，那么也就能够实现为VDDQ测试引脚提供与VDDQ电源网络一样的供电；如果第一电阻标识R1处未焊接0欧姆的第一电阻，那么就相当于不再给VDDQ测试引脚供电，这时候仅是将待测芯片802中的其他VDDQ电源引脚连接到一起，然后通过VDDQ测试引脚与测试板803上的测试点可以将待测试的电源信号引出，从而在电源噪声测试装置80处于测试模式的时候，基于独立的VDDQ测试引脚，可以在待测芯片802的外部直接测量得到准确的内部电源噪声测试结果。示例性地，图9示出了本公开实施例提供的一种内部电源噪声的测试结果示意图。如图9所示，该测试结果是在待测芯片802的外部，具体是第一测试点处测量得到的。也就是说，按照本公开实施例的方式组装测试平台，然后通过第一测试点对芯片中的内部电源进行测试，这样可以更加准确的测试到芯片内部DIE的电源噪声。
本公开实施例提供了一种电源噪声测试装置，该电源噪声测试装置涉及半导体存储器技术，尤其涉及SDRAM的测试验证，具体是利用特殊的封装设计，可以在待测芯片的电源测量中更加准确。其中，封装基板中设置有独立于第一电源网络的第一测试焊盘，待测芯片中对应设置有独立于第一电源网络的第一测试引脚；然后将封装基板和待测芯片进行封装以形成半导体结构，再将该半导体结构放置在测试板上。这样，通过独立于第一电源网络的第一测试引脚经过第一测试焊盘与测试板上的第一测试点进行电连接，从而能够通过外部的第一测试点可以对半导体结构中待测芯片内部的电源噪声进行测试，而且还能够提高电源噪声的测试准确度。
在本公开的又一实施例中，参见图10，其示出了本公开实施例提供一种电源噪声测试方法的流程示意图。如图10所示，该方法可以包括：
S1001：在测试模式下，通过测试板上的第一测试点对待测芯片中第一电源类型对应的内部电源进行噪声测试；其中，第一测试点与第一电源类型具有对应关系，且第一电源类型为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项。
需要说明的是，在本公开实施例中，该方法应用于前述实施例所述的电源噪声测试装置，其可以看作对SDRAM芯片中的内部电源进行噪声测试的方法。
还需要说明的是，这里的电源噪声测试装置可以包括测试板、封装基板和待测芯片；而且待测芯片、封装基板和测试板依次叠放。在一种具体的实施例中，测试板还设置有与封装基板中的多个焊盘阵列相对应的多个焊点阵列，且每一个焊点阵列中至少包括电源焊点；其中，多个焊点阵列中属于第一电源类型的电源焊点被划分为第一测试焊点和第一电源焊点集合，第一电源焊点集合中的电源焊点与第一电源焊盘集合中的电源焊盘对应电连接，且第一电源焊点集合中的电源焊点全部电连接在一起，以形成第一电源网络；其中，第一测试焊点独立于第一电源网络。
在本公开实施例中，测试板中的多个焊点阵列与封装基板中的多个焊盘阵列之间具有对应关系，每一个焊点分别与对应焊盘进行电连接。这样，以第一电源类型为例，不仅封装基板中的电源焊盘需要进行划分，以独立出一个电源焊盘作为第一测试焊盘，然后将其他的电源焊盘全部连接以形成第一电源网络；对应地，待测芯片中的电源引脚也需要进行划分，以独立出一个电源引脚作为第一测试引脚，然后其他电源引脚与对应的电源焊盘电连接，以实现除了第一测试引脚之外的电源引脚也全部电连接到第一电源网络，但是第一测试引脚与第一电源网络未连接；对应地，测试板中的电源焊点也需要进行同样划分，以独立出一个电源焊点作为第一测试焊点，然后第一测试引脚依次经过第一测试焊盘、第一测试焊点与第一测试点电连接，使得在待测芯片的外部，通过第一测试点能够实现对待测芯片中第一电源类型对应的内部电源进行噪声测试。
进一步地，在一些实施例中，测试板还设置有第一电阻标识，该方法还可以包括：在工作模式下，确定第一电阻标识处焊接第一电阻，通过第一电阻控制第一测试焊点与第一电源网络处于电连接状态。
进一步地，在一些实施例中，该方法还可以包括：在测试模式下，确定第一电阻标识处未焊接第一电阻，以使得第一测试焊点与第一电源网络处于断开状态。
在本公开实施例中，第一电阻的阻值可以为0欧姆。
在本公开实施例中，由于待测芯片对应的电源类型可以有多个(例如，VDD1电源类型、VDD2电源类型和VDDQ电源类型等)，而第一电源类型仅是其中的任意一项；那么在测试板上可以设置的电阻标识也可以有多个，而且电阻标识的数量与电源类型的数量具有关联关系；换句话说，不同的电源类型在测试板上也可以对应设置有不同的电阻标识。
示例性地，以第一电源类型为例，测试板上设置有第一电源类型对应的第一电阻标识，该第一电阻标识用于将第一测试焊点与第一电源网络隔开。其中，在测试模式下，第一测试焊点需要独立于第一电源网络，这时候第一电阻标识处未焊接第一电阻，以使得第一测试焊点与第一电源网络之间断开；在系统正常运行即工作模式下，第一测试焊点也需要供电，这时候第一电阻标识处需要焊接第一电阻，以使得第一测试焊点与第一电源 网络之间电连接。这样，通过第一电阻标识处是否焊接第一电阻，从而能够实现第一测试焊点与第一电源网络之间的连接或断开，以便当处于测试模式时，能够在待测芯片的外部直接测量得到准确的内部电源噪声测试结果。
本公开实施例提供了一种电源噪声测试方法，具体提供了一种通过修改封装基板的设计来精确测量芯片内部电源噪声的方法，一方面，在封装基板的设计中修改电源引脚的网络分布；另一方面，在测试板(例如，系统主板)中添加相应的测试点，在测试模式下断开0欧姆的第一电阻，然后根据相应电源的测试点进行内部电源噪声测量；如此，根据前述实施例提供的技术方案，在测试模式下利用相应的测试点可以直接测量到芯片内部电源噪声的准确情况，从而能够提高电源噪声的测试准确度。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例基于该电源噪声测试装置，通过在封装基板上独立出一个管脚作为第一测试引脚使用，并且在测试板上设置第一测试点，然后由第一测试引脚与第一测试点连接，不仅能够将用于测试电源噪声的信号通过第一测试点引出，同时实现了该测试信号独立于第一电源类型对应的第一电源网络；如此，通过测试板上的第一测试点对待测芯片中的内部电源进行噪声测试，可以提高电源噪声的测试准确度。

Claims (20)

  1. 一种封装基板，所述封装基板包括多个焊盘阵列，且每一个焊盘阵列中至少包括电源焊盘；其中：
    所述多个焊盘阵列中属于同一电源类型的电源焊盘被划分为测试焊盘和电源焊盘集合；其中，所述电源焊盘集合包括属于所述同一电源类型且除所述测试焊盘之外的其他电源焊盘，且所述电源焊盘集合中的电源焊盘全部电连接在一起；所述测试焊盘用于对待测芯片中所述同一电源类型对应的内部电源进行噪声测试。
  2. 根据权利要求1所述的封装基板，其中，所述封装基板包括四个焊盘阵列；其中，所述四个焊盘阵列呈上下对称且左右对称结构。
  3. 根据权利要求1所述的封装基板，其中，所述封装基板还包括导电层；其中，在所述导电层中，所述电源焊盘集合中的电源焊盘采用铺铜方式进行电连接以形成第一电源网络，且所述测试焊盘独立于所述第一电源网络。
  4. 根据权利要求1所述的封装基板，其中，所述封装基板的表面设置有金手指；其中，在所述同一电源类型中，所述测试焊盘与所述金手指之间的距离小于所述电源焊盘集合中的电源焊盘与所述金手指之间的距离。
  5. 根据权利要求4所述的封装基板，其中，所述封装基板的表面还放置有所述待测芯片，且所述待测芯片包括多个引脚阵列，每一个引脚阵列中至少包括电源引脚；其中：
    所述多个引脚阵列中属于同一电源类型的电源引脚被划分为测试引脚和电源引脚集合；其中，所述电源引脚集合中的电源引脚与所述电源焊盘集合中的电源焊盘对应电连接，所述测试引脚与所述测试焊盘电连接，以使得所述测试焊盘能够通过所述测试引脚对所述待测芯片中所述同一电源类型对应的内部电源进行噪声测试。
  6. 根据权利要求5所述的封装基板，其中，所述封装基板还设置有金属过孔和金属走线；其中，所述测试焊盘通过所述金属走线和所述金属过孔电连接到所述金手指，所述金手指与所述测试引脚之间采用打金线方式进行电连接，以实现所述测试焊盘与所述测试引脚电连接到一起。
  7. 根据权利要求1所述的封装基板，其中，每一个焊盘阵列至少包括VDD1电源焊盘、VDD2电源焊盘和VDDQ电源焊盘；
    其中，所述同一电源类型为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项。
  8. 根据权利要求7所述的封装基板，其中，
    所述多个焊盘阵列中属于VDD1电源类型的电源焊盘被划分为VDD1电源测试焊盘和VDD1电源焊盘集合；其中，所述VDD1电源焊盘集合中 的电源焊盘全部电连接以形成VDD1电源网络，且所述VDD1电源测试焊盘独立于所述VDD1电源网络，所述VDD1电源测试焊盘用于对所述待测芯片内部的VDD1电源进行噪声测试；
    所述多个焊盘阵列中属于VDD2电源类型的电源焊盘被划分为VDD2电源测试焊盘和VDD2电源焊盘集合；其中，所述VDD2电源焊盘集合中的电源焊盘全部电连接以形成VDD2电源网络，且所述VDD2电源测试焊盘独立于所述VDD2电源网络，所述VDD2电源测试焊盘用于对所述待测芯片内部的VDD2电源进行噪声测试；
    所述多个焊盘阵列中属于VDDQ电源类型的电源焊盘被划分为VDDQ电源测试焊盘和VDDQ电源焊盘集合；其中，所述VDDQ电源焊盘集合中的电源焊盘全部电连接以形成VDDQ电源网络，且所述VDDQ电源测试焊盘独立于所述VDDQ电源网络，所述VDDQ电源测试焊盘用于对所述待测芯片内部的VDDQ电源进行噪声测试。
  9. 一种电源噪声测试装置，所述电源噪声测试装置包括如权利要求1至8任一项所述的封装基板、待测芯片和测试板；其中：
    所述测试板设置有第一电源类型对应的第一测试点；
    所述待测芯片至少包括所述第一电源类型对应的电源引脚，且所述电源引脚被划分为第一测试引脚和除所述第一测试引脚之外的第一电源引脚集合；
    所述封装基板至少包括所述第一电源类型对应的电源焊盘，且所述电源焊盘被划分为第一测试焊盘和除所述第一测试焊盘之外的第一电源焊盘集合；
    其中，所述第一电源引脚集合中的电源引脚与所述第一电源焊盘集合中的电源焊盘对应电连接，所述第一测试引脚与所述第一测试焊盘电连接，且所述第一测试焊盘还与所述第一测试点电连接，以使得所述第一测试点能够通过所述第一测试焊盘和所述第一测试引脚对所述待测芯片中所述第一电源类型对应的内部电源进行噪声测试。
  10. 根据权利要求9所述的电源噪声测试装置，其中，所述待测芯片、所述封装基板和所述测试板依次叠放。
  11. 根据权利要求9所述的电源噪声测试装置，其中，所述测试板还设置有与所述封装基板中的多个焊盘阵列相对应的多个焊点阵列，且每一个焊点阵列中至少包括电源焊点；其中：
    所述多个焊点阵列中属于所述第一电源类型的电源焊点被划分为第一测试焊点和第一电源焊点集合，所述第一电源焊点集合中的电源焊点与所述第一电源焊盘集合中的电源焊盘对应电连接，且所述第一电源焊点集合中的电源焊点全部电连接在一起，以形成第一电源网络；其中，所述第一测试焊点独立于所述第一电源网络。
  12. 根据权利要求11所述的电源噪声测试装置，其中，所述测试板还 设置有第一金属走线；其中，所述第一测试焊盘与所述第一测试焊点连接，且所述第一测试焊点通过所述第一金属走线与所述第一测试点电连接，以实现所述第一测试焊盘与所述第一测试点的电连接。
  13. 根据权利要求11所述的电源噪声测试装置，其中，所述测试板还设置有第一电阻标识，且所述第一电阻标识包括第一焊点和第二焊点；
    其中，所述第一焊点与所述第一测试焊点连接，所述第二焊点与所述第一电源网络连接。
  14. 根据权利要求13所述的电源噪声测试装置，其中，
    在测试模式下，所述第一电阻标识处未焊接第一电阻，以使得所述第一测试焊点与所述第一电源网络处于断开状态；
    在工作模式下，所述第一电阻标识处焊接第一电阻，以使得所述第一测试焊点与所述第一电源网络处于电连接状态。
  15. 根据权利要求14所述的电源噪声测试装置，其中，所述第一电阻的阻值为0欧姆。
  16. 根据权利要求13所述的电源噪声测试装置，其中，所述第一电源类型为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项；
    其中，在所述测试板上，不同的第一电源类型对应设置有不同的第一测试点和不同的第一电阻标识。
  17. 一种电源噪声测试方法，应用于权利要求9所述的电源噪声测试装置，所述方法包括：
    在测试模式下，通过所述测试板上的第一测试点对所述待测芯片中第一电源类型对应的内部电源进行噪声测试；
    其中，所述第一测试点与第一电源类型具有对应关系，且所述第一电源类型为VDD1电源类型、VDD2电源类型和VDDQ电源类型中的任意一项。
  18. 根据权利要求17所述的方法，其中，所述测试板还设置有与所述封装基板中的多个焊盘阵列相对应的多个焊点阵列，且每一个焊点阵列中至少包括电源焊点；其中：
    所述多个焊点阵列中属于所述第一电源类型的电源焊点被划分为第一测试焊点和第一电源焊点集合，所述第一电源焊点集合中的电源焊点与所述第一电源焊盘集合中的电源焊盘对应电连接，且所述第一电源焊点集合中的电源焊点全部电连接在一起，以形成第一电源网络；其中，所述第一测试焊点独立于所述第一电源网络。
  19. 根据权利要求18所述的方法，其中，所述测试板还设置有第一电阻标识，所述方法还包括：
    在工作模式下，确定所述第一电阻标识处焊接第一电阻，通过所述第一电阻控制所述第一测试焊点与所述第一电源网络处于电连接状态。
  20. 根据权利要求19所述的方法，其中，所述方法还包括：
    在测试模式下，确定所述第一电阻标识处未焊接第一电阻，以使得所述第一测试焊点与所述第一电源网络处于断开状态。
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