Classifications

• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
  • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
  • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
  • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
  • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

• the present disclosure relates to a semiconductor display device and a spatial phase modulation device.
• a phase modulation device has a panel structure in which a liquid crystal layer is sandwiched between electrodes, and controls the phase of incident light in an analog manner by controlling the voltage applied to the liquid crystal layer.
• the phase modulation device is desired to have analog drive and high speed pixel circuits.
• switching elements within pixels such as transistors such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), are required to have high withstand voltage and low leakage performance.
• MOSFETs Metal-Oxide-Semiconductor Field-Effect Transistors
• oxide semiconductors have high breakdown voltage and low leakage characteristics, they have a problem of extremely low electron mobility.
• this configuration poses a problem in that the response performance of the pixel circuit using an oxide semiconductor is insufficient with respect to the input frequency of image signals.
• a current sink circuit is used to reduce the parasitic resistance during the write operation as a means to reduce the influence of the source follower effect, which simultaneously activates multiple row scan lines and supplies image signals for multiple pixels at the same time.
• a method has been proposed to reduce this.
• multiple row scanning lines are simultaneously activated and image signals are supplied to multiple pixels at the same time, multiple digital-to-analog conversion circuits and analog buffers are required, which increases the scale of the signal line drive circuit. There are issues such as slow shrinkage of picture frames and chip sizes.
• the present disclosure provides a display device in which a pixel circuit can output an appropriate output.
• a semiconductor display device includes a pixel circuit, a pixel array, a first drive circuit, a first signal line, a second drive circuit, and a second signal line.
• the pixel circuit includes a display element.
• the pixel array includes the pixel circuits in a two-dimensional array in a first direction and a second direction intersecting the first direction.
• the first drive circuit controls driving of the pixel circuits in the first direction in the pixel array.
• the first signal line transmits a drive signal from the first drive circuit to the pixel circuit belonging to the first direction.
• the second drive circuit transmits a reference signal to the pixel circuits belonging to the second direction in the pixel array.
• the second signal line transmits the reference signal from the second drive circuit to the pixel circuit belonging to the second direction.
• the pixel circuit includes a memory circuit and a comparison circuit.
• the memory circuit stores digital grayscale values indicating the display intensity of the pixel circuit.
• the comparison circuit is connected to the memory circuit and compares the digital grad
• a first transistor whose output end is connected to the drive terminal of the display element; and a second transistor whose one end is connected to the comparison circuit and the other end is connected to the gate of the first transistor. Good too.
• a first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element, the first transistor, and the second substrate.
• the semiconductor device may include two transistors, the second substrate may include the memory circuit and the comparison circuit, and the first transistor and second transistor may include an oxide semiconductor.
• the second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage.
• the reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
• the device may further include a resistor connected between the gate of the first transistor and the power supply voltage.
• a first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element, the first transistor, and the second substrate.
• the semiconductor device may include two transistors, the second substrate may include the memory circuit and the comparison circuit, and the first transistor and second transistor may include an oxide semiconductor.
• the second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage.
• the reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
• the resistor may be a pull-up resistor or a pull-down resistor.
• the display device may include a first transistor whose gate is connected to the comparison circuit and whose output terminal is connected to the drive terminal of the display element.
• a first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element and the first transistor.
• the second substrate may include the memory circuit and the comparison circuit, and the first transistor may include an oxide semiconductor.
• the second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage.
• the reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
• the pixel circuit may further include a level shift circuit that is connected to the comparison circuit and controls the voltage of the input signal.
• a first transistor whose output end is connected to the drive terminal of the display element; and a second transistor whose one end is connected to the level shift circuit and the other end is connected to the gate of the first transistor. It's okay.
• a first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element, the first transistor, and the second substrate.
• the second substrate may include the memory circuit, the comparison circuit, and the level shift circuit, and the first transistor and the second transistor may include an oxide semiconductor. good.
• the second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage.
• the reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
• a spatial phase modulation device includes any of the semiconductor display devices described above, the pixel circuit is a circuit that constitutes a reflective pixel, and the display element is a liquid crystal.
• the pitch of the pixel circuit may be 3.6 um or less.
• FIG. 1 is a diagram schematically showing a semiconductor display device according to an embodiment.
• FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
• FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
• FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
• FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
• FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
• FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
• FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
• FIG. 1 is a diagram schematically showing a laser processing device according to an embodiment.
• FIG. 1 is a diagram schematically illustrating an optical computing device according to an embodiment.
• FIG. 1 is a schematic diagram of a stacked structure of a semiconductor device according to an embodiment.
• FIG. 1 is a block diagram schematically showing a semiconductor display device according to an embodiment.
• the semiconductor display device 1 includes a pixel array 10 , a control circuit 12 , a vertical drive circuit 14 , a horizontal drive circuit 16 , a first signal line 140 , and a second signal line 160 .
• the pixel array 10 includes a plurality of pixel circuits 100 arranged in an array in a first direction and a second direction intersecting the first direction.
• Each pixel circuit 100 includes a display element.
• Each pixel circuit 100 included in this pixel array 10 allows the semiconductor display device 1 to display an image or display for phase modulation.
• the first direction and the second direction represent, by way of non-limiting example, a line direction and a column direction, respectively.
• the control circuit 12 is a circuit that controls the display of the image displayed on the pixel array 10 or the display for phase modulation.
• the control circuit 12 controls each of the pixel circuits 100 in the pixel array 10 by sending appropriate control signals to the vertical drive circuit 14 and the horizontal drive circuit 16 .
• the vertical drive circuit 14 (first drive circuit) transmits a signal that controls which line of the pixel circuit 100 in the pixel array 10 is to be driven. Pixel circuits 100 belonging to the same line are connected to the same first signal line 140. The vertical drive circuit 14 outputs a signal (drive signal) for controlling the drive of the pixel circuit 100 belonging to each line via the first signal line 140 .
• the horizontal drive circuit 16 (second drive circuit) transmits a signal indicating the display intensity or phase modulation degree for each column to the pixel circuit 100 whose drive is controlled by the vertical drive circuit 14 . Pixel circuits 100 belonging to the same column are connected to the same second signal line 160. The horizontal drive circuit 16 outputs a signal (reference signal) for controlling the intensity, etc. of the pixel circuit 100 belonging to each column via the second signal line 160 .
• the horizontal drive circuit 16 starts outputting a ramp signal at a timing controlled by the control circuit 12 for each column.
• the pixel circuit 100 reads the signal value of the lamp signal transmitted from the horizontal drive circuit 16 via the second signal line 160 at an appropriate timing to drive the light emitting element or phase modulation element with appropriate intensity or phase modulation degree. Drive.
• the semiconductor display device 1 can display an appropriate image or set an appropriate degree of phase modulation in the pixel array 10.
• FIG. 2 is a diagram schematically showing an example of the pixel circuit 100.
• the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a phase modulation element Pm as a display element, and a first transistor Tr1 that controls the drive of the phase modulation element Pm based on signals transmitted from respective signal lines. , a second transistor Tr2, and a capacitor C.
• the memory circuit 102 stores digital gradation values indicating the phase modulation degree (display intensity of the display element) of the phase modulation element Pm.
• the memory circuit 102 is, by way of non-limiting example, SRAM (Static Random Access Memory).
• the stored digital gradation values may be input from the horizontal drive circuit 16 via the second signal line 160, for example, before display.
• the comparison circuit 104 is connected to the memory circuit 102 and compares the digital gradation value stored in the memory circuit 102 with the count value output from the counter 200 provided outside the pixel circuit 100 and outputs the result. .
• the first transistor Tr1 operates as a switch that writes a signal that determines the modulation intensity of the phase modulation element Pm into the capacitor C.
• the first transistor Tr1 is, for example, an n-type transistor including an oxide semiconductor, and has a drain connected to the signal line DT, and a source connected to one end of the capacitor C and the phase modulation element Pm.
• the second transistor Tr2 operates as a switch that controls the timing of driving the first transistor Tr1.
• the second transistor Tr2 is, for example, an n-type transistor including an oxide semiconductor, and has a drain connected to the comparator circuit 104, a source connected to the gate of the first transistor Tr1, and a gate connected to the signal line GT. .
• the oxide semiconductor included in the first transistor Tr1 and the second transistor Tr2 may be formed of, for example, IGZO, or other oxides such as oxides containing oxides of zinc, tin, and indium. It may be a transistor comprising:
• One end of the capacitor C is connected to the source of the first transistor Tr1, and the other end is connected to the reference voltage line VCOM.
• the phase modulation element Pm is, for example, an element including a liquid crystal, and one end is connected to one end of the capacitor C, and the other end is connected to the reference voltage line VCOM.
• Comparison circuit 104 compares the gradation value stored in memory circuit 102 and the count value output from counter 200 .
• This count value is, for example, a value that is counted up from a minimum value to a maximum value.
• the comparison circuit 104 outputs a voltage for driving the first transistor Tr1 to the drain of the second transistor Tr2 at the timing when the count value exceeds the gradation value.
• the second transistor Tr2 When the second transistor Tr2 is turned on by the signal line GT, it outputs a voltage to drive the gate of the first transistor Tr1 at a timing corresponding to the output from the comparator circuit 104.
• the signal line GT is connected to the first signal line 140 in FIG. 1, for example. That is, at the timing when the line to which the pixel circuit 100 belongs is selected and the counter value exceeds the gradation value, the second transistor Tr2 outputs a signal that drives the first transistor Tr1.
• the first transistor Tr1 outputs a signal to the capacitor C according to the voltage value applied to the signal line DT at the timing when the drive signal is input to the gate. A signal value corresponding to the voltage of the signal line DT output from the first transistor Tr1 is written into the capacitor C.
• the signal line DT is connected to the second signal line 160 in FIG. 1, for example.
• a ramp signal from the horizontal drive circuit 16 is input to the second signal line 160 as a reference signal.
• This ramp signal is a signal that transitions from the minimum value (predetermined minimum value) to the maximum value (predetermined maximum value) of the display value or modulation value.
• the start timing of the ramp signal output by the horizontal drive circuit 16 and the count of the counter 200 may be synchronized.
• capacitor C is charged with the voltage of the ramp signal ( signal value of the reference signal) is stored. As a result, a voltage corresponding to the gradation value stored in the memory circuit 102 is stored in the capacitor C.
• the phase modulation element Pm performs display according to the voltage written in the capacitor C.
• the angle of the liquid crystal molecules in the phase modulation element Pm is set according to the voltage written to the capacitor C, and the degree of phase modulation is set for each pixel circuit 100 based on the difference in this angle. .
• the signal for controlling the phase modulation degree is written into the capacitor C from the ramp-shaped reference signal at an appropriate timing, so that the electron mobility is lower than that of the MOSFET. Even in the case of using an oxide semiconductor with a low sensitivity, it is possible to read and display appropriate pixel values without insufficient response speed. Therefore, appropriate phase modulation processing can be achieved using a transistor including an oxide semiconductor having high breakdown voltage and low leakage characteristics.
• the semiconductor display device 1 can output an analog display signal based on the digital gradation value to the display element without going through a digital-to-analog conversion circuit. Therefore, according to the semiconductor display device 1 of the present disclosure, it is also possible to drive all pixels at the same timing.
• the first transistor Tr1 and the second transistor Tr2 are N-type transistors, but they are not limited to this, and P-type transistors can also be implemented by adjusting the control voltage. Is possible. Although embodiments other than the first embodiment will be described as n-type transistors, they may be p-type transistors as well.
• the oxide semiconductor is p-type, the oxide semiconductor may be formed of a substance containing an oxide of copper, silver, tin, or the like.
• the count value output by the counter 200 is assumed to count up, the present invention is not limited to this.
• the count value output by the counter 200 may be a value that counts down from the maximum value to the minimum value.
• the voltage applied to the signal line DT may also be a downward ramp signal whose voltage value decreases from a predetermined maximum value to a predetermined minimum value. The same applies to the following embodiments.
• FIG. 3 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the second embodiment.
• the pixel circuit 100 includes a resistor R connected to the gate of the first transistor Tr1.
• the resistor R is a resistor that pulls down the gate voltage of the first transistor Tr1, and stabilizes the potential of the gate of the first transistor Tr1.
• the semiconductor display device 1 can perform display (phase modulation) based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. It becomes possible to do so.
• FIG. 4 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the third embodiment.
• the pixel circuit 100 has a resistor that is used as a pull-up resistor instead of the pull-down resistor in the configuration of the second embodiment described above.
• One end of the resistor R is connected to the gate of the first transistor Tr1, and the other end is connected to the positive power supply voltage.
• This is a resistor that pulls up the gate voltage of the first transistor Tr1 of the resistor R, and stabilizes the potential of the gate of the first transistor Tr1.
• the semiconductor display device 1 can perform display (phase modulation) based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. It becomes possible to do so. Compared to the second embodiment described above, there is no need for a grounding path for each display pixel (pixel circuit 100), so the wiring layout area can be reduced and resources can be secured for the area of this wiring. You can also do it.
• the resistor R is a pull-down or pull-up resistor, but this can also be determined depending on, for example, the conductivity type of the first transistor Tr1. For example, if the first transistor Tr1 is an N-type, a pull-down resistor may be provided, and if the first transistor Tr1 is a P-type, a pull-up resistor may be provided.
• the pixel circuit includes two oxide semiconductors, but in this embodiment, the structure of the transistor is changed.
• FIG. 5 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the fourth embodiment.
• the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a first transistor Tr1, a capacitor C, and a phase modulation element Pm as a display element.
• the memory circuit 102, capacitor C, and phase modulation element Pm operate in the same manner as in each of the above embodiments.
• Comparison circuit 104 compares the digital gradation value stored in memory circuit 102 and the counter value output from counter 200 provided outside pixel circuit 100, as in each of the above-described embodiments. Output the result to the gate of the first transistor Tr1.
• the first transistor Tr1 is, for example, an n-type oxide semiconductor, and has a drain connected to the signal line DT, a source connected to one end of the capacitor C and one end of the phase modulation element Pm, and a gate connected to the comparator circuit 104. be done.
• the configuration may be such that the second transistor in each of the above-described embodiments is not provided.
• a signal based on the comparison result output from the comparison circuit 104 is directly applied to the gate of the first transistor Tr1. Then, similar to the embodiment described above, a ramp-shaped signal is transferred from the signal line DT to the capacitor C at the timing when the result of comparing the gradation value and the counter value is obtained.
• the semiconductor display device 1 can perform display based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. (phase modulation). By not providing the second transistor Tr2, it is possible to reduce the region in which the transistor is formed.
• FIG. 6 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the fifth embodiment.
• the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a first transistor Tr1, a second transistor Tr2, and a phase modulation element Pm.
• phase modulation element Pm The operations of the memory circuit 102, comparator circuit 104, second transistor Tr2, first transistor Tr1, and phase modulation element Pm are approximately the same as in the above embodiment.
• the first transistor Tr1 transfers the signal value from the signal line DT to one end of the phase modulation element Pm at a timing corresponding to the gradation value stored in the memory circuit 102.
• the degree of phase modulation of the phase modulation element Pm is controlled based on the signal value transferred from the first transistor Tr1.
• the semiconductor display device 1 can generate appropriate display signals using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. It becomes possible to display (phase modulation) based on
• the first transistor Tr1 which is an oxide semiconductor, is used as a transistor to transfer signals based on pixel values, and an appropriate voltage is applied to transfer signals for an appropriate period of time. It becomes possible to control the display on the screen.
• the phase modulation element Pm includes a liquid crystal, it is possible to hold the voltage by the capacitance related to the liquid crystal.
• FIG. 7 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the sixth embodiment.
• the pixel circuit 100 may further include a level shift circuit 106 in addition to the configuration of the first embodiment. That is, the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a level shift circuit 106, a first transistor Tr1, a second transistor Tr2, a capacitor C, and a phase modulation element Pm.
• the level shift circuit 106 is connected between the comparison circuit 104 and the second transistor Tr2.
• the level shift circuit 106 converts the signal output from the comparison circuit 104 to a predetermined voltage level and outputs the same.
• the output of this level shift circuit 106 is applied to the gate of the first transistor Tr1 via the second transistor Tr2, thereby converting the output of the comparator circuit 104 to an appropriate voltage level for driving the first transistor Tr1. can be applied.
• the semiconductor display device 1 can perform display based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. (phase modulation).
• phase modulation By providing the level shift circuit 106, it becomes possible to control the first transistor Tr1, which is an oxide semiconductor, with more precision.
• phase modulation element including, for example, a liquid crystal is used as a display element, but a light emitting element can also be used as a display element. That is, the configuration of the semiconductor display device 1 including an oxide semiconductor can also be applied to a display device of a light emitting device that realizes a general display such as a display.
• FIG. 8 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the seventh embodiment.
• the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a third transistor Tr3, a fourth transistor Tr4, a capacitor C, and a light emitting element L as a display element.
• the memory circuit 102 stores digital gradation values that define the intensity at which the light emitting element L emits light.
• the comparison circuit 104 compares the gradation value stored in the memory circuit 102 and the count value output from the counter 200 provided outside the pixel circuit 100, and outputs the comparison result and a drive signal.
• the third transistor Tr3 is, for example, a transistor including an n-type oxide semiconductor, and its drain is connected to the power supply voltage line VCC.
• the fourth transistor Tr4 is, for example, a transistor including an n-type oxide semiconductor, and has a drain connected to the signal line VSIG, a source connected to the gate of the third transistor Tr3, and a gate connected to the output of the comparison circuit 104. be done.
• One end of the capacitor C is connected to the gate of the third transistor Tr3 and the source of the fourth transistor Tr4, and the other end is connected to the source of the third transistor Tr3.
• the light-emitting element L is, for example, a light-emitting element such as an LED (Light Emitting Diode), an organic EL (Electroluminescence) including an organic LED, or an inorganic EL.
• the light emitting element is not limited to these, and may be other types of elements whose emission intensity (brightness) is determined by the voltage applied to one end.
• One end of the light emitting element L to which a voltage corresponding to the light emission intensity is applied is connected to the source of the third transistor Tr3 and the other end of the capacitor C, and the other end is grounded.
• Digital gradation values that determine the light emission intensity of the light emitting element L are stored in the memory circuit 102 .
• the comparison circuit 104 compares the gradation value stored in the memory circuit 102 with the count value input from the external counter 200, and when the counter value exceeds the gradation value, outputs a signal to the gate of the fourth transistor Tr4. Outputs a signal to drive the fourth transistor Tr4.
• the fourth transistor Tr4 transfers the voltage applied to the signal line VSIG to the capacitor C at the timing when the driving signal is input.
• a ramp-like reference signal synchronized with the counter 200 is applied to the signal line VSIG. For example, a ramp signal that transitions from a predetermined minimum value to a predetermined maximum value for applying a voltage corresponding to the minimum to maximum brightness of the light emitting element L is applied to the signal line VSIG.
• a voltage Vcc which is the power supply voltage of the oxide semiconductor, is applied to the drain of the third transistor Tr3 from the power supply voltage line VCC.
• Vcc the power supply voltage of the oxide semiconductor
• a voltage corresponding to the emission intensity is applied to the anode of the light emitting element L, and a current flows appropriately, so that the light emitting element L emits light at an intensity based on the gradation stored in the memory circuit 102.
• the semiconductor display device 1 is capable of controlling the light emission intensity of not only a phase modulation element but also a light emitting element in a display device such as a general display. Also in this form, the response speed is insufficient for emitting light based on a signal converted from a digital signal into an analog intensity voltage in a pixel circuit using an oxide semiconductor having high breakdown voltage and low leakage characteristics as in each of the above embodiments. It becomes possible to control without
• the pixel circuits 100 according to the fourth to seventh embodiments may include the pull-down resistor according to the second embodiment or the pull-up resistor according to the third embodiment. Furthermore, the pixel circuit 100 according to the fourth embodiment, fifth embodiment, or seventh embodiment may include the level shift circuit according to the sixth embodiment.
• Semiconductor display device 1 can, for example, form a suitable reflective film on the side opposite to the display surface of the phase modulation element Pm as shown in Figure 2 to reflect the light that has passed through the liquid crystal element and output it from the display surface. It can operate as a modulator.
• the degree of phase modulation by the liquid crystal can be controlled by taking into account the double pass caused by reflection.
• FIG. 9 is an example in which the pixel circuit 100 is used as a reflective pixel in this way, and is a diagram showing an example in which the semiconductor display device 1 is applied to a laser processing device.
• the laser processing device 3 includes a light source 300 , a mirror 302 , a phase modulation device including a semiconductor display device 1 , a mirror 304 , an optical system 306 , a condensing section 308 , and a support section 310 .
• the light source 300 may be, for example, a solid laser, a liquid laser, a gas laser, or a semiconductor laser such as a LD (Laser Diode).
• the light source 300 emits laser light using a pulse transmission method, for example.
• the laser light may be linearly polarized.
• Mirrors 302 and 304 are mirrors that reflect the laser light output from the light source 300.
• the phase modulation device includes, for example, a semiconductor display device 1 that includes a liquid crystal as a phase modulation element.
• the pixel circuit of the semiconductor display device 1 is a circuit that constitutes a reflective pixel, and the display element included in the pixel circuit is a liquid crystal.
• the pixel circuits of this semiconductor display device 1 may have a pixel pitch that allows appropriate phase modulation in the laser processing device 3 , for example, a pixel pitch of 3.6 ⁇ m or less.
• the phase modulator appropriately modulates the phase of the laser beam reflected by the mirror 302 and outputs it to the mirror 304 .
• the optical system 306 may be an imaging optical system, for example, a double-sided telecentric optical system in which the reflecting surface of the phase modulation device and the entrance pupil plane of the condenser 308 are in an imaging relationship.
• the condensing unit 308 condenses the laser beam and irradiates it onto the surface of the target Ob.
• the support part 310 supports the object so that the upper surface of the object is parallel to the horizontal plane, for example, by adsorbing the object Ob.
• the support portion 310 may be configured to be able to translate and rotate within a horizontal plane, for example.
• the laser beam emitted from the light source 300 is reflected by the mirror 302 and enters the phase modulation device.
• the phase modulation device light that has been appropriately phase modulated in a phase modulation element in a pixel circuit provided as a reflective pixel in the semiconductor display device 1 is emitted to the mirror 304 as reflected light.
• the laser light is phase modulated and emitted without modifying the polarization plane of the phase modulation device.
• the phase modulated laser beam output from the phase modulation device is reflected by the mirror 304 to the optical system 306 .
• the optical system 306 forms a telecentric optical system in which the reflecting surface of the phase modulator and the entrance pupil plane of the condenser 308 are in an imaging relationship, so the laser output from the phase modulator The light is imaged at the entrance pupil plane of the condenser 308 .
• the condensing unit 308 focuses and irradiates the laser beam on the object Ob-shaped plane, which is placed at an appropriate position by the support unit 310, and the image formed on the incident plane is focused on the object Ob at a predetermined magnification. to be projected onto the surface of As a result, a modified region of the pattern of the projected image is formed on the surface of the object Ob.
• an image forming a pattern to be formed in the modified region is formed by a spatial phase modulation device (semiconductor display device 1 ).
• a spatial phase modulation device semiconductor display device 1 .
• such a spatial phase modulation device exhibits highly accurate reforming performance due to its high response speed, and also has low leakage characteristics, making it possible to reduce power consumption. becomes.
• FIG. 10 is a diagram schematically showing an optical computing device 4 including a semiconductor display device 1 as a spatial phase modulation device.
• the optical computing device 4 includes a light source 400, a light valve 402, a display section of a plurality of semiconductor display devices 1, and a detection section 404.
• a transmissive phase modulation device can be used as a display part of semiconductor display device 1. It can be formed using The display section is formed including, for example, the oxide semiconductor shown in FIG. 2 and the like, a phase modulation element, and wiring.
• the display portions of the semiconductor display device 1 are overlapped with each other with a predetermined interval.
• the display section of this semiconductor display device 1 will be referred to as a spatial phase modulator.
• the light source 400 irradiates the light valve 402 with laser light.
• the light valve 402 is, for example, a light transmission type optical modulator, and modulates the light intensity of the laser light incident from the light source 400 based on a control signal (image data) input from the outside. As a result, the light valve 402 generates a pattern of image light according to the control signal input from the outside.
• the light valve 402 irradiates the first spatial phase modulator with the generated image light.
• the image light is phase modulated by the first spatial phase modulator, and the light acquired thereby is irradiated to the second spatial phase modulator.
• the light irradiated to the second spatial phase modulator is phase modulated by the second spatial phase modulator, and the light acquired thereby is irradiated to the third spatial phase modulator.
• the image light is phase modulated by each spatial phase modulator, and the light output from the last spatial phase modulator is detected by the detection unit 404.
• the detection unit 404 estimates image data input to the light valve 402 based on the input light.
• the light source 400 and the light valve 402 may be omitted.
• the first spatial phase modulator may be irradiated with image light input from the outside.
• the light-transmitting paper surface on which characters or pictures are written is used as the light input source for the first spatial phase modulator.
• the first spatial phase modulator may be placed on the surface of the paper and detect external light transmitted through the surface of the paper.
• the phase distribution that determines the processing content in the optical computing device 4 is formed by the semiconductor display device 1 that operates as a spatial phase modulation device. This makes it possible to realize optical computing with low power consumption and the ability to change calculation content.
• the semiconductor display device 1 may be formed from a plurality of stacked semiconductor substrates.
• FIG. 11 is a schematic diagram showing a non-limiting example of the stacked structure of the semiconductor display device 1.
• the structure corresponding to the semiconductor display device 1 particularly the pixel circuit 100 of the semiconductor display device 1 , may be formed by forming two semiconductor layers and stacking them so as to overlap each other.
• the semiconductor display device 1 may include, for example, a first substrate 50 and a second substrate 52, and may be formed by appropriately laminating these two substrates. Conductive layers such as electrodes and wiring are appropriately formed on the contact surfaces of the first substrate 50 and the second substrate 52 to electrically connect them at appropriate locations.
• the first substrate 50 has, for example, a display element, and the display element is arranged on the first substrate 50 so that a display is performed on the display element toward the top of the figure.
• the semiconductor display device 1 may include an appropriate optical system for the display element. Further, in the semiconductor display device 1 , an appropriate coating may be applied on the upper surface of the first substrate 50 to protect the display element. In such a definition, the second substrate 52 is placed farther from the display surface of the semiconductor display device 1 than the first substrate 50 .
• the pixel circuit 100 of the semiconductor display device 1 includes a first transistor Tr1, a second transistor Tr2, a memory circuit 102, and a comparison circuit 104.
• elements may be formed on each substrate as follows.
• the first substrate 50 includes at least a display element, a first transistor Tr1 and a second transistor Tr2 including an oxide semiconductor, and the second substrate 52 may include a memory circuit 102 and a comparison circuit 104. .
• the second transistor Tr2 if the second transistor Tr2 is not provided, at least the first transistor Tr1 including an oxide semiconductor may be provided on the first substrate 50.
• this level shift circuit 106 may be provided on the second substrate 52.
• the semiconductor display device 1 includes the light emitting element L, in which the transistor in the pixel circuit 100 is provided on the first substrate 50, and the memory circuit 102 etc. is provided on the second substrate 52. You can also use it as
• the first substrate 50 and the second substrate 52 in this way, it is possible to form a layer that forms a transistor including an oxide semiconductor and a layer that forms other transistors, such as a MOSFET, separately. Therefore, the complexity and complexity of the process can be reduced.
• first substrate 50 and second substrate 52 may be formed, for example, in a CoC (Chip on Chip) format in which chips are stacked together, or in a CoW (Chip on Wafer) format in which chips and wafers are stacked. Alternatively, it may be formed in a WoW (Wafer on Wafer) format in which wafers are stacked.
• CoC Chip on Chip
• CoW Chip on Wafer
• WoW WoW
• electrical connections such as wiring on the first substrate 50 and the second substrate 52 can be formed by any method such as micro bumps, hybrid junctions, via holes, etc.
• the above stacked structure is given as a non-limiting example, and the semiconductor display device 1 according to the present disclosure does not have semiconductors formed on separate chips or the like and then bonded together, as described above. It may be formed in a separate layer in the process.
• circuits such as the memory circuit 102 and the comparison circuit 104, particularly a circuit having a MOSFET as a structure, are formed on the substrate as a second semiconductor layer.
• a first semiconductor layer including a pixel circuit 100 including an oxide semiconductor is laminated on the formed second semiconductor layer. It can be formed in the form of
• the semiconductor display device displays analog intensity information when a digital signal is input using an oxide semiconductor as a transistor that controls switches in a pixel circuit. It becomes possible to form pixels. As a result, these semiconductor display devices are able to improve the light focusing area due to high phase stability, expand the viewing angle due to strong image pitch, reduce chip size due to the layered structure, and improve image quality due to high refresh rate. It can be realized.
• a pixel circuit including a display element; a pixel array including the pixel circuits in a two-dimensional array in a first direction and a second direction intersecting the first direction; a first drive circuit that controls driving of the pixel circuits belonging to the first direction in the pixel array; a first signal line that transmits a drive signal from the first drive circuit to the pixel circuit belonging to the first direction; a second drive circuit that transmits a reference signal to the pixel circuits in the second direction in the pixel array; a second signal line that transmits the reference signal from the second drive circuit to the pixel circuit belonging to the second direction; Equipped with The pixel circuit is a memory circuit that stores digital gradation values indicating display intensity of the pixel circuit; a comparison circuit that is connected to the memory circuit and compares the digital gradation value stored in the memory circuit with a counter signal; Equipped with Semiconductor display device.
• the semiconductor display device comprising:
• the semiconductor display device formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
• the first substrate includes the display element, the first transistor, and the second transistor,
• the second substrate includes the memory circuit and the comparison circuit, the first transistor and the second transistor include an oxide semiconductor;
• the semiconductor display device according to (2).
• the semiconductor display device (Four) a capacitor connected between a drive terminal of the display element and a predetermined voltage; Furthermore, The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
• the semiconductor display device according to (2) or (3).
• the semiconductor display device formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
• the first substrate includes the display element, the first transistor, and the second transistor,
• the second substrate includes the memory circuit and the comparison circuit, the first transistor and the second transistor include an oxide semiconductor;
• the semiconductor display device according to (5).
• the semiconductor display device (7) a capacitor connected between a drive terminal of the display element and a predetermined voltage; Furthermore, The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
• the semiconductor display device according to (5) or (6).
• the resistor is a pull-up resistor or a pull-down resistor;
• the semiconductor display device according to any one of (5) to (7).
• the semiconductor display device (Ten) formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
• the first substrate includes the display element and the first transistor,
• the second substrate includes the memory circuit and the comparison circuit,
• the first transistor includes an oxide semiconductor.
• the semiconductor display device (11) a capacitor connected between a drive terminal of the display element and a predetermined voltage; Furthermore, The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
• the semiconductor display device according to (9) or (10).
• the pixel circuit is a level shift circuit connected to the comparison circuit and controlling the voltage of the input signal;
• the semiconductor display device formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
• the first substrate includes the display element, the first transistor, and the second transistor,
• the second substrate includes the memory circuit, the comparison circuit, and the level shift circuit, and the first transistor and the second transistor include an oxide semiconductor.
• the semiconductor display device according to (13).
• the semiconductor display device (15) a capacitor connected between a drive terminal of the display element and a predetermined voltage; Furthermore, The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
• the semiconductor display device according to (13) or (14).
• the pixel circuit is a circuit that constitutes a reflective pixel, the display element is a liquid crystal; Spatial phase modulator.
• the pitch of the pixel circuit is 3.6 um or less, The spatial phase modulation device according to (16).
• 1 Semiconductor display device, 10: Pixel array, 100: Pixel circuit, 102: Memory circuit, 104: Comparison circuit, 106: Level shift circuit, Tr1, Tr2, Tr3, Tr4: transistor, C: Capacitor, R: Resistance Pm: Phase modulation element, L: light emitting element, 12: Control circuit, 14: Vertical drive circuit, 140: 1st signal line, 16: Horizontal drive circuit, 160: 2nd signal line, 200: counter, 3: Laser processing equipment, 300: Light source, 302, 304: mirror, 306: Optical system, 308: Light collecting section, 310: Support part, 4: Optical computing equipment, 400: light source, 402: Light valve, 404: Detection unit, 50: 1st board, 52: 2nd board

Landscapes

• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Theoretical Computer Science (AREA)
• Chemical & Material Sciences (AREA)
• Crystallography & Structural Chemistry (AREA)
• Nonlinear Science (AREA)
• Mathematical Physics (AREA)
• Optics & Photonics (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (1)

Family

ID=88834989

Family Applications (1)

Country Status (2)

Citations (9)

• 2023
  • 2023-04-18 JP JP2024521619A patent/JPWO2023223745A1/ja active Pending
  • 2023-04-18 WO PCT/JP2023/015455 patent/WO2023223745A1/ja not_active Ceased

Patent Citations (9)

Also Published As

Similar Documents

Legal Events