WO2023221364A1 - 测试电路、显示面板及显示装置 - Google Patents

测试电路、显示面板及显示装置 Download PDF

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Publication number
WO2023221364A1
WO2023221364A1 PCT/CN2022/122428 CN2022122428W WO2023221364A1 WO 2023221364 A1 WO2023221364 A1 WO 2023221364A1 CN 2022122428 W CN2022122428 W CN 2022122428W WO 2023221364 A1 WO2023221364 A1 WO 2023221364A1
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WIPO (PCT)
Prior art keywords
conductor
electrostatic discharge
wire
signal line
substrate
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PCT/CN2022/122428
Other languages
English (en)
French (fr)
Inventor
金玉
徐磊
顾维杰
周至奕
颜玥
王青青
Original Assignee
昆山国显光电有限公司
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Publication of WO2023221364A1 publication Critical patent/WO2023221364A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • This application relates to the field of display, and specifically to a test circuit, a display panel and a display device.
  • a display panel with a traditional structure usually includes a display area and a non-display area located around the display area.
  • a multi-layer circuit structure is provided in display technology.
  • the multi-layer circuit structure will cause the display panel to have poor resistance to electrostatic damage.
  • Embodiments of the present application provide a test circuit, a display panel and a display device, aiming to improve the yield rate of the display panel.
  • the display panel includes: a substrate; a first conductor layer disposed on the substrate, the first conductor layer including a first conductor extending along a first direction; a second conductor layer located on The side of the first conductor layer facing away from the substrate, the second conductor layer including a second conductor extending along the second direction, the second conductor including an overlapping section, the orthographic projection of the overlapping section on the substrate and the first conductor layer on the substrate.
  • the orthographic projections are overlapped and arranged; the electrostatic discharge part is arranged on at least one side of the overlapping section in the second direction, and the electrostatic discharge part is used to discharge the static electricity of the second conductor.
  • the electrostatic discharge part includes a release wire
  • the release wire includes a main body and an electrostatic discharge end disposed at one end of the main body, and the orthographic projection of at least part of the electrostatic discharge end on the substrate is in line with the second conductor.
  • the orthographic projections on the substrate are arranged to at least partially overlap.
  • the release conductor and the second conductor are insulated or connected through a via hole.
  • the release wire is provided on the first wire layer.
  • the number of electrostatic discharge terminals is multiple, and the plurality of electrostatic discharge terminals are arranged side by side and spaced apart along the second direction and connected to the main body, and the orthographic projection of each electrostatic discharge terminal on the substrate is respectively The orthographic projection of the second conductor on the substrate is at least partially overlapped.
  • the extension width of the electrostatic discharge end in the second direction gradually decreases along the direction away from the main body part.
  • the electrostatic discharge part further includes a discharge capacitor
  • the discharge capacitor includes a first electrode plate and a second electrode plate that are stacked along the thickness direction of the substrate, and the first electrode plate and the second electrode plate are stacked along the thickness direction of the substrate.
  • One of the plates is electrically connected to the release wire.
  • the first electrode plate and the release wire are both located on the first wire layer and connected to each other.
  • the second electrode plate is located on the third conductive layer, and the third conductive layer is located between the first conductive layer and the second conductive layer.
  • the electrostatic discharge ends of the at least two release wires are located on both sides of the overlapping section in the second direction, and the first electrode plate is connected to the overlapping section. Between the discharge conductors where the electrostatic discharge ends are located on both sides of the second direction.
  • the overlapping area of the orthographic projections of the first electrode plate and the second electrode plate on the substrate is greater than or equal to the overlap of the orthographic projections of the overlapping section and the first conductor on the substrate. area.
  • the number of second conductors is multiple, the overlapping sections of the plurality of second conductors are arranged at intervals along the first direction, and the overlapping sections of each second conductor are arranged in the second direction. At least one side of the device is provided with an electrostatic discharge part.
  • the discharge capacitors of the plurality of electrostatic discharge parts are connected in parallel with each other.
  • the second plates of the discharge capacitors of the plurality of electrostatic discharge parts are connected in parallel to each other.
  • the test circuit further includes a power line, and the second plate is connected to the power line.
  • the overlapping area of the orthographic projection of the overlapping section and the first conductor on the substrate is greater than or equal to 450 ⁇ m 2 .
  • the line width of the first conductive line is greater than or equal to 30 ⁇ m, and the line width of the second conductive line is greater than or equal to 15 ⁇ m.
  • the electrostatic discharge part includes a transistor, the transistor includes a source, a drain and a gate, and the drain and the gate are connected to each other;
  • the test circuit also includes a power supply signal line, one of the source electrode and the drain electrode of the transistor is electrically connected to the second conductor, and the other is electrically connected to the power supply signal line.
  • the power signal line includes a first signal line
  • the source is electrically connected to the second conductor
  • the drain is electrically connected to the first signal line
  • the voltage on the second conductor is greater than V Gh + n
  • the power signal line includes a second signal line
  • the source is electrically connected to the second signal line
  • the drain is electrically connected to the second conductor
  • the voltage on the second conductor is less than V GL - m
  • more than two transistors are connected between the second conductor and the power signal line.
  • the source electrode and the drain electrode are located on the second conductor layer.
  • the gate electrode is located on the first conductor layer.
  • it also includes a chip bonding pad and a test pad, and at least part of the second wire is connected between the chip bonding pad and the test pad;
  • At least one electrostatic discharge portion is located on a side of the overlapping section of the chip pad away from the second conductor to which it is connected, and/or, at least one electrostatic releasing section is located between the overlapping section and the test pad.
  • a second aspect embodiment of the present application also provides a display panel, including the test circuit of any of the above-mentioned first aspect embodiments.
  • the display panel includes a display area and a cutting area, and at least part of the test circuit is located in the display area or the cutting area.
  • At least part of the first conductor is located in the cutting area.
  • At least part of the electrostatic discharge portion is located in the cutting area.
  • the first wire is a detection wire and is used to transmit data control signals.
  • the second conductor includes a clock conductor.
  • a second embodiment of the present application further provides a display device, which is prepared and formed from the display panel of any of the above-mentioned first embodiments.
  • the test circuit includes a substrate, a first conductor layer, a second conductor layer and an electrostatic discharge part provided on the substrate.
  • the first conductor layer includes a first conductor
  • the second conductor layer includes a second conductor. Since the first conductor and the second conductor extend in different directions, the overlapping section of the second conductor at least partially overlaps the first conductor.
  • the second conductive layer is located on the side of the first conductive layer facing away from the substrate. During the preparation process of the second conductive layer, since the second conductive layer is exposed to the air, static electricity is easily generated on the second conductive layer.
  • an electrostatic discharge part is provided on at least one side of the overlapping section in the second direction.
  • the electrostatic releasing part can release static electricity on the second conductor, thereby improving the conduction of static electricity to the breakdown of the overlapping section.
  • Figure 1 shows a schematic top view of a display panel according to an embodiment of the present application
  • Figure 2 is a partial enlarged view of the Q area in Figure 1 in an example
  • Figure 3 is a partial cross-sectional view taken at F-F in Figure 2;
  • Figure 4 is a partial enlarged structural diagram of the P area in Figure 2;
  • Figure 5 is a partial enlarged structural schematic diagram of position P in Figure 2 in another embodiment
  • Figure 6 is a partial enlarged structural schematic diagram of position P in Figure 2 in yet another embodiment
  • Figure 7 is a partial enlarged structural diagram of Q in Figure 1 in yet another embodiment
  • Figure 8 is a partial enlarged structural diagram of position I in Figure 7;
  • Figure 9 is a partial enlarged structural schematic diagram of position I in another embodiment of Figure 7;
  • Figure 10 is a partially enlarged structural schematic diagram of position I in Figure 7 in yet another embodiment
  • Figure 11 is a partial enlarged structural schematic diagram of position I in Figure 7 in yet another embodiment
  • Second conductor layer 31. Second conductor; 311. Overlapping section;
  • Electrostatic discharge part 41. Release wire; 411. Electrostatic discharge terminal; 412. Main body part; 42. Release capacitor; 421. First plate; 422. Second plate; 43. Transistor; 431. Source; 432. Drain; 433. Gate;
  • Test pad
  • Chip pad
  • AA display area
  • NA non-display area
  • GP chip pad area
  • CA cutting area
  • LA wiring area
  • CP test pad area
  • X first direction
  • Y second direction
  • Z thickness direction
  • the lighting test (Cell Test; CT) circuit will be arranged on the display device's integrated circuit (IC) pin on the side away from the display area. After the CT test, the CT circuit will be removed by secondary cutting.
  • the scan control signal line (such as the clock signal line) will overlap with the detection wire included in the CT circuit, which results in the formation of parasitic capacitance between the scan control signal line and the detection wire.
  • the detection wires include, for example, a red test line for testing red sub-pixels, a green test line for testing green sub-pixels, and a blue test line for testing blue sub-pixels.
  • the scan control signal line is located above the detection wire, that is, the scan control signal is prepared after the detection wire is prepared. Moreover, the scan control signal line will be exposed to the air for a period of time during the manufacturing process, which causes static electricity to easily accumulate on the scan control signal line. The static electricity will charge the parasitic capacitance formed between the scan control signal line and the detection wire.
  • An embodiment of the present application provides a display panel, which may be an organic light emitting diode (OLED) display panel.
  • a display panel which may be an organic light emitting diode (OLED) display panel.
  • Figure 1 shows a top view of the display panel 100 according to an embodiment of the present application.
  • Figure 2 shows an example of a partial enlarged view of the Q area in Figure 1.
  • Figure 3 is The cross-sectional view at F-F in Figure 2.
  • the display panel 100 provided by the embodiment of the present application includes a test circuit 100a.
  • the test circuit 100a provided by the embodiment of the present application for the display panel 100 includes: a substrate 10, a first conductor layer 20, and a second conductor layer 30. and the electrostatic discharge part 40; the first conductor layer 20 is provided on the substrate 10, and the first conductor layer 20 includes a first conductor 21 extending in the first direction; the second conductor layer 30 is located on the side of the first conductor layer 20 away from the substrate 10 , the second conductor layer 30 includes a second conductor 31 extending along the second direction, the second conductor 31 includes an overlapping section 311, the orthographic projection of the overlapping section 311 on the substrate 10 and the orthographic projection of the first conductor layer 20 on the substrate 10 The orthographic projections are overlapped; the electrostatic discharge part 40 is provided on at least one side of the overlapping section 311 in the second direction, and the electrostatic discharge part 40 is used to discharge the static electricity of the second conductor 31 .
  • the display panel 100 includes a substrate 10 and a first conductor layer 20, a second conductor layer 30 and an electrostatic discharge part 40 provided on the substrate 10.
  • the first conductor layer 20 includes the first conductor 21
  • the second conductor layer 30 includes the second conductor 31 . Since the first conductor 21 and the second conductor 31 extend in different directions, the overlapping section 311 of the second conductor 31 and the first conductor 31 overlap. The conductors 21 at least partially overlap.
  • the second conductive layer 30 is located on the side of the first conductive layer 20 away from the substrate 10.
  • an electrostatic discharge part 40 is provided on at least one side of the overlapping section 311 in the second direction.
  • the electrostatic discharge part 40 can discharge static electricity on the second conductor 31, thereby improving electrostatic conduction.
  • the overlapping section 311 breaks down the first conductor 21 .
  • the substrate 10 includes a substrate.
  • the substrate can be made of glass, polyimide (PI) or other light-transmitting materials.
  • the substrate 10 may also include a support layer located on the side of the substrate away from the first conductor layer 20 , and the support layer may include a steel plate layer and/or a foam layer.
  • a layer structure such as a buffer layer may also be provided between the substrate and the first conductive layer 20 .
  • the first conductor 21 can be arranged in various ways.
  • the first conductor 21 is the above-mentioned detection conductor CT.
  • the second conductive line 31 can be arranged in various ways.
  • the second conductive line 31 is the above-mentioned scanning control signal line GIP.
  • the static electricity on the scan control signal line GIP can be released through the electrostatic discharge part 40, which can reduce the amount of static electricity transferred to the overlapping section 311, thereby improving the problem of breakdown of the detection wire CT.
  • the detection wire CT includes a first detection wire CT-R, a second detection wire CT-G and a third detection wire CT-B. At least part of the first detection wire CT-R, the second detection wire CT-G and the third detection wire CT-B all extend along the first direction, and the parts of the first detection wire CT-R and the second detection wire extending along the first direction
  • the detection wire CT-G and the third detection wire CT-B are arranged side by side along the second direction.
  • the second conductor 31 includes overlapping sections 311 respectively overlapping the first detection conductor CT-R, the second detection conductor CT-G and the third detection conductor CT-B, and the electrostatic discharge part 40 is located on all overlapping sections. At least one side of the segment 311 in the second direction to reduce the transmission to any overlapping segment 311 and breakdown any of the first detection wire CT-R, the second detection wire CT-G and the third detection wire CT-B. one's risk.
  • the scan control signal line GIP includes a first signal line ECK1, a second signal line ECK2, a third signal line SIN, a fourth signal line SCK1, and a fifth signal line SCK2. At least part of the first signal line ECK1, the second signal line ECK1, and the fifth signal line SCK2.
  • the signal line ECK2, the third signal line SIN, the fourth signal line SCK1 and the fifth signal line SCK2 extend along the second direction, and the portions of the first signal line ECK1, the second signal line ECK2 and the third signal line extending along the second direction
  • the line SIN, the fourth signal line SCK1 and the fifth signal line SCK2 are arranged side by side along the first direction, and each of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1 and the fifth signal line Overlapping sections 311 are provided on SCK2, and the overlapping sections 311 of each of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1 and the fifth signal line SCK2 are in the second direction.
  • An electrostatic discharge part 40 is provided on at least one side of each of the two sides.
  • an insulating layer is provided between the first conductor layer 20 and the second conductor layer 30 to ensure the insulation between the first conductor 21 and the second conductor 31 and to avoid short-circuit connection between the first conductor 21 and the second conductor 31 .
  • the display panel 100 further includes a display area AA and a non-display area NA surrounding the display area AA.
  • the first conductive line 21 and the overlapping section 311 are both located in the non-display area NA.
  • Figure 4 is a partially enlarged structural diagram of the P area in Figure 2.
  • the electrostatic discharge part 40 includes a release wire 41 .
  • the release wire 41 includes a main body 412 and an electrostatic discharge end 411 disposed at one end of the main body 412 , and at least partially The orthographic projection of the electrostatic discharge end 411 on the substrate 100 and the orthographic projection of the second conductor 31 on the substrate 100 are at least partially overlapped.
  • the electrostatic discharge end 411 of the release wire 41 and the orthographic projection of the second conductor 31 are at least partially overlapped, so that static electricity can be conducted to the electrostatic discharge end 411 and the static electricity can be released through the electrostatic discharge end 411 .
  • the installation method of the electrostatic discharge part 40 is simple, and the preparation of the electrostatic discharge part 40 is convenient.
  • release wire 41 and the second wire 31 There are many ways to connect the release wire 41 and the second wire 31.
  • an insulation layer is provided between the release wire 41 and the second wire 31.
  • the release wire 41 and the second wire 31 can be insulated from each other and form a parasitic Capacitor settings.
  • an insulation layer is provided between the release wire 41 and the second wire 31, and an opening is provided on the insulation layer, and the release wire 41 and the second wire 31 are connected through a via hole, that is, The release wire 41 and the second wire 31 are electrically connected, so that the static electricity on the second wire 31 can be directly conducted to the release wire 41 and the static electricity can be released through the release wire 41 .
  • the release wire 41 can be arranged on the same layer as the first wire 21, that is, the release wire 41 is located on the first wire layer 20, so that the release wire 41 can be connected to the first wire 21. Synchronous preparation can simplify the preparation method of the display template and improve the preparation efficiency of the test circuit 100a. In other optional embodiments, the release wire 41 and the first wire 21 can also be arranged in different layers.
  • each discharge wire 41 can include one electrostatic discharge end 411.
  • FIG. 5 is a partially enlarged structural schematic diagram of position P in FIG. 2 in another embodiment.
  • the number of electrostatic discharge ends 411 is multiple, and the plurality of electrostatic discharge ends 411 are arranged side by side and spaced apart along the second direction and connected to the main body 412,
  • the orthographic projection of each electrostatic discharge terminal 411 on the substrate 100 is at least partially overlapped with the orthographic projection of the second conductor 31 on the substrate 100 .
  • FIG. 6 is a partially enlarged structural diagram of position P in FIG. 2 in yet another embodiment.
  • the extension width of the electrostatic discharge end 411 in the second direction gradually decreases along the direction away from the main body portion 412 .
  • the electrostatic discharge capability of the electrostatic discharge end 411 can be further improved.
  • the electrostatic discharge part 40 further includes a discharge capacitor 42 .
  • the discharge capacitor 42 includes a first electrode plate 421 and a second electrode plate 422 that are stacked along the thickness direction of the substrate 10 . And one of the first electrode plate 421 and the second electrode plate 422 is electrically connected to the release wire 41 .
  • the release wire 41 is connected to the first plate 421 or the second plate 422 of the discharge capacitor 42, so that static electricity can be conducted by the release wire 41 and stored to the release capacitor 42, which can improve the electrostatic discharge part. 40% electrostatic discharge capability.
  • the first electrode plate 421 and the second electrode plate 422 can be arranged in various positions.
  • the first electrode plate 421 and the release wire 41 are both located on the first conductor layer 20 and are electrically connected. Such an arrangement enables the first plate 421, the release wire 41 and the first wire 21 to be prepared and formed in the same process step, which can effectively improve the preparation efficiency of the test circuit 100a.
  • the second electrode plate 422 is located on the third conductive layer 50 , and the third conductive layer 50 is located between the first conductive layer 20 and the second conductive layer 30 . That is, the second electrode plate 422 is located on the side of the third conductor layer 50 facing the substrate 10.
  • the second electrode plate 422 can be prevented from being exposed to the air. , thereby preventing static electricity from accumulating on the second plate 422 , so that the discharge capacitor 42 can store more static electricity accumulated on the second conductor 31 .
  • the third conductor layer 50 may also be located between the first conductor layer 20 and the substrate 10 .
  • a first insulation layer is provided between the first conductor layer 20 and the third conductor layer 50
  • a second insulating layer is provided between the third conductor layer 50 and the second conductor layer 30 to ensure that the first conductor 21 , the first electrode plate 421, the second conductor 31 and the second electrode plate 422 are insulated from each other.
  • release wires 41 are provided on both sides of the overlapping section 311 in the second direction, thereby reducing the conduction of static electricity generated on both sides of the overlapping section 311 in the second direction to the overlapping section 311 This position further improves the electrostatic discharge capability of the electrostatic discharge part 40 and improves the problem of the first conductor 21 being broken down.
  • the first electrode plate 421 is connected between the two electrostatic discharge ends 411 located on both sides of the overlapping section 311 in the second direction and between the release wires 41 .
  • This allows the static electricity generated on both sides of the overlapping section 311 in the second direction to be conducted to the discharge capacitor 42 , further improving the electrostatic discharge capability of the electrostatic discharge part 40 and better improving the problem of breakdown of the first conductor 21 .
  • the overlapping area of the orthographic projection of the overlapping section 311 and the first wire 21 on the substrate 10 is greater than or equal to 450 ⁇ m 2 .
  • the overlapping area of the orthographic projection of the overlapping section 311 and the first conductive line 21 on the substrate 10 is 15 ⁇ m ⁇ 30 ⁇ m; or the overlapping area of the orthographic projection of the overlapping section 311 and the first conductive line 21 on the substrate 10 is 15 ⁇ m ⁇ 45 ⁇ m; or the overlapping area of the orthographic projection of the overlapping section 311 and the first conductor 21 on the substrate 10 is 15 ⁇ m ⁇ 60 ⁇ m.
  • the line width of the first conductive line 21 is greater than 30 ⁇ m.
  • the line width of the second conductor 31 is usually 15 ⁇ m.
  • the line width of the first conductor 21 is greater than 30 ⁇ m, it can be ensured that the overlapping area of the orthographic projection of the overlapping section 311 and the first conductor 21 on the substrate 10 is greater than or equal to 450 ⁇ m 2 , less prone to breakdown.
  • the line width of the second conductive line 31 is greater than or equal to 15 ⁇ m.
  • the overlapping area of the orthographic projection of the first electrode plate 421 and the second electrode plate 422 on the substrate 10 is greater than or equal to the orthographic projection of the overlapping section 311 and the first conductor 21 on the substrate 10 of overlapping area.
  • Making the capacitance of the discharge capacitor 42 larger than the capacitance of the parasitic capacitance formed by the overlapping section 311 and the first conductor 21 can further reduce the load on the parasitic capacitance, thereby improving the problem of the first conductor 21 being broken down.
  • the number of the second conductive wires 31 There are many ways to set the number of the second conductive wires 31. For example, there may be only one second conductive wire 31.
  • the number of the second conductive lines 31 is multiple.
  • the second conductive lines 31 may include the first signal line ECK1, the second signal line ECK2, the third signal line SIN, The fourth signal line SCK1 and the fifth signal line SCK2.
  • the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2 each include an overlapping section 311, and the first signal line ECK1, the second signal line ECK2, and the fifth signal line SCK2
  • the overlapping sections 311 of the three signal lines SIN, the fourth signal line SCK1 and the fifth signal line SCK2 are spaced apart along the first direction. That is, the overlapping sections 311 of the plurality of second conductive wires 31 are spaced apart along the first direction, and the overlapping sections 311 of each second conductive wire 31 are provided with electrostatic discharge portions 40 on at least one side in the second direction.
  • each second conductor 31 there are multiple second conductors 31 , and the second conductors 31 all overlap with the first conductors 21 to form overlapping sections 311 , and the overlapping sections 311 of each second conductor 31 are respectively connected with the first conductors 31 .
  • Different positions of the conductors 21 overlap, and there is a risk of breakdown by parasitic capacitance at different positions of the first conductor 21 .
  • each overlapping section 311 is provided with an electrostatic discharge portion 40 on at least one side in the second direction, which can reduce the risk of breakdown at different locations on the first conductor 21 .
  • the second plates 422 of the discharge capacitors 42 of the multiple electrostatic discharge parts 40 are connected in parallel with each other. This allows static electricity on different second electrode plates 422 to be conducted to each other, further improving the electrostatic discharge capability of the electrostatic discharge part 40 .
  • the test circuit 100a further includes a power line Vdd, and the second plate 422 is connected to the power line.
  • the power line has the characteristic of signal stability, which makes the signal on the release capacitor 42 stable and avoids the disturbance caused by the unstable signal of the release capacitor 42 .
  • Figure 7 is a partially enlarged structural schematic diagram of Q in Figure 1 in yet another embodiment.
  • Figure 8 is a partially enlarged structural schematic diagram of I in Figure 7.
  • Figure 9 is a diagram 7. A partial enlarged structural diagram of position I in another embodiment.
  • the electrostatic discharge part 40 includes a transistor 43 , the transistor 43 includes a source 431 , a drain 432 and a gate 433 , and the drain 432 and the gate 433 interconnected; the test circuit 100a also includes a power signal line 60 , one of the source 431 and the drain 432 of the transistor 43 is electrically connected to the second conductor 31 , and the other is electrically connected to the power signal line 60 .
  • the static electricity on the second wire 31 can be conducted to the power signal line 60 through the transistor 43 .
  • the type of transistor 43 may be an N-type transistor or a P-type transistor. In the embodiment of the present application, the transistor 43 is a P-type transistor for illustration.
  • the power signal line 60 can be a first signal line 61
  • the source 431 is electrically connected to the second wire 31
  • the drain 432 is electrically connected to the first signal line 61. connect.
  • the power signal line 60 can be a first signal line 61
  • the source 431 is electrically connected to the second wire 31
  • the drain 432 is electrically connected to the first signal line 61. connect.
  • V Gh is the voltage on the first signal line 61 , for example, the first signal line 61 is a high-level signal line, V Gh is 7V, and V Th is the turn-on voltage of the source 431 and drain 432 of the transistor 43 .
  • the voltage V 31 on the second conductor 31 can be limited to a suitable voltage value. under.
  • the power signal line 60 may be a second signal line 62
  • the source 431 is electrically connected to the second signal line 62
  • the drain 432 is electrically connected to the second conductor 31 .
  • V 31 on the second conductor 31 is less than V GL -m
  • the voltage V 31 on the second conductor 31 can be limited to a suitable voltage value. above.
  • Figure 10 is a partially enlarged structural diagram of position I in Figure 7 in yet another embodiment.
  • the power signal line 60 may include either a first signal line 61 or a second signal line 62 .
  • the static electricity can be conducted to the first signal line 61
  • the holes on the second signal line 62 can be conducted to the second conductor 31 and neutralize the static electricity on the second conductor 31 to reduce the static electricity.
  • the electrostatic voltage on the second wire 31 is greater than or equal to V GL -
  • more than two transistors 43 are connected between the second conductor 31 and the power signal line 60 .
  • two transistors 43 are provided between the second conductor 31 and the second signal line 62, and two transistors 43 are disposed between the second conductor 31 and the first signal line 61.
  • the electrostatic voltage on the second conductor 31 is greater than or Equal to V GL -2
  • the electrostatic potential on the second conductor 31 can be limited to a smaller range.
  • the source electrode 431 and the drain electrode 432 are located on the second conductor layer 30, so that the second conductor 31 can be prepared and formed in the same process as the source electrode 431 and the drain electrode 432, and can facilitate the connection between the second conductor 31 and the source electrode. 431 or drain 432 connection.
  • the gate electrode 433 is located on the first conductive line layer 20, so that the gate electrode 433 and the first conductive line 21 can be formed in the same process, which helps to improve the preparation efficiency of the test circuit 100a.
  • the transistor 43 also includes a first semiconductor part
  • the test circuit 100a also includes a driving transistor TFT
  • the driving transistor TFT includes a second semiconductor part
  • the first semiconductor part and the second semiconductor part are arranged on the same layer, so that the first semiconductor part and The second semiconductor part can be manufactured and formed in the same process, which can further improve the manufacturing efficiency of the test circuit 100a.
  • the source electrode 431 and the drain electrode 432 of the driving transistor may be arranged in the same layer as the source electrode 431 and the drain electrode 432 of the transistor 43 .
  • the gate electrode 433 of the driving transistor can be arranged in the same layer as the gate electrode 433 of the transistor 43, which can further improve the preparation efficiency of the test circuit 100a.
  • the test circuit 100a further includes a chip pad 80 and a test pad 70, and at least part of the second wire 31 is connected between the chip pad 80 and the test pad 70.
  • At least one electrostatic discharging part 40 is located on a side of the chip pad 80 away from the overlapping section of the second wire 31 to which it is connected, so as to discharge the static electricity generated on the chip pad 80 .
  • At least one electrostatic discharge portion 40 is located between the overlapping section 311 and the test pad 70 .
  • the static electricity generated by the test pad 70 can be released, and the amount of static electricity conducted from the test pad 70 to the overlapping section 311 can be reduced.
  • At least one electrostatic discharge portion 40 is located between the overlapping section 311 and the chip pad 80 , which can reduce the amount of static electricity conducted from the chip pad 80 to the overlapping section 311 .
  • the non-display area NA includes the chip pad area GP, the cutting area CA, the wiring area LA and the test pad area CP which are arranged in sequence.
  • the chip pad 80 is located in the pad area GA
  • the first wire 21 is located in the wiring area LA
  • the test pad 70 is located in the test pad area CP.
  • the display panel 100 further includes a cutting area CA, and at least part of the test circuit 100a is located in the cutting area CA.
  • the test circuit 100a can be cut and removed. The area of the non-display area of the display device can be reduced and the narrow frame design of the display device can be realized.
  • the electrostatic discharge part 40 is located in the cutting area CA.
  • the electrostatic discharge portion 40 can be cut and removed, thereby reducing the area of the non-display area of the display device and achieving a narrow frame design of the display device.
  • the display panel 100 may be a display motherboard including a plurality of display areas AA, and the display motherboard includes the above-mentioned cutting area CA.
  • the above-mentioned electrostatic discharge part 40 may be cut, that is, the display panel for preparing a display screen may not include the electrostatic discharge part 40 .
  • the display panel 100 may also be a display panel used to prepare a display screen, that is, the display panel 100 does not include the cutting area CA, and the electrostatic discharge part 40 may also be located in the non-cutting area of the display panel 100 , that is, the electrostatic discharge part 40 may be a display panel used to prepare a display screen.
  • the first wire 21 is located in the cutting area CA.
  • the first wire 21 can be cut and removed, thereby reducing the area of the non-display area of the display device and achieving a narrow frame design of the display device.
  • the first wire 21 may be a detection wire and used to transmit control signals.
  • the first wire 21 is used to perform a lighting test on the display device before cutting to form the display device.
  • the first conductive wire 21 is not needed during use of the display device, so the first conductive wire 21 can be located in the cutting area CA.
  • An embodiment of the present invention also provides a display device.
  • the display device includes the display panel according to any one of the above first aspect embodiments. Therefore, the display device provided by the second aspect embodiment of the present invention has the display panel according to any one of the above first aspect embodiments. The beneficial effects will not be repeated here.
  • Display devices in embodiments of the present invention include but are not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control, smart landline phones, consoles and other devices with display functions. .
  • PDAs personal digital assistants
  • tablet computers e-books
  • televisions access control
  • smart landline phones consoles and other devices with display functions.

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Abstract

一种测试电路(100a)、显示面板(100)及显示装置，测试电路(100a)包括：基板(10)；第一导线层(20)，设置于基板(10)，第一导线层(20)包括沿第一方向延伸的第一导线(21)；第二导线层(30)，位于第一导线层(20)背离基板的一侧，第二导线层(30)包括沿第二方向延伸的第二导线(31)，第二导线(31)包括交叠段(311)，交叠段(311)在基板(10)上的正投影和第一导线层在基板上的正投影至少部分交叠设置；静电释放部(40)，设置于交叠段(311)在第二方向的至少一侧，静电释放部(40)用于释放第二导线(31)的静电。在测试电路(100a)中，在交叠段(311)在第二方向上的至少一侧设置静电释放部(40)，静电释放部(40)能够释放第二导线(31)上的静电，从而改善静电传导至交叠段(311)击穿第一导线(21)的问题。

Description

测试电路、显示面板及显示装置
本申请要求于2022年05月20日提交中国专利局、申请号为202210549077.9、申请名称为“测试电路、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示领域，具体涉及一种测试电路、显示面板及显示装置。
背景技术
随着显示面板技术的不断更新，小尺寸显示面板正逐渐朝着轻薄化、高屏占比、超窄边框甚至无边框化发展。传统结构的显示面板通常包括显示区域及位于显示区域周侧的非显示区域。显示技术中为了减小非显示区域的尺寸，会设置多层电路结构。但是多层电路结构会导致显示面板抗静电击伤能力差，层叠设置的两个导线之间会存在电容，静电可能会通过该电容将导线击穿，从而导致显示面板的良率较低。
发明内容
本申请实施例提供一种测试电路、显示面板及显示装置，旨在提高显示面板的良率。
本申请第一方面的实施例提供一种测试电路，显示面板包括：基板；第一导线层，设置于基板，第一导线层包括沿第一方向延伸的第一导线；第二导线层，位于第一导线层背离基板的一侧，第二导线层包括沿第二方向延伸的第二导线，第二导线包括交叠段，交叠段在基板上的正投影和第一导线层在基板上的正投影交叠设置；静电释放部，设置于交叠段在第二方向的至少一侧，静电释放部用于释放第二导线的静电。
根据本申请第一方面的实施方式，静电释放部包括释放导线，释放导线包括主体部和设置于主体部一端的静电释放端，且至少部分静电释放端在基板上的正投影与第二导线在基板上的正投影至少部分交叠设置。
根据本申请第一方面前述任一实施方式，释放导线和第二导线绝缘设置或者释放导线和第二导线过孔连接。
根据本申请第一方面前述任一实施方式，释放导线设置于第一导线层。
根据本申请第一方面前述任一实施方式，静电释放端的个数为多个，多个静电释放端沿第二方向并 排间隔设置并连接于主体部，各静电释放端在基板上的正投影分别与第二导线在基板上的正投影至少部分交叠设置。
根据本申请第一方面前述任一实施方式，沿远离主体部的方向，静电释放端在第二方向上的延伸宽度逐渐减小。
根据本申请第一方面前述任一实施方式，静电释放部还包括释放电容，释放电容包括沿基板的厚度方向层叠设置的第一极板和第二极板，且第一极板和第二极板中的一者与释放导线电连接。
根据本申请第一方面前述任一实施方式，第一极板和释放导线均位于第一导线层并相互连接。
根据本申请第一方面前述任一实施方式，第二极板位于第三导线层，第三导线层位于第一导线层和第二导线层之间。
根据本申请第一方面前述任一实施方式，释放导线至少为两个，至少两个释放导线的静电释放端位于交叠段在第二方向的两侧，第一极板连接于位于交叠段在第二方向两侧的静电释放端所在的释放导线之间。
根据本申请第一方面前述任一实施方式，第一极板和第二极板在基板上的正投影的交叠面积大于或等于交叠段和第一导线在基板上的正投影的交叠面积。
根据本申请第一方面前述任一实施方式，第二导线的个数为多个，多个第二导线的交叠段沿第一方向间隔设置，各第二导线的交叠段在第二方向的至少一侧均设置有静电释放部。
根据本申请第一方面前述任一实施方式，多个静电释放部的释放电容相互并联连接。
根据本申请第一方面前述任一实施方式，多个静电释放部的释放电容的第二极板相互并联连接。
根据本申请第一方面前述任一实施方式，测试电路还包括电源线，第二极板连接于电源线。
根据本申请第一方面前述任一实施方式，交叠段和第一导线在基板上的正投影的交叠面积大于或等于450μm 2。
根据本申请第一方面前述任一实施方式，第一导线的线宽大于或等于30μm，第二导线的线宽大于或等于15μm。
根据本申请第一方面前述任一实施方式，静电释放部包括晶体管，晶体管包括源极、漏极和栅极，且漏极和栅极相互连通；
测试电路还包括电源信号线，晶体管的源极和漏极中的一者与第二导线电连接，另一者与电源信号线电连接。
根据本申请第一方面前述任一实施方式，电源信号线包括第一信号线，源极和第二导线电连接，漏极和第一信号线电连接，第二导线上的电压大于V Gh+n|V Th|，其中，V Gh为第一信号线上的电压，V Th为晶体管的源极和漏极的导通电压，n为第二导线和第一信号线之间连接的晶体管个数。
根据本申请第一方面前述任一实施方式，电源信号线包括第二信号线，源极和第二信号线电连接，漏极和第二导线电连接，第二导线上的电压小于V GL-m|V Th|，其中，V GL为第二信号线上的电压，V Th为晶体管的源极和漏极的导通电压，m为第二导线和第二信号线之间连接的晶体管个数。
根据本申请第一方面前述任一实施方式，第二导线和电源信号线之间连接有两个以上的晶体管。
根据本申请第一方面前述任一实施方式，源极和漏极位于第二导线层。
根据本申请第一方面前述任一实施方式，栅极位于第一导线层。
根据本申请第一方面前述任一实施方式，还包括芯片焊盘和测试焊盘，至少部分第二导线连接于芯片焊盘和测试焊盘之间；
至少一个静电释放部位于芯片焊盘背离其连接的第二导线上交叠段的一侧，和/或，至少一个静电释放部位于交叠段和测试焊盘之间。
本申请第二方面的实施例还提供一种显示面板，包括上述任一第一方面实施例的测试电路。
根据本申请第二方面的实施方式，显示面板包括显示区和切割区域，至少部分测试电路位于显示区或切割区域。
根据本申请第二方面前述任一实施方式，至少部分所述第一导线位于切割区域。
根据本申请第二方面前述任一实施方式，至少部分所述静电释放部位于切割区域。
根据本申请第二方面前述任一实施方式，第一导线为检测导线并用于传输数据控制信号。
根据本申请第二方面前述任一实施方式，第二导线包括时钟导线。
本申请第二方面的实施例还提供一种显示装置，由上述任一第一方面实施例的显示面板制备成型。
在本申请实施例提供的测试电路中，测试电路包括基板和设置于基板的第一导线层、第二导线层和静电释放部。第一导线层包括第一导线，第二导线层包括第二导线，由于第一导线和第二导线沿不同方向延伸，使得第二导线的交叠段与第一导线至少部分交叠。第二导线层位于第一导线层背离基板的一侧，在第二导线层的制备过程中，由于第二导线层裸露于空气中，第二导线层上极易产生静电。由于第二导线层的交叠段和第一导线层至少部分交叠设置，使得交叠段和第一导线层之间产生寄生电容，静电极易通过交叠段击穿第一导线，从而导致第一导线连接不良。在本申请实施例提供的测试电路中，在交叠段在第二方向上的至少一侧设置静电释放部，静电释放部能够释放第二导线上的静电，从而改善静电传导至交叠段击穿第一导线的问题。
附图说明
通过阅读以下参照附图对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显，其中，相同或相似的附图标记表示相同或相似的特征，附图并未按照实际的比例绘制。
图1示出根据本申请一种实施例的显示面板的俯视示意图；
图2是图1中Q区域在一种示例中的局部放大图；
图3是图2中F-F处的局部剖视图；
图4是图2中P区域的局部放大结构示意图；
图5是另一实施例中图2中P处的局部放大结构示意图；
图6是又一实施例中图2中P处的局部放大结构示意图；
图7是又一实施例中图1中Q处的局部放大结构示意图；
图8是图7中I处的局部放大结构示意图；
图9是图7另一实施例中I处的局部放大结构示意图；
图10是又一实施例中图7中I处的局部放大结构示意图；
图11是还一实施例中图7中I处的局部放大结构示意图；
附图标记说明：
100、显示面板；100a、测试电路；
10、基板；
20、第一导线层；21、第一导线；
30、第二导线层；31、第二导线；311、交叠段；
40、静电释放部；41、释放导线；411、静电释放端；412、主体部；42、释放电容；421、第一极板；422、第二极板；43、晶体管；431、源极；432、漏极；433、栅极；
50、第三导线层；
60、电源信号线；61、第一信号线；62、第二信号线；
70、测试焊盘；
80、芯片焊盘；
AA、显示区；NA、非显示区；GP、芯片焊盘区；CA、切割区域；LA、走线区；CP、测试焊盘区；
X、第一方向；Y、第二方向；Z、厚度方向。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅被配置为解释本申请，并不被配置为限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示 例来提供对本申请更好的理解。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
应当理解，在描述部件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将部件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
随着显示面板技术的不断更新，小尺寸显示面板正逐渐朝着轻薄化、高屏占比、超窄边框甚至无边框化发展。为了缩小显示装置的边框，相关技术中，显示面板上会将点亮测试(Cell Test；CT)电路设置于显示装置的集成电路(integrated circuit，IC)引脚远离显示区的一侧，在完成CT测试后，会选择将CT电路二次切割去除。
当CT电路设置于IC引脚下方时，扫描控制信号线(例如时钟信号线)会与CT电路包括的检测导线交叠，这就导致扫描控制信号线和检测导线之间形成寄生电容。检测导线例如包括用于测试红色子像素的红色测试线、用于测试绿色子像素的绿色测试线和用于测试蓝色子像素的蓝色测试线。
发明人发现，在显示面板的制备过程中，扫描控制信号线位于检测导线的上方，即在制备完检测导线后制备扫描控制信号。且扫描控制信号线在制程中会裸露于空气中一段时间，这就导致扫描控制信号线上极易积累静电，静电会对扫描控制信号线和检测导线之间形成寄生电容进行充电。当寄生电容上的电荷量足够大时，根据ΔV＝ΔQ/C，其中ΔV为扫描控制信号线和检测导线交叠位置的压差，ΔQ为电荷量，C为电容量。当压差较大时极易击穿检测导线，导致扫描控制信号线和检测导线发生微短路，并在后续制程中由于走线短路放热烧焦导致显示装置发生异常屏体无法工作。
发明人进一步研究发现，在检测导线中，尤其是在红色测试线和绿色测试线中，由于红色测试线和绿色测试线的线宽较小，导致寄生电容的极板面积较小，根据ΔV＝ΔQ/C，压差会更大，因此红色测试线和绿色测试线更容易发生击穿。
为解决上述问题，本申请实施例提供了一种测试电路、显示面板及显示装置，以下将结合附图对显示面板及显示装置的各实施例进行说明。
本申请实施例提供一种显示面板，该显示面板可以是有机发光二极管(Organic Light Emitting Diode， OLED)显示面板。
请一并参阅图1至图3，图1示出根据本申请一种实施例的显示面板100的俯视示意图，图2示出一种示例的图1中Q区域的局部放大图，图3是图2中F-F处的剖视图。
如图1至图3所示，本申请实施例提供的显示面板100包括测试电路100a。
测试电路100a的设置方式有多种，请继续参阅图1至图3，本申请实施例提供的用于显示面板100的测试电路100a包括：基板10、第一导线层20、第二导线层30以及静电释放部40；第一导线层20设置于基板10，第一导线层20包括沿第一方向延伸的第一导线21；第二导线层30位于第一导线层20背离基板10的一侧，第二导线层30包括沿第二方向延伸的第二导线31，第二导线31包括交叠段311，交叠段311在基板10上的正投影和第一导线层20在基板10上的正投影交叠设置；静电释放部40设置于交叠段311在第二方向的至少一侧，静电释放部40用于释放第二导线31的静电。
在本申请实施例提供的用于显示面板100的测试电路100a中，显示面板100包括基板10和设置于基板10的第一导线层20、第二导线层30和静电释放部40。第一导线层20包括第一导线21，第二导线层30包括第二导线31，由于第一导线21和第二导线31沿不同方向延伸，使得第二导线31的交叠段311与第一导线21至少部分交叠。第二导线层30位于第一导线层20背离基板10的一侧，在第二导线层30的制备过程中，由于第二导线层30裸露于空气中，第二导线层30上极易产生静电。由于第二导线层30的交叠段311和第一导线层20至少部分交叠设置，使得交叠段311和第一导线层20之间产生寄生电容，静电极易通过交叠段311击穿第一导线21，从而导致第一导线21连接不良。在本申请实施例提供的测试电路100a中，在交叠段311于第二方向上的至少一侧设置静电释放部40，静电释放部40能够释放第二导线31上的静电，从而改善静电传导至交叠段311击穿第一导线21的问题。
基板10的设置方式有多种，可选的，基板10包括衬底，衬底可以采用玻璃、聚酰亚胺(Polyimide，PI)等透光材料制成。基板10还可以包括位于衬底背离第一导线层20一侧的支撑层，支撑层可以包括钢板层和/或泡棉层。衬底和第一导线层20之间还可以设置缓冲层等层结构。
第一导线21的设置方式有多种，例如第一导线21为上述检测导线CT。第二导线31的设置方式有多种，例如第二导线31为上述扫描控制信号线GIP。
在这些可选的实施例中，通过静电释放部40能够释放扫描控制信号线GIP上的静电，能够减少传递至交叠段311的静电量，进而改善检测导线CT被击穿的问题。
可选的，检测导线CT包括第一检测导线CT-R、第二检测导线CT-G和第三检测导线CT-B。至少部分第一检测导线CT-R、第二检测导线CT-G和第三检测导线CT-B均沿第一方向延伸，且沿第一方向延伸的部分第一检测导线CT-R、第二检测导线CT-G和第三检测导线CT-B沿第二方向并排设置。
可选的，第二导线31包括分别与第一检测导线CT-R、第二检测导线CT-G和第三检测导线CT-B交 叠的交叠段311，静电释放部40位于所有交叠段311在第二方向上的至少一侧，以降低传递至任一交叠段311并击穿第一检测导线CT-R、第二检测导线CT-G和第三检测导线CT-B中任一者的风险。
可选的，扫描控制信号线GIP包括第一信号线ECK1、第二信号线ECK2、第三信号线SIN、第四信号线SCK1和第五信号线SCK2，至少部分第一信号线ECK1、第二信号线ECK2、第三信号线SIN、第四信号线SCK1和第五信号线SCK2沿第二方向延伸，且沿第二方向延伸的部分第一信号线ECK1、第二信号线ECK2、第三信号线SIN、第四信号线SCK1和第五信号线SCK2沿第一方向并排设置，各第一信号线ECK1、第二信号线ECK2、第三信号线SIN、第四信号线SCK1和第五信号线SCK2上均设置有交叠段311，且各第一信号线ECK1、第二信号线ECK2、第三信号线SIN、第四信号线SCK1和第五信号线SCK2的交叠段311在第二方向的至少一侧均设置有静电释放部40。
可选的，第一导线层20和第二导线层30之间设置有绝缘层，以保证第一导线21和第二导线31之间的绝缘，避免第一导线21和第二导线31短路连接。
可选的，请继续参阅图1至图3，显示面板100还包括显示区AA和环绕显示区AA的非显示区NA。第一导线21和交叠段311均位于非显示区NA。
请参阅图2至图4，图4是图2中P区域的局部放大结构示意图。
如图2至图4所示，在一些可选的实施例中，静电释放部40包括释放导线41，释放导线41包括主体部412和设置于主体部412一端的静电释放端411，且至少部分静电释放端411在基板100上的正投影与第二导线31在基板100上的正投影至少部分交叠设置。
在这些可选的实施例中，释放导线41的静电释放端411和第二导线31的正投影至少部分交叠设置，使得静电能够传导至静电释放端411，并通过静电释放端411释放静电。且静电释放部40的设置方式简单，便于静电释放部40的制备。
释放导线41和第二导线31之间的连接方式设置有多种，例如释放导线41和第二导线31之间设置有绝缘层，释放导线41和第二导线31之间可以相互绝缘并形成寄生电容设置。
或者，在另一些可选的实施例中，释放导线41和第二导线31之间设置有绝缘层，且绝缘层上设置有开孔，释放导线41和第二导线31通过过孔连接，即释放导线41和第二导线31电连接，使得第二导线31上的静电可以直接传导至释放导线41并通过释放导线41释放静电。
释放导线41的层位置设置方式有多种，可选的，释放导线41可以与第一导线21同层设置，即释放导线41位于第一导线层20，使得释放导线41可以与第一导线21同步制备，能够简化显示模板的制备方法，提高测试电路100a的制备效率。在另一些可选的实施例中，释放导线41和第一导线21也可以不同层设置。
静电释放端411的设置方式有多种，如图4所示，各释放导线41可以包括一个静电释放端411。
在另一些可选的实施例中，请一并参阅图2和图5，图5是另一实施例中图2中P处的局部放大结构示意图。
在另一些可选的实施例中，如图2和图5所示，静电释放端411的个数为多个，多个静电释放端411沿第二方向并排间隔设置并连接于主体部412，各静电释放端411在基板100上的正投影分别与第二导线31在基板100上的正投影至少部分交叠设置。
在这些可选的实施例中，通过在主体部412上连接多个静电释放端411，且各静电释放端411均与第二导线31交叠设置，能够提高释放导线41的释放能力，使得释放导线41能够释放更多的静电。
请一并参阅图2和图6，图6是又一实施例中图2中P处的局部放大结构示意图。
在一些可选的实施例中，如图2和图6所示，沿远离主体部412的方向，静电释放端411在第二方向上的延伸宽度逐渐减小。能够进一步提高静电释放端411的静电释放能力。
请继续参阅图2，在一些可选的实施例中，静电释放部40还包括释放电容42，释放电容42包括沿基板10的厚度方向层叠设置的第一极板421和第二极板422，且第一极板421和第二极板422中的一者与释放导线41电连接。
在这些可选的实施例中，释放导线41和释放电容42的第一极板421或第二极板422连接，使得静电能够由释放导线41传导并存储至释放电容42，能够提高静电释放部40的静电释放能力。
第一极板421和第二极板422的设置位置有多种，在一些可选的实施例中，第一极板421和释放导线41均位于第一导线层20并电连接。如此设置使得第一极板421、释放导线41和第一导线21能够在同一工艺步骤中制备成型，能够有效提高测试电路100a的制备效率。
可选的，第二极板422位于第三导线层50，第三导线层50位于第一导线层20和第二导线层30之间。即第二极板422位于第三导线层50朝向基板10的一侧，在测试电路100a的制备过程中，当第二导线层30裸露于空气中时，能够避免第二极板422裸露于空气中，进而避免第二极板422上累积静电，使得释放电容42能够储存更多第二导线31上累积的静电。
在另一些实施例中，第三导线层50也可以位于第一导线层20和基板10之间。
可选的，第一导线层20和第三导线层50之间设置有第一绝缘层，第三导线层50和第二导线层30之间设置有第二绝缘层，以保证第一导线21、第一极板421、第二导线31和第二极板422中两两相互绝缘设置。
在一些可选的实施例中，释放导线41至少为两个，至少两个释放导线41的静电释放端411位于交叠段311在第二方向的两侧。
在这些可选的实施例中，交叠段311在第二方向的两侧均对应设置有释放导线41，因此能够减少交叠段311在第二方向上两侧产生的静电传导至交叠段311所在位置，进一步提高静电释放部40的静电释 放能力，改善第一导线21被击穿的问题。
可选的，第一极板421连接于位于交叠段311在第二方向两侧的两个静电释放端411所在的释放导线41之间。使得交叠段311在第二方向上两侧产生的静电均能够传导至释放电容42，进一步提高静电释放部40的静电释放能力，更好地改善第一导线21被击穿的问题。
在一些可选的实施例中，交叠段311和第一导线21在基板10上的正投影的交叠面积大于或等于450μm 2。例如交叠段311与第一导线21在基板10上的正投影的交叠面积为15μm×30μm；或者交叠段311与第一导线21在基板10上的正投影的交叠面积为15μm×45μm；或者交叠段311与第一导线21在基板10上的正投影的交叠面积为15μm×60μm。在这些可选的实施例中，交叠段311与第一导线21在基板10上的正投影的交叠面积越大，交叠段311与第一导线21之间形成的寄生电容C越大，根据ΔV＝ΔQ/C，交叠段311与第一导线21之间形成的压差越小，越不容易发生击穿。
可选的，第一导线21的线宽大于30μm。第二导线31的线宽通常为15μm，当第一导线21的线宽大于30μm时，能够保证交叠段311和第一导线21在基板10上的正投影的交叠面积大于或等于450μm 2，更不容易发生击穿。可选的，第二导线31的线宽大于或等于15μm。
在一些可选的实施例中，第一极板421和第二极板422在基板10上的正投影的交叠面积大于或等于交叠段311和第一导线21在基板10上的正投影的交叠面积。使得释放电容42的电容量大于交叠段311与第一导线21形成的寄生电容的电容量，能够进一步减小寄生电容处的载荷，进而改善第一导线21被击穿的问题。
第二导线31的个数设置方式有多种，例如第二导线31的设置数量可以只有一个。
在另一些可选的实施例中，第二导线31的个数为多个，例如如上所述，第二导线31可以包括第一信号线ECK1、第二信号线ECK2、第三信号线SIN、第四信号线SCK1和第五信号线SCK2。第一信号线ECK1、第二信号线ECK2、第三信号线SIN、第四信号线SCK1和第五信号线SCK2均包括交叠段311，且第一信号线ECK1、第二信号线ECK2、第三信号线SIN、第四信号线SCK1和第五信号线SCK2的交叠段311沿第一方向间隔设置。即多个第二导线31的交叠段311沿第一方向间隔设置，各第二导线31的交叠段311在第二方向的至少一侧均设置有静电释放部40。
在这些可选的实施例中，第二导线31为多个，且第二导线31均与第一导线21交叠形成交叠段311，各第二导线31的交叠段311分别与第一导线21的不同位置交叠，第一导线21的不同位置存在被寄生电容击穿的风险。在本实施例中，各交叠段311在第二方向的至少一侧均设置有静电释放部40，能够改善第一导线21上不同位置被击穿的风险。
可选的，多个静电释放部40的释放电容42的第二极板422相互并联连接。使得不同第二极板422上的静电能够相互传导，进一步提高静电释放部40的静电释放能力。
在一些可选的实施例中，测试电路100a还包括电源线Vdd，第二极板422连接于电源线。电源线具有信号稳定的特性，使得释放电容42上的信号稳定，能够避免释放电容42信号不稳定带来的扰动。
请一并参阅图1、图7至图9，图7是又一实施例中图1中Q处的局部放大结构示意图，图8是图7中I处的局部放大结构示意图，图9是图7另一实施例中I处的局部放大结构示意图。
在另一些实施例中，如图1、图7至图9所示，静电释放部40包括晶体管43，晶体管43包括源极431、漏极432和栅极433，且漏极432和栅极433相互连通；测试电路100a还包括电源信号线60，晶体管43的源极431和漏极432中的一者与第二导线31电连接，另一者与电源信号线60电连接。
在这些可选的实施例中，当第二导线31上产生静电时，第二导线31上的静电能够通过晶体管43传导至电源信号线60。晶体管43的类型可以为N型晶体管，或者P型晶体管。本申请实施例以晶体管43为P型晶体管进行举例说明。
电源信号线60的设置方式有多种，如图8所示，电源信号线60可以为第一信号线61，源极431和第二导线31电连接，漏极432和第一信号线61电连接。例如当第二导线31和第一信号线61之间连接有n个晶体管43时，如果第二导线31上的电压V 31大于V Gh+n|V Th|，那么n个晶体管43导通，那么第二导线31上的电压会经由n个晶体管43至第一信号线61，因此第二导线31上的电压V 31小于或者等于V Gh+n|V Th|。其中V Gh为第一信号线61上的电压，例如第一信号线61为高电平信号线，V Gh为7V，V Th为晶体管43的源极431和漏极432的导通电压。
在这些可选的实施例中，通过合理设置晶体管43的数量，即通过改变V Gh+n|V Th|中n的数量，可以将第二导线31上的电压V 31限定于合适的电压值之下。
在另一些实施例中，如图9所示，电源信号线60可以为第二信号线62，源极431和第二信号线62电连接，漏极432和第二导线31电连接。
在这些可选的实施例中，当第二导线31和第二信号线62之间连接有m个晶体管43时，如果第二导线31上的电压V 31小于V GL-m|V Th|，那么m个晶体管43导通，那么第二信号线62的电压会经由m个晶体管43至第二导线31，因此第二导线31上的电压V 31大于或等于V GL-m|V Th|，其中V GL为第二信号线62上的电压，例如第二信号线62为低电平信号线，V GL为-7V，V Th为晶体管43的源极431和漏极432的导通电压。
在这些可选的实施例中，通过合理设置晶体管43的数量，即通过改变V GL-m|V Th|中m的数量，可以将第二导线31上的电压V 31限定于合适的电压值之上。
请参阅图7和图10，图10是又一实施例中图7中I处的局部放大结构示意图。
可选的，如图7和图10所示，电源信号线60既可以包括第一信号线61，也可以包括第二信号线62。在这些实施例中，当第二导线31上的静电势能高于第一信号线61时，静电能够传导至第一信号线61， 当第二导线31上的静电低于第一信号线61时，第二信号线62上的空穴能够传导至第二导线31并与第二导线31上的静电中和减少静电。第二导线31上的静电电压大于或等于V GL-|V Th|，并小于或者等于V Gh+|V Th|。
可选的，如图11所示，第二导线31和电源信号线60之间连接有两个以上的晶体管43。例如第二导线31和第二信号线62之间设置有两个晶体管43，第二导线31和第一信号线61之间设置有两个晶体管43，那么第二导线31上的静电电压大于或等于V GL-2|V Th|，并小于或者等于V Gh+2|V Th|。能够将第二导线31上的静电电位限在一个更小的范围之内。
可选的，源极431和漏极432位于第二导线层30，使得第二导线31能够与源极431、漏极432在同一工艺制程中制备成型，并能够便于第二导线31与源极431或漏极432连接。
可选的，栅极433位于第一导线层20，使得栅极433能够与第一导线21在同一工艺制程中制备成型，有助于提高测试电路100a的制备效率。
可选的，晶体管43还包括第一半导体部，测试电路100a还包括驱动晶体管TFT，驱动晶体管TFT包括第二半导体部，第一半导体部和第二半导体部同层设置，使得第一半导体部和第二半导体部能够在同一工艺制程中制备成型，能够进一步提高测试电路100a的制备效率。
可选的，驱动晶体管的源极431和漏极432可以与晶体管43的源极431和漏极432同层设置。驱动晶体管的栅极433可以与晶体管43的栅极433同层设置，能够进一步提高测试电路100a的制备效率。
在一些可选的实施例中，测试电路100a还包括芯片焊盘80和测试焊盘70，至少部分第二导线31连接于芯片焊盘80和测试焊盘70之间。
静电释放部40的设置位置有多种，例如至少一个静电释放部40位于芯片焊盘80背离其连接的第二导线31上交叠段的一侧，以释放芯片焊盘80上产生的静电。
和/或，至少一个静电释放部40位于交叠段311和测试焊盘70之间。能够释放测试焊盘70产生的静电，减少测试焊盘70向交叠段311传导的静电量。
和/或，至少一个静电释放部40位于交叠段311和芯片焊盘80之间，能够减少芯片焊盘80向交叠段311传导的静电量。
可选的，请继续参阅图3，在远离显示区AA的方向，非显示区NA包括依次设置的芯片焊盘区GP、切割区域CA、走线区LA和测试焊盘区CP。芯片焊盘80位于焊盘区GA，第一导线21位于走线区LA，测试焊盘70位于测试焊盘区CP。在对显示面板100进行切割形成显示面板时，可以将走线区LA和测试焊盘区CP切割除去，实现显示面板的窄边框设计。
在一些可选的实施例中，显示面板100还包括切割区域CA，至少部分测试电路100a位于切割区域CA，当对显示面板100进行切割形成显示装置时，能够将至少部分测试电路100a切割除去，能够减小显 示装置非显示区的面积，实现显示装置的窄边框设计。
可选的，静电释放部40位于切割区域CA。当对显示面板100进行切割形成显示装置时，能够将静电释放部40切割除去，能够减小显示装置非显示区的面积，实现显示装置的窄边框设计。
可选的，显示面板100可以为包括多个显示区AA的显示母板，显示母板包括上述的切割区域CA。在对显示母板进行处理以形成用于制备显示屏的显示板时，可以对上述的静电释放部40切割处理，即用于制备显示屏的显示板可以不包括静电释放部40。
可选的，在另一些实施例中，显示面板100还可为用于制备显示屏的显示板，即显示面板100不包括切割区CA，静电释放部40还可以位于显示面板100的非切割区，即静电释放部40可以为用于制备显示屏的显示板。
在一些可选的实施例中，第一导线21位于切割区域CA。当对显示面板100进行切割形成显示装置时，能够将第一导线21切割除去，能够减小显示装置非显示区的面积，实现显示装置的窄边框设计。
如上，第一导线21可以为检测导线并用于传输控制信号，第一导线21用于在切割形成显示装置之前对显示装置进行点亮测试。在显示装置的使用过程中无需第一导线21，因此可以令第一导线21位于切割区域CA。
本发明实施例还提供一种显示装置，显示装置包括上述任一第一方面实施例的显示面板，因此本发明第二方面实施例提供的显示装置具有上述第一方面任一实施例的显示面板具有的有益效果，在此不再赘述。
本发明实施例中的显示装置包括但不限于手机、个人数字助理(Personal Digital Assistant，简称：PDA)、平板电脑、电子书、电视机、门禁、智能固定电话、控制台等具有显示功能的设备。
依照本申请如上文的实施例，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本申请的原理和实际应用，从而使所属技术领域技术人员能很好地利用本申请以及在本申请基础上的修改使用。本申请仅受权利要求书及其全部范围和等效物的限制。

Claims (10)

  1. 一种测试电路，其特征在于，包括：
    基板；
    第一导线层，设置于所述基板，所述第一导线层包括沿第一方向延伸的第一导线；
    第二导线层，位于所述第一导线层背离所述基板的一侧，所述第二导线层包括沿第二方向延伸的第二导线，所述第二导线包括交叠段，所述交叠段在所述基板上的正投影和所述第一导线层在所述基板上的正投影交叠设置；
    静电释放部，设置于所述交叠段在所述第二方向的至少一侧，所述静电释放部用于释放所述第二导线的静电。
  2. 根据权利要求1所述的测试电路，其中，所述静电释放部包括释放导线，所述释放导线包括主体部和设置于所述主体部一端的静电释放端，且所述静电释放端在所述基板上的正投影与所述第二导线在所述基板上的正投影至少部分交叠设置；
    优选的，所述释放导线和所述第二导线绝缘设置或者所述释放导线和所述第二导线过孔连接；
    优选的，所述释放导线设置于所述第一导线层。
  3. 根据权利要求2所述的测试电路，其中，所述静电释放端的个数为多个，多个所述静电释放端沿所述第二方向并排间隔设置并连接于所述主体部，各所述静电释放端在所述基板上的正投影分别与所述第二导线在所述基板上的正投影至少部分交叠设置。
  4. 根据权利要求2所述的测试电路，其中，沿远离所述主体部的方向，所述静电释放端在所述第二方向上的延伸宽度逐渐减小。
  5. 根据权利要求2所述的测试电路，其中，所述静电释放部还包括释放电容，所述释放电容包括沿所述基板的厚度方向层叠设置的第一极板和第二极板，且第一极板和第二极板中的一者与所述释放导线电连接；
    优选的，所述第一极板和所述释放导线均位于所述第一导线层并电连接；
    优选的，所述第二极板位于第三导线层，所述第三导线层位于所述第一导线层和所述第二导线层之间；
    优选的，所述释放导线至少为两个，至少两个所述释放导线的静电释放端位于所述交叠段在所述第二方向的两侧，所述第一极板连接于位于所述交叠段在所述第二方向两侧的静电释放端所在的所述释放导线之间；
    优选的，所述第一极板和所述第二极板在所述基板上的正投影的交叠面积大于或等于所述交叠段和 所述第一导线在所述基板上的正投影的交叠面积；
    优选的，所述第二导线的个数为多个，多个所述第二导线的所述交叠段沿所述第一方向间隔设置，各所述第二导线的所述交叠段在所述第二方向的至少一侧均设置有所述静电释放部；
    优选的，多个所述静电释放部的所述释放电容相互并联连接；
    优选的，多个所述静电释放部的所述释放电容的所述第二极板相互并联连接；
    优选的，所述测试电路还包括电源线，所述第二极板连接于所述电源线。
  6. 根据权利要求1所述的测试电路，其中，所述交叠段和所述第一导线在所述基板上的正投影的交叠面积大于或等于450μm 2；
    优选的，所述第一导线的线宽大于或等于30μm，所述第二导线的线宽大于或等于15μm。
  7. 根据权利要求1所述的测试电路，其中，
    所述静电释放部包括晶体管，所述晶体管包括源极、漏极和栅极，且所述漏极和所述栅极电连接；
    所述测试电路还包括电源信号线，所述晶体管的所述源极和所述漏极中的一者与所述第二导线电连接，另一者与所述电源信号线电连接；
    优选的，所述电源信号线包括第一信号线，所述源极和所述第二导线电连接，所述漏极和所述第一信号线电连接，所述第二导线上的电压大于V Gh+n|V Th|，其中，V Gh为所述第一信号线上的电压，V Th为所述晶体管的源极和漏极的导通电压，n为所述第二导线和所述第一信号线之间连接的所述晶体管个数；
    和/或，所述电源信号线包括第二信号线，所述源极和所述第二信号电连接，所述漏极和所述第二导线电连接，所述第二导线上的电压小于V GL-m|V Th|，其中，V GL为第二信号线上的电压，V Th为晶体管的源极和漏极的导通电压，m为所述第二导线和所述第二信号线之间连接的所述晶体管个数；
    优选的，所述第二导线和所述电源信号线之间连接有两个以上的所述晶体管；
    优选的，所述源极和所述漏极位于所述第二导线层；
    优选的，所述栅极位于所述第一导线层。
  8. 根据权利要求1所述的测试电路，其中，还包括芯片焊盘和测试焊盘，至少部分所述第二导线连接于所述芯片焊盘和所述测试焊盘之间；
    至少一个所述静电释放部位于所述芯片焊盘背离其连接的所述第二导线上所述交叠段的一侧；
    和/或，至少一个所述静电释放部位于所述交叠段和所述测试焊盘之间。
  9. 一种显示面板，其中，所述显示面板包括权利要求1-8任一项所述的测试电路；
    优选的，所述显示面板包括显示区和切割区域，至少部分所述测试电路位于所述显示区或所述切割区域；
    优选的，所述第一导线位于所述切割区域；
    优选的，所述静电释放部位于所述切割区域；
    优选的，所述第一导线为检测导线并用于传输数据控制信号；
    优选的，所述第二导线包括时钟导线。
  10. 一种显示装置，包括如权利要求9所述的显示面板。
PCT/CN2022/122428 2022-05-20 2022-09-29 测试电路、显示面板及显示装置 WO2023221364A1 (zh)

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