WO2023221351A1 - 氮化镓hemt器件及其制造方法 - Google Patents

氮化镓hemt器件及其制造方法 Download PDF

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WO2023221351A1
WO2023221351A1 PCT/CN2022/120766 CN2022120766W WO2023221351A1 WO 2023221351 A1 WO2023221351 A1 WO 2023221351A1 CN 2022120766 W CN2022120766 W CN 2022120766W WO 2023221351 A1 WO2023221351 A1 WO 2023221351A1
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metal layer
layer
gallium nitride
interlayer insulating
interconnection
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PCT/CN2022/120766
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French (fr)
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王鹏飞
林敏之
刘磊
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苏州东微半导体股份有限公司
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application belongs to the technical field of gallium nitride devices, and relates, for example, to a gallium nitride HEMT device and a manufacturing method thereof.
  • Gallium nitride high electron mobility transistor (HEMT) devices can achieve ultra-fast switching frequencies. High hopes are placed on the future communications field.
  • the manufacturing of gallium nitride substrates is difficult.
  • gallium nitride layers are usually prepared on silicon substrates to prepare HEMT devices.
  • gallium nitride HEMT devices on silicon substrates are different from traditional silicon-based power devices.
  • the electrode arrangement of the device is different, making the gallium nitride HEMT device package incompatible with the traditional silicon-based power device package.
  • This application provides a gallium nitride HEMT device and a manufacturing method thereof to achieve compatibility between the gallium nitride HEMT device packaging and the silicon-based power device packaging.
  • gallium nitride base layer located on the silicon substrate
  • a HEMT device formed on the gallium nitride base layer including a gate electrode, a source electrode and a drain electrode;
  • a drain electrode is located on the back side of the silicon substrate, and the drain electrode is in contact with the third interconnection metal layer.
  • An embodiment of the present application provides a method for manufacturing a gallium nitride HEMT device, including:
  • HEMT device Forming a HEMT device on the gallium nitride base layer, including the gate, source and drain of the HEMT device;
  • first interconnection metal layer Forming a first interconnection metal layer and etching the first interconnection metal layer to form a gate electrode and a source electrode, the drain electrode being electrically connected to the front through hole through the first interconnection metal layer bottom;
  • a third interconnection metal layer is formed in the back through hole, and the third interconnection metal layer is in contact with the first interconnection metal layer in the front through hole;
  • a drain electrode is formed on the back side of the silicon substrate.
  • Embodiments of the present application also provide a method for manufacturing a gallium nitride HEMT device, including:
  • HEMT device Forming a HEMT device on the gallium nitride base layer, including the gate, source and drain of the HEMT device;
  • the metal layer is electrically connected to the drain electrode;
  • a third interconnection metal layer is formed in the back through hole, and the third interconnection metal layer is in contact with the first interconnection metal layer in the front through hole;
  • a drain electrode is formed on the back side of the silicon substrate.
  • Figures 1 and 2 are schematic cross-sectional structural diagrams of two embodiments of gallium nitride HEMT devices of the present application;
  • 3 to 10 are schematic cross-sectional structural diagrams of the main process nodes of one embodiment of the manufacturing method of the gallium nitride HEMT device of the present application.
  • FIG 1 is a schematic cross-sectional structural diagram of an embodiment of a gallium nitride HEMT device provided by the present application.
  • the gallium nitride HEMT device of the present application includes a silicon substrate 1, and a nitrogen layer located on the silicon substrate 1.
  • the gallium base layer 2 is an insulating layer 3 located on the gallium nitride base layer 2 .
  • the gallium nitride base layer 2 usually includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer.
  • the material of the gallium nitride base layer 2 is not limited in the embodiments of this application.
  • the material of the insulating layer 3 is usually silicon nitride.
  • the HEMT device formed on the gallium nitride base layer 2 includes the gate electrode 13, the source electrode 12 and the drain electrode 11 of the HEMT device.
  • the source electrode 12 and the drain electrode 11 form ohmic contact with the gallium nitride base layer 2, and the gate electrode 13 Set to control the on and off of the HEMT device.
  • the front through hole 4 penetrates from the upper surface of the gallium nitride base layer 2 to the lower surface of the gallium nitride base layer 2.
  • the front through hole 4 should be located on at least one side of the HEMT device.
  • the front through hole 4 is exemplarily shown in Figure 1 Located on both sides of the HEMT device.
  • the first interlayer insulating layer 5 covering the formed HEMT device and the sidewall of the positive through hole 4 is formed in the first interlayer insulating layer 5 to lead out the gate electrode 13, the source electrode 12 and the drain electrode 11 respectively.
  • the first interconnection metal layer 6 can fill the front through hole 4, or the first interconnection metal layer 6 can only cover the sidewalls and bottom of the front through hole 4.
  • the first interconnection metal layer 6 can fill the front through hole 4.
  • the layer 6 fills the positive hole 4 as an example for illustration.
  • the first interconnection metal layer 6 extends to the first interlayer insulating layer 5 to form a gate electrode and a source electrode respectively. Based on the cross-sectional positional relationship, the source electrode and the first interconnection leading out the gate electrode 13 are not shown in FIG. 1 The via hole and the first interconnection metal layer are shown, but as a conventional technique, the structures of the gate electrode and the source electrode should be known to those skilled in the art.
  • the first interconnection metal layer in the positive through hole 4 is electrically connected to the drain electrode 11, so that the drain electrode 11 can be electrically connected to the bottom of the gallium nitride base layer 2.
  • the drain electrode 11 directly passes through the first
  • the interconnection metal layer 6 is electrically connected to the bottom of the gallium nitride base layer 2 (ie, the bottom of the positive through hole 4).
  • a passivation layer can also be provided on the first interconnection metal layer 6 and the first interlayer insulating layer 5.
  • the passivation layer plays a role in protecting the gallium nitride HEMT device. As a conventional technology, it is not shown in Figure 1 Passivation layer structure. An opening is provided in the passivation layer, and the opening exposes the gate electrode and the source electrode.
  • a back via 20 is formed in the silicon substrate 1 , and a third interconnect metal layer 21 is formed in the back via 20 .
  • the third interconnect metal layer 21 is in contact with the first interconnect metal layer 6 in the front via 4 .
  • the drain electrode 22 located on the back side of the silicon substrate 1 is in contact with the third interconnection metal layer 21, so that the drain electrode 11 is electrically connected to the third interconnection metal layer 21 through the first interconnection metal layer 6 and the third interconnection metal layer 21.
  • the drain electrode 22 on the back side of the silicon substrate 1 ie, the back side of the chip) is compatible with the packaging of traditional silicon-based power devices.
  • FIG 2 is a schematic cross-sectional structural diagram of another embodiment of a gallium nitride HEMT device provided by this application.
  • the gallium nitride HEMT device shown in Figure 2 is based on the structure shown in Figure 1, with a first interlayer insulating layer 5 and the first interconnection metal layer 6, a second interlayer insulating layer 7 is provided, a second interconnection via is formed in the second interlayer insulating layer 7, and a second interconnection via is formed in the second interlayer insulating layer 7.
  • the second interconnection metal layer 8 will extend to the second interlayer insulating layer 7 to form a gate electrode, a source electrode, the second interlayer insulating layer 7 and the second interconnection metal layer 8 respectively.
  • the purpose is to rearrange the gate electrode and source electrode to form a better electrode connection position.
  • the structure of the gate electrode and the source electrode is not shown in FIG. 2 , but as a conventional technology, the structure of the gate electrode and the source electrode should be known to those skilled in the art.
  • the second interlayer insulating layer is provided. 7 and the second interconnection metal layer 8, it is only necessary to lead the gate electrode and the source electrode through the second interconnection via hole. This structure is not shown in the embodiment of the present application. If in the first interlayer insulating layer 5 and the first interconnection metal layer 6, the drain electrode 11 is not electrically connected to the bottom of the positive through hole 4 through the first interconnection metal layer 6, then the second interlayer insulating layer is disposed.
  • the drain electrode 11 can be electrically connected to the first interconnection metal layer 6 in the positive through hole 4 through the second interconnection metal layer 8, that is, the second interconnection metal layer 8 will
  • the first interconnection metal layer 6 in the front through hole 4 is electrically connected to the drain electrode 11, thereby electrically connecting the drain electrode 11 to the bottom of the front through hole 4.
  • the gallium nitride HEMT device of the present application also includes a passivation layer 9 located on the second interconnection metal layer 8 and the second interlayer insulating layer 7. There should be an opening in the passivation layer 9. The opening exposes the gate and source electrodes of the gallium nitride HEMT device.
  • the passivation layer 9 plays a protective role in the gallium nitride HEMT device. Based on the positional relationship of the cross section, the opening structure in the passivation layer 9 is not shown in Figure 2, but as a conventional technology, this structure should be understood by those skilled in the art. Known.
  • FIGS. 3 to 10 are schematic cross-sectional structural diagrams of main process nodes of an embodiment of the manufacturing method of a gallium nitride HEMT device of the present application.
  • a method for manufacturing a gallium nitride HEMT device in this application includes:
  • a gallium nitride base layer 2 is formed on the provided silicon substrate 1, and an insulating layer 3 is formed on the gallium nitride base layer.
  • the material of the insulating layer 3 is usually silicon nitride.
  • the gate electrode 13 of the HEMT device is formed on the gallium nitride base layer 2 .
  • the gate electrode 13 is used to control the HEMT device to turn on and off.
  • the position of the positive through hole 4 is defined through the photolithography process, and then the insulating layer 3 and the gallium nitride base layer 2 are etched to form the positive through hole 4 in the gallium nitride base layer 2.
  • the through hole 4 penetrates from the upper surface of the gallium nitride base layer 2 to the lower surface of the gallium nitride base layer 2 .
  • a first interlayer insulating layer 5 is formed covering the formed HEMT device and the bottom and sidewalls of the positive through hole 4 .
  • FIG. 7 the position of the first interconnection via hole is defined through a photolithography process, and then the first interlayer insulating layer 5 is etched to form the first interconnection in the first interlayer insulating layer 5 A through hole is formed and the silicon substrate 1 at the bottom of the front through hole 4 is exposed, and then a first interconnection metal layer 6 is formed within the formed first interconnection through hole and the front through hole 4 .
  • FIG. 7 only exemplarily shows the first interconnection via hole leading out the source electrode 12 and the drain electrode 11 and the first interconnection metal layer 6 and the first interconnection metal layer 6 located in the front through hole 4 .
  • the first interconnection via leading out the gate 13 and the first interconnection metal layer are not shown.
  • the drain electrode can be directly electrically connected through the first interconnection metal layer. to the bottom of the positive through hole, and extend the first interconnection metal layer to the first interlayer insulating layer to form a gate electrode and a source electrode, and then form a gate electrode located on the first interlayer insulating layer and the first interconnection metal layer.
  • a passivation layer, a back via hole in the silicon substrate, a third interconnect metal layer and a drain electrode are sufficient.
  • the embodiment of the present application will next describe the manufacturing method of the gallium nitride HEMT device of the present application by taking the formation of a second interlayer insulating layer and a second interconnection metal layer to adjust the arrangement of the gate electrode and the source electrode as an example.
  • a second interlayer insulating layer 7 is formed over the first interlayer insulating layer 5 and the first interconnection metal layer 6 . Afterwards, the position of the second interconnection via hole is defined through a photolithography process, and then the second interlayer insulating layer 7 is etched to form a second interconnection via hole in the second interlayer insulating layer 7 .
  • FIG. 8 only exemplarily shows the second interconnection electrically connecting the first interconnection metal layer 6 in the positive through hole 4 and the first interconnection metal layer 6 leading out the drain electrode 11 .
  • the second interconnection via hole and the second interconnection metal layer leading out the gate electrode 13 and the source electrode 12 are not shown.
  • a passivation layer 9 is formed on the second interlayer insulating layer 7 and the second interconnection metal layer 8, and then the position of the opening is defined through a photolithography process, and then the passivation layer 9 is Etching is performed to form openings in the passivation layer 9, and the formed openings expose the gate electrode and source electrode of the HEMT device.
  • the passivation layer 9 protects the gallium nitride HEMT device. Based on the cross-sectional position, the opening structure in the passivation layer 9 is not shown in Figure 9 .
  • the silicon substrate 1 is thinned and etched to form a back via 20 in the silicon substrate 1 , and then a third interconnect metal layer 21 is formed in the back via 20 .
  • the interconnection metal layer 21 is in contact with the first interconnection metal layer 6 in the positive through hole 4.
  • a drain electrode 22 is formed on the back side of the silicon substrate 1, that is, the drain electrode 11 passes through the first interconnection metal layer 6 and the second interconnection metal layer 6.
  • the connection metal layer 8 and the third interconnection metal layer 21 are electrically connected to the drain electrode 22 on the back side of the silicon substrate 1 (ie, the back side of the chip).
  • a gallium nitride base layer is prepared on a silicon substrate. After the HEMT device is manufactured on the gallium nitride base layer, a part of the gallium nitride base layer is etched away to form a positive through hole, so that the drain electrode can be electrically connected conveniently. to the bottom of the gallium nitride base layer, so that during the back via manufacturing process, the back via can be directly etched to the metal (first interconnection metal layer) on the front of the chip by etching the silicon substrate layer, without the need for additional etching.
  • the drain electrode on the back of the chip can be formed by etching the gallium nitride base layer, which simplifies the manufacturing process of the gallium nitride HEMT device.
  • the source electrode and gate electrode are set on the front of the chip, and the drain electrode is set on the back of the chip, which is compatible with Traditional silicon-based power device packaging.

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Abstract

本申请实施例提供的一种氮化镓HEMT器件，包括硅衬底；位于所述硅衬底上的氮化镓基底层；在所述氮化镓基底层上形成的HEMT器件，包括栅极、源极和漏极；从所述氮化镓基底层上表面贯穿至下表面的正穿孔；覆盖所述HEMT器件及所述正穿孔侧壁的第一层间绝缘层，在所述第一层间绝缘层中的第一互连通孔；位于所述第一互连通孔和所述正穿孔内的第一互连金属层，所述正穿孔内的第一互连金属层和所述漏极电性连接；在所述硅衬底中形成的背穿孔，位于所述背穿孔内的第三互连金属层，所述第三互连金属层与所述正穿孔内的第一互连金属层接触连接；位于所述硅衬底背面且与所述第三互连金属层接触连接的漏电极。

Description

氮化镓HEMT器件及其制造方法
本申请要求在2022年5月18日提交中国专利局、申请号为202210551950.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于氮化镓器件技术领域，例如涉及一种氮化镓HEMT器件及其制造方法。
背景技术
随着5G时代的到来，通信领域对于高频、高功率射频器件的需求越来越强烈，氮化镓高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)器件由于可以实现超快开关频率，在未来通信领域被寄予了厚望。氮化镓衬底的制造困难大，为了降低生产成本，目前通常是在硅衬底上制备氮化镓层来制备HEMT器件，但是硅衬底上的氮化镓HEMT器件与传统的硅基功率器件的电极排布方式不同，造成氮化镓HEMT器件封装与传统的硅基功率器件封装不兼容。
发明内容
本申请提供一种氮化镓HEMT器件及其制造方法，以实现氮化镓HEMT器件封装与硅基功率器件封装相兼容。
本申请实施例提供的一种氮化镓HEMT器件，包括：
硅衬底；
位于所述硅衬底上的氮化镓基底层；
在所述氮化镓基底层上形成的HEMT器件，所述HEMT器件包括栅极、源极和漏极；
从所述氮化镓基底层上表面贯穿至所述氮化镓基底层下表面的正穿孔；
覆盖所述HEMT器件及所述正穿孔侧壁的第一层间绝缘层，在所述第一层间绝缘层中形成的分别将所述栅极、所述源极和所述漏极引出的第一互连通孔；
位于所述第一互连通孔和所述正穿孔内的第一互连金属层，所述正穿孔内的所述第一互连金属层和所述漏极电性连接；
在所述硅衬底中形成的背穿孔，位于所述背穿孔内的第三互连金属层，所述第三互连金属层与所述正穿孔内的所述第一互连金属层接触连接；
位于所述硅衬底背面的漏电极，所述漏电极与所述第三互连金属层接触连接。
本申请实施例提供的一种氮化镓HEMT器件的制造方法，包括：
在提供的硅衬底上形成氮化镓基底层；
在所述氮化镓基底层上形成HEMT器件，包含HEMT器件的栅极、源极和漏极；
进行光刻和刻蚀，在所氮化镓基底层中形成正穿孔，所述正穿孔从所述氮化镓基底层上表面贯穿至所述氮化镓基底层下表面；
覆盖所述HEMT器件及所述正穿孔的底部和侧壁形成第一层间绝缘层；
进行光刻和刻蚀，在所述第一层间绝缘层中形成第一互连通孔并将所述正穿孔底部的硅衬底暴露出来；
形成第一互连金属层并对所述第一互连金属层进行刻蚀以形成栅电极和源电极，所述漏极通过所述第一互连金属层电性连接至所述正穿孔的底部；
在所述第一层间绝缘层和所述第一互连金属层之上形成钝化层；
对所述钝化层进行刻蚀，在所述钝化层中形成开口，将所述栅电极和源电极暴露出来；
对所述硅衬底进行减薄和刻蚀，在所述硅衬底中形成背穿孔；
在所述背穿孔内形成第三互连金属层，所述第三互连金属层与所述正穿孔内的第一互连金属层接触连接；
在所述硅衬底背面形成漏电极。
本申请实施例还提供了一种氮化镓HEMT器件的制造方法，包括：
在提供的硅衬底上形成氮化镓基底层；
在所述氮化镓基底层上形成HEMT器件，包含HEMT器件的栅极、源极和漏极；
进行光刻和刻蚀，在所氮化镓基底层中形成正穿孔，所述正穿孔从所述氮化镓基底层上表面贯穿至所述氮化镓基底层下表面；
覆盖所述HEMT器件及所述正穿孔的底部和侧壁形成第一层间绝缘层；
进行光刻和刻蚀，在所述第一层间绝缘层中形成第一互连通孔并将所述正穿孔底部的硅衬底暴露出来；
在所述第一互连通孔及所述正穿孔内形成第一互连金属层；
在所述第一层间绝缘层和所述第一互连金属层之上形成第二层间绝缘层；
进行光刻和刻蚀，在所述第二层间绝缘层内形成第二互连通孔；
形成第二互连金属层并对所述第二互连金属层进行刻蚀以形成栅电极和源电极，且所述第二互连金属层将所述正穿孔内的所述第一互连金属层与所述漏极电性连接；
在所述第二层间绝缘层和所述第二互连金属层之上形成钝化层；
对所述钝化层进行刻蚀，在所述钝化层中形成开口，将所述栅电极和源电极暴露出来；
对所述硅衬底进行减薄和刻蚀，在所述硅衬底中形成背穿孔；
在所述背穿孔内形成第三互连金属层，所述第三互连金属层与所述正穿孔内的第一互连金属层接触连接；
在所述硅衬底背面形成漏电极。
附图说明
图1和图2是本申请的氮化镓HEMT器件的两个实施例的剖面结构示意图；
图3至图10是本申请的氮化镓HEMT器件的制造方法的一个实施例的主要 工艺节点的剖面结构示意图。
具体实施方式
图1是本申请提供的氮化镓HEMT器件的一个实施例的剖面结构示意图，如图1所示，本申请的氮化镓HEMT器件包括硅衬底1，位于硅衬底1之上的氮化镓基底层2，位于氮化镓基底层2上的绝缘层3。氮化镓基底层2通常包括氮化镓(GaN)层和铝镓氮(AlGaN)层，本申请实施例中不限定氮化镓基底层2的材料。绝缘层3的材料通常为氮化硅。
在氮化镓基底层2上形成的HEMT器件，包括HEMT器件的栅极13、源极12和漏极11，源极12和漏极11与氮化镓基底层2形成欧姆接触，栅极13设置为控制HEMT器件的开启和关断。
从氮化镓基底层2的上表面贯穿至氮化镓基底层2的下表面的正穿孔4，正穿孔4应位于HEMT器件的至少一侧，图1中示例性的示出了正穿孔4位于HEMT器件的两侧。
覆盖所形成的HEMT器件及正穿孔4的侧壁的第一层间绝缘层5，在第一层间绝缘层5中形成的分别将所述栅极13、源极12和漏极11引出的第一互连通孔，在所述第一互连通孔和正穿孔4内形成的第一互连金属层6。在正穿孔内4，第一互连金属层6可以填满正穿孔4，也可以是第一互连金属层6仅覆盖正穿孔4的侧壁和底部，图1中以第一互连金属层6填满正穿孔4为例进行说明。
第一互连金属层6延伸至第一层间绝缘层5上分别形成栅电极、源电极，基于剖面的位置关系，在图1中未将源电极，以及将栅极13引出的第一互连通孔和第一互连金属层示出，但是作为常规技术，栅电极和源电极的结构应为本领域的技术人员所知悉。
正穿孔4内的第一互连金属层和漏极11电性连接，从而可以将漏极11电性连接到氮化镓基底层2的底部，在图1中，漏极11直接通过第一互连金属层6电性连接到氮化镓基底层2的底部(即正穿孔4的底部)。
在第一互连金属层6和第一层间绝缘层5之上还可以设置钝化层，钝化层对氮化镓HEMT器件起到保护的作用，作为常规技术，图1中未示出钝化层结构。钝化层中设有开口，开口将栅电极和源电极暴露出来。
在硅衬底1中形成背穿孔20，在背穿孔20内形成的第三互连金属层21，第三互连金属层21与正穿孔4内的第一互连金属层6接触连接。位于硅衬底1背面的漏电极22，漏电极22与第三互连金属层21接触连接，从而漏极11通过第一互连金属层6、和第三互连金属层21电性连接到硅衬底1背面(即芯片背面)的漏电极22，这样可以兼容传统的硅基功率器件的封装。
图2是本申请提供的氮化镓HEMT器件的另一个实施例的剖面结构示意图，图2所示的氮化镓HEMT器件是在图1所示结构的基础上，在第一层间绝缘层5和第一互连金属层6之上设有第二层间绝缘层7，在第二层间绝缘层7中形成有第二互连通孔，在所述第二互连通孔内形成有第二互连金属层8，第二互连金属层8会延伸至第二层间绝缘层7上分别形成栅电极、源电极，第二层间绝缘层7和第二互连金属层8的目的是将栅电极和源电极进行重新排布，以形成更好的电极连接位置。基于剖面的位置关系，图2中未展示栅电极和源电极的结构，但是作为常规技术，栅电极和源电极的结构应为本领域的技术人员所知悉。
在第一层间绝缘层5和第一互连金属层6中，若漏极11已经通过第一互连金属层6电性连接到正穿孔4的底部，则在设置第二层间绝缘层7和第二互连金属层8时，仅需要将栅电极和源电极通过第二互连通孔引出即可，该结构在本申请实施例中未示出。若在第一层间绝缘层5和第一互连金属层6中，漏极11没有通过第一互连金属层6电性连接到正穿孔4的底部，则在设置第二层间绝缘层7和第二互连金属层8时，可以将漏极11通过第二互连金属层8电性连接至正穿孔4内的第一互连金属层6，即第二互连金属层8将正穿孔4内的第一互连金属层6与漏极11电性连接，从而将漏极11电性连接到正穿孔4的底部，该结构如图2所示。
如图2，本申请的氮化镓HEMT器件还包括位于第二互连金属层8和第二层间绝缘层7之上的钝化层9，钝化层9中应设有开口，所述开口将氮化镓HEMT器件的栅电极和源电极暴露出来。钝化层9对氮化镓HEMT器件起到保护的作用，基于剖面的位置关系，图2中未展示钝化层9中的开口结构，但是作为常规技术，该结构应为本领域的技术人员所知悉。
图3至图10是本申请的氮化镓HEMT器件的制造方法的一个实施例的主要工艺节点的剖面结构示意图。如图3至图10所示，本申请的一种氮化镓HEMT器件的制造方法，包括：
首先，如图3所示，在提供的硅衬底1上形成氮化镓基底层2，在氮化镓基底层上形成绝缘层3，绝缘层3的材料通常为氮化硅。之后在氮化镓基底层2上形成HEMT器件的源极12和漏极11，源极12和漏极11与氮化镓基底层2形成欧姆接触。
接下来，如图4所示，在氮化镓基底层2上形成HEMT器件的栅极13，栅极13用来控制HEMT器件开启和关断。
接下来，如图5所示，通过光刻工艺定义正穿孔4的位置，然后对绝缘层3和氮化镓基底层2进行刻蚀，在氮化镓基底层2中形成正穿孔4，正穿孔4从氮化镓基底层2的上表面贯穿至氮化镓基底层2的下表面。
接下来，如图6所示，覆盖所形成的HEMT器件及正穿孔4的底部和侧壁形成第一层间绝缘层5。
接下来，如图7所示，通过光刻工艺定义第一互连通孔的位置，然后对第一层间绝缘层5进行刻蚀，在第一层间绝缘层5中形成第一互连通孔并将正穿孔4底部的硅衬底1暴露出来，然后在所形成的第一互连通孔及正穿孔4内形成第一互连金属层6。基于剖面的位置关系，图7中仅示例性的示出了将源极12和漏极11引出的第一互连通孔和第一互连金属层6以及位于正穿孔4中的第一互连金属层6，而没有展示出将栅极13引出的第一互连通孔和第一互连金属层。
需要说明的是，本申请的氮化镓HEMT器件的制造方法，在上述形成第一层间绝缘层和第一互连金属层时，可以直接将漏极通过第一互连金属层电性连接至正穿孔的底部，并将第一互连金属层延伸至第一层间绝缘层之上形成栅电极和源电极，之后形成位于第一层间绝缘层和第一互连金属层之上的钝化层、位于硅衬底中的背穿孔和第三互连金属层及漏电极即可。本申请实施例接下来以形成第二层间绝缘层和第二互连金属层来调整栅电极和源电极的排布为例来描述本申请的氮化镓HEMT器件的制造方法。
接下来，如图8所示，在第一层间绝缘层5和第一互连金属层6之上形成第二层间绝缘层7。之后，通过光刻工艺定义第二互连通孔的位置，然后对第二层间绝缘层7进行刻蚀，在第二层间绝缘层7内形成第二互连通孔。然后淀积形成第二互连金属层8，并对第二互连金属层8进行刻蚀形成栅电极和源电极，且第二互连金属层8将正穿孔4内的第一互连金属6与将漏极引出的第一互连金属层6电性连接，即漏极11通过第一互连金属层6和第二互连金属层8电性连接到氮化镓基底层2的底部。基于剖面的位置关系，图8中仅示例性的示出了将正穿孔4内的第一互连金属层6与将漏极11引出的第一互连金属层6电性连接的第二互连通孔和第二互连金属层，而没有展示出将栅极13和源极12引出的第二互连通孔和第二互连金属层。
接下来，如图9所示，在第二层间绝缘层7和第二互连金属层8之上形成钝化层9，之后通过光刻工艺定义开口的位置，然后对钝化层9进行刻蚀以在钝化层9中形成开口，所形成的开口将HEMT器件的栅电极和源电极暴露出来。钝化层9对氮化镓HEMT器件起到保护的作用，基于剖面的位置关系，图9中未展示钝化层9中的开口结构。
接下来，如图10所示，对硅衬底1进行减薄和刻蚀，在硅衬底1中形成背穿孔20，之后在背穿孔20内形成第三互连金属层21，第三互连金属层21与正穿孔4内的第一互连金属层6接触连接，最后，在硅衬底1的背面形成漏电极22，即漏极11通过第一互连金属层6、第二互连金属层8、第三互连金属层21 电性连接到硅衬底1背面(即芯片背面)的漏电极22。
本申请在硅衬底上制备氮化镓基底层，在氮化镓基底层上制造HEMT器件后，将一部分氮化镓基底层刻蚀掉形成正穿孔，从而可以方便的将漏极电性连接到氮化镓基底层的底部，这样在进行背穿孔制造工艺时，通过刻蚀硅衬底层就可以直接将背穿孔刻蚀到芯片正面的金属(第一互连金属层)，不需要额外刻蚀氮化镓基底层就可以形成芯片背面的漏电极，这简化了氮化镓HEMT器件的制造工艺，同时，将源电极和栅电极设置于芯片正面，将漏电极设置于芯片背面，可以兼容传统的硅基功率器件的封装。

Claims (10)

  1. 一种氮化镓高电子迁移率晶体管HEMT器件，包括：
    硅衬底；
    位于所述硅衬底上的氮化镓基底层；
    在所述氮化镓基底层上形成的HEMT器件，所述HEMT器件包括栅极、源极和漏极；
    从所述氮化镓基底层上表面贯穿至所述氮化镓基底层下表面的正穿孔；
    覆盖所述HEMT器件及所述正穿孔侧壁的第一层间绝缘层，在所述第一层间绝缘层中形成的分别将所述栅极、所述源极和所述漏极引出的第一互连通孔；
    位于所述第一互连通孔和所述正穿孔内的第一互连金属层，所述正穿孔内的所述第一互连金属层和所述漏极电性连接；
    在所述硅衬底中形成的背穿孔，位于所述背穿孔内的第三互连金属层，所述第三互连金属层与所述正穿孔内的所述第一互连金属层接触连接；
    位于所述硅衬底背面的漏电极，所述漏电极与所述第三互连金属层接触连接。
  2. 如权利要求1所述的氮化镓HEMT器件，其中，所述第一互连金属层延伸至所述第一层间绝缘层上分别形成栅电极、源电极，所述漏极通过所述第一互连金属层电性连接至所述正穿孔的底部。
  3. 如权利要求2所述的氮化镓HEMT器件，还包括位于所述第一互连金属层和所述第一层间绝缘层之上的钝化层，所述钝化层中设有开口，所述开口将所述栅电极和所述源电极暴露出来。
  4. 如权利要求2所述的氮化镓HEMT器件，还包括：
    位于所述第一层间绝缘层和所述第一互连金属层之上的第二层间绝缘层，在所述第二层间绝缘层中形成的第二互连通孔；
    位于所述第二互连通孔内的第二互连金属层，所述第二互连金属层延伸至所述第二层间绝缘层上分别形成栅电极、源电极。
  5. 如权利要求1所述的氮化镓HEMT器件，还包括：
    位于所述第一层间绝缘层和所述第一互连金属层之上的第二层间绝缘层，在所述第二层间绝缘层中形成的第二互连通孔；
    位于所述第二互连通孔内的第二互连金属层，所述第二互连金属层延伸至所述第二层间绝缘层上分别形成栅电极、源电极，且所述第二互连金属层将所述正穿孔内的所述第一互连金属层与所述漏极电性连接。
  6. 如权利要求4或5所述的氮化镓HEMT器件，还包括位于所述第二互连金属层和所述第二层间绝缘层之上的钝化层，所述钝化层中设有开口，所述开口将所述栅电极和所述源电极暴露出来。
  7. 如权利要求1所述的氮化镓HEMT器件，其中，所述氮化镓基底层包括氮化镓层和铝镓氮层。
  8. 如权利要求1所述的氮化镓HEMT器件，其中，所述正穿孔位于所述HEMT器件的至少一侧。
  9. 一种氮化镓HEMT器件的制造方法，包括：
    在提供的硅衬底上形成氮化镓基底层；
    在所述氮化镓基底层上形成HEMT器件，包含HEMT器件的栅极、源极和漏极；
    进行光刻和刻蚀，在所氮化镓基底层中形成正穿孔，所述正穿孔从所述氮化镓基底层上表面贯穿至所述氮化镓基底层下表面；
    覆盖所述HEMT器件及所述正穿孔的底部和侧壁形成第一层间绝缘层；
    进行光刻和刻蚀，在所述第一层间绝缘层中形成第一互连通孔并将所述正穿孔底部的硅衬底暴露出来；
    形成第一互连金属层并对所述第一互连金属层进行刻蚀以形成栅电极和源电极，所述漏极通过所述第一互连金属层电性连接至所述正穿孔的底部；
    在所述第一层间绝缘层和所述第一互连金属层之上形成钝化层；
    对所述钝化层进行刻蚀，在所述钝化层中形成开口，将所述栅电极和源电极暴露出来；
    对所述硅衬底进行减薄和刻蚀，在所述硅衬底中形成背穿孔；
    在所述背穿孔内形成第三互连金属层，所述第三互连金属层与所述正穿孔内的第一互连金属层接触连接；
    在所述硅衬底背面形成漏电极。
  10. 一种氮化镓HEMT器件的制造方法，包括：
    在提供的硅衬底上形成氮化镓基底层；
    在所述氮化镓基底层上形成HEMT器件，包含HEMT器件的栅极、源极和漏极；
    进行光刻和刻蚀，在所氮化镓基底层中形成正穿孔，所述正穿孔从所述氮化镓基底层上表面贯穿至所述氮化镓基底层下表面；
    覆盖所述HEMT器件及所述正穿孔的底部和侧壁形成第一层间绝缘层；
    进行光刻和刻蚀，在所述第一层间绝缘层中形成第一互连通孔并将所述正穿孔底部的硅衬底暴露出来；
    在所述第一互连通孔及所述正穿孔内形成第一互连金属层；
    在所述第一层间绝缘层和所述第一互连金属层之上形成第二层间绝缘层；
    进行光刻和刻蚀，在所述第二层间绝缘层内形成第二互连通孔；
    形成第二互连金属层并对所述第二互连金属层进行刻蚀以形成栅电极和源电极，且所述第二互连金属层将所述正穿孔内的所述第一互连金属层与所述漏极电性连接；
    在所述第二层间绝缘层和所述第二互连金属层之上形成钝化层；
    对所述钝化层进行刻蚀，在所述钝化层中形成开口，将所述栅电极和源电极暴露出来；
    对所述硅衬底进行减薄和刻蚀，在所述硅衬底中形成背穿孔；
    在所述背穿孔内形成第三互连金属层，所述第三互连金属层与所述正穿孔内的第一互连金属层接触连接；
    在所述硅衬底背面形成漏电极。
PCT/CN2022/120766 2022-05-18 2022-09-23 氮化镓hemt器件及其制造方法 WO2023221351A1 (zh)

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