WO2023216585A1 - 一种量子比特耦合方法和结构 - Google Patents

一种量子比特耦合方法和结构 Download PDF

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WO2023216585A1
WO2023216585A1 PCT/CN2022/138770 CN2022138770W WO2023216585A1 WO 2023216585 A1 WO2023216585 A1 WO 2023216585A1 CN 2022138770 W CN2022138770 W CN 2022138770W WO 2023216585 A1 WO2023216585 A1 WO 2023216585A1
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qubit
pad
coplanar waveguide
bus resonator
coupling
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PCT/CN2022/138770
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English (en)
French (fr)
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李红珍
张新
李辰
姜金哲
徐哲
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苏州元脑智能科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena

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  • This application relates to the field of quantum computing technology, and in particular to a qubit coupling method and structure.
  • Superconducting quantum circuit is one of the main candidates for building large-scale quantum processors. It is an analog circuit composed of a superconducting qubit array and its control and readout lines that work in a low-temperature environment.
  • the flip-chip process is a major manufacturing process for addressing qubit 2D arrays.
  • the qubit array and the control and readout circuits are separately manufactured on two independent substrates, and then superconducting bumps are used to connect the two substrates.
  • the bottom surface is bonded at corresponding positions to realize circuit interconnection to alleviate the problem of wiring congestion.
  • the qubit array is usually manufactured on the first chip (corresponding to the top chip of the Flip-chip package). As shown in Figure 1, taking the Transmon qubit array as an example, the qubit units are distributed on a rectangular array grid.
  • the qubit unit includes: a superconducting quantum interference device (SQUID) composed of a Josephson junction (JJ) and a bypass capacitor.
  • the bypass capacitor is in the shape of a cross, and the cross intersection is located at the center of the array grid.
  • Each qubit unit includes four main capacitor arms and three secondary capacitor arms.
  • the primary capacitive arm is used to capacitively couple the nearest neighbor qubit unit, and the secondary capacitive arm is used to capacitively couple or inductively couple with the SQUID, control and readout lines.
  • the SQUID composed of JJ is shown in Figure 1, and the control lines and readout lines are not shown.
  • the qubit unit inside the array can be capacitively coupled with the four nearest neighbor qubit units through the main capacitor arm, and the qubit unit located in the array has an idle main capacitor arm that does not participate in coupling, located at The qubit unit at the top corner of the array has two idle main capacitor arms that do not participate in coupling.
  • the incomplete utilization of edge qubits will, on the one hand, reduce the number of two-bit gates in the array, and as the size of the array increases, the number of two-bit gates will be reduced more. For example: a 4 ⁇ 4 array can build 32 two-bit gates, but only 24 two-bit gates after coupling; a 6 ⁇ 6 array can build 72 two-bit gates, but only 60 after coupling.
  • edge qubits may become the boundary of algorithm execution, for example: simulating a two-dimensional quantum random walk, where the quantum state transfers to the edge qubits with a certain probability to stop walking; simulating topological time crystals , the time translation symmetry will be broken at the boundary.
  • Non-patent document 1 records that as early as 2018, the John M. Martinis research group first proposed using flip-chip to design qubit addressing in a 2D array.
  • Non-patent Document 2 records the Sycamore quantum processor released by John M. Martinis's research group in 2019.
  • the processor consists of two high-resistance silicon chips.
  • the first chip uses a rectangular lattice array and contains 54 qubits, with neighbor coupling. Adjustable, the second chip (corresponding to the bottom chip of the flip-chip package) routes the control and readout lines.
  • Non-patent documents 3 and 4 record the Zu Chongzhi quantum processor released by Zhu Xiaobo’s research group.
  • the processor consists of two sapphire chips.
  • the first chip contains 66 qubits, arranged in 11 rows and 6 columns, forming a two-dimensional rectangular lattice pattern. The near-neighbor coupling is also adjustable.
  • the second chip carries control and readout lines. The block chips are held together by indium bump alignment.
  • Non-patent Document 5 records the Tianmu-1 quantum processor released by Zhu Shiyao's team, which layouts 6 ⁇ 6 qubits with adjustable neighbor coupling into a square array. All qubits are located on the first chip (sapphire substrate). Segment control and readout lines are located on the second chip (high-resistance silicon substrate), and the two chips are electrically connected via indium bump bonding.
  • these quantum processors add adjustable couplers to turn on or off neighbor coupling for qubits inside the 2D array, they are not fully utilized because there is no long-range coupling between qubits at the edge of the 2D array.
  • Non-patent document 1 B Foxen, J Y Mutus, E Lucero, et al. Qubit compatible superconducting interconnects[J]. Quantum Sci. Technol.3,014005(2018).
  • Non-patent document 2 Frank Arute, Kunal Arya, Ryan Babbush, et al. Quantum supremacy using a programmable superconducting processor[J]. Nature 574,505-510(2019).
  • Non-patent document three Yulin Wu, Wan-Su Bao, Sirui Cao, et al. Strong quantum computational advantage using a superconducting quantum processor [J]. PhysRevLett.127.180501(2021).
  • Non-patent document four Qingling Zhu, Sirui Cao, Fusheng Chen, et al. Quantum Computational Advantage via 60-Qubit 24-Cycle Random Circuit Sampling[J].10.1016/j.scib.2021.10.017(2021).
  • some embodiments of the present application provide a qubit coupling method and structure to overcome the problem that the qubits in the array are not fully utilized in the existing technology, and thus edge quantum problems occur during the execution of certain algorithms. Bits become a matter of algorithm execution boundaries.
  • the technical solutions adopted in this application are as follows:
  • a qubit coupling method is provided that is suitable for a flip-chip packaged quantum circuit chip.
  • the quantum circuit chip includes a first chip and a second chip bonded to each other and a qubit array.
  • the qubit array at least includes a first arrangement.
  • the grid points arranged in the direction and the second arrangement direction include at least M rows of grid points along the first arrangement direction, at least N rows of grid points along the second arrangement direction, and each row of grid points includes at least one grid point.
  • the method includes:
  • a bus resonator is used to couple the qubit units located at the grid points at both ends of the current row, where the current row is arranged along the first arrangement direction or the second arrangement direction, and the qubit unit includes a main capacitor arm, and the main capacitor arm is along the first arrangement direction. and a second arrangement direction arrangement for coupling qubit units located at nearest neighbor grid points.
  • a bus resonator to couple the qubit units located at the grid points at both ends of the current row includes:
  • the uncoupled main capacitor arm is sequentially provided with the interdigitated fingers, the coplanar waveguide and the first pad corresponding to the uncoupled main capacitor arm; among them, the qubit unit, interdigitated finger, The coplanar waveguide and the first pad are provided on the first chip;
  • the second part of the bus resonator, the second pad is provided on the second chip
  • interdigitates corresponding to the uncoupled main capacitor arm, the coplanar waveguide and the first pad are sequentially provided on the uncoupled main capacitor arm, including:
  • the relative positional relationship between the main capacitor arm and the interdigitated fingers is determined through simulation.
  • setting the second part of the bus resonator in the vertical projection direction of the current row also includes:
  • a suspended bridge is provided at the intersection of the second part of the bus resonator.
  • the suspended bridge is used to connect the traces in the same arrangement direction and insulate the traces in different arrangement directions.
  • a qubit coupling structure in a second aspect, includes: a first part of a bus resonator, a first pad, a second part of a bus resonator, and a second pad;
  • the first part of the bus resonator, the first pad and the qubit unit located on the array grid point are arranged on the first chip, the second part of the bus resonator is arranged, the second pad is arranged on the second chip, and the first part of the bus resonator is Includes: interdigitated and coplanar waveguides;
  • the first chip and the second chip are bonded through bumps between the first pad and the second pad, and the qubit units are connected row by row to form a closed grid network, thereby realizing coupling between qubits at the edge of the array.
  • the qubit coupling structure also includes a qubit array.
  • the qubit array includes a grid point array repeatedly arranged in at least a first arrangement direction and a second arrangement direction, and a qubit unit arranged on the grid points;
  • the qubit unit includes a superconducting quantum interferometer, bypass capacitor, main capacitor arm, and secondary capacitor arm;
  • the superconducting quantum interferometer is coupled to the bypass capacitor through a subcapacitive arm;
  • a qubit unit is capacitively coupled to the nearest qubit unit via a main capacitor arm.
  • the first part of the bus resonator is sequentially arranged along the first arrangement direction or the second arrangement direction: the interdigitated fingers corresponding to the uncoupled main capacitor arm, the coplanar waveguide and the first pad;
  • the interdigitated fingers are connected to one end of the coplanar waveguide;
  • the other end of the coplanar waveguide is connected to the first pad, and the connection point transitions from the trapezoidal width of the coplanar waveguide to the width of the first pad.
  • the line width of the interdigitated fingers is w
  • the finger length is l
  • a gap with a width of s is provided around the interdigitated fingers
  • the length of the coplanar waveguide is L, the width is W, and a gap of width S is provided around the coplanar waveguide;
  • the interdigital width and coplanar waveguide width are determined by the 50 ⁇ matching impedance
  • the interdigital length and the coplanar waveguide length are determined by the bus resonator frequency and the interdigital coupling capacitance;
  • the positional relationship between the interdigitated fingers and the uncoupled main capacitor arm is determined by the coupling strength.
  • a gap is provided around the wiring of the second part of the bus resonator, and the gap width is S;
  • a suspension bridge is provided at the intersection of the second part of the bus resonator to connect the wiring in the same arrangement direction and insulate the wiring between different arrangement directions;
  • the suspended bridge includes: bridge body, third pad;
  • the third pad is connected to the second part of the bus resonator in the same direction;
  • the third bonding pad is arranged on both sides of the second part of the bus resonator in another direction;
  • the bridge spans the second part of the bus resonator in another direction, and is electrically connected to the third pads on both sides of the bus resonator in the other direction at the intersection.
  • first pad and the second pad are square;
  • Cylindrical titanium nitride films are provided on the surfaces of both the first pad and the second pad;
  • the titanium nitride film has a preset thickness, and the cross-sectional diameter of the titanium nitride film is equal to the side length of the first pad and the second pad;
  • a cylindrical conductive pillar is provided on the surface of the titanium nitride film, and the cylindrical conductive pillar has a preset diameter and a preset height.
  • This application is compatible with the existing flip-chip process on the premise of realizing long-range coupling of qubits at the edge of the array;
  • the bus resonator using the flip-chip design disclosed in this application has weak crosstalk at the Josephson junction and ensures the working performance of the qubit.
  • Figure 1 is a schematic diagram of a traditional qubit array and a flip-chip packaged quantum circuit chip
  • Figure 1a is a schematic diagram of a traditional qubit array
  • Figure 1b is a schematic diagram of a flip-chip packaged quantum circuit chip
  • Figure 2 is a schematic diagram of a qubit coupling method provided by some embodiments of the present application.
  • Figure 3 is a schematic diagram of long-range coupling of two array edge qubits mediated by a bus resonator provided by some embodiments of the present application;
  • Figure 4 is a schematic diagram of a qubit array and qubit unit provided by some embodiments of the present application.
  • Figure 5 is a schematic diagram of the structure and design of a bus resonator provided by some embodiments of the present application.
  • Words such as “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up”, “down”, “left”, “right”, etc. are only used to express relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • FIG. 1a The existing superconducting quantum circuit architecture is shown in Figure 1.
  • Figure 1a a 4 ⁇ 4 array is taken as an example (the control readout lines for addressing qubits are not shown).
  • the qubits at the edge of the 2D superconducting qubit array are not fully utilized, that is, there are idle main capacitor arms.
  • Figure 1b illustrates the flip-chip design of a 2D array.
  • the first chip (corresponding to the top chip of the flip-chip package) contains the 2D array of all qubits and a small section of readout and control lines.
  • the second chip (corresponding to the flip-chip package) -The bottom chip of the chip package) contains a large section of readout and control lines and other auxiliary components.
  • the first chip is flipped and packaged with the second chip through bump bonding to obtain a superconducting quantum processor.
  • a qubit coupling method is provided that is suitable for a flip-chip packaged quantum circuit chip.
  • the quantum circuit chip includes a first chip and a second chip bonded to each other and a qubit array.
  • the qubit array at least includes The grid points arranged in one arrangement direction and the second arrangement direction include at least M rows of grid points along the first arrangement direction, at least N rows of grid points along the second arrangement direction, and each row of grid points includes at least one grid point.
  • One qubit coupling method involves:
  • Step S1 Iterate through each row in the array and perform the following operations:
  • a bus resonator is used to couple the qubit units located at the grid points at both ends of the current row, where the current row is arranged along the first arrangement direction or the second arrangement direction, and the qubit unit includes a main capacitor arm, and the main capacitor arm is along the first arrangement direction. and a second arrangement direction arrangement for coupling qubit units located at nearest neighbor grid points.
  • using a bus resonator to couple the qubit units located at the grid points at both ends of the current row includes:
  • Step S11 Arrange the interdigitated fingers, coplanar waveguide and first pad corresponding to the uncoupled main capacitor arm in sequence along the lattice point extending direction to both ends of the current row; wherein, the qubit unit, The interdigitated fingers, the coplanar waveguide and the first pad are provided on the first chip;
  • Step S12 Set the second part of the bus resonator in the vertical projection direction of the current row
  • Step S13 Set the second bonding pad at the vertical projection position of the first bonding pad
  • the second part of the bus resonator, the second pad is provided on the second chip
  • Step S14 Bond the first pad and the second pad.
  • the interdigitated fingers corresponding to the uncoupled main capacitor arm, the coplanar waveguide and the first pad are sequentially provided on the uncoupled main capacitor arm, including:
  • the relative positional relationship between the main capacitor arm and the interdigitated fingers is determined through simulation.
  • the second part of setting the bus resonator in the vertical projection direction of the current row also includes:
  • a suspended bridge is provided at the intersection of the second part of the bus resonator.
  • the suspended bridge is used to connect the traces in the same arrangement direction and insulate the traces in different arrangement directions.
  • flip-chip is a chip interconnection technology in traditional integrated circuits, and because it is compatible with superconducting quantum circuits, it has become the main interconnection technology for multi-layer dense wiring of 2D arrays of superconducting qubits.
  • the qubit layer chip and the lead layer chip can be manufactured separately and vertically interconnected through superconducting bump bonding, effectively isolating the impact of lead crosstalk on qubit performance;
  • Superconducting quantum interference device is the superconducting quantum interferometer.
  • the core part of the superconducting qubit is a loop composed of two Josephson junctions connected in parallel. It is essentially a nonlinear oscillator. Its nonlinearity originates from the superconducting Josephson junction. Sen effect, the lowest two energy levels are encoded as the calculation space of qubits, and the working frequency of qubits can be modulated by the magnetic flux generated by the external current;
  • Transmon is a superconducting qubit, based on the improved design of superconducting charge qubits.
  • a bypass capacitor cross or plate structure
  • it can greatly smooth the charge dispersion relationship and effectively suppress the charge. noise.
  • the mainstream superconducting qubits in the world basically adopt this structure.
  • the two qubits mediated by the bus resonator are spatially separated.
  • the size of the transmon qubit is less than 300 ⁇ m ⁇ 300 ⁇ m.
  • the total length of the bus resonator is close to 1cm.
  • the distance between the qubits separated by the meandering arrangement is More than 3mm, achieving long-range coupling between edge qubits in a 2D array of qubits.
  • Qubit 1-bus resonator-qubit 2 constitute a three-body system, and the total Hamiltonian is as follows:
  • the first term is the qubit free term, ⁇ i represents the frequency of qubit i, represents the Pauli Z operator of qubit i; the second term is the bus resonator free term, ⁇ b represents the bus resonator frequency, a + (a) represents the photon generation (annihilation) operator; gi represents the resonance of qubit i with the bus
  • the coupling strength between devices if the self-capacitance Ci of qubit i, the self-capacitance Cb of the bus resonator and the interdigital coupling capacitance Cg,i are known, then Represents the Pauli raising (lowering) operator for qubit i.
  • the bus resonator frequency ⁇ b satisfies the dispersion strong coupling mechanism, that is,
  • the bus resonator maintains the vacuum light field state, that is, a + a ⁇ 0, so that only the virtual photons transmitted by the qubit occupy the bus resonator.
  • the total Hamiltonian Apply unit canonical transformation satisfy:
  • the transformed effective Hamiltonian is approximately:
  • J 12 (g 1 g 2 /2)(1/ ⁇ 1 +1/ ⁇ 2 ) represents the effective qubit-qubit coupling strength.
  • J12 reflects the fact that bus resonators can mediate long-range coupling between qubits.
  • the qubit can be modeled as a nonlinear LC circuit, and the bus resonator can be modeled as a linear LC circuit.
  • the bus resonator can be modeled as a linear LC circuit.
  • virtual photons only occur between the bus resonator and the qubit. exchange, thereby mediating interactions between effective qubits.
  • the two qubit frequencies ⁇ 1 /2 ⁇ and ⁇ 2 /2 ⁇ (within the range of 4-6GHz) and the self-capacitances C 1 and C 2 (determined by ⁇ 1 and ⁇ 2 respectively), given the bus resonator frequency ⁇ b /2 ⁇ (more than 1GHz larger than ⁇ 1 /2 ⁇ and ⁇ 2 /2 ⁇ ), self-capacitance C b (approximately determined by ⁇ b ) and effective qubit-qubit coupling strength J 12 /2 ⁇ (1-10MHz), calculated
  • the qubit-bus resonator coupling strengths g 1 /2 ⁇ and g 2 /2 ⁇ further obtain the coupling capacitances C g1 and C g2 .
  • the geometric parameters of the bus resonator can be designed based on the bus resonator frequency ⁇ b and the coupling capacitances C g1 and C g2 .
  • a qubit coupling structure including: a first part of a bus resonator, a first pad, a second part of the bus resonator, and a second pad;
  • the first part of the bus resonator, the first pad and the qubit unit located on the array grid point are arranged on the first chip, the second part of the bus resonator is arranged, the second pad is arranged on the second chip, and the first part of the bus resonator is Includes: interdigitated and coplanar waveguides;
  • the first chip and the second chip are bonded through bumps between the first pad and the second pad, and the qubit units are connected row by row to form a closed grid network, thereby realizing coupling between qubits at the edge of the array.
  • the qubit coupling structure also includes a qubit array.
  • the qubit array includes a grid point array repeatedly arranged in at least a first arrangement direction and a second arrangement direction, and a qubit unit arranged on the grid points;
  • the qubit unit includes a superconducting quantum interferometer, a bypass capacitor, a main capacitor arm, and a secondary capacitor arm;
  • the superconducting quantum interferometer is coupled to the bypass capacitor through a subcapacitive arm;
  • a qubit unit is capacitively coupled to the nearest qubit unit via a main capacitor arm.
  • the first part of the bus resonator is sequentially arranged along the first arrangement direction or the second arrangement direction: the interdigitated fingers corresponding to the uncoupled main capacitor arm, the coplanar waveguide and the first pad;
  • the interdigitated fingers are connected to one end of the coplanar waveguide;
  • the other end of the coplanar waveguide is connected to the first pad, and the connection point transitions from the trapezoidal width of the coplanar waveguide to the width of the first pad.
  • the length of the interdigitated fingers is l
  • the line width is w
  • a gap with a width of s is provided around the interdigitated fingers
  • the length of the coplanar waveguide is L, the width is W, and a gap of width S is provided around the coplanar waveguide;
  • the interdigital width and coplanar waveguide width are determined by the 50 ⁇ matching impedance
  • the bus resonator can be geometrically designed and the geometric parameters of the bus resonator can be determined.
  • the geometric parameters include the coplanar waveguide length (center conductor length L), width (center conductor width W and gap slot line width S), interdigital finger length (center conductor length l), finger width (center conductor width w and gap slot line width). Width s), as shown in part (a) of Figure 5.
  • the width W of the coplanar waveguide and the gap S around the waveguide are taken to be 10 ⁇ m and 5 ⁇ m respectively, and the w and s of the interdigitation are taken to be 20 ⁇ m and 10 ⁇ m respectively.
  • the interdigital length l and the coplanar waveguide length L are determined by the bus resonator frequency ⁇ b and the interdigital coupling capacitances C g1 and C g2 .
  • the relationship between length L and frequency ⁇ b is: where ⁇ represents the resonant microwave wavelength transmitted in the coplanar waveguide, c represents the vacuum light speed, and ⁇ eff represents the effective dielectric constant of the substrate.
  • ⁇ represents the resonant microwave wavelength transmitted in the coplanar waveguide
  • c represents the vacuum light speed
  • ⁇ eff represents the effective dielectric constant of the substrate.
  • the existence of the interdigitation becomes a reflection boundary, causing a frequency shift in the waveguide frequency. It is necessary to simulate the transmission characteristics of the entire bus resonator model to correct L.
  • the coupling capacitances C g1 and C g2 also need to be determined by simulation admittance characteristics.
  • the model is the coupling of the interdigital finger and a main capacitive arm of the qubit.
  • the length of the interdigital finger is parameterized.
  • the frequency sweep analysis results in a series of different sweep frequencies and different interdigits.
  • For the coupling capacitance corresponding to the finger length take the bus resonator frequency ⁇ b /2 ⁇ and the interdigit length corresponding to the coupling capacitance C g, 1 , C g, 2 as the interdigit length l required at both ends of the bus resonator respectively. .
  • the positional relationship between the interdigitated fingers and the uncoupled main capacitor arm is determined by the coupling strength. Usually, the positional relationship between the interdigitated fingers and the uncoupled main capacitor arm is determined through simulation.
  • a suspension bridge is provided at the intersection of the second part of the bus resonator to connect the traces in the same arrangement direction and make the connections between different arrangement directions trace insulation;
  • the suspended bridge includes: bridge body, third pad;
  • the third pad is connected to the second part of the bus resonator in the same direction;
  • the third bonding pad is arranged on both sides of the second part of the bus resonator in another direction;
  • the bridge spans the second part of the bus resonator in another direction, and is electrically connected to the third pads on both sides of the bus resonator in the other direction at the intersection.
  • the first pad and the second pad are square;
  • Cylindrical titanium nitride films are provided on the surfaces of both the first pad and the second pad;
  • the titanium nitride film has a preset thickness, and the cross-sectional diameter of the titanium nitride film is equal to the side length of the first pad and the second pad;
  • a cylindrical conductive pillar is provided on the surface of the titanium nitride film, and the cylindrical conductive pillar has a preset diameter and a preset height.
  • Routing design requires determining the trace patterns that make up the bus resonators based on addressability and minimizing crosstalk. Since the function of the interdigitated finger is to fix the addressing coupling parameters, in this patent, the interdigitated finger is located near the main capacitor arm of the edge qubit that requires long-range coupling on the first chip, and no wiring is required.
  • the main object of wiring design is the coplanar waveguide that constitutes the bus resonator.
  • the design methods include vertical interconnection and cross-line direct connection.
  • I, II, III, IV, V, VI, VII where I, II, III, V, VI, Part VII is provided on the first chip.
  • I and VII represent a short section connected to the interdigital short circuit
  • II and VI represent a meandering section
  • III and V represent a small section connected to the bump short circuit
  • IV represent a short circuit connection to the two bumps.
  • the total length is L.
  • Vertical interconnection embodies flip-chip design, involving III, V, and IV.
  • III, V and IV on the two chips When the two ends of III, V and IV on the two chips are routed to their respective bump positions, first transition to form square pads. Note that the square pads on the two chips need to be aligned. Then, a circular cross-section titanium nitride film and an indium pillar are grown simultaneously on the square pad. The edge of the titanium nitride film is tangent to the square structure. The edge of the indium pillar should be far away from the edge of the titanium nitride film to avoid indium bumps after bonding. Direct contact with the surface of the coplanar waveguide center conductor.
  • the width of the central conductor is 10 ⁇ m, the thickness is 100 nm, and the side length of the transition to the square pad is 25 ⁇ m; the thickness of the titanium nitride film is 50-80 nm, and the diameter is 25 ⁇ m; the thickness of the indium pillar is selected to be about 10 ⁇ m, and the diameter is about 15 ⁇ m.
  • the square pad and titanium nitride film on the first chip, the indium bumps that vertically connect the two chips, and the titanium nitride film and square pad on the second chip form vias to vertically interconnect III and IV, V and IV. , as shown in part (b) of Figure 5.
  • the direct cross-line connection occurs on the second chip, involving V.
  • the wiring of section V on the second chip is carried out along the projection line of the main capacitor arm of the qubit on the second chip.
  • Cross-line direct connection refers to the processing method when the V segments of multiple bus resonators intersect in the projection area and intersect with other control lines.
  • the cross-line adopts the air bridge process.
  • the bridge arch connection requires the center conductor of section V that needs to be crossed.
  • the bottom of the bridge passes through the coplanar waveguide that does not require a cross-line (V section of other bus resonators or control and readout lines), as shown in the figure. As shown in part (c) of 5.
  • a bus resonator can connect a group of symmetric edge qubits, and multiple bus resonators can be used to connect all symmetric edge qubits in pairs, turning the entire 2D array of qubits into a cyclic lattice network.
  • the quantum state of an edge qubit on the first chip is "exchanged” through the electric dipole interaction into a virtual photon that enters the bus resonator coupled to it, transmitted from the second chip to the other end, and then "exchanged” through the electric dipole interaction Return to the quantum state and excite symmetric edge qubits.
  • the bus resonator realizes the long-distance coupling function of two edge qubits through this process.
  • the geometric design is performed according to the bus resonator design process disclosed in some embodiments of this application. and wiring design to achieve long-range coupling of two edge qubits. Table 1 shows the circuit parameters.
  • the direct coupling parameters are calculated from the effective coupling parameters, as shown in Table 2.
  • bus resonator-mediated virtual photon exchange can occur.
  • the bus resonator geometric parameters are determined according to the impedance matching and circuit parameters, as shown in Table 3.
  • the length of each section of the coplanar waveguide is further divided as shown in Table 4.
  • the projected area of the 4 ⁇ 4 array of first chip qubits on the second chip is 1200 ⁇ m ⁇ 1200 ⁇ m
  • the cross-line direct connection length IV is 3262 ⁇ m.
  • Increasing the 2D array of qubits means extending the direct connection length IV across the wires.
  • a qubit coupling method is described in detail with reference to Figure 1 .
  • the method is suitable for flip-chip packaged quantum circuit chips.
  • the quantum circuit chip includes a first chip and a second chip bonded to each other and a qubit array.
  • the qubit array at least includes grids arranged in a first arrangement direction and a second arrangement direction. Points include at least M rows of grid points along the first arrangement direction, at least N rows of grid points along the second arrangement direction, and each row of grid points includes at least one grid point.
  • One qubit coupling method involves:
  • Step S1 Iterate through each row in the array and perform the following operations:
  • a bus resonator is used to couple the qubit units located at the grid points at both ends of the current row, where the current row is arranged along the first arrangement direction or the second arrangement direction, and the qubit unit includes a main capacitor arm, and the main capacitor arm is along the first arrangement direction. and a second arrangement direction arrangement for coupling qubit units located at nearest neighbor grid points.
  • using a bus resonator to couple the qubit units located at the grid points at both ends of the current row includes:
  • Step S11 Arrange the interdigitated fingers, coplanar waveguide and first pad corresponding to the uncoupled main capacitor arm in sequence along the lattice point extending direction to both ends of the current row; wherein, the qubit unit, The interdigitated fingers, the coplanar waveguide and the first pad are provided on the first chip;
  • Step S12 Set the second part of the bus resonator in the vertical projection direction of the current row
  • Step S13 Set the second bonding pad at the vertical projection position of the first bonding pad
  • the second part of the bus resonator, the second pad is provided on the second chip
  • Step S14 Bond the first pad and the second pad.
  • the interdigitated fingers corresponding to the uncoupled main capacitor arm, the coplanar waveguide and the first pad are sequentially provided on the uncoupled main capacitor arm, including:
  • the relative positional relationship between the main capacitor arm and the interdigitated fingers is determined through simulation.
  • the second part of setting the bus resonator in the vertical projection direction of the current row also includes:
  • a suspended bridge is provided at the intersection of the second part of the bus resonator.
  • the suspended bridge is used to connect the traces in the same arrangement direction and insulate the traces in different arrangement directions.
  • a qubit coupling structure is specifically described in conjunction with Figures 3-5.
  • the qubit can be modeled as a nonlinear LC circuit, and the bus resonator can be modeled as a linear LC circuit.
  • the bus resonator can be modeled as a linear LC circuit.
  • virtual photons only occur between the bus resonator and the qubit. exchange, thereby mediating interactions between effective qubits.
  • the two qubit frequencies ⁇ 1 /2 ⁇ and ⁇ 2 /2 ⁇ (within the range of 4-6GHz) and the self-capacitances C 1 and C 2 (determined by ⁇ 1 and ⁇ 2 respectively), given the bus resonator frequency ⁇ b /2 ⁇ (more than 1GHz larger than ⁇ 1 /2 ⁇ and ⁇ 2 /2 ⁇ ), self-capacitance C b (approximately determined by ⁇ b ) and effective qubit-qubit coupling strength J 12 /2 ⁇ (1-10MHz), calculated
  • the qubit-bus resonator coupling strengths g 1 /2 ⁇ and g 2 /2 ⁇ further obtain the coupling capacitances C g1 and C g2 .
  • the geometric parameters of the bus resonator can be designed based on the bus resonator frequency ⁇ b and the coupling capacitances C g1 and C g2 .
  • a qubit coupling structure includes: a first part of a bus resonator, a first pad, a second part of the bus resonator, and a second pad;
  • the first part of the bus resonator, the first pad and the qubit unit located on the array grid point are arranged on the first chip, the second part of the bus resonator is arranged, the second pad is arranged on the second chip, and the first part of the bus resonator is Includes: interdigitated and coplanar waveguides;
  • the first chip and the second chip are bonded through bumps between the first pad and the second pad, and the qubit units are connected row by row to form a closed grid network, thereby realizing coupling between qubits at the edge of the array.
  • the qubit coupling structure also includes a qubit array.
  • the qubit array includes a grid point array repeatedly arranged in at least a first arrangement direction and a second arrangement direction, and a qubit unit arranged on the grid points;
  • the qubit unit includes a superconducting quantum interferometer, a bypass capacitor, a main capacitor arm, and a secondary capacitor arm;
  • the superconducting quantum interferometer is coupled to the bypass capacitor through a subcapacitive arm;
  • a qubit unit is capacitively coupled to the nearest qubit unit via a main capacitor arm.
  • the first part of the bus resonator is sequentially arranged along the first arrangement direction or the second arrangement direction: the interdigitated fingers corresponding to the uncoupled main capacitor arm, the coplanar waveguide and the first pad;
  • the interdigitated fingers are connected to one end of the coplanar waveguide;
  • the other end of the coplanar waveguide is connected to the first pad, and the connection point transitions from the trapezoidal width of the coplanar waveguide to the width of the first pad.
  • the length of the interdigitated fingers is l
  • the line width is w
  • a gap with a width of s is provided around the interdigitated fingers
  • the length of the coplanar waveguide is L, the width is W, and a gap of width S is provided around the coplanar waveguide;
  • the interdigital width and coplanar waveguide width are determined by the 50 ⁇ matching impedance
  • the bus resonator can be geometrically designed and the geometric parameters of the bus resonator can be determined.
  • the geometric parameters include the coplanar waveguide length (center conductor length L), width (center conductor width W and gap slot line width S), interdigital finger length (center conductor length l), finger width (center conductor width w and gap slot line width). Width s), as shown in part (a) of Figure 5.
  • the width W of the coplanar waveguide and the gap S around the waveguide are taken to be 10 ⁇ m and 5 ⁇ m respectively, and the w and s of the interdigital fingers are taken to be 20 ⁇ m and 10 ⁇ m respectively.
  • the interdigital length l and the coplanar waveguide length L are determined by the bus resonator frequency ⁇ b and the interdigital coupling capacitances C g1 and C g2 .
  • the relationship between length L and frequency ⁇ b is: where ⁇ represents the resonant microwave wavelength transmitted in the coplanar waveguide, c represents the vacuum light speed, and ⁇ eff represents the effective dielectric constant of the substrate.
  • ⁇ represents the resonant microwave wavelength transmitted in the coplanar waveguide
  • c represents the vacuum light speed
  • ⁇ eff represents the effective dielectric constant of the substrate.
  • the existence of the interdigitation becomes a reflection boundary, causing a frequency shift in the waveguide frequency. It is necessary to simulate the transmission characteristics of the entire bus resonator model to correct L.
  • the coupling capacitances C g1 and C g2 also need to be determined by simulation admittance characteristics.
  • the model is the coupling of the interdigital finger and a main capacitive arm of the qubit.
  • the length of the interdigital finger is parameterized.
  • the frequency sweep analysis results in a series of different sweep frequencies and different interdigits.
  • For the coupling capacitance corresponding to the finger length take the bus resonator frequency ⁇ b /2 ⁇ and the interdigit length corresponding to the coupling capacitance C g, 1 , C g, 2 as the interdigit length l required at both ends of the bus resonator respectively. .
  • the positional relationship between the interdigitated fingers and the uncoupled main capacitor arm is determined by the coupling strength. Typically, the positional relationship between the interdigitated fingers and the uncoupled main capacitor arm is determined through simulation.
  • a suspension bridge is provided at the intersection of the second part of the bus resonator to connect the traces in the same arrangement direction and make the connections between different arrangement directions trace insulation;
  • the suspended bridge includes: bridge body, third pad;
  • the third pad is connected to the second part of the bus resonator in the same direction;
  • the third bonding pad is arranged on both sides of the second part of the bus resonator in another direction;
  • the bridge spans the second part of the bus resonator in another direction, and is electrically connected to the third pads on both sides of the bus resonator in the other direction at the intersection.
  • the first pad and the second pad are square;
  • Cylindrical titanium nitride films are provided on the surfaces of both the first pad and the second pad;
  • the titanium nitride film has a preset thickness, and the cross-sectional diameter of the titanium nitride film is equal to the side length of the first pad and the second pad;
  • a cylindrical conductive pillar is provided on the surface of the titanium nitride film, and the cylindrical conductive pillar has a preset diameter and a preset height.
  • Routing design requires determining the trace patterns that make up the bus resonators based on addressability and minimizing crosstalk. Since the function of the interdigitated finger is to fix the addressing coupling parameters, in this patent, the interdigitated finger is located near the main capacitor arm of the edge qubit that requires long-range coupling on the first chip, and no wiring is required.
  • the main object of wiring design is the coplanar waveguide that constitutes the bus resonator.
  • the design methods include vertical interconnection and cross-line direct connection.
  • I, II, III, IV, V, VI, VII where I, II, III, V, VI, Part VII is provided on the first chip.
  • I and VII represent a short section connected to the interdigital short circuit
  • II and VI represent a meandering section
  • III and V represent a small section connected to the bump short circuit
  • IV represent a short circuit connection to the two bumps.
  • the total length is L.
  • Vertical interconnection embodies flip-chip design, involving III, V, and IV.
  • III, V and IV on the two chips When the two ends of III, V and IV on the two chips are routed to their respective bump positions, first transition to form square pads. Note that the square pads on the two chips need to be aligned. Then, a circular cross-section titanium nitride film and an indium pillar are grown simultaneously on the square pad. The edge of the titanium nitride film is tangent to the square structure. The edge of the indium pillar should be far away from the edge of the titanium nitride film to avoid indium bumps after bonding. Direct contact with the surface of the coplanar waveguide center conductor.
  • the width of the central conductor is 10 ⁇ m, the thickness is 100 nm, and the side length of the transition to the square pad is 25 ⁇ m; the thickness of the titanium nitride film is 50-80 nm, and the diameter is 25 ⁇ m; the thickness of the indium pillar is selected to be about 10 ⁇ m, and the diameter is about 15 ⁇ m.
  • the square pad and titanium nitride film on the first chip, the indium bumps that vertically connect the two chips, and the titanium nitride film and square pad on the second chip form vias to vertically interconnect III and IV, V and IV. , as shown in part (b) of Figure 5.
  • the direct cross-line connection occurs on the second chip, involving V.
  • the wiring of section V on the second chip is carried out along the projection line of the main capacitor arm of the qubit on the second chip.
  • Cross-line direct connection refers to the processing method when the V segments of multiple bus resonators intersect in the projection area and intersect with other control lines.
  • the cross-line adopts the air bridge process.
  • the bridge arch connection requires the center conductor of section V that needs to be crossed.
  • the bottom of the bridge passes through the coplanar waveguide that does not require a cross-line (V section of other bus resonators or control and readout lines), as shown in the figure. As shown in part (c) of 5.
  • a bus resonator can connect a group of symmetric edge qubits, and multiple bus resonators can be used to connect all symmetric edge qubits in pairs, turning the entire 2D array of qubits into a cyclic lattice network.
  • the quantum state of an edge qubit on the first chip is "exchanged” through the electric dipole interaction into a virtual photon that enters the bus resonator coupled to it, transmitted from the second chip to the other end, and then "exchanged” through the electric dipole interaction Return to the quantum state and excite symmetric edge qubits.
  • the bus resonator realizes the long-distance coupling function of two edge qubits through this process.
  • a design process of a qubit coupling structure is elaborated.
  • the qubit has a 4 ⁇ 4 array, in which one bus resonator mediates two edge qubits, and the geometry is performed according to the bus resonator design process recorded in some embodiments of this application and the structure recorded in some embodiments of this application.
  • Design and wiring design to achieve long-range coupling of two edge qubits The following table shows the circuit parameters.
  • the direct coupling parameters are calculated from the effective coupling parameters, as shown in the table below.
  • bus resonator-mediated virtual photon exchange can occur.
  • bus resonator geometric parameters based on impedance matching and circuit parameters, as shown in the table below.
  • each section of the coplanar waveguide is further divided as shown in the table below.
  • the projected area of the 4 ⁇ 4 array of first chip qubits on the second chip is 1200 ⁇ m ⁇ 1200 ⁇ m
  • the cross-line direct connection length IV is 3262 ⁇ m.
  • all mutually symmetrical qubits at the edge of the qubit 2D array are connected through long-range coupling to construct a closed lattice network.
  • the processes described above with reference to the flowcharts may be implemented as computer software programs.
  • some embodiments of the present application include a computer program product including a computer program loaded on a computer-readable medium, the computer program containing program code for performing the method illustrated in the flowchart.
  • the computer program may be downloaded and installed from the network through the communication device, or from memory, or from ROM.
  • the computer program is executed by an external processor, the above-described functions defined in the methods of some embodiments of the application are performed.
  • the computer-readable medium in some embodiments of the present application may be a computer-readable signal medium or a non-volatile computer-readable storage medium, or any combination of the above two.
  • the non-volatile computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof.
  • non-volatile computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard drives, random access memory (RAM), read only memory (ROM), Erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • a non-volatile computer-readable storage medium may be any tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device.
  • the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, in which computer-readable program code is carried. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.
  • a computer-readable signal medium may also be any computer-readable medium other than non-volatile computer-readable storage media that can be sent, propagated, or transmitted for use by or in connection with an instruction execution system, apparatus, or device program used.
  • Program code contained on a computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency, radio frequency), etc., or any suitable combination of the above.
  • the above-mentioned computer-readable medium may be included in the above-mentioned server; it may also exist separately without being assembled into the server.
  • the computer-readable medium carries one or more programs.
  • the server in response to detecting that the peripheral mode of the terminal is not activated, obtains the frame rate of the application on the terminal. ;
  • the frame rate meets the screen off condition, determine whether the user is obtaining screen information of the terminal; in response to the determination result that the user is not obtaining screen information of the terminal, control the screen to enter the immediate dimming mode.
  • Computer program code for performing the operations of some embodiments of the present application may be written in one or more programming languages, including object-oriented programming languages—such as Java, Smalltalk, C++, and Includes conventional procedural programming languages—such as "C” or similar programming languages.
  • the program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
  • the remote computer can be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (such as an Internet service provider through Internet connection).
  • LAN local area network
  • WAN wide area network
  • Internet service provider such as an Internet service provider through Internet connection

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Abstract

本申请提供一种量子比特耦合方法和结构，涉及量子计算技术领域。方法适用于倒装封装的量子电路芯片，方法包括：遍历量子比特阵列中的每一行，执行操作：使用总线谐振器耦合位于当前行两端格点上的量子比特单元，其中，当前行沿第一排列方向或第二排列方向排列，量子比特单元包括主电容臂，主电容臂沿第一排列方向和第二排列方向排布，用于耦合位于最近邻格点的量子比特单元。使用本申请记载的量子比特耦合方法，实现量子比特阵列边缘的量子比特之间的长程耦合，将整个量子比特2D阵列变成封闭的格点网络，打破硬件对执行特定量子算法的边界限制。

Description

一种量子比特耦合方法和结构
相关申请的交叉引用
本申请要求于2022年05月11日提交中国专利局，申请号为202210506504.5，申请名称为“一种量子比特耦合方法和结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及量子计算技术领域，特别涉及一种量子比特耦合方法和结构。
背景技术
超导量子电路是构建大型量子处理器的主要候选者之一，是由工作于低温环境的超导量子比特阵列及其控制、读出线组成的模拟电路。Flip-chip工艺是寻址量子比特2D阵列的一种主要制造工艺，通过将量子比特阵列与控制和读出电路单独制造在两块独立的衬底上，再使用超导凸点将两块衬底表面相应位置键合，实现电路互联，以缓解布线拥挤的问题。通常将量子比特阵列制造于第一芯片(对应于Flip-chip封装的顶部芯片)，如图1所示，以Transmon量子比特阵列为例，量子比特单元分布于矩形阵列格点上。量子比特单元包括：由约瑟夫森结(Josephson junction，JJ)构成的超导量子干涉仪(Superconducting quantum interference device,SQUID)和旁路电容，旁路电容为十字形状，十字交点位于阵列格点中心，每个量子比特单元包括四条主电容臂，三条次电容臂。主电容臂用于电容耦合最近邻量子比特单元，次电容臂用于与SQUID、控制和读出线电容耦合或电感耦合。图1中示出了由JJ构成的SQUID，未示出控制线和读出线。
对于二维量子比特阵列，阵列内部的量子比特单元可以通过主电容臂与最近邻的四个量子比特单元进行电容耦合，而位于阵列的量子比特单元存在一条不参与耦合的闲置主电容臂，位于阵列顶角的量子比特单元则存在两条不参与耦合的闲置主电容臂。边缘量子比特未完全利用，一方面会降低阵列的二比特门数量，并且随着阵列规模的提高，对二比特门降低的数量越多。例如：4×4阵列可构建32个二比特门，耦合后只有24个二比特门；6×6阵列可构建72个二比特门，耦合后只有60个。另一方面，在执行某些算法过程中，边缘量子比特可能成为算法执行的边界，例如：模拟二维量子随机行走，量子态转移到边缘量子比特上会有一定概率停止行走；模拟拓扑时间晶体，时间平移对称性会在边界处破缺。
非专利文献一记载了John M.Martinis研究组早在2018年，首次提出使用flip-chip设计2D阵列中的量子比特寻址。非专利文献二记载了John M.Martinis研究组于2019年发布的Sycamore量子处理器，处理器由两块高阻硅芯片组成，第一芯片采用矩形晶格阵列，包含54个量子比特，近邻耦合可调，第二芯片(对应于Flip-chip封装的底部芯片)对控制和读出线进行布线。非专利文献三、四记载了朱晓波研究组发布的祖冲之号量子处理器。处理器由两块蓝宝石芯片组成，第一芯片包含66个量子比特，排列成11行6列，形成二维矩形晶格图案，同样近邻耦合可调，第二芯片承载控制和读出线，两块芯片通过铟凸点对齐固定在一起。非专利文献五记载了朱诗尧团队发布的天目1号量子处理器，将6×6个具有可调近邻耦合的量子比特布局为一个方形阵列，所有量子比特位于第一芯片(蓝宝石衬底)，大段控制和读出线位于第二芯片(高阻硅衬底)，两块芯片通过铟凸点键合实现电气连接。虽然这些量子处理器对于2D阵列内部的量子比特，通过加入可调耦合器来打开或关闭近邻耦合，但是由于2D阵列边缘的量子比特之间没有 长程耦合，所以并未对其完全利用。
可见，在硬件执行特定量子算法时，存在边界限制的问题。
非专利文献一：B Foxen,J Y Mutus,E Lucero,et al.Qubit compatible superconducting interconnects[J].Quantum Sci.Technol.3,014005(2018).
非专利文献二：Frank Arute,Kunal Arya,Ryan Babbush,et al.Quantum supremacy using a programmable superconducting processor[J].Nature 574,505-510(2019).
非专利文献三：Yulin Wu,Wan-Su Bao,Sirui Cao,et al.Strong quantum computational advantage using a superconducting quantum processor[J].PhysRevLett.127.180501(2021).
非专利文献四：Qingling Zhu,Sirui Cao,Fusheng Chen,et al.Quantum Computational Advantage via 60-Qubit 24-Cycle Random Circuit Sampling[J].10.1016/j.scib.2021.10.017(2021).
非专利文献五：X Zhang,W Jiang,J Deng,et al.Observation of a symmetry-protected topological time crystal with superconducting qubits[J].arXiv:2109.05577(2021)arXiv:2109.05577(2021)。
发明内容
为了解决现有技术的问题，本申请一些实施例提供了一种量子比特耦合方法和结构，以克服现有技术中未完全利用阵列中的量子比特，进而在执行某些算法过程中，边缘量子比特成为算法执行边界的问题。为了解决上述的一个或多个技术问题，本申请采用的技术方案如下：
第一方面，提供一种量子比特耦合方法适用于倒装封装的量子电路芯片，量子电路芯片包括相互键合的第一芯片和第二芯片以及量子比特阵列，量子比特阵列至少包括按第一排列方向和第二排列方向排列的格点，沿第一排列方向至少包括M行格点，沿第二排列方向至少包括N行格点，每行格点中至少包括一个格点，方法包括：
遍历量子比特阵列中的每一行，执行以下操作：
使用总线谐振器耦合位于当前行两端格点上的量子比特单元，其中，当前行沿第一排列方向或第二排列方向排列，量子比特单元包括主电容臂，主电容臂沿第一排列方向和第二排列方向排布，用于耦合位于最近邻格点的量子比特单元。
进一步地，使用总线谐振器耦合位于当前行两端格点上的量子比特单元包括：
沿格点向当前行两端延伸方向，对未耦合的主电容臂依次设置与未耦合的主电容臂对应的叉指，共面波导和第一焊盘；其中，量子比特单元，叉指，共面波导和第一焊盘设置于第一芯片；
在当前行的垂直投影方向设置总线谐振器第二部分；
在第一焊盘的垂直投影位置设置第二焊盘；
总线谐振器第二部分，第二焊盘设置于第二芯片；
键合第一焊盘和第二焊盘。
进一步地，对未耦合的主电容臂依次设置与未耦合的主电容臂对应的叉指，共面波导和第一焊盘，包括：
根据阻抗匹配条件，获取叉指宽度和共面波导宽度；
根据总线谐振器频率和叉指耦合电容，获取叉指长度和共面波导长度；
根据耦合强度，获得未耦合的主电容臂与叉指的位置关系；
通过仿真确定主电容臂与叉指的相对位置关系。
进一步地，在当前行的垂直投影方向设置总线谐振器第二部分还包括：
在总线谐振器第二部分的交叉处设置悬空桥，悬空桥用于连接同一排列方向上的走线并且使不同排列方向之间的走线绝缘。
第二方面，提供一种量子比特耦合结构，结构包括：总线谐振器第一部分，第一焊盘，总线谐振器第二部分，第二焊盘；
其中，总线谐振器第一部分，第一焊盘和位于阵列格点上的量子比特单元设置于第一芯片，总线谐振器第二部分，第二焊盘设置于第二芯片，总线谐振器第一部分包括：叉指和共面波导；
第一芯片与第二芯片通过第一焊盘与第二焊盘之间的凸点键合，将量子比特单元逐行连接成为封闭格点网络，实现阵列边缘量子比特之间的耦合。
进一步地，量子比特耦合结构还包括量子比特阵列，量子比特阵列包括至少按第一排列方向和第二排列方向重复排列的格点阵列，以及设置于格点上的量子比特单元；
量子比特单元包括超导量子干涉仪，旁路电容，主电容臂，次电容臂；
超导量子干涉仪通过次电容臂与旁路电容耦合；
量子比特单元通过主电容臂电容耦合最近的量子比特单元。
进一步地，总线谐振器第一部分沿第一排列方向或第二排列方向依次设置：与未耦合的主电容臂对应的叉指，共面波导和第一焊盘；
叉指与共面波导的一端连接；
共面波导的另一端连接第一焊盘，连接处由共面波导的宽度梯形过渡至第一焊盘的宽度。
进一步地，叉指的线宽为w，指长为l，叉指周围设置有宽度为s的间隙；
共面波导长度为L，宽度为W，共面波导周围设置有宽度为S的间隙；
当上述量子比特耦合结构应用于蓝宝石衬底的量子电路芯片时，W/S＝10:5，w/s＝10:5；
当上述量子比特耦合结构应用于高阻硅衬底的量子电路芯片时，W/S＝10:6，w/s＝10:6；
叉指宽度和共面波导宽度由50Ω匹配阻抗决定；
叉指长度和共面波导长度由总线谐振器频率和叉指耦合电容决定；
叉指与未耦合的主电容臂的位置关系由耦合强度决定。
进一步地，总线谐振器第二部分的走线周围设置有间隙，间隙宽度为S；
在第二芯片上，总线谐振器第二部分的交叉点设置有悬空桥，用于连接同一排列方向上的走线，并且使不同排列方向之间的走线绝缘；
悬空桥包括：桥体，第三焊盘；
第三焊盘与同一走向的总线谐振器第二部分连接；
第三焊盘设置于另一走向的总线谐振器第二部分两侧；
桥体跨域另一走向的总线谐振器第二部分，并且在交叉处与另一走向的总线谐振器两侧的第三焊盘电性连接。
进一步地，第一焊盘和第二焊盘为正方形；
第一焊盘和第二焊盘的表面均设置有圆柱形氮化钛膜；
氮化钛膜具有预设厚度，氮化钛膜横截面直径与第一焊盘和第二焊盘的边长相等；
氮化钛膜表面设置有圆柱形导电柱，圆柱形导电柱具有预设直径和预设高度。
本申请一些实施例提供的技术方案带来的有益效果是：
1.使用本申请公开的总线谐振器的耦合方式，实现量子比特阵列边缘的量子比特之间的长程耦合，将整个量子比特2D阵列变成封闭的格点网络，打破硬件对执行特定量子算法的边界限制；
2.增加了可构建的两比特门的数量，对于有限量子比特阵列规模的量子处理器而 言，增加两比特门的数量可以增加可编码的量子线路；
3.本申请在实现阵列边缘量子比特长程耦合的前提下与现有flip-chip工艺兼容；
4.采用本申请公开的flip-chip设计的总线谐振器，对约瑟夫森结串扰微弱，保障量子比特工作性能。
附图说明
为了更清楚地说明本申请一些实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种传统量子比特阵列和flip-chip封装量子电路芯片的示意图；
其中，图1a是一种传统量子比特阵列的示意图；
图1b是一种flip-chip封装量子电路芯片的示意图；
图2是本申请一些实施例提供的一种量子比特耦合方法示意图；
图3是本申请一些实施例提供的一种总线谐振器介导两个阵列边缘量子比特长程耦合示意图；
图4是本申请一些实施例提供的一种量子比特阵列和量子比特单元示意图；
图5是本申请一些实施例提供的一种总线谐振器结构和设计示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的一些实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。说明书附图中的编号，仅表示对各个功能部件或模块的区分，不表示部件或模块之间的逻辑关系。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面，将参照附图详细描述根据本公开的各个实施例。需要注意的是，在附图中，将相同的附图标记赋予基本上具有相同或类似结构和功能的组成部分，并且将省略关于它们的重复描述。
现有的超导量子电路架构如图1所示。如图1a，以4×4阵列为例(寻址量子比特的控制可读出线未画出)。2D超导量子比特阵列边缘的量子比特未被完全利用，即有闲置的主电容臂。图1b示意了2D阵列的flip-chip设计，第一芯片(对应于flip-chip封装的顶部芯片)包含所有量子比特组成的2D阵列以及一小段读出和控制线，第二芯片(对应于flip-chip封装的底部芯片)包含大段读出和控制线以及其他辅助元件，将第一芯片倒装后与第二芯片通过凸点键合封装，得到超导量子处理器。
为了解决现有技术中未完全利用阵列中的量子比特，进而在执行某些算法过程中， 边缘量子比特成为算法执行边界的问题。本申请公开一种量子比特耦合方法和结构，将量子比特阵列耦合成为封闭的格点网络，具体的技术方案如下：
在一些实施例中，提供一种量子比特耦合方法适用于倒装封装的量子电路芯片，量子电路芯片包括相互键合的第一芯片和第二芯片以及量子比特阵列，量子比特阵列至少包括按第一排列方向和第二排列方向排列的格点，沿第一排列方向至少包括M行格点，沿第二排列方向至少包括N行格点，每行格点中至少包括一个格点。一种量子比特耦合方法包括：
步骤S1：遍历阵列中的每一行，执行以下操作：
使用总线谐振器耦合位于当前行两端格点上的量子比特单元，其中，当前行沿第一排列方向或第二排列方向排列，量子比特单元包括主电容臂，主电容臂沿第一排列方向和第二排列方向排布，用于耦合位于最近邻格点的量子比特单元。
具体地，如图2所示，使用总线谐振器耦合位于当前行两端格点上的量子比特单元包括：
步骤S11：沿格点向当前行两端延伸方向，对未耦合的主电容臂依次设置与未耦合的主电容臂对应的叉指，共面波导和第一焊盘；其中，量子比特单元，叉指，共面波导和第一焊盘设置于第一芯片；
步骤S12：在当前行的垂直投影方向设置总线谐振器第二部分；
步骤S13：在第一焊盘的垂直投影位置设置第二焊盘；
总线谐振器第二部分，第二焊盘设置于第二芯片；
步骤S14：键合第一焊盘和第二焊盘。
具体地，对未耦合的主电容臂依次设置与未耦合的主电容臂对应的叉指，共面波导和第一焊盘，包括：
根据阻抗匹配条件，获取叉指宽度和共面波导宽度；
根据总线谐振器频率和叉指耦合电容，获取叉指长度和共面波导长度；
根据耦合强度，获得未耦合的主电容臂与叉指的位置关系；
通过仿真确定主电容臂与叉指的相对位置关系。
具体地，在当前行的垂直投影方向设置总线谐振器第二部分还包括：
在总线谐振器第二部分的交叉处设置悬空桥，悬空桥用于连接同一排列方向上的走线并且使不同排列方向之间的走线绝缘。
需要说明的是：倒装芯片(flip-chip)是传统集成电路中的一种芯片互联技术，又因与超导量子电路兼容而成为对超导量子比特2D阵列多层密集布线的主要互联技术之一，量子比特层芯片和引线层芯片可以单独制造，通过超导凸点键合垂直互联，有效隔离引线串扰对量子比特性能的影响；
Superconducting quantum interference device，SQUID，即超导量子干涉仪，超导量子比特的核心部分，由两个约瑟夫森结并联在一起构成的回路，本质上是非线性振荡器，其非线性源于超导约瑟夫森效应，最低两个能级被编码为量子比特的计算空间，量子比特工作频率能被外加电流产生的磁通调制；
Transmon是一种超导量子比特，基于超导电荷量子比特的改良设计，通过在约瑟夫森结回路之外并联一个旁路电容器(十字或平板结构)，可以极大平滑电荷色散关系，有效压制电荷噪音。目前国际上主流的超导量子比特基本上都采用这种结构。
以下将详细阐述本申请一些实施例所依据的具体原理。
在超导量子电路中，量子比特与量子比特耦合有两种方式：一种是近邻电容耦合，即两个量子比特各自的一条主电容臂相互靠近以满足寻址耦合参数要求，如图1所示，现方案中2D阵列内部的量子比特之间耦合采用这种方式。可以进一步在两个量子比特之间插入一个可调耦合器调谐近邻耦合。另一种是通过总线谐振器介导耦合，总线谐振器 充当量子比特长程耦合的媒介，与量子比特只发生虚光子交换，因此是一种有效的量子数据总线结构，本专利采用这种耦合方式。通过总线谐振器介导的两个量子比特，空间上是隔开的，一般transmon量子比特的尺寸小于300μm×300μm，总线谐振器总长度接近1cm，通过蜿蜒排布后隔开的量子比特距离超过3mm，实现量子比特2D阵列中边缘量子比特之间的长程耦合。
量子比特1-总线谐振器-量子比特2构成一个三体系统，总哈密顿量如下：
Figure PCTCN2022138770-appb-000001
其中第一项为量子比特自由项，ωi表示量子比特i的频率，
Figure PCTCN2022138770-appb-000002
表示量子比特i的泡利Z算符；第二项为总线谐振器自由项，ωb表示总线谐振器频率，a +(a)表示光子产生(湮灭)算符；gi表示量子比特i与总线谐振器之间的耦合强度，如果已知量子比特i的自电容Ci、总线谐振器的自电容Cb和叉指耦合电容Cg,i，则
Figure PCTCN2022138770-appb-000003
表示量子比特i的泡利升(降)算符。
总线谐振器的正常工作需要保证两点：
1.总线谐振器频率ω b满足色散强耦合机制，即|ω b-ω i|＞＞g i，这样量子比特状态变化对总线谐振器来说相当于微扰；
2.总线谐振器维持真空光场状态，即a +a≈0，这样总线谐振器中只有量子比特传递的虚光子占据。在该条件下对总哈密顿量
Figure PCTCN2022138770-appb-000004
施加单位正则变换
Figure PCTCN2022138770-appb-000005
满足：
Figure PCTCN2022138770-appb-000006
其中，Δ i＝ω i-ω b表示频率失谐。变换后的有效哈密顿量近似为：
Figure PCTCN2022138770-appb-000007
其中，
Figure PCTCN2022138770-appb-000008
是与量子比特状态相关的频率偏移，J 12＝(g 1g 2/2)(1/Δ 1+1/Δ 2)表示有效量子比特-量子比特耦合强度。J12就反映了总线谐振器可介导量子比特之间的长程耦合。
如图3所示，量子比特可模型化为非线性LC电路，总线谐振器可模型化为线性LC电路，色散强耦合和真空光场条件下，总线谐振器只与量子比特之间发生虚光子交换，从而介导有效量子比特之间相互作用。
已知两个量子比特频率ω 1/2π、ω 2/2π(4-6GHz范围内)和自电容C 1、C 2(分别由ω 1、ω 2决定)，给定总线谐振器频率ω b/2π(比ω 1/2π、ω 2/2π大1GHz以上)、自电容C b(近似由ω b决定)和有效量子比特-量子比特耦合强度J 12/2π(1-10MHz)，计算得到量子比特-总线谐振器耦合强度g 1/2π、g 2/2π，进一步得到耦合电容C g1、C g2。由总线谐振器 频率ω b和耦合电容C g1、C g2就可以设计总线谐振器的几何参数。
在本申请一些实施例中，提供一种量子比特耦合结构，包括：总线谐振器第一部分，第一焊盘，总线谐振器第二部分，第二焊盘；
其中，总线谐振器第一部分，第一焊盘和位于阵列格点上的量子比特单元设置于第一芯片，总线谐振器第二部分，第二焊盘设置于第二芯片，总线谐振器第一部分包括：叉指和共面波导；
第一芯片与第二芯片通过第一焊盘与第二焊盘之间的凸点键合，将量子比特单元逐行连接成为封闭格点网络，实现阵列边缘量子比特之间的耦合。
具体地，量子比特耦合结构还包括量子比特阵列，量子比特阵列包括至少按第一排列方向和第二排列方向重复排列的格点阵列，以及设置于格点上的量子比特单元；
如图4所示，量子比特单元包括超导量子干涉仪，旁路电容，主电容臂，次电容臂；
超导量子干涉仪通过次电容臂与旁路电容耦合；
量子比特单元通过主电容臂电容耦合最近的量子比特单元。
具体地，总线谐振器第一部分沿第一排列方向或第二排列方向依次设置：与未耦合的主电容臂对应的叉指，共面波导和第一焊盘；
叉指与共面波导的一端连接；
共面波导的另一端连接第一焊盘，连接处由共面波导的宽度梯形过渡至第一焊盘的宽度。
具体地，叉指的指长为l，线宽为w，叉指周围设置有宽度为s的间隙；
共面波导长度为L，宽度为W，共面波导周围设置有宽度为S的间隙；
当上述量子比特耦合结构应用于蓝宝石衬底的量子电路芯片时，W/S＝10:5，w/s＝10:5；
当上述量子比特耦合结构应用于高阻硅衬底的量子电路芯片时，W/S＝10:6，w/s＝10:6；
叉指宽度和共面波导宽度由50Ω匹配阻抗决定；
根据阻抗匹配和电路参数可以对总线谐振器进行几何设计，确定总线谐振器的几何参数。几何参数包括共面波导长度(中心导体长度L)、宽度(中心导体宽度W与间隙槽线宽度S)和叉指指长(中心导体长度l)、指宽(中心导体宽度w与间隙槽线宽度s)，如图5中(a)部分所示。
当第一芯片和第二芯片都选择蓝宝石衬底，共面波导的宽度W和波导周围间隙S分别取10μm和5μm，叉指的w和s分别取20μm和10μm。
叉指长度l和共面波导长度L由总线谐振器频率ω b和叉指耦合电容C g1、C g2决定。对于两端不含叉指的二分之波长共面波导，长度L与频率ω b之间满足关系：
Figure PCTCN2022138770-appb-000009
其中λ表示共面波导中传输的共振微波波长，c表示真空光速，ε eff表示衬底有效介电常数。但是叉指的存在成为反射边界，导致波导频率频移，需要仿真整个总线谐振器模型的传输特性对L进行修正。耦合电容C g1、C g2也需要仿真导纳特性确定，模型为叉指和量子比特的一条主电容臂耦合，对叉指指长参数化，扫频分析得到一系列不同扫频频率、不同叉指指长对应的耦合电容，取总线谐振器频率ω b/2π和耦合电容C g，1、C g，2对应的叉指指长分别作为总线谐振器两端所需的叉指指长l。
叉指与未耦合的主电容臂的位置关系由耦合强度决定。通常，通过仿真确定叉指与 未耦合主电容臂之间的位置关系。
总线谐振器第二部分的走线周围设置有间隙，间隙宽度为S；
在第二芯片上，如图5中(c)部分所示，总线谐振器第二部分的交叉点设置有悬空桥，用于连接同一排列方向上的走线，并且使不同排列方向之间的走线绝缘；
悬空桥包括：桥体，第三焊盘；
第三焊盘与同一走向的总线谐振器第二部分连接；
第三焊盘设置于另一走向的总线谐振器第二部分两侧；
桥体跨域另一走向的总线谐振器第二部分，并且在交叉处与另一走向的总线谐振器两侧的第三焊盘电性连接。
具体地，如图5中(b)部分所示，第一焊盘和第二焊盘为正方形；
第一焊盘和第二焊盘的表面均设置有圆柱形氮化钛膜；
氮化钛膜具有预设厚度，氮化钛膜横截面直径与第一焊盘和第二焊盘的边长相等；
氮化钛膜表面设置有圆柱形导电柱，圆柱形导电柱具有预设直径和预设高度。
布线设计需要根据可寻址性和串扰最小化确定组成总线谐振器的走线形式。由于叉指的作用是固定寻址耦合参数，在本专利中叉指位于第一芯片上需要长程耦合的边缘量子比特主电容臂附近，不需要布线。布线设计的对象主要是组成总线谐振器的共面波导，设计方法包括垂直互联和跨线直连。
为简化描述，以一条总线谐振器为例，假设将共面波导分为7段，标注为Ⅰ、Ⅱ、Ⅲ、Ⅳ、Ⅴ、Ⅵ、Ⅶ，其中，Ⅰ、Ⅱ、Ⅲ、Ⅴ、Ⅵ、Ⅶ部分设置于第一芯片。如图5所示，Ⅰ和Ⅶ表示与叉指短路连接的一小段，Ⅱ和Ⅵ表示蜿蜒段，Ⅲ和Ⅴ表示与凸点短路连接的一小段，Ⅳ表示与两个凸点短路连接的直连段，只有Ⅳ位于第二芯片，其他各段位于第一芯片，总长度为L。
垂直互联体现的就是flip-chip设计，涉及Ⅲ和Ⅴ、Ⅳ。当两块芯片上的Ⅲ和Ⅴ以及Ⅳ的两端走线到各自的凸点位置时，先过渡形成方形焊盘，注意两块芯片上的方形焊盘需要对齐。然后在方形焊盘上同步生长圆形截面的氮化钛膜和铟柱，氮化钛膜边缘与方形结构相切，铟柱边缘要远离氮化钛膜边缘，以免键合后的铟凸点直接接触共面波导中心导体表面。比如，中心导体宽度为10μm，厚度为100nm，过渡到方形焊盘的边长为25μm；氮化钛膜的厚度为50-80nm，直径为25μm；铟柱的厚度选择在10μm左右，直径约为15μm。第一芯片上的方形焊盘和氮化钛膜、垂直连接两块芯片的铟凸点、第二芯片上的氮化钛膜和方形焊盘形成通路，将Ⅲ和Ⅳ、Ⅴ和Ⅳ垂直互联，如图5中(b)部分所示。
跨线直连发生在第二芯片，涉及Ⅴ。为了尽可能减少布线对第一芯片上量子比特的影响，Ⅴ段在第二芯片上的布线沿量子比特的主电容臂在第二芯片上的投影线进行。跨线直连指的是多条总线谐振器的Ⅴ段在投影区域交叉以及与其他控制线交叉时的处理方式。跨线采用空气桥工艺，桥拱连接需要Ⅴ段需要跨线的中心导体，桥底穿过不需要跨线的共面波导(其他总线谐振器的Ⅴ段或控制和读出线)，如图5中(c)部分所示。一条总线谐振器可连接一组对称的边缘量子比特，使用多条总线谐振器将所有对称的边缘量子比特两两连接，可将整个量子比特2D阵列变成可循环的格点网络。第一芯片上一个边缘量子比特的量子态通过电偶极相互作用“交换”成虚光子进入与其耦合的总线谐振器，从第二芯片传输到另一端，再通过电偶极相互作用“交换”回量子态，激发对称的边缘量子比特。总线谐振器通过该过程实现两个边缘量子比特长程耦合的功能。
在本申请一些实施例中，以量子比特4×4阵列的其中一条总线谐振器介导两个边缘量子比特为例，按照在本申请一些实施例中公开的总线谐振器设计流程，进行几何设计和布线设计，实现两个边缘量子比特的长程耦合。其中表1示出了电路参数。
表1电路参数
Figure PCTCN2022138770-appb-000010
由有效耦合参数计算得到直接耦合参数，如表2所示。
表2直接耦合参数
Figure PCTCN2022138770-appb-000011
给定频率满足|ω i-ω b|＞＞g i，可发生总线谐振器介导的虚光子交换。根据阻抗匹配和电路参数确定总线谐振器几何参数，如表3所示。
表3总线谐振器几何参数
Figure PCTCN2022138770-appb-000012
进一步划分共面波导各段长度如表4所示。
表4共面波导各段长度
编号 Ⅰ Ⅱ Ⅲ Ⅳ Ⅴ Ⅵ Ⅶ
长度 250μm 1742.5μm 281μm 3262μm 281μm 1742.5μm 250μm
按每个transmon量子比特的尺寸为300μm×300μm计算，第一芯片量子比特4×4阵列在第二芯片上的投影区域为1200μm×1200μm，跨线直连长度Ⅳ为3262μm。增加量子比特2D阵列意味着延长跨线直连长度Ⅳ。
扩展到多条总线谐振器，将量子比特2D阵列边缘所有相互对称的量子比特通过长程耦合连接起来，构造成封闭的格点网络。
上述所有可选技术方案，可以采用任意结合形成本申请的可选实施例，在此不再一一赘述。
在本申请一些实施例中，结合图1，具体阐述一种量子比特耦合方法。该方法适用于倒装封装的量子电路芯片，量子电路芯片包括相互键合的第一芯片和第二芯片以及量子比特阵列，量子比特阵列至少包括按第一排列方向和第二排列方向排列的格点，沿第一排列方向至少包括M行格点，沿第二排列方向至少包括N行格点，每行格点中至少包括一个格点。一种量子比特耦合方法包括：
步骤S1：遍历阵列中的每一行，执行以下操作：
使用总线谐振器耦合位于当前行两端格点上的量子比特单元，其中，当前行沿第一排列方向或第二排列方向排列，量子比特单元包括主电容臂，主电容臂沿第一排列方向和第二排列方向排布，用于耦合位于最近邻格点的量子比特单元。
具体地，如图1所示，使用总线谐振器耦合位于当前行两端格点上的量子比特单元包括：
步骤S11：沿格点向当前行两端延伸方向，对未耦合的主电容臂依次设置与未耦合的主电容臂对应的叉指，共面波导和第一焊盘；其中，量子比特单元，叉指，共面波导和第一焊盘设置于第一芯片；
步骤S12：在当前行的垂直投影方向设置总线谐振器第二部分；
步骤S13：在第一焊盘的垂直投影位置设置第二焊盘；
总线谐振器第二部分，第二焊盘设置于第二芯片；
步骤S14：键合第一焊盘和第二焊盘。
具体地，对未耦合的主电容臂依次设置与未耦合的主电容臂对应的叉指，共面波导和第一焊盘，包括：
根据阻抗匹配条件，获取叉指宽度和共面波导宽度；
根据总线谐振器频率和叉指耦合电容，获取叉指长度和共面波导长度；
根据耦合强度，获得未耦合的主电容臂与叉指的位置关系；
通过仿真确定主电容臂与叉指的相对位置关系。
具体地，在当前行的垂直投影方向设置总线谐振器第二部分还包括：
在总线谐振器第二部分的交叉处设置悬空桥，悬空桥用于连接同一排列方向上的走线并且使不同排列方向之间的走线绝缘。
在本申请的一些实施例中，结合图3-图5具体阐述一种量子比特耦合结构。
如图3所示，量子比特可模型化为非线性LC电路，总线谐振器可模型化为线性LC电路，色散强耦合和真空光场条件下，总线谐振器只与量子比特之间发生虚光子交换，从而介导有效量子比特之间相互作用。
已知两个量子比特频率ω 1/2π、ω 2/2π(4-6GHz范围内)和自电容C 1、C 2(分别由ω 1、ω 2决定)，给定总线谐振器频率ω b/2π(比ω 1/2π、ω 2/2π大1GHz以上)、自电容C b(近似由ω b决定)和有效量子比特-量子比特耦合强度J 12/2π(1-10MHz)，计算得到量子比特-总线谐振器耦合强度g 1/2π、g 2/2π，进一步得到耦合电容C g1、C g2。由总线谐振器频率ω b和耦合电容C g1、C g2就可以设计总线谐振器的几何参数。
一种量子比特耦合结构，包括：总线谐振器第一部分，第一焊盘，总线谐振器第二部分，第二焊盘；
其中，总线谐振器第一部分，第一焊盘和位于阵列格点上的量子比特单元设置于第一芯片，总线谐振器第二部分，第二焊盘设置于第二芯片，总线谐振器第一部分包括：叉指和共面波导；
第一芯片与第二芯片通过第一焊盘与第二焊盘之间的凸点键合，将量子比特单元逐行连接成为封闭格点网络，实现阵列边缘量子比特之间的耦合。
具体地，量子比特耦合结构还包括量子比特阵列，量子比特阵列包括至少按第一排列方向和第二排列方向重复排列的格点阵列，以及设置于格点上的量子比特单元；
如图4所示，量子比特单元包括超导量子干涉仪，旁路电容，主电容臂，次电容臂；
超导量子干涉仪通过次电容臂与旁路电容耦合；
量子比特单元通过主电容臂电容耦合最近的量子比特单元。
具体地，总线谐振器第一部分沿第一排列方向或第二排列方向依次设置：与未耦合的主电容臂对应的叉指，共面波导和第一焊盘；
叉指与共面波导的一端连接；
共面波导的另一端连接第一焊盘，连接处由共面波导的宽度梯形过渡至第一焊盘的宽度。
具体地，叉指的指长为l，线宽为w，叉指周围设置有宽度为s的间隙；
共面波导长度为L，宽度为W，共面波导周围设置有宽度为S的间隙；
当上述量子比特耦合结构应用于蓝宝石衬底的量子电路芯片时，W/S＝10:5，w/s＝10:5；
当上述量子比特耦合结构应用于高阻硅衬底的量子电路芯片时，W/S＝10:6，w/s＝10:6；
叉指宽度和共面波导宽度由50Ω匹配阻抗决定；
根据阻抗匹配和电路参数可以对总线谐振器进行几何设计，确定总线谐振器的几何参数。几何参数包括共面波导长度(中心导体长度L)、宽度(中心导体宽度W与间隙槽线宽度S)和叉指指长(中心导体长度l)、指宽(中心导体宽度w与间隙槽线宽度s)，如图5中(a)部分所示。
当第一芯片和第二芯片都选择蓝宝石衬底，共面波导的宽度W和波导周围间隙S分别取10μm和5μm，，叉指的w和s分别取20μm和10μm。
叉指长度l和共面波导长度L由总线谐振器频率ω b和叉指耦合电容C g1、C g2决定。对于两端不含叉指的二分之波长共面波导，长度L与频率ω b之间满足关系：
Figure PCTCN2022138770-appb-000013
其中λ表示共面波导中传输的共振微波波长，c表示真空光速，ε eff表示衬底有效介电常数。但是叉指的存在成为反射边界，导致波导频率频移，需要仿真整个总线谐振器模型的传输特性对L进行修正。耦合电容C g1、C g2也需要仿真导纳特性确定，模型为叉指和量子比特的一条主电容臂耦合，对叉指指长参数化，扫频分析得到一系列不同扫频频率、不同叉指指长对应的耦合电容，取总线谐振器频率ω b/2π和耦合电容C g，1、C g，2对应的叉指指长分别作为总线谐振器两端所需的叉指指长l。
叉指与未耦合的主电容臂的位置关系由耦合强度决定。通常，通过仿真确定叉指与未耦合主电容臂之间的位置关系。
总线谐振器第二部分的走线周围设置有间隙，间隙宽度为S；
在第二芯片上，如图5中(c)部分所示，总线谐振器第二部分的交叉点设置有悬空桥，用于连接同一排列方向上的走线，并且使不同排列方向之间的走线绝缘；
悬空桥包括：桥体，第三焊盘；
第三焊盘与同一走向的总线谐振器第二部分连接；
第三焊盘设置于另一走向的总线谐振器第二部分两侧；
桥体跨域另一走向的总线谐振器第二部分，并且在交叉处与另一走向的总线谐振器两侧的第三焊盘电性连接。
具体地，如图5中(b)部分所示，第一焊盘和第二焊盘为正方形；
第一焊盘和第二焊盘的表面均设置有圆柱形氮化钛膜；
氮化钛膜具有预设厚度，氮化钛膜横截面直径与第一焊盘和第二焊盘的边长相等；
氮化钛膜表面设置有圆柱形导电柱，圆柱形导电柱具有预设直径和预设高度。
布线设计需要根据可寻址性和串扰最小化确定组成总线谐振器的走线形式。由于叉指的作用是固定寻址耦合参数，在本专利中叉指位于第一芯片上需要长程耦合的边缘量子比特主电容臂附近，不需要布线。布线设计的对象主要是组成总线谐振器的共面波导，设计方法包括垂直互联和跨线直连。
为简化描述，以一条总线谐振器为例，假设将共面波导分为7段，标注为Ⅰ、Ⅱ、Ⅲ、Ⅳ、Ⅴ、Ⅵ、Ⅶ，其中，Ⅰ、Ⅱ、Ⅲ、Ⅴ、Ⅵ、Ⅶ部分设置于第一芯片。如图5所示，Ⅰ和Ⅶ表示与叉指短路连接的一小段，Ⅱ和Ⅵ表示蜿蜒段，Ⅲ和Ⅴ表示与凸点短路连接的一小段，Ⅳ表示与两个凸点短路连接的直连段，只有Ⅳ位于第二芯片，其他各段位于第一芯片，总长度为L。
垂直互联体现的就是flip-chip设计，涉及Ⅲ和Ⅴ、Ⅳ。当两块芯片上的Ⅲ和Ⅴ以及Ⅳ的两端走线到各自的凸点位置时，先过渡形成方形焊盘，注意两块芯片上的方形焊 盘需要对齐。然后在方形焊盘上同步生长圆形截面的氮化钛膜和铟柱，氮化钛膜边缘与方形结构相切，铟柱边缘要远离氮化钛膜边缘，以免键合后的铟凸点直接接触共面波导中心导体表面。比如，中心导体宽度为10μm，厚度为100nm，过渡到方形焊盘的边长为25μm；氮化钛膜的厚度为50-80nm，直径为25μm；铟柱的厚度选择在10μm左右，直径约为15μm。第一芯片上的方形焊盘和氮化钛膜、垂直连接两块芯片的铟凸点、第二芯片上的氮化钛膜和方形焊盘形成通路，将Ⅲ和Ⅳ、Ⅴ和Ⅳ垂直互联，如图5中(b)部分所示。
跨线直连发生在第二芯片，涉及Ⅴ。为了尽可能减少布线对第一芯片上量子比特的影响，Ⅴ段在第二芯片上的布线沿量子比特的主电容臂在第二芯片上的投影线进行。跨线直连指的是多条总线谐振器的Ⅴ段在投影区域交叉以及与其他控制线交叉时的处理方式。跨线采用空气桥工艺，桥拱连接需要Ⅴ段需要跨线的中心导体，桥底穿过不需要跨线的共面波导(其他总线谐振器的Ⅴ段或控制和读出线)，如图5中(c)部分所示。一条总线谐振器可连接一组对称的边缘量子比特，使用多条总线谐振器将所有对称的边缘量子比特两两连接，可将整个量子比特2D阵列变成可循环的格点网络。第一芯片上一个边缘量子比特的量子态通过电偶极相互作用“交换”成虚光子进入与其耦合的总线谐振器，从第二芯片传输到另一端，再通过电偶极相互作用“交换”回量子态，激发对称的边缘量子比特。总线谐振器通过该过程实现两个边缘量子比特长程耦合的功能。
在本申请的一些实施例中，详细阐述一种量子比特耦合结构的设计过程。该量子比特具有4×4阵列，其中一条总线谐振器介导两个边缘量子比特，按照在本申请一些实施例中记载的总线谐振器设计流程和在本申请一些实施例中记载的结构进行几何设计和布线设计，实现两个边缘量子比特的长程耦合。下表示出了电路参数。
Figure PCTCN2022138770-appb-000014
由有效耦合参数计算得到直接耦合参数，如下表所示。
Figure PCTCN2022138770-appb-000015
给定频率满足|ω i-ω b|＞＞g i，可发生总线谐振器介导的虚光子交换。根据阻抗匹配和电路参数确定总线谐振器几何参数，如下表所示。
Figure PCTCN2022138770-appb-000016
进一步划分共面波导各段长度如下表所示。
编号 Ⅰ Ⅱ Ⅲ Ⅳ Ⅴ Ⅵ Ⅶ
长度 250μm 1742.5μm 281μm 3262μm 281μm 1742.5μm 250μm
按每个transmon量子比特的尺寸为300μm×300μm计算，第一芯片量子比特4×4阵列在第二芯片上的投影区域为1200μm×1200μm，跨线直连长度Ⅳ为3262μm。扩展到多条总线谐振器，将量子比特2D阵列边缘所有相互对称的量子比特通过长程耦合连接起来，构造成封闭的格点网络。
特别地，根据本申请的一些实施例，上文参考流程图描述的过程可以被实现为计算 机软件程序。例如，本申请的一些实施例包括一种计算机程序产品，其包括装载在计算机可读介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信装置从网络上被下载和安装，或者从存储器被安装，或者从ROM被安装。在该计算机程序被外部处理器执行时，执行本申请的一些实施例的方法中限定的上述功能。
需要说明的是，本申请的一些实施例的计算机可读介质可以是计算机可读信号介质或者非易失性计算机可读存储介质或者是上述两者的任意组合。非易失性计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。非易失性计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本申请的一些实施例中，非易失性计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本申请的一些实施例中，计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读信号介质还可以是非易失性计算机可读存储介质以外的任何计算机可读介质，该计算机可读信号介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：电线、光缆、RF(Radio Frequency,射频)等等，或者上述的任意合适的组合。
上述计算机可读介质可以是上述服务器中所包含的；也可以是单独存在，而未装配入该服务器中。上述计算机可读介质承载有一个或者多个程序，当上述一个或者多个程序被该服务器执行时，使得该服务器：响应于检测到终端的外设模式未激活时，获取终端上应用的帧率；在帧率满足息屏条件时，判断用户是否正在获取终端的屏幕信息；响应于判断结果为用户未获取终端的屏幕信息，控制屏幕进入立即暗淡模式。
可以以一种或多种程序设计语言或其组合来编写用于执行本申请的一些实施例的操作的计算机程序代码，程序设计语言包括面向对象的程序设计语言—诸如Java,Smalltalk,C++，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络——包括局域网(LAN)或广域网(WAN)—连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统或系统实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。以上所描述的系统及系统实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本申请一些实施例方案的目的。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。
以上对本申请所提供的技术方案进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及 应用范围上均会有改变之处。综上所述，本说明书内容不应理解为对本申请的限制。
以上所述仅为本申请的较佳实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种量子比特耦合方法，适用于倒装封装的量子电路芯片，所述量子电路芯片包括相互键合的第一芯片和第二芯片以及量子比特阵列，所述量子比特阵列至少包括按第一排列方向和第二排列方向排列的格点，沿所述第一排列方向至少包括M行格点，沿所述第二排列方向至少包括N行格点，每行格点中至少包括一个格点，其特征在于，所述方法包括：
    遍历所述量子比特阵列中的每一行，执行以下操作：
    使用总线谐振器耦合位于当前行两端格点上的量子比特单元，其中，所述当前行沿所述第一排列方向或所述第二排列方向排列，所述量子比特单元包括主电容臂，所述主电容臂沿所述第一排列方向和所述第二排列方向排布，用于耦合位于最近邻格点的量子比特单元。
  2. 根据权利要求1所述的一种量子比特耦合方法，其特征在于，所述使用总线谐振器耦合位于当前行两端格点上的量子比特单元包括：
    沿格点向所述当前行两端延伸方向，对未耦合的主电容臂依次设置与所述未耦合的主电容臂对应的叉指，共面波导和第一焊盘；其中，所述量子比特单元，所述叉指，所述共面波导和所述第一焊盘设置于第一芯片；
    在所述当前行的垂直投影方向设置总线谐振器第二部分；
    在所述第一焊盘的垂直投影位置设置第二焊盘；
    所述总线谐振器第二部分，所述第二焊盘设置于第二芯片；
    键合所述第一焊盘和所述第二焊盘。
  3. 根据权利要求2所述的一种量子比特耦合方法，其特征在于，所述对未耦合的主电容臂依次设置与所述未耦合的主电容臂对应的叉指，共面波导和第一焊盘，包括：
    获取所述总线谐振器的几何参数，以及所述未耦合的主电容臂与对应的叉指的位置关系；所述总线谐振器的几何参数包括所述叉指和所述共面波导的几何参数；
    根据所述叉指和所述共面波导的几何参数，以及所述未耦合的主电容臂与对应的叉指的位置关系，对未耦合的主电容臂依次设置与所述未耦合的主电容臂对应的叉指，共面波导和第一焊盘。
  4. 根据权利要求3所述的方法，其特征在于，所述获取所述总线谐振器的几何参数，包括：
    根据阻抗匹配和电路参数对总线谐振器进行几何设计，确定所述总线谐振器的几何参数。
  5. 根据权利要求4所述的方法，其特征在于，所述共面波导的几何参数包括共面波导长度和共面波导宽度，所述叉指的几何参数包括叉指长度和叉指宽度，所述根据阻抗匹配和电路参数对总线谐振器进行几何设计，确定所述总线谐振器的几何参数，包括：
    根据阻抗匹配条件，获取所述叉指宽度和所述共面波导宽度；
    根据总线谐振器频率和叉指耦合电容，获取所述叉指长度和所述共面波导长度。
  6. 根据权利要求5所述的方法，其特征在于，所述根据总线谐振器频率和叉指耦合电容，获取所述叉指长度和所述共面波导长度，包括：
    根据总线谐振器频率与共面波导长度的关系，确定所述共面波导长度；
    根据总线谐振器频率和叉指耦合电容，确定所述叉指长度。
  7. 根据权利要求6所述的方法，其特征在于，所述根据总线谐振器频率与共面波导长度的关系，确定所述共面波导长度，包括：
    根据总线谐振器频率、衬底有效介电常数和真空光速，确定待修正共面波导长度；
    对所述待修正共面波导长度进行修正，得到共面波导长度。
  8. 根据权利要求7所述的方法，其特征在于，所述对所述待修正共面波导长度进行修正，得到共面波导长度，包括：
    根据仿真总线谐振器模型的传输特性，对所述待修正共面波导长度进行修正，得到共面波导长度。
  9. 根据权利要求6所述的方法，其特征在于，所述根据总线谐振器频率和叉指耦合电容，确定所述叉指长度，包括：
    获取在不同扫频频率下不同叉指长度对应的耦合电容；
    确定第一目标耦合电容、第二目标耦合电容以及与所述总线谐振器频率匹配的目标扫频频率；
    将在所述目标扫频频率下，所述第一目标耦合电容、所述第二目标耦合电容对应的叉指长度分别作为所述总线谐振器两端所需的叉指长度。
  10. 根据权利要求9所述的方法，其特征在于，所述获取在不同扫频频率下不同叉指长度对应的耦合电容，包括：
    基于所述叉指和所述量子比特单元的一条主电容臂耦合的模型进行扫频分析，得到在不同扫频频率下不同叉指长度对应的耦合电容。
  11. 根据权利要求5所述的方法，其特征在于，所述叉指耦合电容基于量子比特-总线谐振器耦合强度确定，所述量子比特-总线谐振器耦合强度根据所述总线谐振器频率、自电容和有效有效量子比特-量子比特耦合强度计算得到。
  12. 根据权利要求11所述的方法，其特征在于，所述获取所述未耦合的主电容臂与对应的叉指的位置关系，包括：
    根据所述耦合强度，获得所述未耦合的主电容臂与所述叉指的位置关系；
    通过仿真确定所述主电容臂与所述叉指的相对位置关系。
  13. 根据权利要求2所述的一种量子比特耦合方法，其特征在于，所述在所述当前行的垂直投影方向设置总线谐振器第二部分还包括：
    在总线谐振器第二部分的交叉处设置悬空桥，所述悬空桥用于连接同一排列方向上的走线并且使不同排列方向之间的走线绝缘。
  14. 根据权利要求2所述的方法，其特征在于，所述第一焊盘和所述第二焊盘为方形焊盘，所述键合所述第一焊盘和所述第二焊盘，包括：
    在所述第一焊盘和所述第二焊盘上同步生长圆形截面的氧化钛膜和铟柱，得到边缘与所述方形焊盘相切的氧化钛膜以及垂直连接所述第一焊盘和所述第二焊盘的铟凸点；
    所述第一芯片上的所述第一焊盘和氧化钛膜、所述铟凸点和所述第二芯片上的所述第二焊盘和氧化钛膜形成通路，以键合所述第一焊盘和所述第二焊盘。
  15. 一种量子比特耦合结构，其特征在于，所述结构包括：总线谐振器第一部分，第一焊盘，总线谐振器第二部分，第二焊盘；
    其中，所述总线谐振器第一部分，所述第一焊盘和位于阵列格点上的量子比特单元设置于第一芯片，所述总线谐振器第二部分，第二焊盘设置于第二芯片，所述总线谐振器第一部分包括：叉指和共面波导；
    所述第一芯片与所述第二芯片通过所述第一焊盘与所述第二焊盘之间的凸点键合，将量子比特单元逐行连接成为封闭格点网络，实现阵列边缘量子比特之间的耦合。
  16. 根据权利要求15所述的一种量子比特耦合结构，其特征在于，所述结构还包括量子比特阵列，所述量子比特阵列包括至少按第一排列方向和第二排列方向重复排列的格点阵列，以及设置于格点上的量子比特单元；
    所述量子比特单元包括超导量子干涉仪，旁路电容，主电容臂，次电容臂；
    所述超导量子干涉仪通过所述次电容臂与旁路电容耦合；
    所述量子比特单元通过所述主电容臂电容耦合最近的量子比特单元。
  17. 根据权利要求16所述的一种量子比特耦合结构，其特征在于，所述总线谐振器第一部分沿第一排列方向或第二排列方向依次设置：与未耦合的主电容臂对应的叉指，共面波导和第一焊盘；
    所述叉指与所述共面波导的一端连接；
    所述共面波导的另一端连接第一焊盘，连接处由共面波导的宽度梯形过渡至所述第一焊盘的宽度。
  18. 根据权利要求17所述的一种量子比特耦合结构，其特征在于，所述叉指的线宽为w，指长为l，所述叉指周围设置有宽度为s的间隙；
    所述共面波导长度为L，宽度为W，所述共面波导周围设置有宽度为S的间隙；
    当所述量子比特耦合结构应用于蓝宝石衬底的量子电路芯片时，W/S＝10:5，w/s＝10:5；
    当所述量子比特耦合结构应用于高阻硅衬底的量子电路芯片时，W/S＝10:6，w/s＝10:6；
    所述叉指宽度和所述共面波导宽度由50Ω匹配阻抗决定；
    所述叉指长度和所述共面波导长度由总线谐振器频率和叉指耦合电容决定；
    所述叉指与所述未耦合的主电容臂的位置关系由耦合强度决定。
  19. 根据权利要求15所述的一种量子比特耦合结构，其特征在于，所述总线谐振器第二部分的走线周围设置有间隙，所述间隙宽度为S；
    在第二芯片上，总线谐振器第二部分的交叉点设置有悬空桥，用于连接同一排列方向上的走线，并且使不同排列方向之间的走线绝缘；
    所述悬空桥包括：桥体，第三焊盘；
    所述第三焊盘与同一走向的总线谐振器第二部分连接；
    所述第三焊盘设置于另一走向的总线谐振器第二部分两侧；
    所述桥体跨域另一走向的总线谐振器第二部分，并且在交叉处与另一走向的总线谐振器两侧的第三焊盘电性连接。
  20. 根据权利要求15所述的一种量子比特耦合结构，其特征在于，所述第一焊盘和第二焊盘为正方形；
    所述第一焊盘和所述第二焊盘的表面均设置有圆柱形氮化钛膜；
    所述氮化钛膜具有预设厚度，所述氮化钛膜横截面直径与所述第一焊盘和所述第二焊盘的边长相等；
    所述氮化钛膜表面设置有圆柱形导电柱，所述圆柱形导电柱具有预设直径和预设高度。
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