WO2023216331A1 - 半导体结构及芯片 - Google Patents

半导体结构及芯片 Download PDF

Info

Publication number
WO2023216331A1
WO2023216331A1 PCT/CN2022/095316 CN2022095316W WO2023216331A1 WO 2023216331 A1 WO2023216331 A1 WO 2023216331A1 CN 2022095316 W CN2022095316 W CN 2022095316W WO 2023216331 A1 WO2023216331 A1 WO 2023216331A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate dielectric
dielectric region
transistor
word line
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/095316
Other languages
English (en)
French (fr)
Inventor
石昊凡
朴相弼
车载龙
李中和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to US18/151,515 priority Critical patent/US12183431B2/en
Publication of WO2023216331A1 publication Critical patent/WO2023216331A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Definitions

  • the present disclosure relates to the technical field of integrated circuit manufacturing, and specifically to a semiconductor structure that can improve the transmission performance of a word line driver circuit, and a chip using the semiconductor structure.
  • the word line driver circuit is an important circuit in the memory.
  • a word line driver circuit usually includes multiple word line driver sub-circuits.
  • a main word line (Main-WordLine, MWL) drives multiple sub-word lines (Sub-WordLine, SWL) through a circuit built with transistors. , thereby realizing the transmission of word line signals in the memory.
  • MWL Main-WordLine
  • SWL sub-word lines
  • layout layout circuits connected to the same main word line are usually laid out in a centralized manner, and multiple word line driver sub-circuits are also usually laid out in a centralized layout, which places higher requirements on layout design.
  • the wiring and layout are usually adjusted accordingly to obtain better electrical signal transmission effects while meeting design specifications.
  • the layouts in related technologies have different problems, such as the existence of island areas and many signal line bends, which lead to various performance attenuations in the electrical signal transmission effect. Therefore, a layout structure of a word line driver circuit with better electrical signal transmission effect is needed.
  • the purpose of the present disclosure is to provide a semiconductor structure and a chip using the semiconductor structure, which are used to overcome, at least to a certain extent, the poor electrical signal transmission effect caused by the word line driving circuit layout layout due to limitations and defects in related technologies. question.
  • a semiconductor structure including: a first active region extending along a first direction and having a first width in a second direction, the second direction being perpendicular to the first direction. ; A second active region extending along the first direction and having the first width in the second direction; a first word line driving transistor group formed based on the first active region, including connecting all Of the two gate dielectric areas of the first active area, one gate dielectric area is connected to the main word line, and the other gate dielectric area is connected to the first control signal line; the second word line driving transistor group is based on The first active region is formed and includes two gate dielectric regions connected to the first active region, one of the gate dielectric regions is connected to the main word line, and the other gate dielectric region is connected to the third two control signal lines; a third word line driving transistor group, formed based on the second active area, including two gate dielectric areas connected to the second active area, and one gate dielectric area connected to the The main word line, the other gate dielectric area
  • a dielectric region, one of the gate dielectric regions is connected to the main word line, and the other gate dielectric region is connected to the fourth control signal line; wherein each of the gate dielectric regions is along the second direction. Extending and having a second width in the first direction.
  • the first word line driving transistor group includes a first transistor and a second transistor.
  • the gate of the first transistor is a first gate dielectric region
  • the gate of the second transistor is a first gate dielectric region.
  • the gate is a second gate dielectric region, and the portion of the first active region between the first gate dielectric region and the second gate dielectric region is the first transistor and the second transistor.
  • the common drain of region, the part of the first active region between the third gate dielectric region and the fourth gate dielectric region is the common drain of the third transistor and the fourth transistor;
  • the third The word line driving transistor group includes a fifth transistor and a sixth transistor.
  • the gate of the fifth transistor is a fifth gate dielectric region.
  • the gate of the sixth transistor is a sixth gate dielectric region.
  • the second gate dielectric region has The portion of the source region between the fifth gate dielectric region and the sixth gate dielectric region is a common drain of the fifth transistor and the sixth transistor; a fourth word line driving transistor group includes A seventh transistor and an eighth transistor, the gate of the seventh transistor is a seventh gate dielectric region, the gate of the eighth transistor is an eighth gate dielectric region, and the second active region is located in the seventh gate dielectric region.
  • the portion between the gate dielectric region and the eighth gate dielectric region is a common drain of the seventh transistor and the eighth transistor.
  • a first gate dielectric region, a second gate dielectric region, a third gate dielectric region, and a fourth gate dielectric region are sequentially formed on the first active region.
  • the first direction is arranged in parallel, and the fifth gate dielectric region, the sixth gate dielectric region, the seventh gate dielectric region, and the eighth gate dielectric region are sequentially located in the second gate dielectric region.
  • the active area is arranged in parallel along the first direction, and the first gate dielectric area, the fourth gate dielectric area, the fifth gate dielectric area, and the eighth gate dielectric area are connected to each other. Describe the main word line.
  • the first gate dielectric region and the fifth gate dielectric region are connected, and the fourth gate dielectric region and the eighth gate dielectric region are connected, so The first gate dielectric region and the fifth gate dielectric region have a first spacing in the first direction, and the fourth gate dielectric region and the eighth gate dielectric region are in the first direction. direction has the first spacing.
  • the second gate dielectric region and the sixth gate dielectric region have the first spacing in the first direction, and the third gate dielectric region There is the first spacing between the seventh gate dielectric region and the seventh gate dielectric region in the first direction.
  • the first gate dielectric region and the fifth gate dielectric region are connected through a first connection structure, the first connection structure extends along the second direction, in The first direction has a third width, and the third width is smaller than the second width; the fourth gate dielectric region and the eighth gate dielectric region are connected through a second connection structure, and the third gate dielectric region
  • the two connection structures extend along the second direction and have the third width in the first direction.
  • a first edge of the first connection structure in the first direction is flush with a first edge of the first gate dielectric region in the first direction.
  • the second edge of the first connection structure in the first direction is flush with the second edge of the fifth gate dielectric region in the first direction; the second connection structure is in the The first edge in the first direction is flush with the first edge of the fourth gate dielectric region in the first direction, and the second edge of the second connection structure in the first direction is flush with the first edge in the first direction.
  • the second edge of the eighth gate dielectric region in the first direction is flush.
  • the first control signal line and the second control signal line are the same signal line, and the third control signal line and the fourth control signal line are the same signal line.
  • the second gate dielectric region is connected to the third gate dielectric region, and the sixth gate dielectric region is connected to the seventh gate dielectric region.
  • the second gate dielectric region and the third gate dielectric region are connected through a third connection structure, and the third connection structure extends along the first direction, in The second direction is located on the side of the first active region away from the second active region; the sixth gate dielectric region and the seventh gate dielectric region are connected through a fourth connection structure, The fourth connection structure extends along the first direction and is located on a side of the second active area away from the first active area in the second direction.
  • the third connection structure connects the first end of the second gate dielectric region and the first end of the third gate dielectric region
  • the fourth connection structure Connect the second end of the sixth gate dielectric region and the second end of the seventh gate dielectric region.
  • the common drain of the first transistor and the second transistor is connected to the corresponding first sub-word line of the first word line driving transistor group through a first wire
  • the The common drain of the third transistor and the fourth transistor is connected to the second sub-word line corresponding to the second word line driving transistor group through a second conductor, and the first conductor and the second conductor are connected to the second sub-word line of the second word line driving transistor group.
  • One direction is parallel, and the first conductor and the second conductor are located on the same metal layer; the common drain of the fifth transistor and the sixth transistor is connected to the third word line driving transistor through a third conductor.
  • the third sub-word line corresponding to the group, the common drain of the seventh transistor and the eighth transistor is connected to the fourth sub-word line corresponding to the fourth word line driving transistor group through a fourth wire, the third The conductive line and the fourth conductive line are parallel in the first direction, and the third conductive line and the fourth conductive line are located on the same metal layer.
  • the first conductive line is connected to the drain of the first P-type transistor corresponding to the first word line driving transistor group, and the second conductive line is connected to the second driving transistor group.
  • the drain of the second P-type transistor corresponding to the transistor group, the third wire is connected to the drain of the third P-type transistor corresponding to the third driving transistor group, and the fourth wire is connected to the fourth driving transistor.
  • the drain of the fourth P-type transistor corresponding to the transistor group, the first P-type transistor, the second P-type transistor, the third P-type transistor, and the fourth P-type transistor are all arranged in the first layout area, the first active area and the second active area are both arranged in the second layout area, and the first layout area and the second layout area are arranged side by side in the second direction.
  • the second gate dielectric region is connected to a fifth conductor
  • the sixth gate dielectric region is connected to a sixth conductor
  • the fifth conductor and the sixth conductor are connected to each other.
  • the first direction is parallel
  • the fifth conductor and the sixth conductor are located on the same metal layer.
  • a semiconductor structure for arranging a memory word line driving circuit and connecting a main word line and a plurality of sub-word lines respectively corresponding to the plurality of word line driving circuits, including: a first layout area, For setting multiple P-type transistors corresponding to multiple word line driving circuits, the gate of each P-type transistor is connected to the main word line, and the drain of each P-type transistor is connected to the corresponding word The sub-word line of the line driver circuit, the source of each P-type transistor is connected to the power supply voltage; the second layout area includes a plurality of semiconductor structures as described in any one of the above, and the semiconductors in the second layout area The structures share the first active area and the second active area; the third layout area includes a plurality of semiconductor structures as described in any one of the above, and the semiconductor structures in the third layout area share the first active area and the second active area. Two active areas; the second layout area, the first layout area, and the third layout area are arranged side by side in sequence in
  • a chip including the semiconductor structure as described in any one of the above.
  • the semiconductor structure provided by the embodiment of the present disclosure can be achieved by arranging four groups of word line driving transistor groups on two straight active regions of equal width, and at the same time arranging the gate dielectric regions of the four groups of word line driving transistor groups with equal width. A uniform and consistent charge path is formed, the four groups of word line driving transistor groups are controlled to have the same electrical characteristics, and the conductivity of the word line driving transistor group is improved, thereby improving the electrical signal transmission effect of the word line driving circuit.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.
  • FIG. 2A is a layout of four word line driving transistor groups in an embodiment of the present disclosure.
  • FIG. 2B is a circuit corresponding to the layout shown in FIG. 2A in one embodiment.
  • Figure 3 is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of the effect of the embodiment shown in FIG. 3 .
  • FIG. 5 is a schematic diagram of a semiconductor structure in another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of the effect of the embodiment shown in FIG. 5 .
  • FIG. 7 is an overall schematic diagram of a semiconductor structure in an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a shallow trench isolation structure corresponding to a semiconductor structure in an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.
  • semiconductor structure 100 may include:
  • the first active area 11 extends along the first direction, has a first width W1 in the second direction, and the second direction is perpendicular to the first direction;
  • the second active region 12 extends along the first direction and has a first width W1 in the second direction;
  • the first word line driving transistor group 21 is formed based on the first active region 11 and includes two gate dielectric regions 30 connected to the first active region 11. One gate dielectric region 30 is connected to the main word line MWL, and the other gate dielectric region 30 is connected to the main word line MWL.
  • the polar dielectric area 30 is connected to the first control signal line CON1;
  • the second word line driving transistor group 22 is formed based on the first active region 11 and includes two gate dielectric regions 30 connected to the first active region 11. One gate dielectric region 30 is connected to the main word line MWL, and the other gate dielectric region 30 is connected to the main word line MWL.
  • the polar dielectric area 30 is connected to the second control signal line CON2;
  • the third word line driving transistor group 23 is formed based on the second active region 12 and includes two gate dielectric regions 30 connected to the second active region 12. One gate dielectric region 30 is connected to the main word line MWL, and the other gate dielectric region 30 is connected to the main word line MWL. The polar dielectric area 30 is connected to the third control signal line CON3;
  • the fourth word line driving transistor group 24 is formed based on the second active region 12 and includes two gate dielectric regions 30 connected to the second active region 12. One gate dielectric region 30 is connected to the main word line MWL, and the other gate dielectric region 30 is connected to the main word line MWL. The polar dielectric area 30 is connected to the fourth control signal line CON4;
  • Each gate dielectric region 30 extends along the second direction and has a second width W2 in the first direction.
  • the embodiment of the present disclosure realizes four word line driving transistor groups by using two active regions with uniform width, and sets each gate dielectric region in each word line driving transistor group to be a rectangle with the same width, which can form a uniform Conductive channels, and eliminate island areas in the layout, reduce the stress of STI (Shallow Trench Isolation, shallow trench isolation structure), improve structural stability, also improve the filling effect of metal wiring, reduce the process defect rate, It reduces production difficulty and improves production efficiency and product yield. In addition, it is also convenient to monitor and optimize device performance in WAT (Wafer Acceptable Test, wafer factory test).
  • WAT Wafer Acceptable Test
  • FIG. 2A and 2B are schematic diagrams of the corresponding relationship between the semiconductor structure 100 and the word line driving circuit in the embodiment of the present disclosure.
  • FIG. 2A is a layout of four word line driving transistor groups in an embodiment of the present disclosure
  • FIG. 2B is a circuit corresponding to the layout shown in FIG. 2A in an embodiment.
  • the first word line driving transistor group 21 includes a first transistor M11 and a second transistor M12 , and the gate of the first transistor M11 is a first gate dielectric region. 31.
  • the gate of the second transistor M12 is the second gate dielectric region 32.
  • the portion of the first active region 11 between the first gate dielectric region 31 and the second gate dielectric region 32 is the first transistor M11 and the second gate dielectric region 32.
  • the second word line driving transistor group 22 includes a third transistor M21 and a fourth transistor M22.
  • the gate of the third transistor M21 is the third gate dielectric region 33.
  • the gate of the fourth transistor M22 is the fourth gate dielectric region 34.
  • a portion of the active region 11 located between the third gate dielectric region 33 and the fourth gate dielectric region 34 is the common drain of the third transistor M21 and the fourth transistor M22;
  • the third word line driving transistor group 23 includes a fifth transistor M31 and a sixth transistor M32.
  • the gate of the fifth transistor M31 is the fifth gate dielectric region 35
  • the gate of the sixth transistor M32 is the sixth gate dielectric region 36.
  • the portion of the two active regions 12 located between the fifth gate dielectric region 35 and the sixth gate dielectric region 36 is the common drain of the fifth transistor M31 and the sixth transistor M32;
  • the fourth word line driving transistor group 24 includes a seventh transistor M41 and an eighth transistor M42.
  • the gate of the seventh transistor M41 is the seventh gate dielectric region 37
  • the gate of the eighth transistor M42 is the eighth gate dielectric region 38.
  • the portion of the two active regions 12 located between the seventh gate dielectric region 37 and the eighth gate dielectric region 38 is the common drain of the seventh transistor M41 and the eighth transistor M42.
  • the first gate dielectric region 31 , the second gate dielectric region 32 , the third gate dielectric region 33 , and the fourth gate dielectric region 34 are sequentially located in the first active region. 11 are arranged in parallel along the first direction, and the fifth gate dielectric region 35, the sixth gate dielectric region 36, the seventh gate dielectric region 37, and the eighth gate dielectric region 38 are sequentially arranged on the second active region 12 Arranged in parallel along the first direction, the first gate dielectric region 31, the fourth gate dielectric region 34, the fifth gate dielectric region 35, and the eighth gate dielectric region 38 are connected to the main word line MWL, and the second gate dielectric region 32 is connected to the first control signal line CON1, the third gate dielectric region 33 is connected to the second control signal line CON2, the sixth gate dielectric region 36 is connected to the third control signal line CON3, and the seventh gate dielectric region 37 is connected to the fourth control signal line CON1. Signal line CON4.
  • the first word line driving transistor group 21 further includes a first P-type transistor MP1
  • the second word line driving transistor group 22 further includes a second P-type transistor MP2, and a third word line driving transistor.
  • the group 23 further includes a third P-type transistor MP3, and the fourth word line driving transistor group 24 further includes a fourth P-type transistor MP4.
  • the source of the first P-type transistor MP1 is connected to the power supply, the gate is connected to the main word line MWL, and the drain is connected to the drain of the first transistor M11 and the first sub-word line SWL1;
  • the source of the second P-type transistor MP2 is connected to Power supply, the gate is connected to the main word line MWL, the drain is connected to the drain of the third transistor M21, and the second sub-word line SWL2 is connected at the same time;
  • the source of the third P-type transistor MP3 is connected to the power supply, and the gate is connected to the main word line MWL.
  • the drain is connected to the drain of the fifth transistor M31, and is also connected to the third sub-word line SWL3; the source of the fourth P-type transistor MP4 is connected to the power supply, the gate is connected to the main word line MWL, and the drain is connected to the drain of the seventh transistor M41. , and connect the fourth sub-word line SWL4 at the same time.
  • the layout shown in FIG. 2B is used as the source of the layout shown in FIG. 2A in this disclosure, in other embodiments of the disclosure, the layout shown in FIG. 2A can also be applied to other circuits, similar circuits or other word line drivers.
  • the layout of the circuit is to improve the electrical signal transmission effect of the centralized layout of the transistors.
  • the layout in the embodiment of the present disclosure is not limited to the word line driving circuit shown in FIG. 2B.
  • Figure 3 is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.
  • the first gate dielectric region 31 and the fifth gate dielectric region 35 are connected, the fourth gate dielectric region 34 and the eighth gate dielectric region 38 are connected, and the first gate dielectric region 31 and the fifth gate dielectric region 35 are connected.
  • a gate dielectric region 31 and a fifth gate dielectric region 35 have a first spacing D1 in the first direction, and a fourth gate dielectric region 34 and an eighth gate dielectric region 38 have a first spacing D1 in the first direction. .
  • the second gate dielectric region 32 and the sixth gate dielectric region 36 to have a first spacing D1 in the first direction
  • the third gate dielectric region 33 and the seventh gate dielectric region 37 to have a first distance D1 in the first direction. There is a first distance D1 in one direction.
  • the first gate dielectric region 31 and the fifth gate dielectric region 35 are connected through a first connection structure 41, the first connection structure 41 extends along the second direction and has a third width W3 in the first direction. , the third width W3 is smaller than the second width W2; the fourth gate dielectric region 34 and the eighth gate dielectric region 38 are connected through the second connection structure 42, the second connection structure 42 extends along the second direction, in the first direction Has a third width W3.
  • a first edge of the first connection structure 41 in the first direction (top in the figure) can be set. edge) is flush with the first edge of the first gate dielectric region 31 in the first direction, and the second edge (lower edge in the figure) in the first direction is flush with the fifth gate dielectric region 35 in the first direction.
  • the second edge of the second connection structure 42 in the first direction is flush with the first edge of the fourth gate dielectric region 34 in the first direction, and the second edge in the first direction It is flush with the second edge of the eighth gate dielectric region 38 in the first direction.
  • FIG. 4 is a schematic diagram of the effect of the embodiment shown in FIG. 3 .
  • the common drains of the first transistor M11 and the second transistor M12 are connected to the corresponding first sub-section of the first word line driving transistor group 21 through the first conductor 51 .
  • the common drains of the word line SWL1, the third transistor M21 and the fourth transistor M22 are connected to the second sub-word line SWL2 corresponding to the second word line driving transistor group 22 through the second conductor 52.
  • the first conductor 51 and the second conductor 52 are in are parallel in the first direction, and the first conductor 51 and the second conductor 52 are located on the same metal layer; the common drains of the fifth transistor M31 and the sixth transistor M32 are connected to the corresponding third word line driving transistor group 23 through the third conductor 53
  • the common drains of the third sub-word line SWL3, the seventh transistor M41 and the eighth transistor M42 are connected to the fourth sub-word line SWL4 corresponding to the fourth word line driving transistor group 24 through the fourth conductor 54.
  • the third conductor 53 and the fourth The conductors 54 are parallel in the first direction, and the third conductor 53 and the fourth conductor 54 are located on the same metal layer.
  • the first sub-word line SWL1, the second sub-word line SWL2, the third sub-word line SWL3, and the fourth sub-word line SWL4 are disposed in the first layout area 400 and connected to the first layout area 400. storage array.
  • the first layout area 400 is used to set PMOS corresponding to multiple word line driving transistor groups to achieve centralized layout of PMOS (see Figure 9 for details).
  • the first wire 51 is connected to the drain of the first P-type transistor MP1 corresponding to the first word line driving transistor group 21
  • the second wire 52 is connected to the second P-type transistor corresponding to the second driving transistor group 22
  • the drain of the transistor MP2 is connected to the drain of the third P-type transistor MP3 corresponding to the third drive transistor group 23
  • the fourth conductor 54 is connected to the fourth P-type transistor MP4 corresponding to the fourth drive transistor group 24.
  • the drain of The source areas 12 are both arranged in the second layout area 401, and the first layout area 400 and the second layout area 401 are arranged side by side in the second direction.
  • the four word line driving transistor groups connected in a centralized layout can be allowed to be connected to the sub-word lines SWL1 ⁇ SWL4 is flatly wired on the same metal layer and connected to the first layout area 400 corresponding to the word line driver circuit. Since the traces are uniform and straight and do not need to pass through layers, the layout design complexity of the wiring metal layer (ie, M0 layer) is reduced, the loading of the wires is reduced, the conductive effect of the wires is optimized, the manufacturing complexity is reduced, and the Productivity.
  • M0 layer the layout design complexity of the wiring metal layer
  • setting the first spacing can avoid the increase in loading caused by bending and cross-layering between traces, and further improves the electrical signal transmission effect of the word line driver circuit.
  • FIG. 5 is a schematic diagram of a semiconductor structure in another embodiment of the present disclosure.
  • the first control signal line CON1 and the second control signal line CON2 are the same signal line
  • the third control signal line CON3 and the fourth control signal line CON4 are the same signal line.
  • the second gate dielectric region 32 is connected to the third gate dielectric region 33
  • the sixth gate dielectric region 36 is connected to the seventh gate dielectric region 37 .
  • the second gate dielectric region 32 and the third gate dielectric region 33 are connected through a third connection structure 43.
  • the third connection structure 43 extends along the first direction and is located away from the first active region 11 in the second direction.
  • One side of the source region 12; the sixth gate dielectric region 36 and the seventh gate dielectric region 37 are connected through a fourth connection structure 44.
  • the fourth connection structure 44 extends along the first direction and is located in the second direction in the second direction. The side of the source area 12 facing away from the first active area 11 .
  • Gate dielectric regions connected to the same control signal lines are connected through the third connection structure 43 and the fourth connection structure 44, which can save the wiring of the control signal lines and provide more space for layout.
  • using the third connection structure 43 and the fourth connection structure 44 with larger areas to realize the connection between the gate dielectric areas is more conducive to making the gate dielectric areas The charges between them are uniform and the charge transfer capability is enhanced.
  • the third connection structure 43 connects the first end of the second gate dielectric region 32 and the first end of the third gate dielectric region 33
  • the fourth connection structure 44 connects the sixth gate.
  • connection structure 43 and the fourth connection structure 44 can also be set to be connected to other parts of each gate dielectric region.
  • connection positions of each connection structure can be designed as long as the shapes of the first active region 11, the second active region 12 and each gate dielectric region are not affected.
  • FIG. 6 is a schematic diagram of the effect of the embodiment shown in FIG. 5 .
  • the second gate dielectric region 32 is connected to the fifth conductor 55
  • the sixth gate dielectric region 36 is connected to the sixth conductor 56
  • the fifth conductor 55 and the sixth conductor 56 They are parallel in the first direction
  • the fifth conductive line 55 and the sixth conductive line 56 are located on the same metal layer.
  • the fifth wire 55 is used to connect the first control signal CON1 (the first control signal CON1 and the second control signal CON2 are the same control signal)
  • the sixth wire 56 is used to connect the third control signal CON3 (the third control signal CON3 and the second control signal CON2 are the same control signal).
  • the four control signals CON4 are the same control signal).
  • connection structure 43 and the fourth connection structure 44 to connect the gate dielectric regions connected to the same control signal, the wires connected to the control signal can be routed straight on the same metal layer. It can not only improve the conductive efficiency of wires and optimize the electrical signal transmission effect, but also reduce the layout design complexity of the wiring metal layer (ie, M0 layer), reduce the manufacturing complexity, and improve production efficiency.
  • the semiconductor structure provided by the embodiments of the present disclosure can enable four word line driving transistor groups connected to the same main word line to realize straight wiring of wires on the same metal layer during layout layout, reducing wire bends. Fold to prevent wires from crossing layers, thereby improving the conductive efficiency of the wires and improving the electrical signal transmission effect.
  • FIG. 7 is an overall schematic diagram of a semiconductor structure in an embodiment of the present disclosure.
  • the semiconductor structure provided by the embodiment of the present disclosure has a relatively straight and uniform gate dielectric region and an active region, and realizes the connection between the gate dielectric regions of the same signal through multiple uniform connection structures.
  • the connection can reduce wiring within the word line driving circuit and make the charges in each gate dielectric region uniform, thereby improving the overall electrical signal transmission effect of the word line driving circuit part.
  • FIG. 8 is a schematic diagram of a shallow trench isolation structure corresponding to a semiconductor structure in an embodiment of the present disclosure.
  • the active areas are not connected.
  • the shallow trench isolation structure 800 has a neat and complete layout, and there are no islands. (STI Iland), which can reduce the stress between STI and the active area and improve the yield and structural stability of integrated circuits.
  • Figure 9 is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.
  • the semiconductor structure 900 is used to set up a memory word line driving circuit, connecting the main word line MWL and a plurality of sub-word lines SWL corresponding to the plurality of word line driving circuits, including:
  • the first layout area 901 is used to set multiple P-type transistors MP corresponding to multiple word line driving circuits.
  • the gate of each P-type transistor MP is connected to the main word line MWL, and the drain of each P-type transistor MP is connected to the main word line MWL.
  • the second layout area 902 includes a plurality of semiconductor structures 910 of the embodiments shown in Figures 1 to 7.
  • the semiconductor structures 910 in the second layout area 902 share the first active area 91 and the second active area 92;
  • the third layout area 903 includes a plurality of semiconductor structures 910 of the embodiments shown in Figures 1 to 7.
  • the semiconductor structures 910 in the third layout area 903 share the first active area 93 and the second active area 94;
  • the second layout area 902, the first layout area 901, and the third layout area 903 are sequentially arranged side by side in the second direction.
  • FIG. 9 shows the semiconductor structure shown in FIG. 6 or FIG. 7
  • the semiconductor structure shown in FIGS. 1 to 5 is also within the protection scope of the embodiment shown in FIG. 9 .
  • the formed word line driving circuit layout not only has uniform and straight active areas, gates, etc.
  • the polar dielectric area also has straight and uniform traces on the same metal layer. That is, the wiring in the M0 layer is generally linear, and the traces from the NMOS layout area (the second layout area 902, the third layout area 903) to the PMOS layout area (the first layout area 901) are not bent, which greatly reduces the metal Wire layer defects (M0defect) improve process stability.
  • the layout design complexity of the wiring metal layer ie, M0 layer
  • the conductive effect of the wires is optimized, the manufacturing complexity is reduced, and the production efficiency is improved.
  • a chip including the semiconductor structure of any one of the above.
  • the semiconductor structure provided by the embodiment of the present disclosure can be achieved by arranging four groups of word line driving transistor groups on two straight active regions of equal width, and at the same time arranging the gate dielectric regions of the four groups of word line driving transistor groups with equal width. A uniform and consistent charge path is formed, the four groups of word line driving transistor groups are controlled to have the same electrical characteristics, and the conductivity of the word line driving transistor group is improved, thereby improving the electrical signal transmission effect of the word line driving circuit.

Landscapes

  • Semiconductor Memories (AREA)

Abstract

一种半导体结构（100），包括：第一有源区（11）和第二有源区（12），均沿第一方向延伸，在第二方向上具有第一宽度（W1）；第一字线驱动晶体管组（21），包括连接第一有源区（11）的两个栅极介质区（30）；第二字线驱动晶体管组（22），包括连接第一有源区（11）的两个栅极介质区（30）；第三字线驱动晶体管组（23），包括连接第二有源区（12）的两个栅极介质区（30）；第四字线驱动晶体管组（24），包括连接第二有源区（12）的两个栅极介质区（30）；其中，每个栅极介质区（30）均沿第二方向延伸且在第一方向上具有第二宽度（W2）。可以改善字线驱动电路的版图布局，通过尺寸一致的有源区和尺寸一致的栅极介质区提高字线驱动电路的电荷传输能力。

Description

半导体结构及芯片
交叉引用
本公开要求于2022年5月7日提交的申请号为202210495446.0、名称为“半导体结构及芯片”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路制造技术领域，具体而言，涉及一种能够提高字线驱动电路传输性能的半导体结构，以及应用该半导体结构的芯片。
背景技术
字线驱动电路是存储器中的重要电路。字线驱动电路通常包括多个字线驱动子电路，每个字线驱动子电路中一条主字线(Main-WordLine，MWL)通过晶体管搭建的电路驱动多条子字线(Sub-WordLine，SWL)，从而实现字线信号在存储器中的传递。在版图布局中，连接同一条主字线的电路通常集中布局，而多个字线驱动子电路也通常集中布局，这对版图设计提出了较高要求。
为了实现字线驱动电路的集中布局，通常对布线、布局做出相应调整，以在满足设计规范的同时下得到更好的电信号传输效果。而相关技术中的版图布局均存在不同问题，例如存在孤岛区域、信号线弯曲较多等问题，导致电信号传输效果的各种性能衰减。因此，需要一种具有更好的电信号传输效果的字线驱动电路的版图结构。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种半导体结构及应用该半导体结构的芯片，用于至少在一定程度上克服由于相关技术的限制和缺陷而导致的字线驱动电路版图布局导致电信号传输效果不佳的问题。
根据本公开的第一方面，提供一种半导体结构，包括：第一有源区，沿第一方向延伸，在第二方向上具有第一宽度，所述第二方向与所述第一方向垂直；第二有源区，沿所述第一方向延伸，在所述第二方向上具有所述第一宽度；第一字线驱动晶体管组，基于所述第一有源区形成，包括连接所述第一有源区的两个栅极介质区，一个所述栅极介质区连接主字线，另一个所述栅极介质区连接第一控制信号线；第二字线驱动晶体管组，基于所述第一有源区形成，包括连接所述第一有源区的两个栅极介质区，一个所述栅极介质区连接所述主字线，另一个所述栅极介质区连接第二控制信号线；第三字线驱动晶体管组，基于所述第二有源区形成，包括连接所述第二有源区的两个栅极介质区，一个所述栅极介质区连 接所述主字线，另一个所述栅极介质区连接第三控制信号线；第四字线驱动晶体管组，基于所述第二有源区形成，包括连接所述第二有源区的两个栅极介质区，一个所述栅极介质区连接所述主字线，另一个所述栅极介质区连接第四控制信号线；其中，每个所述栅极介质区均沿所述第二方向延伸且在所述第一方向上具有第二宽度。
在本公开的一个示例性实施例中，所述第一字线驱动晶体管组包括第一晶体管和第二晶体管，所述第一晶体管的栅极为第一栅极介质区，所述第二晶体管的栅极为第二栅极介质区，所述第一有源区位于所述第一栅极介质区和所述第二栅极介质区之间的部分为所述第一晶体管和所述第二晶体管的共同漏极；第二字线驱动晶体管组，包括第三晶体管和第四晶体管，所述第三晶体管的栅极为第三栅极介质区，所述第四晶体管的栅极为第四栅极介质区，所述第一有源区位于所述第三栅极介质区和所述第四栅极介质区之间的部分为所述第三晶体管和所述第四晶体管的共同漏极；第三字线驱动晶体管组，包括第五晶体管和第六晶体管，所述第五晶体管的栅极为第五栅极介质区，所述第六晶体管的栅极为第六栅极介质区，所述第二有源区位于所述第五栅极介质区和所述第六栅极介质区之间的部分为所述第五晶体管和所述第六晶体管的共同漏极；第四字线驱动晶体管组，包括第七晶体管和第八晶体管，所述第七晶体管的栅极为第七栅极介质区，所述第八晶体管的栅极为第八栅极介质区，所述第二有源区位于所述第七栅极介质区和所述第八栅极介质区之间的部分为所述第七晶体管和所述第八晶体管的共同漏极。
在本公开的一个示例性实施例中，第一栅极介质区、第二栅极介质区、第三栅极介质区、第四栅极介质区顺次在所述第一有源区上沿所述第一方向平行设置，所述第五栅极介质区、所述第六栅极介质区、所述第七栅极介质区、所述第八栅极介质区顺次在所述第二有源区上沿所述第一方向平行设置，所述第一栅极介质区、所述第四栅极介质区、所述第五栅极介质区、所述第八栅极介质区连接所述主字线。
在本公开的一个示例性实施例中，所述第一栅极介质区和所述第五栅极介质区连接，所述第四栅极介质区和所述第八栅极介质区连接，所述第一栅极介质区和所述第五栅极介质区在所述第一方向上具有第一间距，所述第四栅极介质区和所述第八栅极介质区在所述第一方向上具有所述第一间距。
在本公开的一个示例性实施例中，所述第二栅极介质区与所述第六栅极介质区在所述第一方向上具有所述第一间距，所述第三栅极介质区与所述第七栅极介质区在所述第一方向上具有所述第一间距。
在本公开的一个示例性实施例中，所述第一栅极介质区和所述第五栅极介质区通过第一连接结构连接，所述第一连接结构沿所述第二方向延伸，在所述第一方向上具有第三宽度，所述第三宽度小于所述第二宽度；所述第四栅极介质区和所述第八栅极介质区通过第二连接结构连接，所述第二连接结构沿所述第二方向延伸，在所述第一方向上具有所述第三宽度。
在本公开的一个示例性实施例中，所述第一连接结构在所述第一方向上的第一边沿与 所述第一栅极介质区在所述第一方向上的第一边沿齐平，所述第一连接结构在所述第一方向上的第二边沿与所述第五栅极介质区在所述第一方向上的第二边沿齐平；所述第二连接结构在所述第一方向上的第一边沿与所述第四栅极介质区在所述第一方向上的第一边沿齐平，所述第二连接结构在所述第一方向上的第二边沿与所述第八栅极介质区在所述第一方向上的第二边沿齐平。
在本公开的一个示例性实施例中，所述第一控制信号线与所述第二控制信号线为同一信号线，所述第三控制信号线与所述第四控制信号线为同一信号线，所述第二栅极介质区与所述第三栅极介质区连接，所述第六栅极介质区与所述第七栅极介质区连接。
在本公开的一个示例性实施例中，所述第二栅极介质区与所述第三栅极介质区通过第三连接结构连接，所述第三连接结构沿所述第一方向延伸，在所述第二方向上位于所述第一有源区背离所述第二有源区的一侧；所述第六栅极介质区与所述第七栅极介质区通过第四连接结构连接，所述第四连接结构沿所述第一方向延伸，在所述第二方向上位于所述第二有源区背离所述第一有源区的一侧。
在本公开的一个示例性实施例中，所述第三连接结构连接所述第二栅极介质区的第一端与所述第三栅极介质区的第一端，所述第四连接结构连接所述第六栅极介质区的第二端与所述第七栅极介质区的第二端。
在本公开的一个示例性实施例中，所述第一晶体管和所述第二晶体管的共同漏极通过第一导线连接所述第一字线驱动晶体管组对应的第一子字线，所述第三晶体管和所述第四晶体管的共同漏极通过第二导线连接所述第二字线驱动晶体管组对应的第二子字线，所述第一导线和所述第二导线在所述第一方向上平行，且所述第一导线和所述第二导线位于同一金属层；所述第五晶体管和所述第六晶体管的共同漏极通过第三导线连接所述第三字线驱动晶体管组对应的第三子字线，所述第七晶体管和所述第八晶体管的共同漏极通过第四导线连接所述第四字线驱动晶体管组对应的第四子字线，所述第三导线和所述第四导线在所述第一方向上平行，且所述第三导线和所述第四导线位于同一金属层。
在本公开的一个示例性实施例中，所述第一导线连接与所述第一字线驱动晶体管组对应的第一P型晶体管的漏极，所述第二导线连接与所述第二驱动晶体管组对应的第二P型晶体管的漏极，所述第三导线连接与所述第三驱动晶体管组对应的第三P型晶体管的漏极，所述第四导线连接与所述第四驱动晶体管组对应的第四P型晶体管的漏极，所述第一P型晶体管、所述第二P型晶体管、所述第三P型晶体管、所述第四P型晶体管均设置在第一布局区域，所述第一有源区和所述第二有源区均设置在第二布局区域，所述第一布局区域和所述第二布局区域在所述第二方向上并列设置。
在本公开的一个示例性实施例中，所述第二栅极介质区连接第五导线，所述第六栅极介质区连接第六导线，所述第五导线和所述第六导线在所述第一方向上平行，且所述第五导线和所述第六导线位于同一金属层。
根据本公开的第二方面，提供一种半导体结构，用于设置存储器字线驱动电路，连接 主字线和与多个字线驱动电路分别对应的多条子字线，包括：第一布局区域，用于设置多个字线驱动电路对应的多个P型晶体管，每个所述P型晶体管的栅极均连接所述主字线，每个所述P型晶体管的漏极均连接对应的字线驱动电路的子字线，每个所述P型晶体管的源极均连接电源电压；第二布局区域，包括多个如上任一项所述的半导体结构，所述第二布局区域中的半导体结构共用第一有源区和第二有源区；第三布局区域，包括多个如上任一项所述的半导体结构，所述第三布局区域中的半导体结构共用第一有源区和第二有源区；所述第二布局区域、所述第一布局区域、所述第三布局区域在第二方向上顺次并列设置。
根据本公开的第三方面，提供一种芯片，包括如上任一项所述的半导体结构。
本公开实施例提供的半导体结构，通过将四组字线驱动晶体管组分别设置在两个等宽笔直的有源区上，同时设置四组字线驱动晶体管组的栅极介质区等宽，可以形成均匀、一致的电荷通路，控制四组字线驱动晶体管组具有相同的电学特性，提高字线驱动晶体管组的导电能力，从而提高字线驱动电路的电信号传输效果。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开示例性实施例中半导体结构的结构示意图。
图2A是本公开实施例中四个字线驱动晶体管组的版图布局。
图2B是一个实施例中图2A所示布局对应的电路。
图3是本公开一个实施例中半导体结构的示意图。
图4是图3所示实施例的效果示意图。
图5是本公开另一个实施例中半导体结构的示意图。
图6是图5所示实施例的效果示意图。
图7是本公开实施例中半导体结构的整体示意图。
图8是本公开实施例中半导体结构对应的浅沟槽隔离结构的示意图。
图9是本公开一个实施例中半导体结构的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全 面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图1是本公开示例性实施例中半导体结构的结构示意图。
参考图1，半导体结构100可以包括：
第一有源区11，沿第一方向延伸，在第二方向上具有第一宽度W1，第二方向与第一方向垂直；
第二有源区12，沿第一方向延伸，在第二方向上具有第一宽度W1；
第一字线驱动晶体管组21，基于第一有源区11形成，包括连接第一有源区11的两个栅极介质区30，一个栅极介质区30连接主字线MWL，另一个栅极介质区30连接第一控制信号线CON1；
第二字线驱动晶体管组22，基于第一有源区11形成，包括连接第一有源区11的两个栅极介质区30，一个栅极介质区30连接主字线MWL，另一个栅极介质区30连接第二控制信号线CON2；
第三字线驱动晶体管组23，基于第二有源区12形成，包括连接第二有源区12的两个栅极介质区30，一个栅极介质区30连接主字线MWL，另一个栅极介质区30连接第三控制信号线CON3；
第四字线驱动晶体管组24，基于第二有源区12形成，包括连接第二有源区12的两个栅极介质区30，一个栅极介质区30连接主字线MWL，另一个栅极介质区30连接第四控制信号线CON4；
其中，每个栅极介质区30均沿第二方向延伸且在第一方向上具有第二宽度W2。
本公开实施例通过使用宽度均匀的两个有源区实现四个字线驱动晶体管组，并设置每个字线驱动晶体管组中的每个栅极介质区均为宽度相同的矩形，可以形成均匀的导电通道，并且在版图布局中消除孤岛区域，降低STI(Shallow Trench Isolation，浅沟槽隔离结构)的应力，提高结构稳定性，同时也提高了金属布线的填充效果，降低了制程缺陷率，降低了生产难度，提高了生产效率及产品良率。此外，也便于在WAT(Wafer Acceptable  Test，晶圆出厂测试)中对器件性能进行监控和调优。
图2A和图2B是本公开实施例中半导体结构100与字线驱动电路的对应关系示意图。其中图2A是本公开实施例中四个字线驱动晶体管组的版图布局，图2B是一个实施例中图2A所示布局对应的电路。
参考图2A和图2B，在本公开的一个示例性实施例中，第一字线驱动晶体管组21包括第一晶体管M11和第二晶体管M12，第一晶体管M11的栅极为第一栅极介质区31，第二晶体管M12的栅极为第二栅极介质区32，第一有源区11位于第一栅极介质区31和第二栅极介质区32之间的部分为第一晶体管M11和第二晶体管M12的共同漏极；
第二字线驱动晶体管组22包括第三晶体管M21和第四晶体管M22，第三晶体管M21的栅极为第三栅极介质区33，第四晶体管M22的栅极为第四栅极介质区34，第一有源区11位于第三栅极介质区33和第四栅极介质区34之间的部分为第三晶体管M21和第四晶体管M22的共同漏极；
第三字线驱动晶体管组23包括第五晶体管M31和第六晶体管M32，第五晶体管M31的栅极为第五栅极介质区35，第六晶体管M32的栅极为第六栅极介质区36，第二有源区12位于第五栅极介质区35和第六栅极介质区36之间的部分为第五晶体管M31和第六晶体管M32的共同漏极；
第四字线驱动晶体管组24包括第七晶体管M41和第八晶体管M42，第七晶体管M41的栅极为第七栅极介质区37，第八晶体管M42的栅极为第八栅极介质区38，第二有源区12位于第七栅极介质区37和第八栅极介质区38之间的部分为第七晶体管M41和第八晶体管M42的共同漏极。
在本公开的一个示例性实施例中，第一栅极介质区31、第二栅极介质区32、第三栅极介质区33、第四栅极介质区34顺次在第一有源区11上沿第一方向平行设置，第五栅极介质区35、第六栅极介质区36、第七栅极介质区37、第八栅极介质区38顺次在第二有源区12上沿第一方向平行设置，第一栅极介质区31、第四栅极介质区34、第五栅极介质区35、第八栅极介质区38连接主字线MWL，第二栅极介质区32连接第一控制信号线CON1，第三栅极介质区33连接第二控制信号线CON2，第六栅极介质区36连接第三控制信号线CON3，第七栅极介质区37连接第四控制信号线CON4。
参考图2B，在一个实施例中，第一字线驱动晶体管组21还包括第一P型晶体管MP1、第二字线驱动晶体管组22还包括第二P型晶体管MP2、第三字线驱动晶体管组23还包括第三P型晶体管MP3、第四字线驱动晶体管组24还包括第四P型晶体管MP4。第一P型晶体管MP1的源极连接电源，栅极连接主字线MWL，漏极连接第一晶体管M11的漏极，同时连接第一子字线SWL1；第二P型晶体管MP2的源极连接电源，栅极连接主字线MWL，漏极连接第三晶体管M21的漏极，同时连接第二子字线SWL2；第三P型晶体管MP3的源极连接电源，栅极连接主字线MWL，漏极连接第五晶体管M31的漏极，同时连接第三子字线SWL3；第四P型晶体管MP4的源极连接电源，栅极连接主字线MWL， 漏极连接第七晶体管M41的漏极，同时连接第四子字线SWL4。
虽然在本公开中以图2B所示电路作为图2A所示版图布局的来源，但是在本公开的其他实施例中，图2A所示版图布局也可以应用于其他电路相似电路或其他字线驱动电路的版图布局，以提高集中布局的晶体管的电信号传输效果，本公开实施例中的版图布局不以图2B所示字线驱动电路为限。
图3是本公开一个实施例中半导体结构的示意图。
参考图3，在本公开的一个示例性实施例中，第一栅极介质区31和第五栅极介质区35连接，第四栅极介质区34和第八栅极介质区38连接，第一栅极介质区31和第五栅极介质区35在第一方向上具有第一间距D1，第四栅极介质区34和第八栅极介质区38在第一方向上具有第一间距D1。
与此同时，也可以设置第二栅极介质区32与第六栅极介质区36在第一方向上具有第一间距D1，第三栅极介质区33与第七栅极介质区37在第一方向上具有第一间距D1。
在一个实施例中，第一栅极介质区31和第五栅极介质区35通过第一连接结构41连接，第一连接结构41沿第二方向延伸，在第一方向上具有第三宽度W3，第三宽度W3小于第二宽度W2；第四栅极介质区34和第八栅极介质区38通过第二连接结构42连接，第二连接结构42沿第二方向延伸，在第一方向上具有第三宽度W3。
如图3所示，在一个实施例中，为了降低走线角度过多导致的导线上的负载(loading)增加，可以设置第一连接结构41在第一方向上的第一边沿(图中上边沿)与第一栅极介质区31在第一方向上的第一边沿齐平，在第一方向上的第二边沿(图中下边沿)与第五栅极介质区35在第一方向上的第二边沿齐平；第二连接结构42在第一方向上的第一边沿与第四栅极介质区34在第一方向上的第一边沿齐平，在第一方向上的第二边沿与第八栅极介质区38在第一方向上的第二边沿齐平。
图4是图3所示实施例的效果示意图。
参考图4和图2B，在本公开的一个示例性实施例中，第一晶体管M11和第二晶体管M12的共同漏极通过第一导线51连接第一字线驱动晶体管组21对应的第一子字线SWL1，第三晶体管M21和第四晶体管M22的共同漏极通过第二导线52连接第二字线驱动晶体管组22对应的第二子字线SWL2，第一导线51和第二导线52在第一方向上平行，且第一导线51和第二导线52位于同一金属层；第五晶体管M31和第六晶体管M32的共同漏极通过第三导线53连接第三字线驱动晶体管组23对应的第三子字线SWL3，第七晶体管M41和第八晶体管M42的共同漏极通过第四导线54连接第四字线驱动晶体管组24对应的第四子字线SWL4，第三导线53和第四导线54在第一方向上平行，且第三导线53和第四导线54位于同一金属层。
在一个实施例中，第一子字线SWL1、第二子字线SWL2、第三子字线SWL3、第四子字线SWL4设置在第一布局区域400，并从第一布局区域400连接到存储阵列。第一布局区域400用于设置多个字线驱动晶体管组对应的PMOS，以实现PMOS的集中布局(详 细介绍请见图9)。
结合图2B的电路图，第一导线51连接与第一字线驱动晶体管组21对应的第一P型晶体管MP1的漏极，第二导线52连接与第二驱动晶体管组22对应的第二P型晶体管MP2的漏极，第三导线53连接与第三驱动晶体管组23对应的第三P型晶体管MP3的漏极，第四导线54连接与第四驱动晶体管24组对应的第四P型晶体管MP4的漏极，第一P型晶体管MP1、第二P型晶体管MP2、第三P型晶体管MP3、第四P型晶体管MP4均设置在第一布局区域400，第一有源区11和第二有源区12均设置在第二布局区域401，第一布局区域400和第二布局区域401在第二方向上并列设置。
由图4所示实施例可以看出，由于在图3所示实施例中将宽度均匀的栅极介质区错开设置，可以允许集中布局的四个字线驱动晶体管组连接的子字线SWL1～SWL4在同一金属层平直布线，连接到字线驱动电路对应的第一布局区域400。由于走线均匀笔直且无需穿层，降低了布线金属层(即M0层)的版图设计复杂度，降低了导线的负载(loading)，优化了导线的导电效果，降低了制造复杂度，提高了生产效率。
因此，设置第一间距可以避免由于走线之间的弯曲、跨层带来的负载(loading)增加，进一步提高字线驱动电路的电信号传输效果。
图5是本公开另一个实施例中半导体结构的示意图。
参考图5，在本公开的一个示例性实施例中，第一控制信号线CON1与第二控制信号线CON2为同一信号线，第三控制信号线CON3与第四控制信号线CON4为同一信号线，第二栅极介质区32与第三栅极介质区33连接，第六栅极介质区36与第七栅极介质区37连接。
第二栅极介质区32与第三栅极介质区33通过第三连接结构43连接，第三连接结构43沿第一方向延伸，在第二方向上位于第一有源区11背离第二有源区12的一侧；第六栅极介质区36与第七栅极介质区37通过第四连接结构44连接，第四连接结构44沿第一方向延伸，在第二方向上位于第二有源区12背离第一有源区11的一侧。
通过第三连接结构43、第四连接结构44将连接相同控制信号线的栅极介质区连接起来，可以节省控制信号线的走线，为版图布局提供更多空间。此外，相比于直接使用走线连接栅极介质区，使用面积较大的第三连接结构43、第四连接结构44实现栅极介质区之间的连接，更有助于使栅极介质区之间的电荷均匀，电荷传输能力增强。
在图5所示的实施例中，第三连接结构43连接第二栅极介质区32的第一端与第三栅极介质区33的第一端，第四连接结构44连接第六栅极介质区36的第二端与第七栅极介质区37的第二端。通过设置第三连接结构43、第四连接结构44与各栅极介质区的边角相连，可以减少相连的结构的角度总数，进而降低走线角度过多带来的负载(loading)增加效应，降低导线制造难度，提高生产效率。
在本公开的其他实施例中，如果加入其他布局考虑因素，也可以设置第三连接结构43、第四连接结构44与各栅极介质区的其他部分相连，本领域技术人员可以根据实际情 况自行设计各连接结构的连接位置，只要不影响第一有源区11、第二有源区12以及各栅极介质区的形状即可。
图6是图5所示实施例的效果示意图。
参考图6，在本公开的一个示例性实施例中，第二栅极介质区32连接第五导线55，第六栅极介质区36连接第六导线56，第五导线55和第六导线56在第一方向上平行，且第五导线55和第六导线56位于同一金属层。第五导线55用于连接第一控制信号CON1(第一控制信号CON1与第二控制信号CON2为同一控制信号)，第六导线56用于连接第三控制信号CON3(第三控制信号CON3与第四控制信号CON4为同一控制信号)。
由图6可以看出，通过使用第三连接结构43、第四连接结构44将连接有相同控制信号的栅极介质区连接起来，可以使连接控制信号的导线在同一金属层上平直布线，不但能够提高导线的导电效率，优化电信号传输效果，还能降低布线金属层(即M0层)的版图设计复杂度，降低制造复杂度，提高生产效率。
此外，在一个实施例中，当主字线MWL的信号也来自于控制信号生成区域500时，第一栅极介质区31可以通过第七导线57连接主字线MWL，第四栅极介质区34可以通过第八导线58连接主字线MWL。由此，本公开实施例提供的半导体结构，可以使连接同一主字线的四个字线驱动晶体管组，在版图布局时，均能在同一金属层实现导线的平直布线，减小导线弯折，避免导线跨层，从而提高导线的导电效率，提高电信号传输效果。
图7是本公开实施例中半导体结构的整体示意图。
由图7可以看出，本公开实施例提供的半导体结构具有较为笔直均匀的栅极介质区和有源区，且通过多个均匀的连接结构实现了连接相同信号的栅极介质区之间的连接，能够在字线驱动电路内部减少走线，并使各栅极介质区的电荷均匀，从而整体提高字线驱动电路部分的电信号传输效果。
图8是本公开实施例中半导体结构对应的浅沟槽隔离结构的示意图。
参考图8，由于设置了均匀笔直的有源区，各有源区(图中空白区域)之间不连接，在版图布局时，浅沟槽隔离结构800具有整齐、完整的布局，不存在孤岛(STI Iland)，从而可以降低STI和有源区之间的应力，提高集成电路的良品率和结构稳定性。
图9是本公开一个实施例中半导体结构的示意图。
参考图9，半导体结构900用于设置存储器字线驱动电路，连接主字线MWL和与多个字线驱动电路分别对应的多条子字线SWL，包括：
第一布局区域901，用于设置多个字线驱动电路对应的多个P型晶体管MP，每个P型晶体管MP的栅极均连接主字线MWL，每个P型晶体管MP的漏极均连接对应的字线驱动电路的子字线SWL1～SWL8，每个P型晶体管的源极均连接电源电压；
第二布局区域902，包括多个如图1～图7所示实施例的半导体结构910，第二布局区域902中的半导体结构910共用第一有源区91和第二有源区92；
第三布局区域903，包括多个如图1～图7所示实施例的半导体结构910，第三布局区 域903中的半导体结构910共用第一有源区93和第二有源区94；
第二布局区域902、第一布局区域901、第三布局区域903在第二方向上顺次并列设置。
虽然图9中示出了图6或图7所示的半导体结构，但是图1～图5所示的半导体结构也在图9所示实施例的保护范围内。
同时，结合图6所示导线，展示出各半导体结构910的全部控制信号连线，以及控制信号生成区域。
从图9所示实施例可以看出，当将上述实施例中的半导体结构应用的到字线驱动电路的集中布局时，形成的字线驱动电路版图布局不但具有均匀笔直的有源区、栅极介质区，还具有位于同一金属层上的笔直均匀的走线。即，在M0层布线总体呈直线形态，NMOS布局区域(第二布局区域902、第三布局区域903)到PMOS布局区域(第一布局区域901)的走线无弯折，极大降低了金属导线层缺陷(M0defect)，提高了制程稳定性。
同时，由于走线均匀笔直且无需穿层，降低了布线金属层(即M0层)的版图设计复杂度，优化了导线的导电效果，降低了制造复杂度，提高了生产效率。
根据本公开的第三方面，提供一种芯片，包括如上任一项的半导体结构。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例提供的半导体结构，通过将四组字线驱动晶体管组分别设置在两个等宽笔直的有源区上，同时设置四组字线驱动晶体管组的栅极介质区等宽，可以形成均匀、一致的电荷通路，控制四组字线驱动晶体管组具有相同的电学特性，提高字线驱动晶体管组的导电能力，从而提高字线驱动电路的电信号传输效果。

Claims (15)

  1. 一种半导体结构，包括：
    第一有源区，沿第一方向延伸，在第二方向上具有第一宽度，所述第二方向与所述第一方向垂直；
    第二有源区，沿所述第一方向延伸，在所述第二方向上具有所述第一宽度；
    第一字线驱动晶体管组，基于所述第一有源区形成，包括连接所述第一有源区的两个栅极介质区，一个所述栅极介质区连接主字线，另一个所述栅极介质区连接第一控制信号线；
    第二字线驱动晶体管组，基于所述第一有源区形成，包括连接所述第一有源区的两个栅极介质区，一个所述栅极介质区连接所述主字线，另一个所述栅极介质区连接第二控制信号线；
    第三字线驱动晶体管组，基于所述第二有源区形成，包括连接所述第二有源区的两个栅极介质区，一个所述栅极介质区连接所述主字线，另一个所述栅极介质区连接第三控制信号线；
    第四字线驱动晶体管组，基于所述第二有源区形成，包括连接所述第二有源区的两个栅极介质区，一个所述栅极介质区连接所述主字线，另一个所述栅极介质区连接第四控制信号线；
    其中，每个所述栅极介质区均沿所述第二方向延伸且在所述第一方向上具有第二宽度。
  2. 如权利要求1所述的半导体结构，其中，所述第一字线驱动晶体管组包括第一晶体管和第二晶体管，所述第一晶体管的栅极为第一栅极介质区，所述第二晶体管的栅极为第二栅极介质区，所述第一有源区位于所述第一栅极介质区和所述第二栅极介质区之间的部分为所述第一晶体管和所述第二晶体管的共同漏极；
    第二字线驱动晶体管组，包括第三晶体管和第四晶体管，所述第三晶体管的栅极为第三栅极介质区，所述第四晶体管的栅极为第四栅极介质区，所述第一有源区位于所述第三栅极介质区和所述第四栅极介质区之间的部分为所述第三晶体管和所述第四晶体管的共同漏极；
    第三字线驱动晶体管组，包括第五晶体管和第六晶体管，所述第五晶体管的栅极为第五栅极介质区，所述第六晶体管的栅极为第六栅极介质区，所述第二有源区位于所述第五栅极介质区和所述第六栅极介质区之间的部分为所述第五晶体管和所述第六晶体管的共同漏极；
    第四字线驱动晶体管组，包括第七晶体管和第八晶体管，所述第七晶体管的栅极为第七栅极介质区，所述第八晶体管的栅极为第八栅极介质区，所述第二有源区位于所述第七栅极介质区和所述第八栅极介质区之间的部分为所述第七晶体管和所述第八晶体管的共 同漏极。
  3. 如权利要求2所述的半导体结构，其中，第一栅极介质区、第二栅极介质区、第三栅极介质区、第四栅极介质区顺次在所述第一有源区上沿所述第一方向平行设置，所述第五栅极介质区、所述第六栅极介质区、所述第七栅极介质区、所述第八栅极介质区顺次在所述第二有源区上沿所述第一方向平行设置，所述第一栅极介质区、所述第四栅极介质区、所述第五栅极介质区、所述第八栅极介质区连接所述主字线。
  4. 如权利要求3所述的半导体结构，其中，所述第一栅极介质区和所述第五栅极介质区连接，所述第四栅极介质区和所述第八栅极介质区连接，所述第一栅极介质区和所述第五栅极介质区在所述第一方向上具有第一间距，所述第四栅极介质区和所述第八栅极介质区在所述第一方向上具有所述第一间距。
  5. 如权利要求4所述的半导体结构，其中，所述第二栅极介质区与所述第六栅极介质区在所述第一方向上具有所述第一间距，所述第三栅极介质区与所述第七栅极介质区在所述第一方向上具有所述第一间距。
  6. 如权利要求4所述的半导体结构，其中，所述第一栅极介质区和所述第五栅极介质区通过第一连接结构连接，所述第一连接结构沿所述第二方向延伸，在所述第一方向上具有第三宽度，所述第三宽度小于所述第二宽度；所述第四栅极介质区和所述第八栅极介质区通过第二连接结构连接，所述第二连接结构沿所述第二方向延伸，在所述第一方向上具有所述第三宽度。
  7. 如权利要求6所述的半导体结构，其中，所述第一连接结构在所述第一方向上的第一边沿与所述第一栅极介质区在所述第一方向上的第一边沿齐平，所述第一连接结构在所述第一方向上的第二边沿与所述第五栅极介质区在所述第一方向上的第二边沿齐平；所述第二连接结构在所述第一方向上的第一边沿与所述第四栅极介质区在所述第一方向上的第一边沿齐平，所述第二连接结构在所述第一方向上的第二边沿与所述第八栅极介质区在所述第一方向上的第二边沿齐平。
  8. 如权利要求3所述的半导体结构，其中，所述第一控制信号线与所述第二控制信号线为同一信号线，所述第三控制信号线与所述第四控制信号线为同一信号线，所述第二栅极介质区与所述第三栅极介质区连接，所述第六栅极介质区与所述第七栅极介质区连接。
  9. 如权利要求8所述的半导体结构，其中，所述第二栅极介质区与所述第三栅极介质区通过第三连接结构连接，所述第三连接结构沿所述第一方向延伸，在所述第二方向上位于所述第一有源区背离所述第二有源区的一侧；所述第六栅极介质区与所述第七栅极介质区通过第四连接结构连接，所述第四连接结构沿所述第一方向延伸，在所述第二方向上位于所述第二有源区背离所述第一有源区的一侧。
  10. 如权利要求9所述的半导体结构，其中，所述第三连接结构连接所述第二栅极介质区的第一端与所述第三栅极介质区的第一端，所述第四连接结构连接所述第六栅极介质区的第二端与所述第七栅极介质区的第二端。
  11. 如权利要求4所述的半导体结构，其中，所述第一晶体管和所述第二晶体管的共同漏极通过第一导线连接所述第一字线驱动晶体管组对应的第一子字线，所述第三晶体管和所述第四晶体管的共同漏极通过第二导线连接所述第二字线驱动晶体管组对应的第二子字线，所述第一导线和所述第二导线在所述第一方向上平行，且所述第一导线和所述第二导线位于同一金属层；
    所述第五晶体管和所述第六晶体管的共同漏极通过第三导线连接所述第三字线驱动晶体管组对应的第三子字线，所述第七晶体管和所述第八晶体管的共同漏极通过第四导线连接所述第四字线驱动晶体管组对应的第四子字线，所述第三导线和所述第四导线在所述第一方向上平行，且所述第三导线和所述第四导线位于同一金属层。
  12. 如权利要求11所述的半导体结构，其中，所述第一导线连接与所述第一字线驱动晶体管组对应的第一P型晶体管的漏极，所述第二导线连接与所述第二驱动晶体管组对应的第二P型晶体管的漏极，所述第三导线连接与所述第三驱动晶体管组对应的第三P型晶体管的漏极，所述第四导线连接与所述第四驱动晶体管组对应的第四P型晶体管的漏极，所述第一P型晶体管、所述第二P型晶体管、所述第三P型晶体管、所述第四P型晶体管均设置在第一布局区域，所述第一有源区和所述第二有源区均设置在第二布局区域，所述第一布局区域和所述第二布局区域在所述第二方向上并列设置。
  13. 如权利要求5所述的半导体结构，其中，所述第二栅极介质区连接第五导线，所述第六栅极介质区连接第六导线，所述第五导线和所述第六导线在所述第一方向上平行，且所述第五导线和所述第六导线位于同一金属层。
  14. 一种半导体结构，用于设置存储器字线驱动电路，连接主字线和与多个字线驱动电路分别对应的多条子字线，包括：
    第一布局区域，用于设置多个字线驱动电路对应的多个P型晶体管，每个所述P型晶体管的栅极均连接所述主字线，每个所述P型晶体管的漏极均连接对应的字线驱动电路的子字线，每个所述P型晶体管的源极均连接电源电压；
    第二布局区域，包括多个如权利要求1～13任一项所述的半导体结构，所述第二布局区域中的半导体结构共用第一有源区和第二有源区；
    第三布局区域，包括多个如权利要求1～13任一项所述的半导体结构，所述第三布局区域中的半导体结构共用第一有源区和第二有源区；
    所述第二布局区域、所述第一布局区域、所述第三布局区域在第二方向上顺次并列设置。
  15. 一种芯片，包括如权利要求1～14任一项所述的半导体结构。
PCT/CN2022/095316 2022-05-07 2022-05-26 半导体结构及芯片 Ceased WO2023216331A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/151,515 US12183431B2 (en) 2022-05-07 2023-01-09 Semiconductor structure and chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210495446.0 2022-05-07
CN202210495446.0A CN114864538A (zh) 2022-05-07 2022-05-07 半导体结构及芯片

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/151,515 Continuation US12183431B2 (en) 2022-05-07 2023-01-09 Semiconductor structure and chip

Publications (1)

Publication Number Publication Date
WO2023216331A1 true WO2023216331A1 (zh) 2023-11-16

Family

ID=82636708

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/095316 Ceased WO2023216331A1 (zh) 2022-05-07 2022-05-26 半导体结构及芯片

Country Status (2)

Country Link
CN (1) CN114864538A (zh)
WO (1) WO2023216331A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115172364B (zh) * 2022-09-02 2022-12-06 睿力集成电路有限公司 半导体结构及存储器
CN118475111A (zh) * 2023-02-02 2024-08-09 长鑫存储技术有限公司 半导体结构及存储器
CN119012682B (zh) * 2023-05-15 2025-10-21 长鑫存储技术有限公司 一种半导体结构及其制备方法、一种存储器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101246888A (zh) * 2007-02-15 2008-08-20 台湾积体电路制造股份有限公司 集成电路、双端口静态随机存取存储器单元及半导体架构
US7729195B2 (en) * 2006-11-09 2010-06-01 Samsung Electronics Co., Ltd. Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density
CN105719684A (zh) * 2014-12-19 2016-06-29 爱思开海力士有限公司 半导体存储器件的字线驱动器电路
CN107275327A (zh) * 2011-07-26 2017-10-20 瑞萨电子株式会社 半导体器件
CN112885829A (zh) * 2019-11-29 2021-06-01 三星电子株式会社 包括集成标准单元结构的集成电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7729195B2 (en) * 2006-11-09 2010-06-01 Samsung Electronics Co., Ltd. Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density
CN101246888A (zh) * 2007-02-15 2008-08-20 台湾积体电路制造股份有限公司 集成电路、双端口静态随机存取存储器单元及半导体架构
CN107275327A (zh) * 2011-07-26 2017-10-20 瑞萨电子株式会社 半导体器件
CN105719684A (zh) * 2014-12-19 2016-06-29 爱思开海力士有限公司 半导体存储器件的字线驱动器电路
CN112885829A (zh) * 2019-11-29 2021-06-01 三星电子株式会社 包括集成标准单元结构的集成电路

Also Published As

Publication number Publication date
CN114864538A (zh) 2022-08-05

Similar Documents

Publication Publication Date Title
USRE49821E1 (en) Semiconductor integrated circuit
WO2023216331A1 (zh) 半导体结构及芯片
US20080180132A1 (en) Semiconductor device and method of fabricating the same
JP3154411B2 (ja) Ｃａｄによってレイアウトされた２金属層集積回路ゲート・アレイ
CN112992892B (zh) 标准单元版图模板以及半导体结构
US20240429163A1 (en) Semiconductor device
US9196548B2 (en) Methods of using a trench salicide routing layer
WO2024000793A1 (zh) 显示面板及显示装置
KR20050080321A (ko) 소오스 스트래핑을 갖는 플래시 메모리 소자의 셀 어레이
JP2025535215A5 (zh)
US20230360685A1 (en) Semiconductor structure and chip
JP4058234B2 (ja) 半導体装置
CN114203706A (zh) 静态随机存取存储器的存储单元结构及存储器
TWI853269B (zh) 靈敏放大器的版圖形成方法及靈敏放大器的版圖
KR100520239B1 (ko) 반도체 장치의 신호버스라인 배치구조 및 방법
TWI827232B (zh) 均衡電路結構及其製造方法、感測放大及存儲電路結構
CN115798536B (zh) 字线驱动结构、字线驱动器阵列和存储器
KR100697296B1 (ko) 소오스 스트래핑을 갖는 플래시 메모리 소자의 셀 어레이
CN120129242A (zh) 一种存储器件及存储器件的制造方法
CN118398613A (zh) 标准单元的布局结构及其布局方法
CN121793442A (zh) 显示面板及显示装置
CN114188326A (zh) 静态随机存取存储器的存储单元结构及存储器
CN118380428A (zh) 半导体结构及存储器
CN117673076A (zh) 标准单元布局及集成电路
CN118510263A (zh) 半导体结构和芯片

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22941279

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22941279

Country of ref document: EP

Kind code of ref document: A1