WO2023207673A1 - 像素驱动电路及其驱动方法、显示面板和显示装置 - Google Patents

像素驱动电路及其驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2023207673A1
WO2023207673A1 PCT/CN2023/088966 CN2023088966W WO2023207673A1 WO 2023207673 A1 WO2023207673 A1 WO 2023207673A1 CN 2023088966 W CN2023088966 W CN 2023088966W WO 2023207673 A1 WO2023207673 A1 WO 2023207673A1
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Prior art keywords
transistor
electrically connected
signal terminal
electrode
driving
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PCT/CN2023/088966
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English (en)
French (fr)
Inventor
袁长龙
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2023207673A1 publication Critical patent/WO2023207673A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present disclosure relates to the field of display technology, and more specifically, to a pixel driving circuit and a driving method thereof, a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • the display panel of the OLED display uses the driving current provided by the driving pixel circuit to control light emission.
  • the driving transistor When the data voltage is applied to the driving transistor in the pixel driving circuit, the driving transistor outputs a current corresponding to the data voltage to the OLED display, thereby driving the OLED display to emit light with corresponding brightness.
  • obvious flickering problems often occur, which degrades display quality.
  • the present disclosure proposes a pixel driving circuit and a driving method thereof, a display panel and a display device.
  • a pixel driving circuit configured to drive a light-emitting element to emit light.
  • the pixel driving circuit includes:
  • Pixel drive circuit includes:
  • the data writing subcircuit is electrically connected to the data signal terminal, the scanning signal terminal and the driving subcircuit, and under the control of the scanning signal from the scanning signal terminal, writes the data signal from the data signal terminal into the driving subcircuit, and writes the data signal from the data signal terminal to the driving subcircuit.
  • the data signal at the signal end is applied to the leakage compensation point;
  • the light-emitting control subcircuit is electrically connected to the driving sub-circuit, the light-emitting control signal terminal and the light-emitting element.
  • the light-emitting control sub-circuit is configured to control the driving sub-circuit to output the data signal to the light-emitting element under the control of the light-emitting control signal from the light-emitting control signal terminal.
  • Relevant driving current wherein during the light-emitting process of the light-emitting element, the voltage of the leakage compensation point is used to compensate the control electrode voltage of the driving sub-circuit.
  • the data writing sub-circuit includes a first transistor, a second transistor and a first dual-gate transistor, the scan signal terminal includes a first scan signal terminal, a second scan signal terminal and a third scan signal terminal, and the leakage compensation point includes a first Leakage compensation point;
  • control electrode of the first transistor is electrically connected to the first scan signal terminal
  • first electrode of the first transistor is electrically connected to the data signal terminal
  • second electrode of the first transistor is electrically connected to the double gate of the first double-gate transistor.
  • the first leakage compensation point between the first dual-gate transistor and the second scanning signal terminal is electrically connected to the gate, the first pole is connected to the predetermined initial voltage terminal, and the second pole is electrically connected to the control pole of the driving sub-circuit;
  • the control electrode of the second transistor is electrically connected to the third scan signal terminal, the first electrode of the second transistor is electrically connected to the second electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the input terminal of the driving subcircuit.
  • the data writing subcircuit further includes a third transistor and a second double-gate transistor, the scan signal terminal includes a fourth scan signal terminal, and the leakage compensation point further includes a second leakage compensation point;
  • control electrode of the third transistor is electrically connected to the fourth scan signal terminal
  • first electrode of the third transistor is electrically connected to the second electrode of the first transistor
  • second electrode of the third transistor is electrically connected to the second double-gate transistor.
  • the second leakage compensation point between the double gates; the gate electrode of the second double gate transistor is electrically connected to the third scanning signal terminal, the first electrode is electrically connected to the light-emitting control subcircuit, and the second electrode is electrically connected to the control electrode of the driving subcircuit Electrical connection.
  • the data writing sub-circuit further includes a fourth transistor
  • control electrode of the fourth transistor is electrically connected to the fourth scan signal terminal
  • first electrode of the fourth transistor is electrically connected to the second electrode of the first transistor
  • second electrode of the fourth transistor is electrically connected to the first leakage compensation point.
  • the data writing sub-circuit includes a first transistor, a second transistor and a first dual-gate transistor, the scan signal terminal includes a first scan signal terminal and a third scan signal terminal, and the leakage compensation point includes a first leakage compensation point;
  • control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the input of the driving sub-circuit. end;
  • the control electrode of the second transistor is electrically connected to the third scan signal terminal, the first electrode of the second transistor is electrically connected to the data signal terminal, and the second electrode of the second transistor is electrically connected to the gate between the double gates of the first double-gate transistor.
  • the first leakage compensation point is electrically connected to the third scan signal terminal, the first electrode of the second transistor is electrically connected to the data signal terminal, and the second electrode of the second transistor is electrically connected to the gate between the double gates of the first double-gate transistor.
  • the data writing sub-circuit includes a first transistor, a second transistor, a third transistor and a first dual-gate transistor, the leakage compensation point includes a first leakage compensation point, and the scan signal terminal includes a third scan signal terminal;
  • control electrode of the first transistor is electrically connected to the first leakage compensation point between the double gates of the first double-gate transistor, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the first electrode of the first transistor is electrically connected to the second electrode of the second transistor. the second electrode is electrically connected to the first electrode of the third transistor;
  • the control electrode of the second transistor is electrically connected to the third scan signal terminal, the first electrode of the second transistor is electrically connected to the data signal terminal, and the second electrode of the second transistor is electrically connected to the input terminal of the driving subcircuit;
  • the control electrode of the third transistor is electrically connected to the third scan signal terminal, and the second electrode of the third transistor is connected to the first leakage compensation point.
  • the data writing sub-circuit includes a first transistor, a third transistor and a second double-gate transistor, the leakage compensation point includes a first leakage compensation point, and the scan signal terminal includes a first scan signal terminal and a third scan signal terminal;
  • control electrode of the first transistor is electrically connected to the first scan signal terminal
  • first electrode of the first transistor is electrically connected to the data signal terminal
  • second electrode of the first transistor is electrically connected to the third transistor and the second double gate.
  • the control electrode of the third transistor is electrically connected to the fourth scan signal terminal, the first electrode of the third transistor is electrically connected to the first leakage compensation point, and the second electrode of the third transistor is electrically connected to the input terminal of the driving subcircuit.
  • the data writing sub-circuit further includes a fifth transistor
  • control electrode of the fifth transistor is electrically connected to the second scan signal terminal
  • first electrode of the fifth transistor is electrically connected to the predetermined initial voltage terminal
  • second electrode of the fifth transistor is electrically connected to the anode of the light-emitting element
  • the light emission control sub-circuit includes a sixth transistor and a seventh transistor;
  • control electrode of the sixth transistor is electrically connected to the light-emitting control signal terminal
  • first electrode of the sixth transistor is electrically connected to the first power supply
  • second electrode of the sixth transistor is electrically connected to the input terminal of the driving subcircuit
  • the control electrode of the seventh transistor is electrically connected to the light-emitting control signal terminal, the first electrode of the seventh transistor is electrically connected to the output terminal of the driving subcircuit, and the second electrode of the seventh transistor is electrically connected to the light-emitting element.
  • the driver subcircuit includes a driver transistor and a storage capacitor
  • control electrode of the driving transistor is electrically connected to the data writing sub-circuit
  • source electrode of the driving transistor is electrically connected to the data writing sub-circuit
  • drain electrode is electrically connected to the light-emitting control sub-circuit
  • the first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second terminal of the storage capacitor is electrically connected to the first power supply.
  • the driving current drives the light-emitting element to emit light
  • the driving current is K(Vdata-ELVDD) 2
  • K is a constant related to the driving transistor
  • Vdata is the data signal
  • ELVDD is the first power supply voltage
  • a display panel including:
  • a scan signal line configured to provide a scan signal
  • a data signal line configured to provide a data signal
  • An initialization signal line configured to provide an initialization signal
  • control signal line configured to provide a lighting control signal
  • a pixel driving circuit according to an embodiment of the present disclosure.
  • a light-emitting element a first end of the light-emitting element is connected to the pixel driving circuit, and a second end of the light-emitting element is connected to the second power source.
  • a display device including a display panel according to an embodiment of the present disclosure.
  • a pixel driving method is provided, which is applied to the pixel driving circuit according to the embodiment of the present disclosure.
  • the pixel driving method includes:
  • the light-emitting element and the driving sub-circuit are initialized using the initialization signal from the predetermined initial voltage terminal;
  • the driving sub-circuit is controlled to output a driving current related to the data signal to the light-emitting element.
  • the voltage of the leakage compensation point is used to compensate the driver sub-circuit. The control electrode voltage of the circuit.
  • a driving method is provided, which is applied to the display panel according to the embodiment of the present disclosure.
  • the driving method includes:
  • a scanning signal of an effective level to the scanning signal line provide a lighting control signal of an effective level to the control signal line, and provide an initialization signal to the data signal line;
  • a lighting control signal of an effective level is provided to the control signal line.
  • a pixel driving circuit structure is provided. After the data is written into the driving subcircuit, the data signal is applied to the leakage compensation point, so that the leakage compensation point can compensate the control electrode voltage of the driving subcircuit during the light-emitting phase, thereby providing a stable voltage for the gate of the driving transistor and improving the display. Picture quality.
  • Figure 1 shows a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2A shows a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure
  • Figure 2B shows a signal timing diagram of the pixel circuit in Figure 2A
  • 2C to 2F show equivalent circuit diagrams of a pixel circuit at different stages according to embodiments of the present disclosure
  • FIG. 3A shows a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure
  • Figure 3B shows a signal timing diagram of the pixel circuit in Figure 3A
  • FIG. 4A shows a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure
  • FIG. 4B shows a signal timing diagram of the pixel circuit in FIG. 4A
  • FIG. 5A shows a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure
  • Figures 5B to 5C show signal timing diagrams of the pixel circuit in Figure 5A;
  • FIG. 6A shows a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure
  • Figure 6B shows a signal timing diagram of the pixel circuit in Figure 6A
  • Figure 7A shows a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • Figure 7B shows a signal timing diagram of the pixel circuit in Figure 7A
  • FIG. 8A to 8D show cross-sectional views of the first transistor T8 and the first double-gate transistor T1 in the pixel circuit according to embodiments of the present disclosure
  • Figure 9 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 10 shows a schematic diagram of a stacked structure of a display panel according to an embodiment of the present disclosure.
  • FIG. 11 shows a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure.
  • connection method is: Electrical connection or coupling.
  • the two components can be connected or coupled via wired or wireless means.
  • the transistors used in the embodiments of the present disclosure may include switching transistors and driving transistors. Both the switching transistor and the driving transistor can be thin film transistors or field effect transistors or other devices with the same characteristics.
  • a P-type driving transistor is taken as an example for description.
  • the source and drain of the switching transistor used in the embodiment of the present disclosure are symmetrical, so the source and drain can be interchanged.
  • the gate electrode may be called a control electrode
  • one of the source electrode and the drain electrode may be called a first electrode
  • the other of the source electrode and the drain electrode may be called a second electrode.
  • the switching transistor is a P-type thin film transistor.
  • the embodiments of the present disclosure can obviously be applied to the case where the switching transistor is an N-type thin film transistor.
  • first power supply voltage and “second power supply voltage” are only used to distinguish the two power supply voltages from having different amplitudes.
  • first power supply voltage is a relatively high voltage
  • second power supply voltage is a relatively low voltage.
  • Embodiments of the present disclosure provide a pixel driving circuit. After data is written into the driving subcircuit, the data signal is applied to the leakage compensation point, so that the leakage compensation point can adjust the gate voltage of the driving transistor in the driving subcircuit during the light emitting stage. compensation, thereby providing a stable voltage to the gate of the driving transistor and improving the display quality.
  • the pixel driving circuit includes a driving sub-circuit, a data writing sub-circuit and a light-emitting control sub-circuit.
  • the driving subcircuit is connected to the light emitting element.
  • the data writing subcircuit is electrically connected to the data signal terminal, the scanning signal terminal and the driving subcircuit, and under the control of the scanning signal from the scanning signal terminal, writes the data signal from the data signal terminal into the driving subcircuit, and writes the data signal from the data signal terminal to the driving subcircuit.
  • the data signal at the signal end is applied to the leakage compensation point.
  • the light-emitting control subcircuit is electrically connected to the driving sub-circuit, the light-emitting control signal terminal and the light-emitting element.
  • the light-emitting control sub-circuit is configured to control the driving sub-circuit to output the data signal to the light-emitting element under the control of the light-emitting control signal from the light-emitting control signal terminal. associated drive current.
  • the voltage of the leakage compensation point is used to compensate the control electrode voltage of the driving sub-circuit.
  • FIG. 1 shows a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure. This pixel circuit is used, for example, in sub-pixels of an OLED display device.
  • the pixel circuit 100 includes a pixel driving circuit 110 and a light emitting element 120 .
  • the light-emitting element 120 may be an organic electroluminescent diode OLED, or other types of current-driven light-emitting elements.
  • the pixel driving circuit 110 includes a driving sub-circuit 111, a data writing sub-circuit 112 and a light emission control sub-circuit 113.
  • the driving subcircuit 111 is connected to the light emitting element 120 .
  • the driving sub-circuit 111 is configured to control a driving current that drives the light-emitting element 120 to emit light.
  • the data writing sub-circuit 112 is electrically connected to the data signal terminal Vdata, the scanning signal terminal Vscan and the driving sub-circuit 111. Under the control of the scan signal from the scan signal terminal Vscan, the data signal from the data signal terminal Vdata is written into the driving subcircuit 111, and the data signal from the data signal terminal Vdata is written into the driving subcircuit 111. No. is applied to the leakage compensation point M. The leakage compensation point M is connected to the control electrode of the driving sub-circuit 111.
  • the light-emitting control sub-circuit 131 is electrically connected to the driving sub-circuit 111, the light-emitting control signal terminal EM and the light-emitting element 120.
  • the light-emitting control sub-circuit 113 is configured to control the driving sub-circuit 111 to output a driving current related to the data signal to the light-emitting element 120 under the control of the light-emitting control signal from the light-emitting control signal terminal EM.
  • the light-emitting control sub-circuit 113 is connected to the first power supply ELVDD, and the light-emitting element 120 is connected to the second power supply ELVSS.
  • the first power supply VDD may provide a high voltage
  • the second power supply ELVSS may provide a low level, such as ground.
  • the voltage provided by the first power source is higher than the voltage provided by the second power source.
  • the data writing sub-circuit 112 is also connected to the predetermined initial voltage terminal VINT, and under the control of the scan signal Vscan, uses the initialization signal from the predetermined initial voltage terminal VINT to initialize the anode of the light-emitting element 120 and the control electrode of the driving sub-circuit 111 , embodiments of the present disclosure include but are not limited to this situation.
  • the voltage of the leakage compensation point M is used to compensate the control electrode voltage of the driving sub-circuit 111, so that the control electrode of the driving sub-circuit 111 is provided with a stable voltage during the light-emitting phase.
  • the leakage compensation point M is not an actual component in the circuit, but represents a certain point located on a certain circuit in the circuit diagram.
  • the symbol Vdata can represent both the data signal terminal and the level of the data signal.
  • the symbol Vscan can represent both the scanning signal terminal and the level of the scanning signal.
  • the symbol VINT can represent both the predetermined initial voltage terminal and the voltage of the initial signal.
  • the symbol ELVDD can represent both the first power supply and the first power supply voltage provided by the first power supply.
  • the symbol ELVSS can represent both the second power supply and the second power supply. The second supply voltage provided by the power supply.
  • FIG. 2A shows a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit 200 includes a pixel driving circuit 210 and a light emitting element 220.
  • Light emitting element 220 is shown as an OLED.
  • the light-emitting element OLED can be various types of OLED, such as top-emitting, bottom-emitting, double-sided emitting, etc., and can emit red light, green light, blue light, or white light, etc.
  • the embodiments of the present disclosure are not limited to this.
  • the pixel driving circuit 210 includes a driving sub-circuit 211, a data writing sub-circuit 212 and a light emission control sub-circuit 213.
  • the driving subcircuit 211 includes a driving transistor T3 and a storage capacitor CST1.
  • the gate of the driving transistor T3 is electrically connected to the data writing sub-circuit 212 at the node N1, the source of the driving transistor T3 is electrically connected to the data writing sub-circuit 212 at the node N2, and the drain of the driving transistor T3 is electrically connected to the light-emitting control sub-circuit at the node N3. 213.
  • the first terminal of the storage capacitor CST1 is electrically connected to the gate of the driving transistor T3 at the N1 node, and the second terminal of the storage capacitor CST1 is electrically connected to the first power supply ELVDD.
  • the scanning signal terminal includes a first scanning signal terminal SK, a second scanning signal terminal SI and a third scanning signal terminal SS, and the leakage compensation point includes a first leakage compensation point A.
  • the data writing sub-circuit 212 includes a first transistor T8, a second transistor T4, a first double-gate transistor T1 and a second double-gate transistor T2.
  • the first double-gate transistor T1 includes a transistor T1-1 and a transistor T1-2.
  • the second double-gate transistor T2 includes a transistor T2-1 and a transistor T2-2.
  • the first transistor T8, the second transistor T4, the first double-gate transistor T1 and the second double-gate transistor T2 are used as switching transistors.
  • the gate electrode of the first transistor T8 is electrically connected to the first scan signal terminal SK, the first electrode is electrically connected to the data signal terminal Vdata, and the second electrode is electrically connected to the first leakage compensation between the double gates of the first double-gate transistor T1 Point A.
  • the gate electrode of the first double-gate transistor T1 is electrically connected to the second scan signal terminal SI, the first electrode is connected to the predetermined initial voltage terminal VINT, and the second electrode is electrically connected to the gate electrode of the driving transistor T3 in the driving sub-circuit 211 at the N1 node. .
  • the gate electrode of the second transistor T4 is electrically connected to the third scan signal terminal SS, the first electrode is electrically connected to the second electrode of the first transistor T8, and the second electrode is electrically connected to the driving transistor T3 in the driving sub-circuit 211 at the N2 node. source.
  • the gate of the second double-gate transistor T2 is electrically connected to the third scan signal terminal SS, the first electrode is electrically connected to the drain of the driving transistor T3 at the third node N3, and the second electrode is electrically connected to the driving transistor at the first node N1 Gate of T3.
  • the data writing sub-circuit 212 also includes a fifth transistor T7, which is used as a switching transistor.
  • the gate electrode of the fifth transistor T7 is electrically connected to the second scan signal terminal SI, the first electrode is electrically connected to the predetermined initial voltage terminal VINT, and the second electrode is electrically connected to the anode of the light-emitting element 220 at the fourth node N4.
  • the light emission control sub-circuit 213 includes a sixth transistor T5 and a seventh transistor T6.
  • the sixth transistor T5 and the seventh transistor T6 are used as switching transistors.
  • the gate electrode of the sixth transistor T5 is electrically connected to the light emission control signal terminal EM, the first electrode is electrically connected to the first power supply ELVDD, and the second electrode is electrically connected to the source electrode of the driving transistor T3 in the driving sub-circuit 211 at the N1 node.
  • the gate of the seventh transistor T6 is electrically connected to the light-emitting control signal terminal EM, the first electrode is electrically connected to the drain of the driving transistor T3 in the driving sub-circuit 211 at the N3 node, and the second electrode is electrically connected to the light-emitting element at the fourth node N4 220.
  • the first node N1, the second node N2, the third node N3 and the The four nodes N4 do not represent actual existing components, but rather represent the meeting points of relevant circuit connections in the circuit diagram.
  • FIG. 2B shows a signal timing diagram of the pixel circuit in FIG. 2A.
  • the display process of each frame of image may include an initialization stage, a data writing stage, a leakage compensation stage, and a lighting stage.
  • Figure 2B shows the timing waveforms of each signal in each stage.
  • FIG. 2C shows an equivalent circuit diagram of the pixel driving circuit in the initialization stage according to an embodiment of the present disclosure.
  • FIG. 2D shows an equivalent circuit diagram of the pixel driving circuit in the data writing stage according to an embodiment of the present disclosure.
  • FIG. 2E shows is an equivalent circuit diagram of a pixel driving circuit in the leakage compensation stage according to an embodiment of the present disclosure.
  • FIG. 2F shows an equivalent circuit diagram of the pixel driving circuit in the light emitting stage according to an embodiment of the present disclosure.
  • the dotted lines with arrows in FIGS. 2C to 2F represent the current directions of the pixel circuits in corresponding stages.
  • the low level of the second scanning signal SI is the effective level
  • the other scanning signals are high level
  • the light-emitting control signal is high level.
  • the first dual-gate transistor T1 and the fifth transistor T7 are turned on.
  • the first transistor T8 is turned off by the high level of the first scan signal SK.
  • the second transistor T4 and the second double-gate transistor T2 are turned off by the high level of the third scan signal SS.
  • the sixth transistor T5 and the seventh transistor T6 are turned off by the high level of the emission control signal EM.
  • the first double-gate transistor T1 is turned on, and the initialization signal is written to the first double-gate transistor T1 along the initialization path from the predetermined initial voltage terminal VINT to the first node N1 via the first double-gate transistor T1.
  • a node N1 thereby initializing the gate voltage of the driving transistor T3 to VINT.
  • the fifth transistor T7 is turned on, and the initialization signal is written to the fourth node N4 along the initialization path from the predetermined initial voltage terminal VINT to the fourth node N4, thereby initializing the anode voltage of the light-emitting element EL to VINT.
  • the voltage difference between the initial signal terminal VINT and the second power terminal ELVSS should be less than the threshold voltage Voled of the light-emitting element EL.
  • ELVSS is the voltage at the second terminal of the light-emitting element OLED
  • Voled is the luminescence threshold voltage of the light-emitting element EL. This ensures that the light-emitting element EL does not emit light during the initialization phase.
  • the potentials of the first node N1 and the fourth node N4 are both the voltage of the initialization signal VINT.
  • the initialization signal VINT is a low-level signal, which may be ground or other low-level signals, for example.
  • the first terminal of the storage capacitor CST1 connected to the gate of the driving transistor T3 is initialized, and the second terminal of the storage capacitor CST1 is connected to the first power supply ELVDD.
  • the first power supply voltage ELVDD is a high potential voltage relative to VINT, so that the data signal in subsequent stages can be stored in the storage capacitor CST1 more quickly and reliably.
  • the low level of the first scanning signal SK and the third scanning signal SS is the effective level, the other scanning signals are high level, and the light emission control signal is high level.
  • the first transistor T8 is turned on.
  • the second transistor T4 and the second double-gate transistor T2 are turned on.
  • the first double-gate transistor T1 and the fifth transistor T7 are turned off by the high level of the second scan signal SI.
  • the sixth transistor T5 and the seventh transistor T6 are turned off by the high level of the emission control signal EM.
  • the first data signal is input from the data signal terminal Vdata, and the potential amplitude of the first data signal is Vdata.
  • the first transistor T8, the second transistor T4, the driving transistor T3, and the second double-gate transistor T2 are turned on, and the first data signal passes through the first transistor T8, the second transistor T4, along the path from the data signal terminal Vdata to the first node N1.
  • the data writing paths of the driving transistor T3 and the second double-gate transistor T2 are written into the first node N1.
  • the process of writing the first data signal to the first node N1 also charges the storage capacitor CST1. At this time, the potential of the first node N1 increases.
  • the potential of the second node N2 remains at Vdata.
  • Vth represents the threshold voltage of the driving transistor T3.
  • the driving transistor T3 is a P-type transistor as an example, so the threshold voltage Vth here may be a negative value.
  • the potentials of the first node N1 and the third node N3 are both Vdata+Vth.
  • the voltage information with the data signal Vdata and the threshold voltage Vth is stored in the storage capacitor CST1 for subsequent control of the gate of the driving transistor T3 during the light-emitting phase.
  • the low level of the first scanning signal SK is the effective level
  • the other scanning signals are high level
  • the light emission control signal is high level.
  • the first transistor T8 is turned on.
  • the second transistor T4 and the second double-gate transistor T2 are turned off by the high level of the third scan signal SS.
  • the first double-gate transistor T1 and the fifth transistor T7 are turned off by the high level of the second scan signal SI.
  • the sixth transistor T5 and the seventh transistor T6 are turned off by the high level of the light emission control signal.
  • the second data signal is input from the data signal terminal Vdata, and the potential amplitude of the second data signal is Vdata+V0.
  • the first transistor T8 is turned on, and the second data signal is written from the data signal terminal to the first leakage compensation point A via the leakage compensation path of the first transistor T8.
  • the first leakage compensation point A The potential of the first leakage compensation point A can be maintained by the parasitic capacitance between the gate and the source or drain of the first double-gate transistor T1, or by setting the capacitor CST2 at the first leakage compensation point A.
  • the first end of the capacitor CST2 is the first leakage compensation point A and is connected to the second pole of the first transistor T8, and the second end is connected to any stable voltage VREF.
  • the stable voltage VREF can be ELVSS, VINT or ELVDD, or other stable voltages.
  • the voltage V0 may be a dynamically changing value, and the average amplitude of the voltage V0 is approximately equal to the threshold voltage Vth of the driving transistor T3.
  • the amplitude of voltage V0 can be V0 ⁇ Vth ⁇ 0.5, or V0 ⁇ Vth ⁇ 1.
  • the voltage V0 amplitude can be determined by testing the threshold voltage Vth of the driving transistor T3. For example, arbitrarily select a test point on the non-display area of the display panel (the border area around the display area), perform test element area (TEG) detection, and calculate the average threshold voltage Vth of the driving transistor T3 to determine the specific V0 value. Select the width-to-length ratio of the TEG to be consistent with the width-to-length ratio of the display area.
  • the range of voltage V0 can also be optimized accurately through simulation.
  • the potential V A of the first leakage compensation point A is both Vdata+V0.
  • the voltage V N1 of the first node N1 still remains at Vdata+Vth.
  • the potential V A of the first leakage compensation point A is used to subsequently compensate the voltage V N1 threshold voltage of the first node N1 during the light-emitting phase.
  • the low level of the light-emitting control signal EM is the effective level, and the scanning signal is high level.
  • the sixth transistor T5 and the seventh transistor T6 are turned on.
  • the driving transistor T3 is turned on driven by the voltage signal stored in the storage capacitor CST1.
  • the first transistor T8 is turned off by the high level of the first scan signal SK.
  • the second transistor T4 and the second double-gate transistor T2 are turned off by the high level of the third scan signal SS.
  • the first double-gate transistor T1 and the fifth transistor T7 are turned off by the high level of the second scan signal SI.
  • the sixth transistor T5 and the seventh transistor T6 are turned on, and the driving current flows along the path from the first power supply to the light-emitting element EL via the sixth transistor T5, the driving transistor T3 and the seventh transistor T6. path is applied to the light-emitting element EL to cause the light-emitting element EL to emit light.
  • the voltage Vgs between the gate and the source of the driving transistor T3 is the same as the voltage of the first node N1 at this time, and the voltage of the source is the same as the voltage of the second node N2.
  • K ( ⁇ WC ox )/2L
  • K is a parameter related to the process and design of the driving transistor T3. Once the driving transistor T3 is made, the parameter K is a constant.
  • the pixel driving circuit according to the embodiment of the present disclosure can compensate for the threshold Vth of the driving transistor T3, which can solve the problem of threshold voltage drift of the driving transistor T3 due to the process and long-term operation, and eliminate its impact on the driving current I DS . influence, thereby improving the display effect of the display device using it.
  • the first transistor T8 , the second transistor T4 , the fifth transistor T7 , the sixth transistor T5 , the seventh transistor T6 , the first double-gate transistor T1 , the second double-gate transistor T2 and the driving transistor T3 are all It is a P-type transistor, for example, a thin film transistor whose active layer is low-temperature doped polysilicon (LTPS).
  • LTPS low-temperature doped polysilicon
  • the first transistor T8, the second transistor T4, the fifth transistor T7, the sixth transistor T5, the seventh transistor T6, the first double-gate transistor T1, the second double-gate transistor T2 and the driving transistor T3 can also be N-type transistors, such as thin film transistors whose active layer is indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the storage capacitor can be implemented as a single capacitor or a plurality of capacitor units connected in parallel or in series, as long as it can realize its corresponding function.
  • FIG. 3A shows a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit includes transistors T1 to T9, a light-emitting element EL, a storage capacitor (CST1), and capacitors (CST2-1 and CST2-2).
  • the scanning signal terminals include a first scanning signal terminal SK, a second scanning signal terminal SI, a third scanning signal terminal SS and a fourth scanning signal terminal SN.
  • the leakage compensation points include a first leakage compensation point A and a second leakage compensation point B.
  • the transistors T1 to T8, the storage capacitor CST1, the capacitor CST2-1, the scanning signal The signal terminals (the first scanning signal terminal SK, the second scanning signal terminal SI and the third scanning signal terminal SS), the predetermined initial voltage terminal VINT, the control signal terminal EM, the first power supply ELVDD and the second power supply ELVSS are respectively the same as those in FIG. 2A transistors T1 to T8, storage capacitor CST1, capacitor CST2, scanning signal terminals (first scanning signal terminal SK, second scanning signal terminal SI and third scanning signal terminal SS), predetermined initial voltage terminal VINT, control signal terminal EM,
  • the first power supply ELVDD and the second power supply ELVSS have similar functions and similar connection relationships. For the sake of simplicity, no further details are provided in this disclosure.
  • the pixel driving circuit further includes a third transistor T9, the scanning signal terminal further includes a fourth scanning signal terminal SY, and the leakage compensation point further includes a second leakage compensation point B.
  • the gate electrode of the third transistor T9 is electrically connected to the fourth scan signal terminal SY, the first electrode is electrically connected to the second electrode of the first transistor T8, and the second electrode is electrically connected to the gate between the double gates of the second double-gate transistor T2. Second leakage compensation point B.
  • FIG. 3B shows a signal timing diagram of the pixel circuit in FIG. 3A.
  • the display process of each frame of image includes an initialization stage, a data writing stage, a leakage compensation stage and a lighting stage.
  • Figure 3B shows the timing waveforms of each signal in each stage.
  • the initialization phase, data writing phase and lighting phase are respectively similar to the initialization phase, data writing phase and lighting phase in FIG. 2B.
  • no further details are provided in this disclosure.
  • the low level of the first scanning signal SK is the effective level
  • the low level of the fourth scanning signal SY is the effective level.
  • the first transistor T8 is turned on.
  • the third transistor T9 is turned on.
  • the second data signal is input from the data signal terminal Vdata, and the potential amplitude of the second data signal is Vdata+V0.
  • the first transistor T8 is turned on and the third transistor T9 is turned on.
  • the second data signal is written to the first leakage compensation point A along the path from the data signal terminal Vdata to the first leakage compensation point A via the first transistor T8.
  • the second data signal is also written along the path from the data signal terminal Vdata to the first leakage compensation point A.
  • the leakage compensation point B is written to the second leakage compensation point B via the leakage compensation path of the first transistor T8 and the third transistor T9.
  • the method of maintaining the potential of the first leakage compensation point A is similar to the process of the previous embodiment, and will not be described again in this disclosure.
  • the potential of the second leakage compensation point B can be maintained by the parasitic capacitance between the gate and the source or drain of the second double-gate transistor T2, or by setting the capacitor CST2-2 at the second leakage compensation point B.
  • the first terminal of the capacitor CST2-2 is the second leakage compensation point B and is connected to the second pole of the first transistor T8, and the second terminal is connected to any A stable voltage VREF.
  • the stable voltage VREF can be ELVSS, VINT or ELVDD, or other stable voltages.
  • the potential V B of the second leakage compensation point B is both Vdata+V0.
  • the voltage V N1 of the first node N1 still remains at Vdata+Vth.
  • the potential V B of the second leakage compensation point B and the potential V A of the first leakage compensation point A are used to subsequently compensate the voltage V N1 threshold voltage of the first node N1 during the light-emitting phase.
  • V N1 Vdata + Vth
  • VA ⁇ V B ⁇ V N1 Vdata + Vth
  • VA ⁇ V B ⁇ V N1 Vdata + Vth
  • FIG. 4A shows a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit includes transistors T1 to T10, a light-emitting element EL, a storage capacitor CST1, and capacitors (CST2-1 and CST2-2).
  • the scanning signal terminals include a first scanning signal terminal SK, a second scanning signal terminal SI, a third scanning signal terminal SS and a fourth scanning signal terminal SN.
  • the leakage compensation points include a first leakage compensation point A and a second leakage compensation point B.
  • the transistors T1 to T9, the storage capacitor CST1, the capacitor (CST2-1 and CST2-2), the scanning signal terminals (the first scanning signal terminal SK, the second scanning signal terminal SI, the third scanning signal terminal SS and the fourth scan signal terminal SN), the predetermined initial voltage terminal VINT, the control signal terminal EM, the first power supply ELVDD and the second power supply ELVSS are respectively connected with the transistors T1 to T8, the storage capacitor CST1, the capacitor (CST2-1) in Figure 3A and CST2-2), scanning signal terminals (first scanning signal terminal SK, second scanning signal terminal SI, third scanning signal terminal SS and fourth scanning signal terminal SN), predetermined initial voltage terminal VINT, control signal terminal EM,
  • the first power supply ELVDD and the second power supply ELVSS have similar functions and similar connection relationships. For the sake of simplicity, no further details are provided in this disclosure.
  • the pixel driving circuit also includes a fourth transistor T10.
  • the gate electrode of the fourth transistor T10 is electrically connected to the fourth scan signal terminal SY, the first electrode is electrically connected to the second electrode of the first transistor T8, and the second electrode is electrically connected to the gap between the double gates of the first double-gate transistor T1.
  • the first leakage compensation point A is electrically connected to the fourth scan signal terminal SY, the first electrode is electrically connected to the second electrode of the first transistor T8, and the second electrode is electrically connected to the gap between the double gates of the first double-gate transistor T1.
  • FIG. 4B shows a signal timing diagram of the pixel circuit in FIG. 4A.
  • the display process of each frame of image includes an initialization stage, a data writing stage, a leakage compensation stage and a lighting stage.
  • Figure 4B The timing waveforms of the individual signals in each stage are shown.
  • the initialization phase, data writing phase and lighting phase are respectively similar to the initialization phase, data writing phase and lighting phase in FIG. 3B.
  • no further details are provided in this disclosure.
  • the low levels of the first scanning signal SK and the fourth scanning signal SY are effective levels.
  • the first transistor T8 is turned on.
  • the fourth transistor T10 is turned on.
  • the second data signal is input from the data signal terminal Vdata, and the potential amplitude of the second data signal is Vdata+V0.
  • the first transistor T8 and the fourth transistor T10 are turned on, and the second data signal is written along the leakage compensation path from the data signal terminal Vdata to the first leakage compensation point A via the first transistor T8 and the fourth transistor T10. to the first leakage compensation point A.
  • the potential of the first leakage compensation point A increases until the potential of the first leakage compensation point A increases to Vdata+V0.
  • the process of writing the second data signal to the second leakage compensation point B is similar to the process of the previous embodiment, and will not be described in detail in this disclosure.
  • the potential V B of the second leakage compensation point B is both Vdata+V0.
  • the voltage V N1 of the first node N1 still remains at Vdata+Vth.
  • the potential VB of the second leakage compensation point B and the potential V A of the first leakage compensation point A are both used to subsequently compensate the voltage VN1 threshold voltage of the first node N1 during the light-emitting phase.
  • V N1 Vdata + Vth
  • VA ⁇ V B ⁇ V N1 Vdata + Vth
  • VA ⁇ V B ⁇ V N1 Vdata + Vth
  • FIG. 5A shows a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit includes transistors T1 to T8, a light-emitting element EL, and storage capacitors (CST1 and CST2).
  • the scanning signal terminal includes a first scanning signal terminal SK, a second scanning signal terminal SI and a third scanning signal terminal SS, and the leakage compensation point includes a first leakage compensation point A.
  • the transistors (T1 ⁇ T3 and T5 ⁇ T7), the storage capacitor CST1, the capacitor CST2, the scanning signal terminals (the first scanning signal terminal SK, the second scanning signal terminal SI and the third scanning signal terminal SS) , the predetermined initial voltage terminal VINT, the control signal terminal EM, the first power supply ELVDD and the second power supply ELVSS are respectively connected with the transistors (T1 ⁇ T3 and T5 ⁇ T7), storage capacitor CST1, capacitor CST2, scanning signal terminal (th) in Figure 2A a scanning signal terminal SK, a second scanning signal terminal SI and a third scanning signal terminal SS), a predetermined
  • the initial voltage terminal VINT, the control signal terminal EM, the first power supply ELVDD and the second power supply ELVSS have similar functions and similar connection relationships. For the sake of simplicity, no further details are provided in this disclosure.
  • the gate electrode of the first transistor T8 is electrically connected to the first scan signal terminal SK
  • the first electrode is electrically connected to the second electrode of the second transistor T4
  • the second electrode is electrically connected to the driver at the second node N2.
  • the gate electrode of the second transistor T4 is electrically connected to the third scan signal terminal SS
  • the first electrode is electrically connected to the data signal terminal Vdata
  • the second electrode is electrically connected to the first leakage compensation point between the double gates of the first double-gate transistor.
  • FIG. 5B shows a signal timing diagram of the pixel circuit in FIG. 5A.
  • the display process of each frame of image includes an initialization stage, a data writing stage, a leakage compensation stage and a lighting stage.
  • Figure 5B shows the timing waveforms of each signal in each stage.
  • the initialization phase, data writing phase and lighting phase are respectively similar to the initialization phase, data writing phase and lighting phase in FIG. 2B.
  • no further details are provided in this disclosure.
  • the second data signal is input from the data signal terminal Vdata, and the potential amplitude of the second data signal is Vdata+V0.
  • the low level of the third scanning signal SS is an effective level, and the first scanning signal SK is a high level.
  • the second transistor T4 is turned on.
  • the second data signal is written to the first leakage compensation point A along a leakage compensation path from the data signal terminal Vdata to the first leakage compensation point A via the second transistor T4.
  • the potential of the first leakage compensation point A increases until the potential of the first leakage compensation point A increases to Vdata+V0.
  • the potential V A of the first leakage compensation point A is Vdata+V0.
  • VA Vdata + V0
  • V N1 Vdata + Vth
  • VA ⁇ V N1 so that the VSD of the transistor T1-2 in the first double-gate transistor ⁇ 0.
  • the leakage current flowing through the transistor T1-2 is extremely small, and the gate potential of the driving transistor T3 can remain stable, reducing the possibility of flickering and improving the display quality.
  • FIG. 5C shows another signal timing diagram of the pixel circuit in FIG. 5A.
  • the display process of each frame image includes an initialization stage, a data writing stage, a leakage compensation stage and a lighting stage.
  • Figure 5C shows the timing waveforms of each signal in each stage.
  • the data writing stage, leakage compensation stage and light emitting stage are respectively similar to the initial data writing stage, leakage compensation stage and light emitting stage in FIG. 5B.
  • no further details are provided in this disclosure.
  • the low levels of the first scanning signal SK and the second scanning signal SI are effective levels.
  • the first transistor T8 is turned on.
  • the control of the second scan signal SI down the first double-gate transistor T1 is turned on.
  • the initialization signal is input from the predetermined initialization terminal VINT.
  • the voltage of the initialization signal VINT is written to the second node N2 along an initialization path from the predetermined initialization terminal VINT to the second node N2 via the transistor T1-1 and the first transistor T8, thereby initializing the source voltage of the driving transistor T3. is VINT.
  • the initialization process of the gate of the driving transistor T3 and the anode of the light-emitting element EL is the same as that of the corresponding embodiment in FIG. 2C , and will not be described again in this disclosure.
  • FIG. 6A shows a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit includes transistors T1 to T9, a light emitting element EL, and storage capacitors CST1 and CST2.
  • the scanning signal terminal includes a second scanning signal terminal SI and a third scanning signal terminal, and the leakage compensation point includes a first leakage compensation point A.
  • the first power supply ELVDD and the second power supply ELVSS are respectively connected to the transistors T1 to T7, the storage capacitor CST1, the capacitor CST2, the scanning signal terminal (the second scanning signal terminal SI and the third scanning signal terminal SS), and the predetermined initial voltage terminal VINT in Figure 2A , the control signal terminal EM, the first power supply ELVDD and the second power supply ELVSS have similar functions and similar connection relationships. For the sake of simplicity, no further details are provided in this disclosure.
  • the gate electrode of the first transistor T8 is electrically connected to the first leakage compensation point A between the double gates of the first double-gate transistor T1, and the first electrode is electrically connected to the second electrode of the second transistor T4, The second electrode is electrically connected to the first electrode of the third transistor T9.
  • the gate electrode of the third transistor T9 is electrically connected to the third scan signal terminal SS, and the second electrode is connected to the first leakage compensation point A between the double gates of the first double-gate transistor T1.
  • FIG. 6B shows a signal timing diagram of the pixel circuit in FIG. 6A.
  • the display process of each frame image includes an initialization stage, a data writing stage and a lighting stage.
  • Figure 6B shows the timing waveforms of each signal in each stage.
  • the light-emitting stages are respectively similar to the light-emitting stages in FIG. 2B.
  • the charging process of the first leakage compensation point A is completed in the data writing stage. Therefore, it can be considered that the data writing phase of the embodiment of the present disclosure includes a leakage compensation phase.
  • the low level of the second scanning signal SI is an effective level.
  • the first dual-gate transistor T1 is turned on.
  • the initialization signal is along from the predetermined initial voltage terminal VINT
  • the gate of the first transistor T8 is written to the gate of the first transistor T8 through the initialization path of the transistor T1-1, thereby initializing the gate voltage of the first transistor T8 to VINT.
  • the low level of the third scan signal SS is an effective level, and under the control of the third scan signal SS, the third transistor T9 is turned on. Since the gate voltage of the first transistor T8 and the gate voltage of the driving transistor T3 are initialized to VINT in the initialization stage, the first transistor T8 and the driving transistor T3 are turned on. It should be noted that the first transistor T8 and the driving transistor T3 have close threshold voltages Vth.
  • the voltage amplitude of the data signal input from the data signal terminal Vdata is Vdata.
  • the data signal is written along the data from the data signal terminal Vdata to the first leakage compensation point A via the second transistor T4, the first transistor T8 and the third transistor T9.
  • the input path is written to the first leakage compensation point A. At this time, the potential of the first leakage compensation point A increases until the potential of the first leakage compensation point A increases to Vdata+Vth.
  • the potential VA of the first leakage compensation point A is Vdata+Vth
  • the voltage V N1 of the first node N1 is Vdata+Vth.
  • the leakage current flowing through the transistor T1-2 is extremely small, and the gate of the driving transistor T3 The potential can be kept stable, reducing the possibility of flickering and improving display quality.
  • the transistor T2 may be a double-gate transistor or a single-gate transistor. Double-gate transistors can also alleviate the leakage problem of the drive transistor gate to a certain extent.
  • FIG. 7A shows a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit includes transistors T1 to T9, a light emitting element EL, a storage capacitor CST1, and a capacitor CST2.
  • the scanning signal terminal includes a first scanning signal terminal SK, a second scanning signal terminal SI, a third scanning signal terminal SS and a fourth scanning signal terminal SY, and the leakage compensation point includes the first leakage compensation point A.
  • the transistors T1 to T7, the storage capacitor CST1, the capacitor CST2, the scanning signal terminals (the first scanning signal terminal SK, the second scanning signal terminal SI, the third scanning signal terminal SS and the fourth scanning signal terminal SY ), the predetermined initial voltage terminal VINT, the control signal terminal EM, the first power supply ELVDD and the second power supply ELVSS are respectively connected with the transistors T1 to T7, the storage capacitor CST1, the capacitor CST2, the scanning signal terminal (the first scanning signal terminal SK in FIG.
  • the second scanning signal terminal SI the third scanning signal terminal SS and the fourth scanning signal terminal SY
  • the predetermined initial voltage terminal VINT the control signal terminal EM
  • the first power supply ELVDD the second power supply ELVSS
  • the gate electrode of the first transistor T8 is electrically connected to the first scan signal terminal SK, the first electrode is electrically connected to the data signal terminal Vdata, and the second electrode is electrically connected to the third transistor T9 and the second double gate terminal.
  • the first leakage compensation point A also needs to be located at the third transistor T9 and the first double-gate transistor T1.
  • the gate electrode of the third transistor T9 is electrically connected to the fourth scan signal terminal SY, the first electrode is electrically connected to the first leakage compensation point A, and the second electrode is electrically connected to the source electrode of the driving transistor T3 at the N1 node.
  • FIG. 7B shows a signal timing diagram of the pixel circuit in FIG. 7A.
  • the display process of each frame image includes an initialization stage, a data writing stage, a leakage compensation stage and a lighting stage.
  • Figure 7B shows the timing waveforms of each signal in each stage.
  • the leakage compensation stage and the light emitting stage are respectively similar to the leakage compensation stage and the light emitting stage in FIG. 2B.
  • no further details are provided in this disclosure.
  • the low levels of the second scanning signal SI and the fourth scanning signal SY are effective levels.
  • the first dual-gate transistor T1 is turned on.
  • the third transistor T9 is turned on.
  • the voltage of the initialization signal VINT is written to the first node N1 via the first dual-gate transistor T1 and the third transistor T9 along a path from the predetermined initial voltage terminal VINT to the first node N1.
  • the low levels of the third scanning signal SS and the fourth scanning signal SY are effective levels.
  • the second transistor T4 and the second double-gate transistor T2 are turned on.
  • the third transistor T9 is turned on.
  • the first data signal is input from the data signal terminal Vdata, and the potential amplitude of the first data signal is Vdata.
  • the first data signal is written to the first node N1 via the second transistor T4, the driving transistor T3, the second double-gate transistor T2 and the third transistor T9 along the path from the data signal terminal Vdata to the first node N1.
  • the driving transistor T3 is turned off.
  • the potential V A of the first leakage compensation point A is both Vdata+V0.
  • V N1 Vdata + Vth
  • VA ⁇ V N1 so that the VSD of the transistor T1-2 in the first double-gate transistor ⁇ 0.
  • the leakage current flowing through the transistor T1-2 is extremely small, and the gate potential of the driving transistor T3 can remain stable, reducing the possibility of flickering and improving the display quality.
  • FIG. 8A to 8D are cross-sectional views of the first transistor T1 and the first double-gate transistor T1 in the pixel circuit shown in FIG. 4A.
  • a barrier layer 820 , a PI base 810 , an inorganic layer 830 , and insulating layers 840 to 860 are formed on the PI base 810 in sequence.
  • the voltage on the signal line SD1 enters through the source of the first transistor T8.
  • the first leakage compensation point A between the drain of the first transistor T8 and the double gate of the first double-gate transistor T1 is electrically connected through the signal line SD2.
  • a storage capacitor CST2 is provided at the first leakage compensation point A.
  • the first leakage compensation point A can be considered as a plate of the storage capacitor CST2.
  • the gate Gate2 of the first double-gate transistor T1 or the metal layer 870 (shown in FIG. 8B ) under the channel layer serves as the other plate of the storage capacitor CST2.
  • the gate Gate2 of the first double-gate transistor T1 or the metal layer 840 under the channel layer may be electrically connected to any power source that provides a stable potential VREF through the signal line SD1.
  • FIG. 9 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • a display device 900 may include a display panel 910 , a scan driver 920 , a data driver 930 , a lighting control driver 940 , a controller 950 , and a power supply unit 960 that provides an external voltage to the display device 900 .
  • the display panel 910 includes scanning signal lines S0 to Sn, data signal lines DL1 to DLm, control signal lines EM1 to EMn, initialization signal lines VINT, and a plurality of pixel units.
  • the scanning signal lines S0 ⁇ Sn are configured to provide scanning signals.
  • Each scan signal line Sn includes a plurality of scan signal lines, which are respectively used to provide the first scan signal end SK, the second scan signal end SI, the third scan signal end SS and the fourth scan signal line of the above embodiment.
  • Signal terminal SY Signal terminal SY.
  • the data signal lines DL1 to DLm are configured to provide data signals
  • the initialization signal lines VINT are configured to provide initialization signals
  • the control signal lines EM1 to EMn are configured to provide lighting control signals.
  • the pixel unit includes any of the pixel circuits provided in the corresponding embodiments of FIG. 1, FIG. 2A, FIG. 3A, FIG. 4A, FIG. 5A, FIG. 6A, and FIG. 7A.
  • the pixel circuit includes a pixel drive circuit and a light-emitting element.
  • the pixel driving circuit includes any pixel driving circuit provided in the above embodiments. The first terminal of the light-emitting element is connected to the pixel driving circuit and the second terminal is connected to the second power supply ELVSS. where m and n are positive integers.
  • the plurality of pixel units are supplied with external voltages, such as the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage VINT from the power supply unit 960 .
  • the voltage level of the first power supply voltage ELVDD may be higher than the voltage level of the second power supply voltage ELVSS.
  • the display panel 910 includes a plurality of pixel units arranged in an approximate matrix form.
  • the plurality of scan lines S0 - Sn extend substantially in rows in the first direction and are thus parallel to each other, and the plurality of data lines substantially extend in columns in the second direction intersecting the first direction so that they are parallel to each other in the arrangement of pixels.
  • embodiments implemented by the present disclosure are not limited thereto.
  • the pixel units are respectively connected to a plurality of scan lines S0 to Sn for transmitting scan signals to the display panel 910 .
  • Each pixel unit is connected to the scan line corresponding to the corresponding row of pixels, and each pixel is also connected to the scan line of its previous row.
  • embodiments of the present disclosure are not limited thereto.
  • each pixel in the plurality of pixel units is respectively connected to transmit the data signal to the display surface.
  • One of the plurality of data lines DL1 to DLm of the panel 910 and one of the plurality of light-emitting control signal lines EM1 to EMn transmit the light-emitting control signal to the display panel 910 .
  • the scan driver 920 generates a plurality of corresponding scan signals and transmits the plurality of corresponding scan signals to the pixel unit through a plurality of scan lines S0 ⁇ Sn.
  • the data driver 930 transmits data signals to each pixel through a plurality of data lines DL1 ⁇ DLm.
  • the light emission control driver 940 generates a light emission control signal, and transmits the light emission control signal to each pixel unit through a plurality of light emission control signal lines EM1 ⁇ EMn.
  • the controller 950 converts (or changes) the plurality of video signals R, G, and B transmitted from the external source into a plurality of image data signals DR, DG, and DB, and transmits the plurality of image data signals DR, DG, and DB to the data Drive 930.
  • the controller 950 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the clock signal MCLK to generate a control signal to control the driving of the scan driver 920 , the data driver 930 , and the lighting control driver 940 . That is, the controller 950 generates and transmits the scan drive control signal SCS that controls the scan driver 20 , the data drive control signal DCS that controls the data driver 930 , and the light emission control signal ECS that controls the light emission control driver 940 .
  • the plurality of pixels respectively emit light having brightness (for example, predetermined brightness) by the driving current supplied to the OLED in each pixel.
  • the display device 900 can be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.
  • FIG. 10 shows a schematic diagram of a stacked structure of display panels according to an embodiment of the present disclosure.
  • a thin film transistor array TFT1020, an emission layer EML1030, a packaging film layer TFE1040, a touch electrode layer Touch1050, a polarizing layer 1060 and a cover plate 1070 are sequentially formed on the LTPS substrate 1010.
  • the polarizing layer can also be a filter layer.
  • FIG. 11 shows a flowchart of a driving method of a pixel driving circuit according to an embodiment of the present disclosure.
  • a driving method of a pixel driving circuit according to an embodiment of the present disclosure may include the following steps. It should be noted that the sequence number of each step in the following method is only used as a representation of the step for the purpose of description, and should not be regarded as indicating the execution order of the respective steps. Unless explicitly stated, the methods need not be performed in exactly the order shown.
  • step S1110 in the first period, under the control of the scanning signal from the scanning signal terminal, the light-emitting element and the driving sub-circuit are initialized using the initialization signal from the predetermined initial voltage terminal.
  • step S1120 in the second period, under the control of the scanning signal from the scanning signal terminal, the data signal from the data signal terminal is written into the driving subcircuit.
  • step S1130 in the third period, the data signal from the data signal terminal is applied to the leakage compensation point under the control of the scan signal from the scan signal terminal.
  • step S1140 in the fourth period, under the control of the light-emitting control signal from the light-emitting control signal terminal, the driving sub-circuit is controlled to output a driving current related to the data signal to the light-emitting element.
  • the voltage of the leakage compensation point is used to compensate the gate voltage of the driving sub-circuit.
  • the second scan signal SI is at an effective level and the first dual-gate transistor T1 is turned on.
  • the first scan signal SK and the third scan signal SS are at the effective level, the first transistor T8 and the second transistor T4 are turned on, and the first transistor T8 and the second transistor T4 transmit the first signal from the data signal terminal.
  • the data signal is written to the driver subcircuit.
  • the first scan signal is at an effective level, the first transistor T8 is turned on, and the second data signal from the data signal terminal is applied to the first leakage compensation point through the first transistor T8.
  • the fourth scan signal SY is at an effective level
  • the third transistor T9 and/or the fourth transistor T10 are turned on, and the second data signal from the data signal terminal is applied to the third transistor T9 through the turn on.
  • the second leakage compensation point, and/or the second data signal from the data signal terminal is applied to the first leakage compensation point through the fourth transistor T10.
  • the third scan signal SS is at an effective level
  • the second transistor T4 is turned on
  • the second data signal from the data signal terminal is applied to the first leakage compensation through the second transistor T4 point.
  • the first scan signal SK is at an effective level
  • the first transistor T8 is turned on
  • the input end of the driving subcircuit is initialized through the first transistor T8 using the initialization signal.
  • the third scan signal SS is at an effective level
  • the first transistor T8, the second transistor T4 and the third transistor T9 are turned on
  • the second transistor T4 The first data signal from the data signal terminal is written to the input terminal of the driving sub-circuit, and the first data signal from the data signal terminal is applied to the first leakage compensation point A through the first transistor T8 and the third transistor T9.
  • the third scan signal SS and the fourth scan signal SN are at an effective level
  • the second transistor T4 and the third transistor are turned on T9
  • the third transistor T9 is turned on through the third scan signal SS and the fourth scan signal SN.
  • the two double-gate transistors T2, the second transistor T4 and the third transistor T9 pass the third signal from the data signal terminal. A data signal is written into the driver subcircuit.
  • the amplitude of the second data signal is the sum of the amplitude of the first data signal and the amplitude of the additional signal, and the amplitude of the additional signal is related to the threshold voltage of the driving transistor.

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Abstract

一种像素驱动电路（110）及驱动方法、显示面板（610）和显示装置（900）。像素驱动电路（110）配置为驱动发光元件（120）发光，像素驱动电路（110）包括：驱动子电路（111），连接至发光元件（120）；数据写入子电路（112），电连接至数据信号端（Vdata）、扫描信号端（Vscan）和驱动子电路（111），并在来自扫描信号端（Vscan）的扫描信号的控制下，将来自数据信号端（Vdata）的数据信号写入驱动子电路（111），以及将来自数据信号端（Vdata）的数据信号施加至漏电补偿点（M）；以及发光控制子电路（113），电连接至驱动子电路（111）、发光控制信号端（EM）和发光元件（120），发光控制子电路（113）配置为在来自发光控制信号端（EM）的发光控制信号的控制下，控制驱动子电路（111）向发光元件（120）输出与数据信号相关的驱动电流，其中，在发光元件（120）的发光过程中，利用漏电补偿点（M）的电压补偿驱动子电路（113）的控制极电压。

Description

像素驱动电路及其驱动方法、显示面板和显示装置
本申请要求于2022年4月29日提交的、申请号为202210477952.7的中国专利申请的优先权，其全部内容一并在此作为引用。
技术领域
本公开涉及显示技术领域，更具体地，涉及一种像素驱动电路及其驱动方法、显示面板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器是当今平板显示器研究领域的热点之一。
OLED显示器的显示面板利用驱动像素电路提供的驱动电流来控制发光。当数据电压被施加到像素驱动电路中的驱动晶体管时，驱动晶体管向OLED显示器输出与数据电压对应的电流，从而驱动OLED显示器发出相应亮度的光。然而，在低频驱动像素电路中，常会出现较为明显地闪烁问题，劣化显示质量。
发明内容
本公开提出了一种像素驱动电路及其驱动方法、显示面板和显示装置。
根据本公开的一个方面，提出了一种像素驱动电路，配置为驱动发光元件发光，像素驱动电路包括：
像素驱动电路包括：
驱动子电路，连接至发光元件；
数据写入子电路，电连接至数据信号端、扫描信号端和驱动子电路，并在来自扫描信号端的扫描信号的控制下，将来自数据信号端的数据信号写入驱动子电路，以及将来自数据信号端的数据信号施加至漏电补偿点；以及
发光控制子电路，电连接至驱动子电路、发光控制信号端和发光元件，发光控制子电路配置为在来自发光控制信号端的发光控制信号的控制下，控制驱动子电路向发光元件输出与数据信号相关的驱动电流，其中，在发光元件的发光过程中，利用漏电补偿点的电压补偿驱动子电路的控制极电压。
例如，数据写入子电路包括第一晶体管、第二晶体管和第一双栅晶体管，扫描信号端包括第一扫描信号端、第二扫描信号端和第三扫描信号端，漏电补偿点包括第一漏电补偿点；
其中，第一晶体管的控制极电连接至第一扫描信号端，第一晶体管的第一极电连接至数据信号端，第一晶体管的第二极电连接至第一双栅晶体管的双栅之间的第一漏电补偿点，第一双栅晶体管的栅极与第二扫描信号端电连接，第一极与预定初始电压端相连，第二极与驱动子电路的控制极电连接；
第二晶体管的控制极电连接至第三扫描信号端，第二晶体管的第一极电连接至第一晶体管的第二极，第二晶体管的第二极电连接至驱动子电路的输入端。
例如，数据写入子电路还包括第三晶体管和第二双栅晶体管，扫描信号端包括第四扫描信号端，漏电补偿点还包括第二漏电补偿点；
其中，第三晶体管的控制极电连接至第四扫描信号端，第三晶体管的第一极电连接至第一晶体管的第二极，第三晶体管的第二极电连接至第二双栅晶体管的双栅之间的第二漏电补偿点；第二双栅晶体管的栅极与第三扫描信号端电连接，第一极与发光控制子电路电连接，第二极与驱动子电路的控制极电连接。
例如，数据写入子电路还包括第四晶体管；
其中，第四晶体管的控制极电连接至第四扫描信号端，第四晶体管的第一极电连接至第一晶体管的第二极，第四晶体管的第二极电连接至第一漏电补偿点。
例如，数据写入子电路包括第一晶体管、第二晶体管和第一双栅晶体管，扫描信号端包括第一扫描信号端和第三扫描信号端，漏电补偿点包括第一漏电补偿点；
其中，第一晶体管的控制极电连接至第一扫描信号端，第一晶体管的第一极电连接至第二晶体管的第二极，第一晶体管的第二极电连接至驱动子电路的输入端；以及
第二晶体管的控制极电连接至第三扫描信号端，第二晶体管的第一极电连接至数据信号端，第二晶体管的第二极电连接至第一双栅晶体管的双栅之间的第一漏电补偿点。
例如，数据写入子电路包括第一晶体管、第二晶体管、第三晶体管和第一双栅晶体管，漏电补偿点包括第一漏电补偿点，扫描信号端包括第三扫描信号端；
其中，第一晶体管的控制极电连接至第一双栅晶体管的双栅之间的第一漏电补偿点，第一晶体管的第一极电连接至第二晶体管的第二极，第一晶体管的第二极电连接至第三晶体管的第一极；
第二晶体管的控制极电连接至第三扫描信号端，第二晶体管的第一极电连接至数据信号端，第二晶体管的第二极电连接至驱动子电路的输入端；以及
第三晶体管的控制极电连接至第三扫描信号端，第三晶体管的第二极在连接至第一漏电补偿点。
例如，数据写入子电路包括第一晶体管、第三晶体管和第二双栅晶体管，漏电补偿点包括第一漏电补偿点，扫描信号端包括第一扫描信号端和第三扫描信号端；
其中，第一晶体管的控制极电连接至第一扫描信号端，第一晶体管的第一极电连接至数据信号端，第一晶体管的第二极电连接至位于第三晶体管与第二双栅晶体管之间的第一漏电补偿点；以及
第三晶体管的控制极电连接至第四扫描信号端，第三晶体管的第一极电连接至第一漏电补偿点，第三晶体管的第二极电连接至驱动子电路的输入端。
例如，数据写入子电路还包括第五晶体管；
其中，第五晶体管的控制极电连接至第二扫描信号端，第五晶体管的第一极电连接至预定初始电压端，第五晶体管的第二极电连接至发光元件的阳极。
例如，发光控制子电路包括第六晶体管和第七晶体管；
其中，第六晶体管的控制极电连接至发光控制信号端，第六晶体管的第一极电连接至第一电源，第六晶体管的第二极电连接至驱动子电路的输入端；以及
第七晶体管的控制极电连接至发光控制信号端，第七晶体管的第一极电连接至驱动子电路的输出端，第七晶体管的第二极电连接至发光元件。
例如，驱动子电路包括驱动晶体管和存储电容；
其中，驱动晶体管的控制极电连接至数据写入子电路，驱动晶体管的源极电连接至数据写入子电路，漏极电连接至发光控制子电路；以及
存储电容的第一端电连接至驱动晶体管的控制极，存储电容的第二端电连接至第一电源。
例如，当驱动电流驱动发光元件发光时，驱动电流为K(Vdata-ELVDD)2，其中K为与驱动晶体管相关的常数，Vdata为数据信号，ELVDD为第一电源电压。
根据本公开实施例的另一方面，提供了一种显示面板，包括：
扫描信号线，配置为提供扫描信号；
数据信号线，配置为提供数据信号；
初始化信号线，配置为提供初始化信号；
控制信号线，配置为提供发光控制信号；
根据本公开实施例的像素驱动电路；以及
发光元件，发光元件的第一端连接至像素驱动电路，发光元件的第二端连接至第二电源。
根据本公开实施例的另一方面，提供了一种显示装置，包括根据本公开实施例的显示面板。
根据本公开实施例的另一方面，提供了一种像素驱动方法，应用于根据本公开实施例的像素驱动电路，像素驱动方法包括：
在第一时段，来自扫描信号端的扫描信号的控制下，利用来着预定初始电压端的初始化信号对发光元件和驱动子电路进行初始化；
在第二时段，来自扫描信号端的扫描信号的控制下，将来自数据信号端的数据信号写入驱动子电路；
在第三时段，来自扫描信号端的扫描信号的控制下，将来自数据信号端的数据信号施加至漏电补偿点；以及
在第四时段，来自发光控制信号端的发光控制信号的控制下，控制驱动子电路向发光元件输出与数据信号相关的驱动电流，其中，在第四时段中，利用漏电补偿点的电压补偿驱动子电路的控制极电压。
根据本公开实施例的另一方面，提供了一种驱动方法，应用于根据本公开实施例的显示面板，驱动方法包括：
向扫描信号线提供有效电平的扫描信号，向控制信号线提供有效电平的发光控制信号，向数据信号线提供初始化信号；
向扫描信号线提供有效电平的扫描信号，向数据信号线提供数据信号；以及
向控制信号线提供有效电平的发光控制信号。
根据公开实施例的技术方案，提供了一种像素驱动电路结构。在数据写入驱动子电路后，将数据信号施加至漏电补偿点，使得在发光阶段漏电补偿点可以对驱动子电路的控制极电压进行补偿，从而为驱动晶体管的栅极提供稳定电压，提高显示画面质量。
附图说明
通过下面结合附图说明本公开实施例，将使本公开实施例的上述及其它目的、特征和优点更加清楚。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。图中：
图1示出了本公开实施例的像素电路的结构示意图；
图2A示出了根据本公开实施例的另一像素电路的结构示意图；
图2B示出了图2A中的像素电路的信号时序图；
图2C～图2F示出了根据本公开实施例的像素电路在不同阶段的等效电路图；
图3A示出了根据本公开实施例的另一像素电路的结构示意图；
图3B示出了图3A中的像素电路的信号时序图；
图4A示出了根据本公开实施例的另一像素电路的结构示意图；
图4B示出了图4A中的像素电路的信号时序图
图5A示出了根据本公开实施例的另一像素电路的结构示意图；
图5B～5C示出了图5A中的像素电路的信号时序图；
图6A示出了根据本公开实施例的另一像素电路的结构示意图；
图6B示出了图6A中的像素电路的信号时序图；
图7A示出了根据本公开实施例的像素电路的结构示意图；
图7B示出了图7A中的像素电路的信号时序图；
图8A～8D示出了根据本公开实施例的像素电路中的第一晶体管T8和第一双栅晶体管T1的截面图；
图9示出了根据本公开实施例的显示装置的结构示意图；
图10示出了根据本公开实施例的显示面板的堆叠结构的示意图；以及
图11示出了本公开实施例的像素电路的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“连接至”或“相连”可以是指两个组件直接连接，也可以是指两个组件之间经由一个或多个其他组件相连，连接方式为电连接或电耦合。此外，这两个组件还可以通过有线或无线方式相连或相耦合。
根据其功能不同，本公开实施例中采用的晶体管可以包括开关晶体管和驱动晶体管。开关晶体管和驱动晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开示例中，以P型驱动晶体管为例进行描述。
本公开实施例中使用的开关晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，根据其功能，可以将栅极称作控制极，将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。在以下示例中以开关晶体管为P型薄膜晶体管为例进行描述。本领域技术人员可以理解，本公开实施例显然可以应用于开关晶体管为N型薄膜晶体管的情况。
此外，在本公开实施例的描述中，术语“第一电源电压”和“第二电源电压”仅用于区别两个电源电压的幅度不同。例如，下文中以“第一电源电压”为相对高电压、“第二电源电压”为相对低电压为例进行描述。本领域技术人员可以理解，本公开不局限于此。
在低频驱动像素电路中，例如刷新频率为1Hz、5Hz、10Hz、15Hz、30Hz或60Hz时，由于单行发光元件在显示中的发光时间较长，期间驱动晶体管的栅极会出现漏电现象。由于驱动晶体管的栅极电位改变，会引起较为明显的闪烁问题，从而影响显示器的显示效果。
本公开实施例提供了一种像素驱动电路，在数据写入驱动子电路后，将数据信号施加至漏电补偿点，使得在发光阶段漏电补偿点可以对驱动子电路中驱动晶体管的栅极电压进行补偿，从而为驱动晶体管的栅极提供稳定电压，提高显示画面质量。
本公开实施例提供的像素驱动电路包括驱动子电路、数据写入子电路和发光控制子电路。驱动子电路连接至发光元件。数据写入子电路，电连接至数据信号端、扫描信号端和驱动子电路，并在来自扫描信号端的扫描信号的控制下，将来自数据信号端的数据信号写入驱动子电路，以及将来自数据信号端的数据信号施加至漏电补偿点。发光控制子电路，电连接至驱动子电路、发光控制信号端和发光元件，发光控制子电路配置为在来自发光控制信号端的发光控制信号的控制下，控制驱动子电路向发光元件输出与数据信号相关的驱动电流。在发光元件的发光过程中，利用漏电补偿点的电压补偿驱动子电路的控制极电压。
下面，将参照附图详细描述根据本公开的各个实施例。需要注意的是，在附图中，将相同的附图标记赋予基本上具有相同或类似结构和功能的组成部分，并且将省略关于它们的重复描述。
图1示出了本公开实施例的像素电路的结构示意图。该像素电路例如用于OLED显示装置的子像素。
如图1所示，像素电路100包括像素驱动电路110和发光元件120。发光元件120可以是有机电致发光二极管OLED，也可以是其他类型的电流驱动型发光元件。像素驱动电路110包括驱动子电路111、数据写入子电路112和发光控制子电路113。
驱动子电路111连接至发光元件120。驱动子电路111配置为控制驱动发光元件120发光的驱动电流。
数据写入子电路112电连接至数据信号端Vdata、扫描信号端Vscan和驱动子电路111。在来自扫描信号端Vscan的扫描信号的控制下，将来自数据信号端Vdata的数据信号写入驱动子电路111，以及将来自数据信号端Vdata的数据信 号施加至漏电补偿点M。漏电补偿点M与驱动子电路111的控制极相连。
发光控制子电路131电连接至驱动子电路111、发光控制信号端EM和发光元件120。发光控制子电路113配置为在来自发光控制信号端EM的发光控制信号的控制下，控制驱动子电路111向发光元件120输出与数据信号相关的驱动电流。
根据本公开实施例，发光控制子电路113与第一电源ELVDD相连，发光元件120与第二电源ELVSS相连。例如，第一电源VDD提供的可以是高电压，第二电源ELVSS提供的可以是低电平，例如接地。第一电源提供的电压高于第二电源提供的电压。
数据写入子电路112还与预定初始电压端VINT相连，并在扫描信号Vscan的控制下，利用来自预定初始电压端VINT的初始化信号对发光元件120的阳极和驱动子电路111的控制极进行初始化，本公开的实施例包括但不限于此情形。
在发光元件120的发光过程中，利用漏电补偿点M的电压补偿驱动子电路111的控制极电压，使得驱动子电路111的控制极在发光阶段被提供稳定的电压。
需要说明是，在本公开实施例的说明中，漏电补偿点M并非电路中实际存在的部件，而是表示位于电路图中某一电路上的某一点。符号Vdata既可以表示数据信号端又可以表示数据信号的电平。同样地，符号Vscan既可以表示扫描信号端又可以表示扫描信号的电平。符号VINT既可以表示预定初始电压端又可以表示初始信号的电压，符号ELVDD既可以表示第一电源又可以表示第一电源提供的第一电源电压，符号ELVSS既可以表示第二电源又可以第二电源提供的第二电源电压。以下各实施例与此相同，不再赘述。
图2A示出了根据本公开实施例的另一像素电路的结构示意图。如图2A所示，像素电路200包括像素驱动电路210和发光元件220。发光元件220示出为OLED。例如，发光元件OLED可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
像素驱动电路210包括驱动子电路211、数据写入子电路212和发光控制子电路213。
驱动子电路211包括驱动晶体管T3和存储电容CST1。
驱动晶体管T3的栅极在节点N1电连接至数据写入子电路212，驱动晶体管T3的源极在节点N2电连接至数据写入子电路212，漏极在节点N3电连接至发光控制子电路213。存储电容CST1的第一端在N1节点电连接至驱动晶体管T3的栅极，存储电容CST1的第二端电连接至第一电源ELVDD。
扫描信号端包括第一扫描信号端SK、第二扫描信号端SI和第三扫描信号端SS，漏电补偿点包括第一漏电补偿点A。
数据写入子电路212包括第一晶体管T8、第二晶体管T4、第一双栅晶体管T1和第二双栅晶体管T2。第一双栅晶体管T1包括晶体管T1-1和晶体管T1-2。第二双栅晶体管T2包括晶体管T2-1和晶体管T2-2。第一晶体管T8、第二晶体管T4、第一双栅晶体管T1和第二双栅晶体管T2被用作开关晶体管。
第一晶体管T8的栅极电连接至第一扫描信号端SK，第一极电连接至数据信号端Vdata，第二极电连接至第一双栅晶体管T1的双栅之间的第一漏电补偿点A。第一双栅晶体管T1的栅极与第二扫描信号端SI电连接，第一极与预定初始电压端VINT相连，第二极与驱动子电路211中驱动晶体管T3的栅极在N1节点电连接。第二晶体管T4的栅极电连接至第三扫描信号端SS，第一极电连接至第一晶体管T8的第二极，第二极在N2节点电连接至驱动子电路211中驱动晶体管T3的源极。第二双栅晶体管T2的栅极电连接至第三扫描信号端SS，第一极在第三节点N3电连接至驱动晶体管T3的漏极，第二极在第一节点N1电连接至驱动晶体管T3的栅极。
数据写入子电路212还包括第五晶体管T7，第五晶体管T7被用作开关晶体管。第五晶体管T7的栅极电连接至第二扫描信号端SI，第一极电连接至预定初始电压端VINT，第二极在第四节点N4电连接至发光元件220的阳极。
发光控制子电路213包括第六晶体管T5和第七晶体管T6。第六晶体管T5和第七晶体管T6被用作开关晶体管。
第六晶体管T5的栅极电连接至发光控制信号端EM，第一极电连接至第一电源ELVDD，第二极在N1节点电连接至驱动子电路211中驱动晶体管T3的源极。第七晶体管T6的栅极电连接至发光控制信号端EM，第一极在N3节点电连接至驱动子电路211中驱动晶体管T3的漏极，第二极在第四节点N4电连接至发光元件220。
在本公开实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第 四节点N4并非表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
图2B示出了图2A中的像素电路的信号时序图。如图2B所示，每一帧图像的显示过程可以包括初始化阶段、数据写入阶段、漏电补偿阶段和发光阶段。图2B示出了每个阶段中各个信号的时序波形。
图2C示出了根据本公开实施例的像素驱动电路在初始化阶段的等效电路图，图2D示出了根据本公开实施例的像素驱动电路在数据写入阶段的等效电路图，图2E示出了根据本公开实施例的像素驱动电路在漏电补偿阶段的等效电路图。图2F示出了根据本公开实施例的像素驱动电路在发光阶段的等效电路图。图2C～图2F中带箭头的虚线表示像素电路在对应阶段内的电流方向。
接下来，将参考图2A～图2F，详细描述根据本公开实施例的像素驱动电路的操作。
在初始化阶段，第二扫描信号SI的低电平为有效电平，其他扫描信号为高电平，发光控制信号为高电平。在第二扫描信号SI的控制下，第一双栅晶体管T1和第五晶体管T7导通。第一晶体管T8被第一扫描信号SK的高电平截止。第二晶体管T4和第二双栅晶体管T2被第三扫描信号SS的高电平截止。第六晶体管T5和第七晶体管T6被发光控制信号EM的高电平截止。
如图2C所示，在初始化阶段，第一双栅晶体管T1导通，初始化信号沿着从预定初始电压端VINT到第一节点N1经由第一双栅晶体管T1的初始化路径，被写入到第一节点N1，从而对驱动晶体管T3的栅极电压初始化为VINT。第五晶体管T7导通，初始化信号沿着从预定初始电压端VINT到第四节点N4的初始化路径，被写入到第四节点N4，从而将发光元件EL的阳极电压初始化为VINT。
可以理解，初始信号端VINT与第二电源端ELVSS的电压差(VINT-ELVSS)应小于发光元件EL的阈值电压Voled。其中，ELVSS为发光元件OLED的第二端的电压，Voled是发光元件EL的发光阈值电压。由此可以确保在初始化阶段中发光元件EL不会发光。
在经过初始化阶段后，第一节点N1和第四节点N4的电位均为初始化信号VINT的电压。初始化信号VINT为低电平信号，例如可以是接地或者其他低电平信号。存储电容CST1与驱动晶体管T3的栅极连接的第一端被初始化，存储电容CST1的第二端连接第一电源ELVDD。此时，存储电容CST1的两端的电 压为VC＝ELVDD-VN1＝＝ELVDD-VINT。第一电源电压ELVDD为相对于VINT的高电位电压，从而使后续阶段中的数据信号可以被更迅速、更可靠地存储在存储电容CST1中。
在数据写入阶段，第一扫描信号SK和第三扫描信号SS的低电平为有效电平，其他扫描信号为高电平，发光控制信号为高电平。在第一扫描信号SK的控制下，第一晶体管T8导通。在第三扫描信号SS的控制下，第二晶体管T4和第二双栅晶体管T2导通。第一双栅晶体管T1和第五晶体管T7被第二扫描信号SI的高电平截止。第六晶体管T5和第七晶体管T6被发光控制信号EM的高电平截止。
如图2D所示，在数据写入阶段，第一数据信号从数据信号端Vdata输入，第一数据信号的电位幅值为Vdata。第一晶体管T8、第二晶体管T4、驱动晶体管T3、第二双栅晶体管T2导通，第一数据信号沿着从数据信号端Vdata到第一节点N1经由第一晶体管T8、第二晶体管T4、驱动晶体管T3、第二双栅晶体管T2的数据写入路径，被写入第一节点N1。将第一数据信号写入第一节点N1的过程也是对存储电容CST1充电。此时，第一节点N1的电位升高。第二节点N2的电位保持为Vdata，同时根据驱动晶体管T3的自身特性，当第一节点N1的电位增大到Vdata+Vth时，驱动晶体管T3截止，充电过程结束。需要说明的是，Vth表示驱动晶体管T3的阈值电压，由于在本实施例中，驱动晶体管T3是以P型晶体管为例就行说明的，所以此处阈值电压Vth可以是个负值。
在经过数据写入阶段后，第一节点N1和第三节点N3的电位均为Vdata+Vth。此时，将带有数据信号Vdata和阈值电压Vth的电压信息存储在了存储电容CST1中，以用于后续在发光阶段控制驱动晶体管T3的栅极。
在漏电补偿阶段，第一扫描信号SK的低电平为有效电平，其他扫描信号为高电平，发光控制信号为高电平。在第一扫描信号SK的控制下，第一晶体管T8导通。第二晶体管T4和第二双栅晶体管T2被第三扫描信号SS的高电平截止。第一双栅晶体管T1和第五晶体管T7被第二扫描信号SI的高电平截止。第六晶体管T5和第七晶体管T6被发光控制信号的高电平截止。
如图2E所示，在漏电补偿阶段，第二数据信号从数据信号端Vdata输入，第二数据信号的电位幅值为Vdata+V0。第一晶体管T8导通，第二数据信号从数据信号端到第一漏电补偿点A经由第一晶体管T8的漏电补偿路径，被写入到 第一漏电补偿点A。第一漏电补偿点A的电位可以通过第一双栅晶体管T1的栅极与源极或漏极之间的寄生电容保持，也可以通过在第一漏电补偿点A处设置电容CST2保持。在第一漏电补偿点A处设置有电容CST2的情况下，电容CST2的第一端为第一漏电补偿点A，与第一晶体管T8的第二极相连，第二端连接任一稳定电压VREF。稳定电压VREF可以是ELVSS、VINT或ELVDD，也可以是其他稳定电压。在对第一漏电补偿点A进行充电的同时，对电容CST2充电。此时，第一漏电补偿点A的电位升高，直至第一漏电补偿点A的电位增大到Vdata+V0，充电过程结束。
需要说明的是，电压V0可以是一个动态变化的值，电压V0的平均幅值与驱动晶体管T3的阈值电压Vth近似相等。电压V0的幅值可以为V0≈Vth±0.5，或者V0≈Vth±1。电压V0幅值可以通过测试驱动晶体管T3的阈值电压Vth来确定。例如，在显示面板的非显示区域(显示区域外围的边框区域)上任意选择测试点，进行测试单元区(Test Element Group，TEG)检测，计算驱动晶体管T3的阈值电压Vth平均值以确定具体V0的数值。选择TEG的宽长比与显示区域的宽长比一致。电压V0的范围还可以通过仿真进行优化精确。
在经过漏电补偿阶段后，第一漏电补偿点A的电位VA均为Vdata+V0。此时，第一节点N1的电压VN1仍然保持为Vdata+Vth。第一漏电补偿点A的电位VA用于后续在发光阶段对第一节点N1的电压VN1阈值电压进行补偿。
在发光阶段，发光控制信号EM的低电平为有效电平，扫描信号为高电平。发光控制信号EM的控制下，第六晶体管T5和第七晶体管T6导通。驱动晶体管T3在存储电容CST1存储的电压信号的驱动下导通。第一晶体管T8被第一扫描信号SK的高电平截止。第二晶体管T4和第二双栅晶体管T2被第三扫描信号SS的高电平截止。第一双栅晶体管T1和第五晶体管T7被第二扫描信号SI的高电平截止。
如图2F所示，在发光阶段，第六晶体管T5和第七晶体管T6导通，驱动电流沿着从第一电源到发光元件EL经由第六晶体管T5、驱动晶体管T3和第七晶体管T6的发光路径，被施加至发光元件EL以使发光元件EL发光。此时，第二节点N2与第一电源ELVDD相连，第一电源ELVDD的第一电源电压被施加到第二节点N2，VN2＝ELVDD。VA和VN1保持不变，VA＝Vdata+V0，VN1＝Vdata+Vth，VA≈VN1，从而第一双栅晶体管中晶体管T1-2的VSD≈0。此时流过晶体管T1-2 的漏电流极小，驱动晶体管T3的栅极电位可以保持稳定，减少闪烁的可能，提高显示质量。
流经驱动晶体管Td的驱动电流IDS可以根据IDS＝K(Vgs-Vth)2计算得到。驱动晶体管T3的栅极和源极之间的电压Vgs根据此时驱动晶体管T3栅极电压与第一节点N1的电压相同，源极的电压与第二节点N2的电压相同。Vgs＝VN1-VN2＝Vdata+Vth-VDD，由此IDS＝K(Vgs-Vth)2＝K(Vdata+Vth-VDD-Vth)2＝K(Vdata-VDD)2。其中，K＝(μWCox)/2L，K为与驱动晶体管T3的工艺和设计相关的参数，一旦驱动晶体管T3制成，该参数K为常数。
可以看出，以上驱动电流IDS与驱动晶体管T3的驱动晶体管T3的阈值电压Vth均无关。因此，根据本公开实施例的像素驱动电路能够对驱动晶体管T3的阈值Vth的补偿，可以解决驱动晶体管T3由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流IDS的影响，从而可以改善采用其的显示装置的显示效果。
在图2A的示例中，第一晶体管T8、第二晶体管T4、第五晶体管T7、第六晶体管T5、第七晶体管T6、第一双栅晶体管T1、第二双栅晶体管T2以及驱动晶体管T3均为P型晶体管，例如有源层为低温掺杂多晶硅(LTPS)的薄膜晶体管。本领域技术人员可以理解，根据本公开实施例，第一晶体管T8、第二晶体管T4、第五晶体管T7、第六晶体管T5、第七晶体管T6、第一双栅晶体管T1、第二双栅晶体管T2以及驱动晶体管T3也可以为N型晶体管，例如有源层为铟镓锌氧化物(IGZO)的薄膜晶体管，相应改变各晶体管的栅极导通信号的电平即可。
此外，本领域技术人员可以理解，存储电容可以被分别实现为单个电容器或多个并联或串联的电容单元，只需能够实现其相应功能即可。
图3A示出了根据本公开另一实施例的像素电路的结构示意图。如图3A所示，像素电路包括晶体管T1～T9、发光元件EL、存储电容(CST1)以及电容(CST2-1和CST2-2)。扫描信号端包括第一扫描信号端SK、第二扫描信号端SI、第三扫描信号端SS和第四扫描信号端SN，漏电补偿点包括第一漏电补偿点A和第二漏电补偿点B。
在本公开实施例中，晶体管T1～T8、存储电容CST1、电容CST2-1、扫描信 号端(第一扫描信号端SK、第二扫描信号端SI和第三扫描信号端SS)、预定初始电压端VINT、控制信号端EM、第一电源ELVDD以及第二电源ELVSS分别与图2A中的晶体管T1～T8、存储电容CST1、电容CST2、扫描信号端(第一扫描信号端SK、第二扫描信号端SI和第三扫描信号端SS)、预定初始电压端VINT、控制信号端EM、第一电源ELVDD以及第二电源ELVSS具有类似功能和类似的连接关系。为了简明，本公开不再赘述。
如图3A所示，像素驱动电路还包括第三晶体管T9，扫描信号端还包括第四扫描信号端SY，漏电补偿点还包括第二漏电补偿点B。
第三晶体管T9的栅极电连接至第四扫描信号端SY，第一极电连接至第一晶体管T8的第二极，第二极电连接至第二双栅晶体T2的双栅之间的第二漏电补偿点B。
图3B示出了图3A中的像素电路的信号时序图。如图3B所示，每一帧图像的显示过程包括初始化阶段、数据写入阶段、漏电补偿阶段和发光阶段。图3B示出了每个阶段中各个信号的时序波形。
在本公开实施例中，初始化阶段、数据写入阶段和发光阶段分别与图2B中的初始化阶段、数据写入阶段和发光阶段类似。为了简明，本公开不再赘述。
如图3B所示，在漏电补偿阶段中，第一扫描信号SK的低电平为有效电平，第四扫描信号SY的低电平为有效电平。在第一扫描信号SK的控制下，第一晶体管T8导通。在第四扫描信号SY的控制下，第三晶体管T9导通。
在漏电补偿阶段，第二数据信号从数据信号端Vdata输入，第二数据信号的电位幅值为Vdata+V0。第一晶体管T8导通和第三晶体管T9导通。第二数据信号沿着从数据信号端Vdata到第一漏电补偿点A经由第一晶体管T8的路径被写入到第一漏电补偿点A，第二数据信号还沿着从数据信号端Vdata到二漏电补偿点B经由第一晶体管T8和第三晶体管T9的漏电补偿路径，被写入到第二漏电补偿点B。
保持第一漏电补偿点A电位的方法与上一实施例的过程类似，本公开不再赘述。第二漏电补偿点B的电位可以通过第二双栅晶体管T2的栅极与源极或漏极之间的寄生电容保持，也可以通过在第二漏电补偿点B处设置电容CST2-2保持。在第二漏电补偿点B处设置有电容CST2-2的情况下，电容CST2-2的第一端为第二漏电补偿点B，与第一晶体管T8的第二极相连，第二端连接任一稳定电压VREF。 稳定电压VREF可以是ELVSS、VINT或ELVDD，也可以是其他稳定电压。在对第二漏电补偿点B充电的同时，对电容CST2-2充电。此时，第二漏电补偿点B的电位升高，直至第二漏电补偿点B的电位增大到Vdata+V0，充电过程结束。
在经过漏电补偿阶段后，第二漏电补偿点B的电位VB均为Vdata+V0。此时，第一节点N1的电压VN1仍然保持为Vdata+Vth。第二漏电补偿点B的电位VB和第一漏电补偿点A的电位VA都用于后续在发光阶段对第一节点N1的电压VN1阈值电压进行补偿。
在发光阶段，VA＝VB＝Vdata+V0，VN1＝Vdata+Vth，VA≈VB≈VN1，从而第一双栅晶体管中晶体管T1-2的VSD≈0，以及第二双栅晶体管中晶体管T2-1的VSD≈0。此时流过晶体管T1-2和晶体管T2-1的漏电流极小，驱动晶体管T3的栅极电位可以保持稳定，减少闪烁的可能，提高显示质量。
图4A示出了根据本公开另一实施例的像素电路的结构示意图。如图4A所示，像素电路包括晶体管T1～T10、发光元件EL、存储电容CST1以及电容(CST2-1和CST2-2)。扫描信号端包括第一扫描信号端SK、第二扫描信号端SI、第三扫描信号端SS和第四扫描信号端SN，漏电补偿点包括第一漏电补偿点A和第二漏电补偿点B。
在本公开实施例中，晶体管T1～T9、存储电容CST1、电容(CST2-1和CST2-2)、扫描信号端(第一扫描信号端SK、第二扫描信号端SI、第三扫描信号端SS和第四扫描信号端SN)、预定初始电压端VINT、控制信号端EM、第一电源ELVDD以及第二电源ELVSS分别与图3A中的晶体管T1～T8、存储电容CST1、电容(CST2-1和CST2-2)、扫描信号端(第一扫描信号端SK、第二扫描信号端SI、第三扫描信号端SS和第四扫描信号端SN)、预定初始电压端VINT、控制信号端EM、第一电源ELVDD以及第二电源ELVSS具有类似功能和类似的连接关系。为了简明，本公开不再赘述。
如图4A所示，像素驱动电路还包括第四晶体管T10。
第四晶体管T10的栅极电连接至第四扫描信号端SY，第一极电连接至第一晶体管T8的第二极，第二极电连接至第一双栅晶体T1的双栅之间的第一漏电补偿点A。
图4B示出了图4A中的像素电路的信号时序图。如图4B所示，每一帧图像的显示过程包括初始化阶段、数据写入阶段、漏电补偿阶段和发光阶段。图4B 示出了每个阶段中各个信号的时序波形。
在本公开实施例中，初始化阶段、数据写入阶段和发光阶段分别与图3B中的初始化阶段、数据写入阶段和发光阶段类似。为了简明，本公开不再赘述。
如图4B所示，在漏电补偿阶段，第一扫描信号SK和第四扫描信号SY的低电平为有效电平。在第一扫描信号SK的控制下，第一晶体管T8导通。在第四扫描信号SY的控制下，第四晶体管T10导通。
在漏电补偿阶段，第二数据信号从数据信号端Vdata输入，第二数据信号的电位幅值为Vdata+V0。第一晶体管T8和第四晶体管T10导通，第二数据信号沿着从数据信号端Vdata到第一漏电补偿点A经由第一晶体管T8和第四晶体管T10导通的漏电补偿路径，被写入到第一漏电补偿点A。此时，第一漏电补偿点A的电位升高，直至第一漏电补偿点A的电位增大到Vdata+V0。
第二数据信号写入第二漏电补偿点B的过程与上一实施例的过程类似，本公开不再赘述。
在经过漏电补偿阶段后，第二漏电补偿点B的电位VB均为Vdata+V0。此时，第一节点N1的电压VN1仍然保持为Vdata+Vth。第二漏电补偿点B的电位VB和第一漏电补偿点A的电位VA都用于后续在发光阶段对第一节点N1的电压VN1阈值电压进行补偿。
在发光阶段，VA＝VB＝Vdata+V0，VN1＝Vdata+Vth，VA≈VB≈VN1，从而第一双栅晶体管中晶体管T1-2的VSD≈0，以及第二双栅晶体管中晶体管T2-1的VSD≈0。此时流过晶体管T1-2和晶体管T2-1的漏电流极小，驱动晶体管T3的栅极电位可以保持稳定，减少闪烁的可能，提高显示质量。
图5A示出了根据本公开另一实施例的像素电路的结构示意图。如图5A所示，像素电路包括晶体管T1～T8、发光元件EL以及存储电容(CST1和CST2)。扫描信号端包括第一扫描信号端SK、第二扫描信号端SI和第三扫描信号端SS，漏电补偿点包括第一漏电补偿点A。
在本公开实施例中，晶体管(T1～T3和T5～T7)、存储电容CST1、电容CST2、扫描信号端(第一扫描信号端SK、第二扫描信号端SI和第三扫描信号端SS)、预定初始电压端VINT、控制信号端EM、第一电源ELVDD以及第二电源ELVSS分别与图2A中的晶体管(T1～T3和T5～T7)、存储电容CST1、电容CST2、扫描信号端(第一扫描信号端SK、第二扫描信号端SI和第三扫描信号端SS)、预定 初始电压端VINT、控制信号端EM、第一电源ELVDD以及第二电源ELVSS具有类似功能和类似的连接关系。为了简明，本公开不再赘述。
如图5A所示，第一晶体管T8的栅极电连接至第一扫描信号端SK，第一极电连接至第二晶体管T4的第二极，第二极在第二节点N2电连接至驱动晶体管T3的源极。第二晶体管T4的栅极电连接至第三扫描信号端SS，第一极电连接至数据信号端Vdata，第二极电连接至第一双栅晶体管的双栅之间的第一漏电补偿点A。
图5B示出了图5A中的像素电路的信号时序图。如图5B所示，每一帧图像的显示过程包括初始化阶段、数据写入阶段、漏电补偿阶段和发光阶段。图5B示出了每个阶段中各个信号的时序波形。
在本公开实施例中，初始化阶段、数据写入阶段和发光阶段分别与图2B中的初始化阶段、数据写入阶段和发光阶段类似。为了简明，本公开不再赘述。
如图5B所示，在漏电补偿阶段，从数据信号端Vdata输入第二数据信号，第二数据信号的电位幅值为Vdata+V0。第三扫描信号SS的低电平为有效电平，第一扫描信号SK为高电平。在第三扫描信号SS的控制下，第二晶体管T4导通。第二数据信号沿着从数据信号端Vdata到第一漏电补偿点A经由第二晶体管T4的漏电补偿路径，被写入到第一漏电补偿点A。第一漏电补偿点A的电位升高，直至第一漏电补偿点A的电位增大到Vdata+V0。
在经过漏电补偿阶段后，第一漏电补偿点A的电位VA为Vdata+V0。在发光阶段，VA＝Vdata+V0，VN1＝Vdata+Vth，VA≈VN1，从而第一双栅晶体管中晶体管T1-2的VSD≈0。此时流过晶体管T1-2漏电流极小，驱动晶体管T3的栅极电位可以保持稳定，减少闪烁的可能，提高显示质量。
图5C示出了图5A中的像素电路的另一信号时序图。如图5C所示，每一帧图像的显示过程包括初始化阶段、数据写入阶段、漏电补偿阶段和发光阶段。图5C示出了每个阶段中各个信号的时序波形。
在本公开实施例中，数据写入阶段、漏电补偿阶段和发光阶段分别与图5B中的初数据写入阶段、漏电补偿阶段和发光阶段类似。为了简明，本公开不再赘述。
在初始化阶段，第一扫描信号SK和第二扫描信号SI的低电平为有效电平。在第一扫描信号SK的控制下，第一晶体管T8导通。在第二扫描信号SI的控制 下，第一双栅晶体管T1导通。初始化信号从预定初始化端VINT输入。初始化信号VINT的电压沿着从预定初始化端VINT到第二节点N2经由晶体管T1-1和第一晶体管T8的初始化路径，被写入到第二节点N2，从而将驱动晶体管T3的源极电压初始化为VINT。初始化阶段对驱动晶体管T3的栅极和发光元件EL阳极的初始化过程与图2C对应的实施例相同，本公开不再赘述。
在初始化阶段对驱动晶体管T3的栅极电压Vg和源极电压Vs同时进行初始化，使得VGS＝0，驱动晶体管T3处于On-Bias状态，进而改善DTFT的迟滞现象，改善短期残像问题。
图6A示出了根据本公开另一实施例的像素电路的结构示意图。如图6A所示，像素电路包括晶体管T1～T9、发光元件EL以及存储电容CST1和电容CST2。扫描信号端包括第二扫描信号端SI和第三扫描信号端，漏电补偿点包括第一漏电补偿点A。
在本公开实施例中，晶体管T1～T7、存储电容CST1、电容CST2、扫描信号端(第二扫描信号端SI和第三扫描信号端SS)、预定初始电压端VINT、控制信号端EM、第一电源ELVDD以及第二电源ELVSS分别与图2A中的晶体管T1～T7、存储电容CST1、电容CST2、扫描信号端(第二扫描信号端SI和第三扫描信号端SS)、预定初始电压端VINT、控制信号端EM、第一电源ELVDD以及第二电源ELVSS具有类似功能和类似的连接关系。为了简明，本公开不再赘述。
如图6A所示，第一晶体管T8的栅极电连接至第一双栅晶体管T1的双栅之间的第一漏电补偿点A，第一极电连接至第二晶体管T4的第二极，第二极电连接至第三晶体管T9的第一极。第三晶体管T9的栅极电连接至第三扫描信号端SS，第二极连接至第一双栅晶体管T1的双栅之间的第一漏电补偿点A。
图6B示出了图6A中的像素电路的信号时序图。如图6B所示，每一帧图像的显示过程包括初始化阶段、数据写入阶段和发光阶段。图6B示出了每个阶段中各个信号的时序波形。
在本公开实施例中，发光阶段分别与图2B中的发光阶段类似。为了简明，本公开不再赘述。本公开实施例中对第一漏电补偿点A的充电过程在数据写入阶段完成。因此可以认为本公开实施例的数据写入阶段包括漏电补偿阶段。
在初始化阶段，第二扫描信号SI的低电平为有效电平。在第二扫描信号SI的控制下，第一双栅晶体管T1导通。初始化信号沿着从预定初始电压端VINT 到第一晶体管T8的栅极经过晶体管T1-1的初始化路径，被写入到第一晶体管T8的栅极，从而将第一晶体管T8的栅极电压初始化为VINT。
在数据写入阶段，第三扫描信号SS的低电平为有效电平，在第三扫描信号SS的控制下，第三晶体管T9导通。第一晶体管T8的栅极电压和驱动晶体管T3的栅极电压由于在初始化阶段被初始化为VINT，第一晶体管T8和驱动晶体管T3导通。需要说明的是，第一晶体管T8和驱动晶体管T3具有接近的阈值电压Vth。从数据信号端Vdata输入的数据信号的电压幅值为Vdata，数据信号沿着从数据信号端Vdata到第一漏电补偿点A经由第二晶体管T4、第一晶体管T8和第三晶体管T9的数据写入路径，被写入到第一漏电补偿点A。此时，第一漏电补偿点A的电位升高，直至第一漏电补偿点A的电位增大到Vdata+Vth。
在经过漏电补偿阶段后，第一漏电补偿点A的电位VA均为Vdata+Vth，第一节点N1的电压VN1为Vdata+Vth。在发光阶段，VA＝VN1＝Vdata+Vth，从而第一双栅晶体管中晶体管T1-2的VSD≈0，此时流过晶体管T1-2的漏电流极小，驱动晶体管T3的栅极电位可以保持稳定，减少闪烁的可能，提高显示质量。
需要说明的是，晶体管T2可以是双栅极晶体管，也可以是单栅极晶体管。双栅晶体管也可以在一定程度上缓解驱动晶体管栅极的漏电问题。
图7A示出了根据本公开另一实施例的像素电路的结构示意图。如图7A所示，像素电路包括晶体管T1～T9、发光元件EL、存储电容CST1以及电容CST2。扫描信号端包括第一扫描信号端SK、第二扫描信号端SI、第三扫描信号端SS和第四扫描信号端SY，漏电补偿点包括第一漏电补偿点A。
在本公开实施例中，晶体管T1～T7、存储电容CST1、电容CST2、扫描信号端(第一扫描信号端SK、第二扫描信号端SI、第三扫描信号端SS和第四扫描信号端SY)、预定初始电压端VINT、控制信号端EM、第一电源ELVDD以及第二电源ELVSS分别与图2A中的晶体管T1～T7、存储电容CST1、电容CST2、扫描信号端(第一扫描信号端SK、第二扫描信号端SI、第三扫描信号端SS和第四扫描信号端SY)、预定初始电压端VINT、控制信号端EM、第一电源ELVDD以及第二电源ELVSS具有类似功能和类似的连接关系。为了简明，本公开不再赘述。
如图7A所示，第一晶体管T8的栅极电连接至第一扫描信号端SK，第一极电连接至数据信号端Vdata，第二极电连接至位于第三晶体管T9与第二双栅晶体管T2之间的第一漏电补偿点A。第一漏电补偿点A还需要位于第三晶体管T9 与第一双栅晶体管T1之间。第三晶体管T9的栅极电连接至第四扫描信号端SY，第一极电连接至第一漏电补偿点A，第二极在N1节点电连接至驱动晶体管T3的源极。
图7B示出了图7A中的像素电路的信号时序图。如图7B所示，每一帧图像的显示过程包括初始化阶段、数据写入阶段、漏电补偿阶段和发光阶段。图7B示出了每个阶段中各个信号的时序波形。
在本公开实施例中，漏电补偿阶段和发光阶段分别与图2B中的漏电补偿阶段和发光阶段类似。为了简明，本公开不再赘述。
在初始化阶段，第二扫描信号SI和第四扫描信号SY的低电平为有效电平。在第二扫描信号SI的控制下，第一双栅晶体管T1导通。在第四扫描信号SY的控制下，第三晶体管T9导通。初始化信号VINT的电压沿着从预定初始电压端VINT到第一节点N1经由第一双栅晶体管T1和第三晶体管T9，被写入到第一节点N1。
在数据写入阶段，第三扫描信号SS和第四扫描信号SY的低电平为有效电平。在第三扫描信号SS的控制下，第二晶体管T4和第二双栅晶体管T2导通。在第四扫描信号SY的控制下，第三晶体管T9导通。第一数据信号从数据信号端Vdata输入，第一数据信号的电位幅值为Vdata。第一数据信号沿着从数据信号端Vdata到第一节点N1经由第二晶体管T4、驱动晶体管T3、第二双栅晶体管T2和第三晶体管T9，被写入到第一节点N1。当第一节点N1的电位增大到Vdata+Vth时，驱动晶体管T3截止。
在经过漏电补偿阶段后，第一漏电补偿点A的电位VA均为Vdata+V0。在发光阶段，VA＝＝Vdata+V0，VN1＝Vdata+Vth，VA≈VN1，从而第一双栅晶体管中晶体管T1-2的VSD≈0。此时流过晶体管T1-2的漏电流极小，驱动晶体管T3的栅极电位可以保持稳定，减少闪烁的可能，提高显示质量。
图8A～图8D为图4A所示的像素电路中的第一晶体管T1和第一双栅晶体管T1的截面图。
如图8A～图8D所示，在PI基地810上依次形成阻隔层820、PI基地810、无机层830、绝缘层840～860。在第一晶体管T8开启后，信号线SD1上的电压通过第一晶体管T8的源极进入。第一晶体管T8的漏极与第一双栅晶体管T1的双栅之间的第一漏电补偿点A通过信号线SD2电连接。
第一漏电补偿点A处设置有存储电容CST2。第一漏电补偿点A可认为是存储电容CST2的一个极板。第一双栅晶体管T1的栅极Gate2或沟道层下方的金属层870(图8B示出)作为存储电容CST2的另一个极板。第一双栅晶体管T1的栅极Gate2或沟道层下方的金属层840可通过信号线SD1电连接提供稳定电位VREF的任一电源。
本公开还提供了一种显示装置的实施例。图9示出了根据本公开实施例的显示装置的结构示意图。如图9所示，根据本公开实施例的显示装置900可以包括显示面板910、扫描驱动器920、数据驱动器930、发光控制驱动器940、控制器950以及为显示装置900提供外部电压的电源单元960。
显示面板910包括扫描信号线S0～Sn、数据信号线DL1～DLm、控制信号线EM1～EMn、初始化信号线VINT和多个像素单元。扫描信号线S0～Sn配置为提供扫描信号。每一扫描信号线Sn包括多个扫描信号线，该多个信号线分别用于提供上述实施例的第一扫描信号端SK、第二扫描信号端SI、第三扫描信号端SS和第四扫描信号端SY。数据信号线DL1～DLm配置为提供数据信号，初始化信号线VINT配置为提供初始化信号，控制信号线EM1～EMn配置为提供发光控制信号。像素单元包括上述图1、图2A、图3A、图4A、图5A、图6A和图7A对应实施例中提供的任一像素电路。像素电路包括像素驱动电路和发光元件。像素驱动电路包括上述实施例中提供的任一像素驱动电路。发光元件的第一端连接至像素驱动电路第二端连接至第二电源ELVSS。其中m和n为正整数。
多个像素单元被供有外部电压，诸如来自电源单元960的第一电源电压ELVDD、第二电源电压ELVSS、初始化电压VINT。第一电源电压ELVDD的电压电平可比第二电源电压ELVSS的电压电平高。
显示面板910包括以近似矩阵形式排列的多个像素单元。多个扫描线S0～Sn在第一方向上基本延伸成行，从而相互平行，并且多个数据线在与第一方向交叉的第二方向上基本延伸成列，从而在像素的排列中相互平行。然而，本公开实施的实施方式不限于此。
像素单元分别连接至用于将扫描信号传输至显示面板910的多个扫描线S0至Sn之中。每个像素单元都连接至与于相应的像素行相对应的扫描线，而且每个像素也连接至其前一行的扫描线。然而，本公开的实施方式不限于此。
此外，多个像素单元中的每一个像素分别连接至将数据信号传输至显示面 板910的多个数据线DL1～DLm之中的一个数据线，以及将发光控制信号传输至显示面板910的多个发光控制信号线EM1至EMn之中的一个发光控制信号线。
扫描驱动器920产生多个相应的扫描信号并通过多个扫描线S0～Sn将这多个相应的扫描信号传输至像素单元。数据驱动器930通过多个数据线DL1～DLm将数据信号传输至每个像素。发光控制驱动器940产生发光控制信号，并且通过多个发光控制信号线EM1～EMn将发光控制信号传输至每个像素单元。
控制器950将从外部源传输的多个视频信号R、G和B转换(或改变)成多个图像数据信号DR、DG和DB，并将多个图像数据信号DR、DG和DB传输至数据驱动器930。此外，控制器950接收垂直同步信号Vsync、水平同步信号Hsync和时钟信号MCLK以产生控制信号，从而控制扫描驱动器920、数据驱动器930、发光控制驱动器940的驱动。也就是说，控制器950产生并传输控制扫描驱动器20的扫描驱动控制信号SCS、控制数据驱动器930的数据驱动控制信号DCS、以及控制发光控制驱动器940的发光控制信号ECS。
根据通过多个数据线DL1～DLm传输的数据信号，通过提供给每个像素中的OLED的驱动电流，多个像素分别发射具有亮度(例如，预定的亮度)的光。
根据本公开实施例的显示装置900可以是电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图10示出了根据本公开实施例的显示面板的堆叠结构的示意图。如图10所示，在LTPS基板1010上依次形成薄膜晶体管阵列TFT1020、发射层EML1030、封装膜层TFE1040、触摸电极层Touch1050、偏光层1060和盖板1070。偏光层也可以为滤光层。
根据本公开实施例，还提供了一种像素驱动电路的驱动方法。图11示出了根据本公开实施例的像素驱动电路的驱动方法的流程图。如图11所示，根据本公开实施例的像素驱动电路的驱动方法可以包括以下步骤。应注意，以下方法中各个步骤的序号仅作为该步骤的表示以便描述，而不应被看作表示该各个步骤的执行顺序。除非明确指出，否则该方法不需要完全按照所示顺序来执行。
在步骤S1110，在第一时段，来自扫描信号端的扫描信号的控制下，利用来着预定初始电压端的初始化信号对发光元件和驱动子电路进行初始化。
在步骤S1120，在第二时段，来自扫描信号端的扫描信号的控制下，将来自数据信号端的数据信号写入驱动子电路。
在步骤S1130，在第三时段，来自扫描信号端的扫描信号的控制下，将来自数据信号端的数据信号施加至漏电补偿点。
在步骤S1140，在第四时段，来自发光控制信号端的发光控制信号的控制下，控制驱动子电路向发光元件输出与数据信号相关的驱动电流。
在第四时段中，利用漏电补偿点的电压补偿驱动子电路的控制极电压。
根据本公开实施例，例如，在第一时段，第二扫描信号SI为有效电平，第一双栅晶体管T1导通。在第二时段，第一扫描信号SK和第三扫描信号SS为有效电平，第一晶体管T8和第二晶体管T4导通，通过第一晶体管T8和第二晶体管T4将来自数据信号端的第一数据信号写入驱动子电路。在第三时段，第一扫描信号为有效电平，第一晶体管T8导通，通过第一晶体管T8将来自数据信号端的第二数据信号施加至第一漏电补偿点。
例如，在第三时段，第四扫描信号SY为有效电平，第三晶体管T9和/或第四晶体管T10导通，通过第三晶体管T9导通将来自数据信号端的第二数据信号施加至第二漏电补偿点，和/或通过第四晶体管T10导将来自数据信号端的第二数据信号施加至第一漏电补偿点。
根据本公开实施例，例如，在第三时段，第三扫描信号SS为有效电平，第二晶体管T4导通，通过第二晶体管T4将来自数据信号端的第二数据信号施加至第一漏电补偿点。
例如，在第一时段，第一扫描信号SK为有效电平，第一晶体管T8导通，利用初始化信号通过第一晶体管T8对驱动子电路的输入端进行初始化。
根据本公开实施例，例如，在第二时段和第三时段，第三扫描信号SS为有效电平，第一晶体管T8、第二晶体管T4和第三晶体管T9导通，通过第二晶体管T4将来自数据信号端的第一数据信号写入驱动子电路的输入端，以及通过第一晶体管T8和第三晶体管T9将来自数据信号端的第一数据信号施加至第一漏电补偿点A。
根据本公开实施例，例如，在第二时段，第三扫描信号SS和第四扫描信号SN为有效电平，第二双栅晶体管T2、第二晶体管T4和第三晶体管导通T9，通过第二双栅晶体管T2、第二晶体管T4和第三晶体管T9将来自数据信号端的第 一数据信号写入驱动子电路。
根据本公开实施例，例如，第二数据信号的幅值为第一数据信号的幅值和附加信号的幅值之和，附加信号的幅值与驱动晶体管的阈值电压相关。
应当注意的是，在以上的描述中，仅以示例的方式，示出了本公开实施例的技术方案，但并不意味着本公开实施例局限于上述步骤和结构。在可能的情形下，可以根据需要对步骤和结构进行调整和取舍。因此，某些步骤和单元并非实施本公开实施例的总体发明思想所必需的元素。
至此已经结合优选实施例对本公开进行了描述。应该理解，本领域技术人员在不脱离本公开实施例的精神和范围的情况下，可以进行各种其它的改变、替换和添加。因此，本公开实施例的范围不局限于上述特定实施例，而应由所附权利要求所限定。

Claims (21)

  1. 一种像素驱动电路，其特征在于，配置为驱动发光元件发光，所述像素驱动电路包括：
    驱动子电路，连接至所述发光元件；
    数据写入子电路，电连接至数据信号端、扫描信号端和所述驱动子电路，并在来自所述扫描信号端的扫描信号的控制下，将来自所述数据信号端的数据信号写入所述驱动子电路，以及将来自所述数据信号端的数据信号施加至漏电补偿点；以及
    发光控制子电路，电连接至所述驱动子电路、发光控制信号端和所述发光元件，所述发光控制子电路配置为在来自发光控制信号端的发光控制信号的控制下，控制所述驱动子电路向所述发光元件输出与所述数据信号相关的驱动电流，其中，在所述发光元件的发光过程中，利用所述漏电补偿点的电压补偿所述驱动子电路的控制极电压。
  2. 根据权利要求1所述的像素驱动电路，其中，所述数据写入子电路包括第一晶体管、第二晶体管(T4)和第一双栅晶体管，所述扫描信号端包括第一扫描信号端(SK)、第二扫描信号端(SI)和第三扫描信号端(SS)，所述漏电补偿点包括第一漏电补偿点
    (A)；
    其中，所述第一晶体管(T8)的控制极电连接至所述第一扫描信号端(SK)，所述第一晶体管(T8)的第一极电连接至所述数据信号端(Vdata)，所述第一晶体管(T8)的第二极电连接至所述第一双栅晶体管的双栅之间的所述第一漏电补偿点(A)，所述第一双栅晶体管的栅极与第二扫描信号端(SI)电连接，第一极与预定初始电压端相连，第二极与所述驱动子电路的控制极电连接；
    所述第二晶体管(T4)的控制极电连接至所述第三扫描信号端(SS)，所述第二晶体管(T4)的第一极电连接至所述第一晶体管(T8)的第二极，所述第二晶体管(T4)的第二极电连接至所述驱动子电路的输入端。
  3. 根据权利要求2所述的像素驱动电路，其中，所述数据写入子电路还包括第三晶体管(T9)和第二双栅晶体管(T2-1 T2-2)，所述扫描信号端包括第四扫描信号端(SY)，所述漏电补偿点还包括第二漏电补偿点(B)；
    其中，所述第三晶体管(T9)的控制极电连接至所述第四扫描信号端(SY)，所述第三晶体管(T9)的第一极电连接至所述第一晶体管(T8)的第二极，所述第三晶体管 (T9)的第二极电连接至所述第二双栅晶体管的双栅之间的第二漏电补偿点(B)；所述第二双栅晶体管的栅极与第三扫描信号端(SS)电连接，第一极与所述发光控制子电路电连接，第二极与所述驱动子电路的控制极电连接。
  4. 根据权利要求3所述的像素驱动电路，其中，所述数据写入子电路还包括第四晶体管(T10)；
    其中，所述第四晶体管(T10)的控制极电连接至所述第四扫描信号端(SY)，所述第四晶体管(T10)的第一极电连接至所述第一晶体管(T8)的第二极，所述第四晶体管(T10)的第二极电连接至所述第一漏电补偿点(A)。
  5. 根据权利要求1所述的像素驱动电路，其中，所述数据写入子电路包括第一晶体管(T8)、第二晶体管(T4)和第一双栅晶体管(T1-1 T1-2)，所述扫描信号端包括第一扫描信号端(SK)和第三扫描信号端(SS)，所述漏电补偿点包括第一漏电补偿点(A)；
    其中，所述第一晶体管(T8)的控制极电连接至所述第一扫描信号端(SK)，所述第一晶体管(T8)的第一极电连接至所述第二晶体管(T4)的第二极，所述第一晶体管(T8)的第二极电连接至所述驱动子电路的输入端；以及
    所述第二晶体管(T4)的控制极电连接至所述第三扫描信号端(SS)，所述第二晶体管(T4)的第一极电连接至所述数据信号端(Vdata)，所述第二晶体管(T4)的第二极电连接至所述第一双栅晶体管的双栅之间的所述第一漏电补偿点(A)。
  6. 根据权利要求1所述的像素驱动电路，其中，所述数据写入子电路包括第一晶体管(T8)、第二晶体管(T4)、第三晶体管(T9)和第一双栅晶体管(T1-1 T1-2)，所述漏电补偿点包括第一漏电补偿点(A)，所述扫描信号端包括第三扫描信号端(SS)；
    其中，所述第一晶体管(T8)的控制极电连接至所述第一双栅晶体管的双栅之间的第一漏电补偿点(A)，所述第一晶体管(T8)的第一极电连接至所述第二晶体管(T4)的第二极，所述第一晶体管(T8)的第二极电连接至所述第三晶体管(T9)的第一极；
    所述第二晶体管(T4)的控制极电连接至所述第三扫描信号端(SS)，所述第二晶体管(T4)的第一极电连接至所述数据信号端，所述第二晶体管(T4)的第二极电连接至所述驱动子电路的输入端；以及
    所述第三晶体管(T9)的控制极电连接至第三扫描信号端(SS)，所述第三晶体管(T9)的第二极在连接至所述第一漏电补偿点(A)。
  7. 根据权利要求1所述的像素驱动电路，其中，所述数据写入子电路包括第一晶体管(T8)、第三晶体管(T9)和第二双栅晶体管，所述漏电补偿点包括第一漏电补偿点
    (A)，所述扫描信号端包括第一扫描信号端(SK)和第三扫描信号端(SS)；
    其中，所述第一晶体管(T8)的控制极电连接至所述第一扫描信号端(SK)，所述第一晶体管(T8)的第一极电连接至所述数据信号端，所述第一晶体管(T8)的第二极电连接至位于所述第三晶体管(T9)与所述第二双栅晶体管之间的所述第一漏电补偿点
    (A)；以及
    所述第三晶体管(T9)的控制极电连接至第四扫描信号端(SY)，所述第三晶体管(T9)的第一极电连接至所述第一漏电补偿点(A)，所述第三晶体管(T9)的第二极电连接至所述驱动子电路的输入端。
  8. 根据权利要求1所述的像素驱动电路，其中，所述数据写入子电路还包括第五晶体管(T7)；
    其中，所述第五晶体管(T7)的控制极电连接至第二扫描信号端(SI)，所述第五晶体管(T7)的第一极电连接至预定初始电压端(VINT)，所述第五晶体管(T7)的第二极电连接至所述发光元件的阳极。
  9. 根据权利要求1所述的像素驱动电路，其中，所述发光控制子电路包括第六晶体管(T5)和第七晶体管(T6)；
    其中，所述第六晶体管(T5)的控制极电连接至所述发光控制信号端(EM)，所述第六晶体管(T5)的第一极电连接至第一电源(ELVDD)，所述第六晶体管(T5)的第二极电连接至所述驱动子电路的输入端；以及
    所述第七晶体管(T6)的控制极电连接至所述发光控制信号端(EM)，所述第七晶体管(T6)的第一极电连接至所述驱动子电路的输出端，所述第七晶体管(T6)的第二极电连接至所述发光元件。
  10. 根据权利要求1所述的像素驱动电路，其中，所述驱动子电路包括驱动晶体管(T3)和存储电容(C1)；
    其中，驱动晶体管(T3)的控制极电连接至所述数据写入子电路，所述驱动晶体管(T3)的源极电连接至所述数据写入子电路，漏极电连接至所述发光控制子电路；以及
    所述存储电容的第一端电连接至所述驱动晶体管的控制极，所述存储电容的第二端电连接至第一电源(ELVDD)。
  11. 根据权利要求1所述的像素驱动电路，其中，当所述驱动电流驱动所述发光元件发光时，所述驱动电流为K(Vdata-ELVDD)2，其中K为与驱动晶体管相关的常数，Vdata为所述数据信号，ELVDD为第一电源电压。
  12. 一种显示面板，包括：
    扫描信号线，配置为提供扫描信号；
    数据信号线，配置为提供数据信号；
    初始化信号线，配置为提供初始化信号；
    控制信号线，配置为提供发光控制信号；
    根据权利要求1-11任一项所述的像素驱动电路；以及
    发光元件，所述发光元件的第一端连接至所述像素驱动电路，所述发光元件的第二端连接至第二电源。
  13. 一种显示装置，包括根据权利要求12所述的显示面板。
  14. 一种像素驱动方法，应用于根据权利要求1-11任一项所述的像素驱动电路，所述像素驱动方法包括：
    在第一时段，来自所述扫描信号端的扫描信号的控制下，利用来着预定初始电压端的初始化信号对所述发光元件和所述驱动子电路进行初始化；
    在第二时段，来自所述扫描信号端的扫描信号的控制下，将来自所述数据信号端的数据信号写入驱动子电路；
    在第三时段，来自所述扫描信号端的扫描信号的控制下，将来自所述数据信号端的数据信号施加至漏电补偿点；以及
    在第四时段，来自发光控制信号端的发光控制信号的控制下，控制所述驱动子电路向所述发光元件输出与所述数据信号相关的驱动电流，其中，在所述第四时段中，利用所述漏电补偿点的电压补偿所述驱动子电路的控制极电压。
  15. 根据权利要求14所述的方法，其中，
    在第一时段，第二扫描信号(SI)为有效电平，第一双栅晶体管(T1)导通；
    在第二时段，第一扫描信号(SK)和第三扫描信号(SS)为有效电平，第一晶体管(T8)和第二晶体管(T4)导通，通过所述第一晶体管(T8)和所述第二晶体管(T4)将来自所述数据信号端的第一数据信号写入驱动子电路；
    在第三时段，第一扫描信号为有效电平，第一晶体管(T8)导通，通过所述第一晶 体管(T8)将来自所述数据信号端的第二数据信号施加至第一漏电补偿点。
  16. 根据权利要求15所述的方法，其中，
    在第三时段，第四扫描信号为有效电平，第三晶体管(T9)和/或第四晶体管(T10)导通，通过所述第三晶体管(T9)导通将来自所述数据信号端的第二数据信号施加至第二漏电补偿点，和/或通过所述第四晶体管(T10)导将来自所述数据信号端的第二数据信号施加至第一漏电补偿点。
  17. 根据权利要求14所述的方法，其中，
    在第三时段，第三扫描信号(SS)为有效电平，第二晶体管(T4)导通，通过所述第二晶体管(T4)将来自所述数据信号端的第二数据信号施加至第一漏电补偿点。
  18. 根据权利要求17所述的方法，其中，
    在第一时段，第一扫描信号(SK)为有效电平，第一晶体管(T8)导通，利用初始化信号通过所述第一晶体管(T8)对所述驱动子电路的输入端进行初始化。
  19. 根据权利要求14所述的方法，其中，
    在第二时段和第三时段，第三扫描信号(SS)为有效电平，第一晶体管(T8)、第二晶体管(T4)和第三晶体管(T9)导通，通过所述第二晶体管(T4)将来自所述数据信号端的第一数据信号写入驱动子电路的输入端，以及通过所述第一晶体管(T8)和所述第三晶体管(T9)将来自所述数据信号端的第一数据信号施加至第一漏电补偿点。
  20. 根据权利要求14所述的方法，其中，
    在第二时段，第三扫描信号(SS)和第四扫描信号(SN)为有效电平，第二双栅晶体管(T2)、第二晶体管(T4)和第三晶体管导通(T9)，通过所述第二双栅晶体管(T2)、所述第二晶体管(T4)和所述第三晶体管(T9)将来自所述数据信号端的第一数据信号写入所述驱动子电路。
  21. 根据权利要求15-17任一项所述的方法，其中，所述第二数据信号的幅值为所述第一数据信号的幅值和附加信号的幅值之和，所述附加信号的幅值与驱动晶体管的阈值电压相关。
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