WO2023206219A1 - 驱动电路、驱动方法和显示装置 - Google Patents

驱动电路、驱动方法和显示装置 Download PDF

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Publication number
WO2023206219A1
WO2023206219A1 PCT/CN2022/089825 CN2022089825W WO2023206219A1 WO 2023206219 A1 WO2023206219 A1 WO 2023206219A1 CN 2022089825 W CN2022089825 W CN 2022089825W WO 2023206219 A1 WO2023206219 A1 WO 2023206219A1
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WIPO (PCT)
Prior art keywords
pull
node
control
electrically connected
transistor
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Application number
PCT/CN2022/089825
Other languages
English (en)
French (fr)
Inventor
金红贵
于洪俊
刘汉青
王建
张勇
边若梅
王佩佩
段智龙
杨越
李鑫
宋勇
王强
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001011.4A priority Critical patent/CN117321668A/zh
Priority to PCT/CN2022/089825 priority patent/WO2023206219A1/zh
Publication of WO2023206219A1 publication Critical patent/WO2023206219A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving circuit, a driving method and a display device.
  • the driving circuit may only include one pull-down node and one pull-down node control circuit to achieve narrow borders.
  • the transistor characteristics will change during the high temperature and high humidity reliability process.
  • the transistor included in the input circuit will drift in the negative direction under the action of negative bias voltage, and the leakage current will increase.
  • the second input voltage terminal will leak up to the pull-up node and generate noise (noise).
  • the pull-up node reset circuit includes The characteristics of the transistor and the characteristics of the transistor whose gate is electrically connected to the first pull-down control node of the first pull-down node control circuit drift forward, causing the potential of the first pull-down node to drop, and the pull-up node reset circuit The noise reduction capability of the included transistor is reduced, and the potential of the pull-up node cannot be pulled down to a low voltage, causing the drive circuit to output incorrectly, resulting in multiple drive signal outputs.
  • an embodiment of the present disclosure provides a driving circuit including a first pull-down node, a first control circuit and a pull-up node reset circuit;
  • the first control circuit is electrically connected to the first pull-down node, the first control terminal and the first voltage terminal respectively, and is used to control the first control circuit under the control of the first control signal provided by the first control terminal.
  • the pull-down node is connected to the first voltage terminal so that the potential of the first pull-down node is an effective voltage;
  • the pull-up node reset circuit is electrically connected to the first pull-down node, the pull-up node and the second voltage terminal respectively, and is used to control the pull-up when the potential of the first pull-down node is an effective voltage.
  • the node is connected to the second voltage terminal to reset the potential of the pull-up node.
  • the first control terminal is a reset terminal, a first pull-down node or a first pull-down control node.
  • the first control circuit includes a first transistor
  • the gate of the first transistor is electrically connected to the first control terminal, the first pole of the first transistor is electrically connected to the first pull-down node, and the second pole of the first transistor is electrically connected to the first pull-down node.
  • the first voltage terminal is electrically connected;
  • the pull-up node reset circuit includes a second transistor
  • the gate of the second transistor is electrically connected to the first pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the first pull-down node.
  • the two voltage terminals are electrically connected.
  • the driving circuit also includes a reset circuit
  • the reset circuit is electrically connected to the reset terminal, the pull-up node and the first input voltage respectively, and is used to control the first input voltage terminal to provide the voltage under the control of the reset signal provided by the reset terminal.
  • the first input voltage is written to the pull-up node.
  • the driving circuit further includes a first pull-down node control circuit
  • the first pull-down node control circuit is electrically connected to the first pull-down node, the first pull-down control node, the pull-up node, the first control voltage terminal and the third voltage terminal, respectively.
  • the connection between the first control voltage terminal and the first pull-down control node is controlled, and under the control of the potential of the pull-up node, Control the connection between the first pull-down control node and the third voltage terminal, and be used to control the first pull-down node and the first pull-down node under the control of the potential of the first pull-down control node. Control the connection between the voltage terminals, and control the connection between the first pull-down node and the third voltage terminal under the control of the potential of the pull-up node;
  • the first voltage terminal is the first control voltage terminal.
  • the driving circuit according to at least one embodiment of the present disclosure further includes an output circuit
  • the output circuit is electrically connected to the pull-up node, the first pull-down node, the output clock signal terminal, the fourth voltage terminal and the drive signal output terminal respectively, and is used to control the voltage of the pull-up node under the control of the potential of the pull-up node.
  • the output clock signal provided by the output clock signal terminal is written into the driving signal output terminal, and under the control of the potential of the first pull-down node, the connection between the driving signal output terminal and the fourth voltage terminal is controlled. connected between.
  • the drive circuit also includes a second pull-down node and a second control circuit
  • the second control circuit is electrically connected to the second pull-down node, the second control terminal and the fifth voltage terminal respectively, and is used to control the second pull-down node under the control of the second control signal provided by the second control terminal.
  • the node is connected to the fifth voltage terminal so that the potential of the second pull-down node is an effective voltage
  • the pull-up node reset circuit is also electrically connected to the second pull-down node, and is used to control the connection between the pull-up node and the second voltage terminal when the potential of the second pull-down node is an effective voltage. , to reset the potential of the pull-up node.
  • the second control terminal is a reset terminal, a second pull-down node or a second pull-down control node.
  • the second control circuit includes a third transistor; the pull-up node reset circuit further includes a fourth transistor;
  • the gate of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the second pull-down node, and the second electrode of the third transistor is electrically connected to the second pull-down node.
  • Five voltage terminals are electrically connected;
  • the gate electrode of the fourth transistor is electrically connected to the second pull-down node, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the second pull-down node.
  • the voltage terminals are electrically connected.
  • the driving circuit further includes a second pull-down node control circuit
  • the second pull-down node control circuit is electrically connected to the second pull-down node, the second pull-down control node, the pull-up node, the second control voltage terminal and the third voltage terminal respectively, and is used for controlling the Under the control of the second control voltage provided by the two control voltage terminals, the connection between the second control voltage terminal and the second pull-down control node is controlled, and under the control of the potential of the pull-up node, the connection between the second control voltage terminal and the second pull-down control node is controlled.
  • the second pull-down control node is connected to the third voltage terminal, and is used to control the connection between the second pull-down node and the second control voltage terminal under the control of the potential of the second pull-down control node, Under the control of the potential of the pull-up node, control the connection between the second pull-down node and the third voltage terminal;
  • the fifth voltage terminal is the second control voltage terminal.
  • the drive circuit also includes an input circuit, an output reset circuit, an initial reset circuit and an energy storage circuit;
  • the input circuit is electrically connected to the input terminal, the second input voltage terminal and the pull-up node respectively, and is used to control the third input voltage provided by the second input voltage terminal under the control of the input signal provided by the input terminal. Two input voltages are written to the pull-up node;
  • the output reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal and the fourth voltage terminal respectively, and is used to control the drive signal output terminal and the fourth voltage terminal under the control of the frame reset signal provided by the frame reset terminal.
  • the fourth voltage terminals are connected;
  • the initial reset circuit is electrically connected to the initial reset terminal, the pull-up node and the fourth voltage terminal respectively, and is used to control the pull-up node and the fourth voltage terminal under the control of the initial reset signal provided by the initial reset terminal.
  • the fourth voltage terminals are connected;
  • the first end of the energy storage circuit is electrically connected to the pull-up node, the second end of the energy storage circuit is electrically connected to the drive signal output end, and the energy storage circuit is used to store electrical energy.
  • the reset circuit includes a fifth transistor
  • the gate of the fifth transistor is electrically connected to the reset terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first input voltage. terminal electrical connection.
  • the first pull-down node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor;
  • the gate electrode of the sixth transistor and the first electrode of the sixth transistor are both electrically connected to the first control voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first pull-down control node. ;
  • the gate of the seventh transistor is electrically connected to the pull-up node, the first electrode of the seventh transistor is electrically connected to the first pull-down control node, and the second electrode of the seventh transistor is electrically connected to the pull-up node.
  • the third voltage terminal is electrically connected;
  • the gate electrode of the eighth transistor is electrically connected to the first pull-down control node, the first electrode of the eighth transistor is electrically connected to the first control voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first pull-down control node.
  • the first pull-down node is electrically connected;
  • the gate of the ninth transistor is electrically connected to the pull-up node, the first electrode of the ninth transistor is electrically connected to the first pull-down node, and the second electrode of the ninth transistor is electrically connected to the pull-up node.
  • Three voltage terminals are electrically connected.
  • the second pull-down node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;
  • the gate electrode of the tenth transistor and the first electrode of the tenth transistor are both electrically connected to the second control voltage terminal, and the second electrode of the tenth transistor is electrically connected to the second pull-down control node;
  • the gate of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down control node, and the second electrode of the eleventh transistor is electrically connected to The third voltage terminal is electrically connected;
  • the gate electrode of the twelfth transistor is electrically connected to the second pull-down control node, the first electrode of the twelfth transistor is electrically connected to the second control voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the second control voltage terminal.
  • the pole is electrically connected to the second pull-down node;
  • the gate of the thirteenth transistor is electrically connected to the pull-up node, the first electrode of the thirteenth transistor is electrically connected to the second pull-down node, and the second electrode of the thirteenth transistor is electrically connected to the pull-up node.
  • the third voltage terminal is electrically connected.
  • the input circuit includes a fourteenth transistor
  • the gate of the fourteenth transistor is electrically connected to the input terminal, the first electrode of the fourteenth transistor is electrically connected to the second input voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the input terminal.
  • the above-mentioned pull-up node is electrically connected;
  • the output circuit includes a fifteenth transistor and a sixteenth transistor
  • the gate of the fifteenth transistor is electrically connected to the pull-up node, the first pole of the fifteenth transistor is electrically connected to the output clock signal terminal, and the second pole of the fifteenth transistor is electrically connected to the output clock signal terminal.
  • the drive signal output terminal is electrically connected;
  • the gate of the sixteenth transistor is electrically connected to the first pull-down node, the first pole of the sixteenth transistor is electrically connected to the drive signal output terminal, and the second pole of the sixteenth transistor Electrically connected to the fourth voltage terminal;
  • the output reset circuit includes a seventeenth transistor
  • the gate of the seventeenth transistor is electrically connected to the frame reset terminal, the first pole of the seventeenth transistor is electrically connected to the drive signal output terminal, and the second pole of the seventeenth transistor is electrically connected to the frame reset terminal.
  • the fourth voltage terminal is electrically connected;
  • the initial reset circuit includes an eighteenth transistor
  • the gate of the eighteenth transistor is electrically connected to the initial reset terminal, the first pole of the eighteenth transistor is electrically connected to the pull-up node, and the second pole of the eighteenth transistor is electrically connected to the initial reset terminal.
  • the fourth voltage terminal is electrically connected;
  • the energy storage circuit includes a storage capacitor
  • the first end of the storage capacitor is electrically connected to the pull-up node, and the second end of the storage capacitor is electrically connected to the drive signal output end.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a second pull-down node
  • the output circuit is also electrically connected to the second pull-down node, and is used to control the connection between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the second pull-down node.
  • the output circuit also includes a nineteenth transistor
  • the gate of the nineteenth transistor is electrically connected to the second pull-down node, the first pole of the nineteenth transistor is electrically connected to the drive signal output terminal, and the second pole of the nineteenth transistor is electrically connected to The fourth voltage terminal is electrically connected.
  • an embodiment of the present disclosure provides a driving method applied to the above-mentioned driving circuit.
  • the driving method includes:
  • the first control circuit controls the connection between the first pull-down node and the first voltage terminal under the control of the first control signal, so that the potential of the first pull-down node is an effective voltage
  • the pull-up node reset circuit controls the connection between the pull-up node and the second voltage terminal to reset the potential of the pull-up node.
  • the driving circuit also includes a second pull-down node and a second control circuit; the driving method further includes:
  • the second control circuit controls the connection between the second pull-down node and the fifth voltage terminal under the control of the second control signal, so that the potential of the second pull-down node is an effective voltage
  • the pull-up node reset circuit controls the connection between the pull-up node and the second voltage terminal to reset the potential of the pull-up node.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned driving circuit.
  • the display device includes a drive module
  • the driving module includes a plurality of cascaded driving circuits
  • the first input voltage terminal of the last-stage drive circuit included in the drive module is not connected to the corresponding first input voltage, and the last-stage drive circuit is a pseudo drive circuit;
  • the display device further includes multiple rows and columns of pixel circuits disposed in the display area, and the last row of pixel circuits included in the display device is a pseudo pixel driving circuit;
  • the last stage driving circuit is used to provide corresponding driving signals to the last row of pixel circuits, and the last row of pixel circuits does not emit light.
  • Figure 1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure
  • Figure 2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 8 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 9 is a working timing diagram of at least one embodiment of the driving circuit shown in Figure 8 of the present disclosure.
  • Figure 10 is the working timing diagram of the adjacent two-stage drive circuit
  • Figure 11A is the simulation waveform of the relevant driving circuit under the reliability test
  • Figure 11B is a comparison of simulated waveforms under the same reliability conditions of at least one embodiment of the driving circuit shown in Figure 8;
  • Figure 12A is a waveform diagram of the current I1 of M2 and the current I16 of M16 of the relevant driving circuit after the reliability test;
  • FIG. 12B is a waveform diagram of the current I2 of M2 and the current I16 of M16 after the reliability test of at least one embodiment of the driving circuit shown in FIG. 8 of the present disclosure.
  • Figure 13A is a waveform diagram of the potential of PU, the potential of PD1 and the driving signal output by O1 after the reliability test of the relevant driving circuit;
  • Figure 13B is a waveform diagram of the potential of PU, the potential of PD1 and the driving signal output by O1 after the reliability test of at least one embodiment of the driving circuit shown in Figure 8 of the present disclosure;
  • Figure 14 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 15A is the simulation waveform of the relevant driving circuit under the reliability test
  • Figure 15B is a simulation waveform comparison of at least one embodiment of the driving circuit shown in Figure 8 under the same reliability conditions;
  • Figure 16A is a waveform diagram of the current I1 of M2 and the current I16 of M16 after the reliability test of the relevant driving circuit;
  • Figure 16B is a waveform diagram of the current I2 of M2 and the current I16 of M16 after the reliability test of at least one embodiment of the driving circuit shown in Figure 14 of the present disclosure;
  • Figure 17A is a waveform diagram of the potential of PU, the potential of PD1 and the driving signal output by O1 after the reliability test of the relevant driving circuit;
  • Figure 17B is a waveform diagram of the potential of PU, the potential of PD1 and the driving signal output by O1 after the reliability test of at least one embodiment of the driving circuit shown in Figure 14 of the present disclosure;
  • Figure 18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 19 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 20 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 21 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 22 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Figure 23 shows the potential of the initial reset signal provided by STV0, the first start signal STV1, the second start signal STV2, the third start signal STV3, the fourth start signal STV4, and the first clock provided by the first clock signal terminal K11 signal, the second clock signal provided by the second clock signal terminal K12, the third clock signal provided by the third clock signal terminal K13, the fourth clock signal provided by the fourth clock signal terminal K14, and the third clock signal provided by the fifth clock signal terminal K15.
  • the driving circuit includes a first pull-down node PD1, a first control circuit 11 and a pull-up node reset circuit 12;
  • the first control circuit 11 is electrically connected to the first pull-down node PD1, the first control terminal Tr1 and the first voltage terminal V1 respectively, and is used for controlling the first control signal provided by the first control terminal Tr1. Control the connection between the first pull-down node PD1 and the first voltage terminal V1 so that the potential of the first pull-down node PD1 is an effective voltage;
  • the pull-up node reset circuit 12 is electrically connected to the first pull-down node PD1, the pull-up node PU and the second voltage terminal V2 respectively, and is used for when the potential of the first pull-down node PD1 is an effective voltage, Control the connection between the pull-up node PU and the second voltage terminal V2 to reset the potential of the pull-up node PU.
  • the effective voltage when the transistor included in the pull-up node reset circuit 12 is an n-type transistor, the effective voltage may be a high voltage, and when the transistor included in the pull-up node reset circuit 12 is a p-type transistor, the effective voltage may be a high voltage. type transistor, the effective voltage may be a low voltage.
  • the first voltage terminal may be the first control voltage terminal GCH, or the first voltage terminal may be a high voltage terminal, but is not limited thereto.
  • the second voltage terminal V2 may be a low voltage terminal.
  • the driving circuit adds a first control circuit 11.
  • the first control circuit 11 controls the first pull-down node PD1 and the first voltage terminal V1 are connected, so that the potential of the first pull-down node PD1 is an effective voltage
  • the pull-up node reset circuit 12 controls the pull-up node under the control of the potential of the first pull-down node PD1
  • the potential of the PU is reset, which improves the noise reduction capability of the transistors included in the pull-up node reset circuit 12, prevents the drive circuit from erroneously outputting, and enables the drive circuit to correctly output the drive signal.
  • the first control terminal is a reset terminal, a first pull-down node or a first pull-down control node.
  • the driving circuit includes a first pull-down node PD1, a first control circuit 11 and a pull-up node reset circuit 12;
  • the first control circuit 11 is electrically connected to the first pull-down node PD1, the reset terminal R1 and the first voltage terminal V1 respectively, and is used to control the first voltage terminal under the control of the reset control signal provided by the reset terminal R1.
  • the pull-down node PD1 is connected to the first voltage terminal V1, so that the potential of the first pull-down node PD1 is an effective voltage;
  • the pull-up node reset circuit 12 is electrically connected to the first pull-down node PD1, the pull-up node PU and the second voltage terminal V2 respectively, and is used for when the potential of the first pull-down node PD1 is an effective voltage, Control the connection between the pull-up node PU and the second voltage terminal V2 to reset the potential of the pull-up node PU.
  • the first control terminal is the reset terminal R1; when the reset terminal R1 provides a high voltage signal, the first voltage terminal V1 improves reliability. After changing the potential of the first pull-down node PD1, the current of the transistor included in the pull-up node reset circuit 12 increases, and the driver circuit does not output Multi.
  • the reset terminal may be a terminal that controls writing the first input voltage to the pull-up node to reset the potential of the pull-up node.
  • the driving circuit includes a first pull-down node PD1, a first control circuit 11 and a pull-up node reset circuit 12;
  • the first control circuit 11 is electrically connected to the first pull-down node PD1 and the first voltage terminal V1 respectively, and is used to control the first pull-down node PD1 under the control of the potential of the first pull-down node PD1 It is connected to the first voltage terminal V1 so that the potential of the first pull-down node PD1 is an effective voltage;
  • the pull-up node reset circuit 12 is electrically connected to the first pull-down node PD1, the pull-up node PU and the second voltage terminal V2 respectively, and is used for when the potential of the first pull-down node PD1 is an effective voltage, Control the connection between the pull-up node PU and the second voltage terminal V2 to reset the potential of the pull-up node PU.
  • the first control terminal is the first pull-down node PD1; when the potential of the first pull-down node PD1 is a high voltage, the After the reliability of the first voltage terminal V1 is increased, the potential of the first pull-down node PD1 increases the current of the transistors included in the pull-up node reset circuit 12 and enhances the noise reduction of the transistors included in the pull-up node reset circuit 12 Ability so that the drive circuit will not have Multi (multiple) outputs.
  • the driving circuit includes a first pull-down node PD1, a first control circuit 11 and a pull-up node reset circuit 12;
  • the first control circuit 11 is electrically connected to the first pull-down node PD1, the first pull-down control node PD_CN1 and the first voltage terminal V1 respectively, and is used to control the potential of the first pull-down control node PD_CN1. Control the connection between the first pull-down node PD1 and the first voltage terminal V1 so that the potential of the first pull-down node PD1 is an effective voltage;
  • the pull-up node reset circuit 12 is electrically connected to the first pull-down node PD1, the pull-up node PU and the second voltage terminal V2 respectively, and is used for when the potential of the first pull-down node PD1 is an effective voltage, Control the connection between the pull-up node PU and the second voltage terminal V2 to reset the potential of the pull-up node PU.
  • the first control terminal is the first pull-down control node PD_CN1; when the potential of the first pull-down control node PD_CN1 is a high voltage, the After the first voltage terminal V1 improves the reliability of the potential of the first pull-down node PD1, the current of the transistor included in the pull-up node reset circuit 12 increases, and the current of the transistor included in the pull-up node reset circuit 12 is enhanced. Noise reduction capability prevents the drive circuit from Multi output.
  • the first control circuit includes a first transistor
  • the gate of the first transistor is electrically connected to the first control terminal, the first pole of the first transistor is electrically connected to the first pull-down node, and the second pole of the first transistor is electrically connected to the first pull-down node.
  • the first voltage terminal is electrically connected;
  • the pull-up node reset circuit includes a second transistor
  • the gate of the second transistor is electrically connected to the first pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the first pull-down node.
  • the two voltage terminals are electrically connected.
  • the driving circuit may further include a reset circuit
  • the reset circuit is electrically connected to the reset terminal, the pull-up node and the first input voltage terminal respectively, and is used to control the supply of the first input voltage terminal to the reset signal under the control of the reset signal provided by the reset terminal.
  • the first input voltage provided is written to the pull-up node.
  • the driving circuit may further include a reset circuit, and the reset circuit writes the first input voltage to the pull-up node under the control of the reset signal.
  • the driving circuit may further include a first pull-down node control circuit
  • the first pull-down node control circuit is electrically connected to the first pull-down node, the first pull-down control node, the pull-up node, the first control voltage terminal and the third voltage terminal, respectively.
  • the connection between the first control voltage terminal and the first pull-down control node is controlled, and under the control of the potential of the pull-up node, Control the connection between the first pull-down control node and the third voltage terminal, and be used to control the first pull-down node and the first pull-down node under the control of the potential of the first pull-down control node. Control the connection between the voltage terminals, and control the connection between the first pull-down node and the third voltage terminal under the control of the potential of the pull-up node;
  • the first voltage terminal is the first control voltage terminal.
  • the driving circuit may further include a first pull-down node control circuit.
  • the first pull-down node control circuit controls the first pull-down node under the control of the potential of the pull-up node and the first control voltage. The potential and the potential of the first pull-down control node.
  • the third voltage terminal may be a low voltage terminal; the second voltage terminal and the third voltage terminal may be the same voltage terminal, but are not limited thereto.
  • the driving circuit according to at least one embodiment of the present disclosure may further include an output circuit
  • the output circuit is electrically connected to the pull-up node, the first pull-down node, the output clock signal terminal, the fourth voltage terminal and the drive signal output terminal respectively, and is used to control the voltage of the pull-up node under the control of the potential of the pull-up node.
  • the output clock signal provided by the output clock signal terminal is written into the driving signal output terminal, and under the control of the potential of the first pull-down node, the connection between the driving signal output terminal and the fourth voltage terminal is controlled. connected between.
  • the driving circuit may further include an output circuit.
  • the output circuit writes the output clock signal to the driving signal output terminal under the control of the potential of the pull-up node, and writes the output clock signal to the first pull-down node. Under the control of electric potential, the connection between the driving signal output terminal and the fourth voltage terminal is controlled to reduce noise on the driving signal output terminal.
  • the fourth voltage terminal is a low voltage terminal
  • the second voltage terminal, the third voltage terminal and the fourth voltage terminal can be the same voltage terminal, but are not limited to this.
  • the driving circuit may further include a second pull-down node and a second control circuit
  • the second control circuit is electrically connected to the second pull-down node, the second control terminal and the fifth voltage terminal respectively, and is used to control the second pull-down node under the control of the second control signal provided by the second control terminal.
  • the node is connected to the fifth voltage terminal so that the potential of the second pull-down node is an effective voltage
  • the pull-up node reset circuit is also electrically connected to the second pull-down node, and is used to control the connection between the pull-up node and the second voltage terminal when the potential of the second pull-down node is an effective voltage. , to reset the potential of the pull-up node.
  • the fifth voltage terminal may be a second control voltage terminal or a high voltage terminal, but is not limited thereto.
  • the driving circuit adds a second control circuit.
  • the second control circuit controls the connection between the second pull-down node and the fifth voltage terminal.
  • the pull-up node reset circuit controls to reset the potential of the pull-up node under the control of the potential of the second pull-down node, raising the The noise reduction capability of the transistor included in the pull-up node reset circuit prevents the driving circuit from erroneously outputting the driving signal, so that the driving circuit can correctly output the driving signal.
  • the second control terminal is a reset terminal, a second pull-down node or a second pull-down control node, but is not limited to this.
  • the driving circuit described in at least one embodiment of the present disclosure may also include a second pull-down node PD2 and a second control circuit 51;
  • the second control circuit 51 is electrically connected to the second pull-down node PD2, the second control terminal Tr2 and the fifth voltage terminal V5 respectively, and is used to control the voltage under the control of the second control signal provided by the second control terminal Tr2.
  • the second pull-down node PD2 is connected to the fifth voltage terminal V5, so that the potential of the second pull-down node PD2 is an effective voltage;
  • the pull-up node reset circuit 12 is also electrically connected to the second pull-down node PD2, and is used to control the pull-up node PU and the second voltage when the potential of the second pull-down node PD2 is an effective voltage.
  • the terminals V2 are connected to reset the potential of the pull-up node PU.
  • the second control circuit includes a third transistor; the pull-up node reset circuit further includes a fourth transistor;
  • the gate of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the second pull-down node, and the second electrode of the third transistor is electrically connected to the second pull-down node.
  • Five voltage terminals are electrically connected;
  • the gate electrode of the fourth transistor is electrically connected to the second pull-down node, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the second pull-down node.
  • the voltage terminals are electrically connected.
  • the driving circuit described in at least one embodiment of the present disclosure may also include a second pull-down node control circuit 61;
  • the second pull-down node control circuit 61 is electrically connected to the second pull-down node PD2, the second pull-down control node PD_CN2, the pull-up node PU, the second control voltage terminal GCH2 and the third voltage terminal V3 respectively, For controlling the connection between the second control voltage terminal GCH2 and the second pull-down control node PD_CN2 under the control of the second control voltage provided by the second control voltage terminal GCH2, at the pull-up node PU Under the control of the potential of the second pull-down control node PD_CN2, the connection between the second pull-down control node PD_CN2 and the third voltage terminal V3 is controlled, and used to control the second pull-down control node PD_CN2 under the control of the potential of The node PD2 is connected to the second control voltage terminal GCH2, and under the control of the potential of the pull-up node PU, the connection between the second pull-down node PD2 and the third voltage terminal V3 is controlled.
  • the fifth voltage terminal is the second control voltage terminal GCH2, but it is not limited to this.
  • the second pull-down node control circuit 61 controls the second pull-down node PD2 under the control of the potential of the pull-up node PU and the second control voltage. and the potential of the second pull-down control node PD_CN2.
  • the driving circuit may further include an input circuit, an output reset circuit, an initial reset circuit and an energy storage circuit;
  • the input circuit is electrically connected to the input terminal, the second input voltage terminal and the pull-up node respectively, and is used to control the third input voltage provided by the second input voltage terminal under the control of the input signal provided by the input terminal. Two input voltages are written into the pull-up node;
  • the output reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal and the fourth voltage terminal respectively, and is used to control the drive signal output terminal and the fourth voltage terminal under the control of the frame reset signal provided by the frame reset terminal.
  • the fourth voltage terminals are connected;
  • the initial reset circuit is electrically connected to the initial reset terminal, the pull-up node and the fourth voltage terminal respectively, and is used to control the pull-up node and the fourth voltage terminal under the control of the initial reset signal provided by the initial reset terminal.
  • the fourth voltage terminals are connected;
  • the first end of the energy storage circuit is electrically connected to the pull-up node, the second end of the energy storage circuit is electrically connected to the drive signal output end, and the energy storage circuit is used to store electrical energy.
  • the fourth voltage terminal may be a low voltage terminal, and the second voltage terminal, the third voltage terminal and the fourth voltage terminal may be the same voltage terminal, but not in the same voltage terminal. This is the limit.
  • the input circuit writes the second input voltage to the pull-up node under the control of the input signal
  • the output reset circuit controls the drive circuit under the control of the frame reset signal.
  • the driving signal provided by the signal output terminal is reset, and the initial reset circuit resets the potential of the pull-up node under the control of the initial reset signal.
  • the driving circuit described in at least one embodiment of the present disclosure also includes a reset circuit 71 , a first pull-down node control circuit 72 , an output Circuit 73, input circuit 74, output reset circuit 75, initial reset circuit 76 and energy storage circuit 70; the second voltage terminal is the low voltage terminal VGL, and the first voltage terminal is the first control voltage terminal GCH;
  • the reset circuit 71 is electrically connected to the reset terminal R1, the pull-up node PU and the first input voltage terminal VSD respectively, and is used to control the first input voltage terminal VSD under the control of the reset signal provided by the reset terminal R1.
  • An input voltage terminal VSD provides a first input voltage to be written into the pull-up node PU;
  • the first pull-down node control circuit 72 is electrically connected to the first pull-down node PD1, the first pull-down control node PD_CN1, the pull-up node PU, the first control voltage terminal GCH and the low voltage terminal VGL respectively. connection, used to control the connection between the first control voltage terminal GCH and the first pull-down control node PD_CN1 under the control of the first control voltage provided by the first control voltage terminal GCH, on the Under the control of the potential of the pull-down node PU, the connection between the first pull-down control node PD_CN1 and the low voltage terminal VGL1 is controlled, and used to control the connection between the first pull-down control node PD_CN1 and the potential of the first pull-down control node PD_CN1.
  • the first pull-down node PD1 is connected to the first control voltage terminal GCH. Under the control of the potential of the pull-up node PU, the connection between the first pull-down node PD1 and the low voltage terminal VGL is controlled.
  • the output circuit 73 is electrically connected to the pull-up node PU, the first pull-down node PD1, the output clock signal terminal K1, the low voltage terminal VGL and the drive signal output terminal O1 respectively, and is used to operate the pull-up node PU. Under the control of the potential, the output clock signal provided by the output clock signal terminal K1 is controlled to be written into the drive signal output terminal O1, and under the control of the potential of the first pull-down node PD1, the drive signal output is controlled The terminal O1 is connected to the low voltage terminal VGL;
  • the input circuit 74 is electrically connected to the input terminal I1, the second input voltage terminal VDS and the pull-up node PU respectively, and is used to control the second input voltage under the control of the input signal provided by the input terminal I1.
  • the second input voltage provided by the voltage terminal VDS is written into the pull-up node PU;
  • the output reset circuit 75 is electrically connected to the frame reset terminal GCL, the drive signal output terminal O1 and the low voltage terminal VGL respectively, and is used to control the drive under the control of the frame reset signal provided by the frame reset terminal GCL.
  • the signal output terminal O1 is connected to the low voltage terminal VGL;
  • the initial reset circuit 76 is electrically connected to the initial reset terminal STV0, the pull-up node PU and the low voltage terminal VGL respectively, and is used to control the initial reset signal under the control of the initial reset signal provided by the initial reset terminal STV0.
  • the pull-up node PU is connected to the low voltage terminal VGL;
  • the first end of the energy storage circuit 70 is electrically connected to the pull-up node PU, and the second end of the energy storage circuit 70 is electrically connected to the drive signal output terminal O1.
  • the energy storage circuit 70 is used to store electrical energy.
  • the reset circuit includes a fifth transistor
  • the gate of the fifth transistor is electrically connected to the reset terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first input voltage. terminal electrical connection.
  • the first pull-down node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor;
  • the gate electrode of the sixth transistor and the first electrode of the sixth transistor are both electrically connected to the first control voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first pull-down control node. ;
  • the gate of the seventh transistor is electrically connected to the pull-up node, the first electrode of the seventh transistor is electrically connected to the first pull-down control node, and the second electrode of the seventh transistor is electrically connected to the pull-up node.
  • the third voltage terminal is electrically connected;
  • the gate electrode of the eighth transistor is electrically connected to the first pull-down control node, the first electrode of the eighth transistor is electrically connected to the first control voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first pull-down control node.
  • the first pull-down node is electrically connected;
  • the gate of the ninth transistor is electrically connected to the pull-up node, the first electrode of the ninth transistor is electrically connected to the first pull-down node, and the second electrode of the ninth transistor is electrically connected to the pull-up node.
  • Three voltage terminals are electrically connected.
  • the second pull-down node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;
  • the gate electrode of the tenth transistor and the first electrode of the tenth transistor are both electrically connected to the second control voltage terminal, and the second electrode of the tenth transistor is electrically connected to the second pull-down control node;
  • the gate of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down control node, and the second electrode of the eleventh transistor is electrically connected to The third voltage terminal is electrically connected;
  • the gate electrode of the twelfth transistor is electrically connected to the second pull-down control node, the first electrode of the twelfth transistor is electrically connected to the second control voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the second control voltage terminal.
  • the pole is electrically connected to the second pull-down node;
  • the gate of the thirteenth transistor is electrically connected to the pull-up node, the first electrode of the thirteenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the pull-up node.
  • the third voltage terminal is electrically connected.
  • the input circuit includes a fourteenth transistor
  • the gate of the fourteenth transistor is electrically connected to the input terminal, the first electrode of the fourteenth transistor is electrically connected to the second input voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the input terminal.
  • the above-mentioned pull-up node is electrically connected;
  • the output circuit includes a fifteenth transistor and a sixteenth transistor
  • the gate of the fifteenth transistor is electrically connected to the pull-up node, the first pole of the fifteenth transistor is electrically connected to the output clock signal terminal, and the second pole of the fifteenth transistor is electrically connected to the output clock signal terminal.
  • the drive signal output terminal is electrically connected;
  • the gate of the sixteenth transistor is electrically connected to the first pull-down node, the first pole of the sixteenth transistor is electrically connected to the drive signal output terminal, and the second pole of the sixteenth transistor Electrically connected to the fourth voltage terminal;
  • the output reset circuit includes a seventeenth transistor
  • the gate of the seventeenth transistor is electrically connected to the frame reset terminal, the first pole of the seventeenth transistor is electrically connected to the drive signal output terminal, and the second pole of the seventeenth transistor is electrically connected to the frame reset terminal.
  • the fourth voltage terminal is electrically connected;
  • the pull-down node reset circuit includes an eighteenth transistor
  • the gate of the eighteenth transistor is electrically connected to the pull-up node, the first electrode of the eighteenth transistor is electrically connected to the first pull-down node, and the second electrode of the eighteenth transistor is electrically connected to The third voltage terminal is electrically connected;
  • the initial reset circuit includes a nineteenth transistor
  • the gate of the nineteenth transistor is electrically connected to the initial reset terminal, the first pole of the nineteenth transistor is electrically connected to the pull-up node, and the second pole of the nineteenth transistor is electrically connected to the pull-up node.
  • the fourth voltage terminal is electrically connected;
  • the energy storage circuit includes a storage capacitor
  • the first end of the storage capacitor is electrically connected to the pull-up node, and the second end of the storage capacitor is electrically connected to the drive signal output end.
  • the first control circuit 11 includes a first transistor M1; the first control terminal is electrically connected to the reset terminal R1.
  • the reset terminal R1 here refers to: when including multiple cascaded drive circuits, if the current level drive circuit is the nth level, for forward scanning, the reset terminal is connected to n+ The output end of the i-level drive circuit, where i can be a positive integer greater than or equal to 1.
  • the reset end can be and cascaded The signal terminal to which the output terminal is connected;
  • the gate of the first transistor M1 is electrically connected to the reset terminal R1, the source of the first transistor M1 is electrically connected to the first pull-down node PD1, and the drain of the first transistor M1 is electrically connected to the first control node.
  • the voltage terminal GCH is electrically connected;
  • the pull-up node reset circuit 12 includes a second transistor M2;
  • the gate of the second transistor M2 is electrically connected to the first pull-down node PD1, the source of the second transistor M2 is electrically connected to the pull-up node PU, and the drain of the second transistor M2 is electrically connected to the first pull-down node PD1.
  • the low voltage terminal VGL is electrically connected;
  • the reset circuit 71 includes a fifth transistor M5;
  • the gate of the fifth transistor M5 is electrically connected to the reset terminal R1, the source of the fifth transistor M5 is electrically connected to the pull-up node PU, and the drain of the fifth transistor M5 is electrically connected to the third An input voltage terminal VSD is electrically connected;
  • the first pull-down node control circuit 72 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9;
  • the gate of the sixth transistor M6 and the source of the sixth transistor M6 are both electrically connected to the first control voltage terminal GCH, and the drain of the sixth transistor M6 is connected to the first pull-down control node.
  • the gate of the seventh transistor M7 is electrically connected to the pull-up node PU, the source of the seventh transistor M7 is electrically connected to the first pull-down control node PD_CN1, and the drain of the seventh transistor M7 Electrically connected to the low voltage terminal VGL;
  • the gate of the eighth transistor M8 is electrically connected to the first pull-down control node PD_CN1, and the source of the eighth transistor M8 is electrically connected to the first control voltage terminal GCH.
  • the drain is electrically connected to the first pull-down node PD1;
  • the gate of the ninth transistor M9 is electrically connected to the pull-up node PU, the source of the ninth transistor M9 is electrically connected to the first pull-down node PD1, and the drain of the ninth transistor M9 is electrically connected to the pull-up node PU.
  • the low voltage terminal VGL is electrically connected;
  • the input circuit 74 includes a fourteenth transistor M14;
  • the gate of the fourteenth transistor M14 is electrically connected to the input terminal I1, the source of the fourteenth transistor M14 is electrically connected to the second input voltage terminal VDS, and the drain of the fourteenth transistor M14
  • the pole is electrically connected to the pull-up node PU;
  • the output circuit 73 includes a fifteenth transistor M15 and a sixteenth transistor M16;
  • the gate of the fifteenth transistor M15 is electrically connected to the pull-up node PU, the source of the fifteenth transistor M15 is electrically connected to the output clock signal terminal K1, and the drain of the fifteenth transistor M15 The pole is electrically connected to the drive signal output terminal O1;
  • the gate of the sixteenth transistor M16 is electrically connected to the first pull-down node PD1, and the source of the sixteenth transistor M16 is electrically connected to the drive signal output terminal O1.
  • the sixteenth transistor M16 The drain is electrically connected to the low voltage terminal VGL;
  • the output reset circuit 75 includes a seventeenth transistor M17;
  • the gate of the seventeenth transistor M17 is electrically connected to the frame reset terminal GCL, the source of the seventeenth transistor M17 is electrically connected to the drive signal output terminal O1, and the drain of the seventeenth transistor M17 The pole is electrically connected to the low voltage terminal VGL;
  • the initial reset circuit 76 includes an eighteenth transistor M18;
  • the gate of the eighteenth transistor M18 is electrically connected to the initial reset terminal STV0, the source of the eighteenth transistor M18 is electrically connected to the pull-up node PU, and the drain of the eighteenth transistor M18 Electrically connected to the low voltage terminal VGL;
  • the energy storage circuit 70 includes a storage capacitor C1;
  • the first end of the storage capacitor C1 is electrically connected to the pull-up node PU, and the second end of the storage capacitor C1 is electrically connected to the drive signal output terminal O1.
  • all transistors are n-type thin film transistors, but are not limited to this.
  • At least one embodiment of the driving circuit shown in FIG. 8 of the present disclosure is capable of bidirectional scanning
  • the driving circuit can perform forward scanning
  • the driving circuit can perform reverse scanning.
  • VDS provides a high voltage signal and VSD provides a low voltage signal as an example for illustration;
  • the display cycle may include input stages set successively. S1, output stage S2 and reset stage S3;
  • K1 provides a low voltage signal
  • I1 provides a high voltage signal
  • R1 provides a low voltage signal
  • GCH provides a high voltage signal
  • M1 is turned off
  • M14 is turned on
  • the high voltage signal provided by VDS is written to the pull-up node PU, causing the potential of PU to increase by one order
  • M15 opens, and O1 outputs a low voltage signal
  • M6 and M7 are turned on to control the potential of PD_CN1 to be low voltage, M8 is turned off, and M9 is turned on to control the potential of PD1 to be low voltage;
  • K1 provides a high voltage signal
  • I1 provides a low voltage signal
  • R1 provides a high voltage signal
  • GCH provides a high voltage signal.
  • K1 provides a low voltage signal
  • I1 provides a low voltage signal
  • R1 provides a high voltage signal
  • GCH provides a high voltage signal
  • M5 is turned on to reset the potential of the PU and lower the potential of the PU;
  • M6 is turned on, M7 is turned off, the potential of PD_CN1 is high voltage, M8 is turned on, M9 is turned off, the potential of PD1 is high voltage, M2 and M16 are turned on, making the PU and VGL connected, and making O1 outputs a low voltage signal.
  • S0 is the output cut-off holding stage. During the output cut-off holding stage S0, O1 continues to output a low voltage signal.
  • R1 provides a high voltage signal
  • GCH provides a high voltage signal
  • M1 is turned on to raise the potential of PD1.
  • Figure 10 is the working timing diagram of two adjacent levels of drive circuits.
  • K11 is the clock signal connected to the first-level drive circuit
  • K12 is the clock signal connected to the second-level drive circuit
  • PU1 is the clock signal connected to the first-level drive circuit.
  • the pull-up node in the drive circuit I11 is the input signal connected to the input end of the first-level drive circuit
  • O11 is the moving signal output end of the first-level drive circuit;
  • K12 is the clock signal connected to the second-level drive circuit
  • PU2 is the pull-up node in the second-level drive circuit
  • I12 is the input signal connected to the input terminal in the second-level drive circuit
  • O12 is the second-level drive circuit.
  • the drive signal output end, R11 is the reset signal connected to the reset end of the first-level drive circuit.
  • At least one embodiment of the driving circuit shown in FIG. 8 of the present disclosure adds a first transistor M1, which can turn on M1 when the reset signal arrives, and further raise the potential of PD1 through the high level provided by GCH.
  • FIG. 11A is a simulation waveform of a related driving circuit under a reliability test
  • FIG. 11B is a comparison of simulation waveforms of at least one embodiment of the driving circuit shown in FIG. 8 under the same reliability condition.
  • the high potential of PD1 is increased from 1V in the related art to 9V. After the reset signal arrives, the potential of PU and the noise of the driving signal output by O1 are reduced. Small.
  • Figure 12A is a waveform diagram of the current I1 of M2 and the current I16 of M16 of the relevant driving circuit after the reliability test.
  • Figure 12B is the waveform diagram of M2 after the reliability test of at least one embodiment of the driving circuit shown in Figure 8 of the present disclosure. The waveform diagram of the current I2 of M16 and the current I16 of M16.
  • Figure 13A is a waveform diagram of the potential of PU, the potential of PD1 and the driving signal output by O1 after the reliability test of the relevant driving circuit.
  • FIG. 13B is a waveform diagram of the potential of PU, the potential of PD1 and the driving signal output by O1 after the reliability test of at least one embodiment of the driving circuit shown in FIG. 8 of the present disclosure.
  • the reliability test may be a high-temperature and high-humidity reliability test; for example, the reliability test may be a high-temperature reliability test at 60° C. or greater; optionally, the reliability test The reliability test can be a high-temperature reliability test at 85°C; but it is not limited to this.
  • the driving signal output by the relevant driving circuit appears Multi output, and at least one embodiment of the driving circuit shown in Figure 8 of the present disclosure can The drive signal is correctly output and the noise remains small after the reset signal is brought.
  • the relevant driving circuit when the relevant driving circuit outputs normally, within a display period (the display period may be, for example, a frame time), the driving signal output by the relevant driving circuit has only one upward direction. pulse; however, when the driving signal output by the related driving circuit has multiple outputs, the driving signal output by the related driving circuit has multiple upward pulses in one display period. As shown in Figure 13A, within a display period, the driving signal output by O1 has multiple upward pulses, so that a multi-output phenomenon occurs.
  • the only difference between at least one embodiment of the driving circuit shown in FIG. 14 and at least one embodiment of the driving circuit shown in FIG. 8 is that the gate of M1 is electrically connected to the first pull-down node PD1.
  • At least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure adds a first transistor M1, which can turn on M1 when the potential of PD1 is a high voltage, and further raise the potential of PD1 through the high level provided by GCH.
  • FIG. 15A is a simulation waveform of a related driving circuit under a reliability test
  • FIG. 15B is a comparison of simulation waveforms of at least one embodiment of the driving circuit shown in FIG. 8 under the same reliability condition.
  • the high potential of PD1 is increased from 1V in the related art to 11.5V. After the reset signal arrives, the potential of PU and the noise of the driving signal output by O1 decrease.
  • Figure 16A is a waveform diagram of the current I1 of M2 and the current I16 of M16 of the relevant driving circuit after the reliability test.
  • Figure 16B is the waveform diagram of M2 after the reliability test of at least one embodiment of the driving circuit shown in Figure 14 of the present disclosure. The waveform diagram of the current I2 of M16 and the current I16 of M16.
  • Figure 17A is a waveform diagram of the potential of PU, the potential of PD1 and the driving signal output by O1 after the reliability test of the relevant driving circuit.
  • FIG. 17B is a waveform diagram of the potential of PU, the potential of PD1 and the driving signal output by O1 after the reliability test of at least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure.
  • the driving signal output by the relevant driving circuit appears Multi output, and at least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure can The drive signal is correctly output and the noise remains small after the reset signal is brought.
  • the only difference between at least one embodiment of the driving circuit shown in FIG. 18 and at least one embodiment of the driving circuit shown in FIG. 11 is that the gate of M1 is electrically connected to the first pull-down control node PD_CN1.
  • the potential of PD1 and the potential of PD_CN1 are high voltage at the same time, but the high voltage value of PD_CN1 is greater than the high voltage value of PD1. Therefore, compared with the high voltage value shown in Figure 14
  • the size of M1 can be set to be smaller. Since the tube size is smaller, the technical effect of a narrow frame of the display panel can be further achieved.
  • only one pull-down node (the first pull-down node PD1 ) is provided, which can not only reduce the number of transistors used, but also facilitate the realization of a narrow frame of the display panel, and can also use only one pull-down node.
  • the pull-up node reset circuit can Under the control of the potential of the first pull-down node, the potential of the pull-up node is controlled to be reset, thereby improving the noise reduction capability of the transistor included in the pull-up node reset circuit and preventing the driver circuit from erroneously outputting, so that The driving circuit can correctly output the driving signal.
  • FIG. 19 based on at least one embodiment of the driving circuit shown in FIG.
  • the driving circuit further includes a reset circuit 71 , a first pull-down node control circuit 72 , an output Circuit 73, input circuit 74, output reset circuit 75, initial reset circuit 76 and energy storage circuit 70; the second voltage terminal is the low voltage terminal VGL, and the first voltage terminal is the first control voltage terminal GCH;
  • the reset circuit 71 is electrically connected to the reset terminal R1, the pull-up node PU and the first input voltage terminal VSD respectively, and is used to control the first input voltage terminal VSD under the control of the reset signal provided by the reset terminal R1.
  • An input voltage terminal VSD provides a first input voltage to be written into the pull-up node PU;
  • the first pull-down node control circuit 72 is electrically connected to the first pull-down node PD1, the first pull-down control node PD_CN1, the pull-up node PU, the first control voltage terminal GCH and the low voltage terminal VGL respectively. connection, used to control the connection between the first control voltage terminal GCH and the first pull-down control node PD_CN1 under the control of the first control voltage provided by the first control voltage terminal GCH, on the Under the control of the potential of the pull-down node PU, the connection between the first pull-down control node PD_CN1 and the low voltage terminal VGL1 is controlled, and used to control the connection between the first pull-down control node PD_CN1 and the potential of the first pull-down control node PD_CN1.
  • the first pull-down node PD1 is connected to the first control voltage terminal GCH. Under the control of the potential of the pull-up node PU, the connection between the first pull-down node PD1 and the low voltage terminal VGL is controlled.
  • the output circuit 73 is electrically connected to the pull-up node PU, the first pull-down node PD1, the second pull-down node PD2, the output clock signal terminal K1, the low voltage terminal VGL and the drive signal output terminal O1 respectively, and is used for Under the control of the potential of the pull-up node PU, the output clock signal provided by the output clock signal terminal K1 is controlled to be written into the drive signal output terminal O1, and under the control of the potential of the first pull-down node PD1, Control the connection between the drive signal output terminal O1 and the low voltage terminal VGL, and control the connection between the drive signal output terminal O1 and the low voltage terminal VGL under the control of the potential of the second pull-down node PD2 connected;
  • the input circuit 74 is electrically connected to the input terminal I1, the second input voltage terminal VDS and the pull-up node PU respectively, and is used to control the second input voltage under the control of the input signal provided by the input terminal I1.
  • the second input voltage provided by the voltage terminal VDS is written into the pull-up node PU;
  • the output reset circuit 75 is electrically connected to the frame reset terminal GCL, the drive signal output terminal O1 and the low voltage terminal VGL respectively, and is used to control the drive under the control of the frame reset signal provided by the frame reset terminal GCL.
  • the signal output terminal O1 is connected to the low voltage terminal VGL;
  • the initial reset circuit 76 is electrically connected to the initial reset terminal STV0, the pull-up node PU and the low voltage terminal VGL respectively, and is used to control the initial reset signal under the control of the initial reset signal provided by the initial reset terminal STV0.
  • the pull-up node PU is connected to the low voltage terminal VGL;
  • the first end of the energy storage circuit 70 is electrically connected to the pull-up node PU, and the second end of the energy storage circuit 70 is electrically connected to the drive signal output terminal O1.
  • the energy storage circuit 70 is used to store electrical energy.
  • the first control circuit 11 includes a first transistor M1; both the first control terminal and the second control terminal are reset. terminal R1;
  • the gate of the first transistor M1 is electrically connected to the reset terminal R1, the source of the first transistor M1 is electrically connected to the first pull-down node PD1, and the drain of the first transistor M1 is electrically connected to the first control node.
  • the voltage terminal GCH is electrically connected;
  • the pull-up node reset circuit 12 includes a second transistor M2;
  • the gate of the second transistor M2 is electrically connected to the first pull-down node PD1, the source of the second transistor M2 is electrically connected to the pull-up node PU, and the drain of the second transistor M2 is electrically connected to the first pull-down node PD1.
  • the low voltage terminal VGL is electrically connected;
  • the second control circuit 51 includes a third transistor M3; the pull-up node reset circuit 12 also includes a fourth transistor M4;
  • the gate of the third transistor M3 is electrically connected to the reset terminal R1, the source of the third transistor M3 is electrically connected to the second pull-down node PD2, and the drain of the third transistor M3 is electrically connected to the second pull-down node PD2.
  • the control voltage terminal GCH2 is electrically connected;
  • the gate of the fourth transistor M4 is electrically connected to the second pull-down node PD2, the source of the fourth transistor M4 is electrically connected to the pull-up node PU, and the drain of the fourth transistor M4 is electrically connected to the pull-down node PD2.
  • the low voltage terminal VGL is electrically connected;
  • the reset circuit 71 includes a fifth transistor M5;
  • the gate of the fifth transistor M5 is electrically connected to the reset terminal R1, the source of the fifth transistor M5 is electrically connected to the pull-up node PU, and the drain of the fifth transistor M5 is electrically connected to the third An input voltage terminal VSD is electrically connected;
  • the first pull-down node control circuit 72 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9;
  • the gate of the sixth transistor M6 and the source of the sixth transistor M6 are both electrically connected to the first control voltage terminal GCH, and the drain of the sixth transistor M6 is connected to the first pull-down control node.
  • the gate of the seventh transistor M7 is electrically connected to the pull-up node PU, the source of the seventh transistor M7 is electrically connected to the first pull-down control node PD_CN1, and the drain of the seventh transistor M7 Electrically connected to the low voltage terminal VGL;
  • the gate of the eighth transistor M8 is electrically connected to the first pull-down control node PD_CN1, and the source of the eighth transistor M8 is electrically connected to the first control voltage terminal GCH.
  • the drain is electrically connected to the first pull-down node PD1;
  • the gate of the ninth transistor M9 is electrically connected to the pull-up node PU, the source of the ninth transistor M9 is electrically connected to the first pull-down node PD1, and the drain of the ninth transistor M9 is electrically connected to the pull-up node PU.
  • the low voltage terminal VGL is electrically connected;
  • the second pull-down node control circuit 61 includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13;
  • the gate of the tenth transistor M10 and the source of the tenth transistor M10 are both electrically connected to the second control voltage terminal GCH2, and the drain of the tenth transistor M10 is electrically connected to the second pull-down control node PD_CN2. ;
  • the gate of the eleventh transistor M11 is electrically connected to the pull-up node PU, and the source of the eleventh transistor M11 is electrically connected to the second pull-down control node PD_CN2.
  • the drain is electrically connected to the low voltage terminal VGL;
  • the gate of the twelfth transistor M12 is electrically connected to the second pull-down control node PD_CN2, and the source of the twelfth transistor M12 is electrically connected to the second control voltage terminal GCH2.
  • the twelfth transistor M12 The drain of M12 is electrically connected to the second pull-down node PD2;
  • the gate of the thirteenth transistor M13 is electrically connected to the pull-up node PU, the source of the thirteenth transistor M13 is electrically connected to the second pull-down node PD2, and the second electrode of the tenth transistor Electrically connected to the third voltage terminal;
  • the input circuit 74 includes a fourteenth transistor M14;
  • the gate of the fourteenth transistor M14 is electrically connected to the input terminal I1, the source of the fourteenth transistor M14 is electrically connected to the second input voltage terminal VDS, and the drain of the fourteenth transistor M14
  • the pole is electrically connected to the pull-up node PU;
  • the output circuit 73 includes a fifteenth transistor M15 and a sixteenth transistor M16;
  • the gate of the fifteenth transistor M15 is electrically connected to the pull-up node PU, the source of the fifteenth transistor M15 is electrically connected to the output clock signal terminal K1, and the drain of the fifteenth transistor M15 The pole is electrically connected to the drive signal output terminal O1;
  • the gate of the sixteenth transistor M16 is electrically connected to the first pull-down node PD1, and the source of the sixteenth transistor M16 is electrically connected to the drive signal output terminal O1.
  • the sixteenth transistor M16 The drain is electrically connected to the low voltage terminal VGL;
  • the output reset circuit 75 includes a seventeenth transistor M17;
  • the gate of the seventeenth transistor M17 is electrically connected to the frame reset terminal GCL, the source of the seventeenth transistor M17 is electrically connected to the drive signal output terminal O1, and the drain of the seventeenth transistor M17 The pole is electrically connected to the low voltage terminal VGL;
  • the initial reset circuit 76 includes an eighteenth transistor M18;
  • the gate of the eighteenth transistor M18 is electrically connected to the initial reset terminal STV0, the source of the eighteenth transistor M18 is electrically connected to the pull-up node PU, and the drain of the eighteenth transistor M18 Electrically connected to the low voltage terminal VGL;
  • the energy storage circuit 70 includes a storage capacitor C1;
  • the first end of the storage capacitor C1 is electrically connected to the pull-up node PU, and the second end of the storage capacitor C1 is electrically connected to the drive signal output terminal O1.
  • the output circuit 73 also includes a nineteenth transistor M19;
  • the gate of the nineteenth transistor M19 is electrically connected to the second pull-down node PD2, and the source of the nineteenth transistor M19 is electrically connected to the drive signal output terminal O1.
  • the drain electrode is electrically connected to the low voltage terminal VGL.
  • all transistors may be n-type thin film transistors, but are not limited to this.
  • At least one embodiment of the driving circuit shown in FIG. 20 of the present disclosure is capable of bidirectional scanning
  • the driving circuit can perform forward scanning
  • the driving circuit can perform reverse scanning.
  • At least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure uses two pull-down nodes: a first pull-down node PD1 and a second pull-down node PD2;
  • the potential of the second control voltage When the potential of the first control voltage is a high voltage, the potential of the second control voltage may be a low voltage; when the potential of the second control voltage is a low voltage, the potential of the first control voltage may be It is high voltage; but it is not limited to this.
  • the potential of the first control voltage is a high voltage
  • the output phase included in the display cycle, and the output set after the output phase are turned off.
  • the potential of PD1 is high voltage
  • the potential of PD2 is a high voltage during the reset phase included in the display cycle and the output cutoff holding phase set after the reset phase;
  • the transistor controlled by PD1 and the transistor controlled by PD2 are turned on alternately, thereby improving the threshold voltage drift of the transistor.
  • R1 When the potential of the second control voltage is high voltage, during the reset phase included in the display cycle, R1 provides a high voltage signal, and M3 is turned on to pull up the potential of PD2.
  • the only difference between at least one embodiment of the driving circuit shown in Figure 21 and at least one embodiment of the driving circuit shown in Figure 20 is that: the gate of M1 is electrically connected to the first pull-down node PD1, and the gate of M3 is electrically connected to the first pull-down node PD1.
  • the second pull-down node PD2 is electrically connected.
  • the first control voltage when the first control voltage is a high voltage, when the potential of PU is a low voltage and the potential of PD1 is a high voltage, M1 is turned on, and further the voltage provided by the GCH is The first control voltage raises the potential of PD1;
  • the gate of M1 is electrically connected to the first pull-down control node PD_CN1
  • the gate of M2 is electrically connected to the first pull-down control node PD_CN1.
  • the second pull-down control node PD_CN2 is electrically connected.
  • the size of M1 can be set smaller;
  • the second control voltage is a high voltage
  • the potential of PD2 and the potential of PD_CN2 are high voltage at the same time, but the high voltage value of PD_CN2 is greater than the high voltage value of PD2. Therefore, compared with at least one implementation of the driving circuit shown in Figure 20 For example, the size of M3 can be set smaller.
  • the potential of the pull-up node will not be reset through M5 (the drain of M5 is not connected to the corresponding first input voltage), and the output of the driving signal output terminal is complete. clock signal until reset after frame.
  • the middle row is affected by reset and M14 leakage noise, and the Multi output cycle of the drive signal output terminal has no obvious pattern.
  • the threshold voltage of M1 is 0.29V
  • the threshold voltage of M8 is 6.92V
  • the threshold voltage of M2 is 14.79V
  • the potential of PU, PD1 potential, and the waveform of the drive signal output from the drive signal output terminal the high voltage value of PD1 is 1.33V
  • the low voltage value of PU is -11V
  • the potential of PU is low voltage, it will fluctuate upward by 1.7V many times, but The drive signal can be output normally.
  • the drift of the threshold voltage of M2 caused the potential of the PU to fluctuate to a certain extent.
  • the potential of the PU was still a low voltage and would not cause false output of the driving signal. There were other reasons for the increase in the potential of the PU.
  • bidirectional scanning has a negative drift in the threshold voltage of M14 after reliability, which leads to an increase in leakage current and an increase in PU noise.
  • a flicker phenomenon is prone to occur when paired with a single pull-down node.
  • the embodiment of the present disclosure adds a first control circuit 11.
  • the first control circuit 11 controls the connection between the first pull-down node PD1 and the first voltage terminal V1. are connected, so that the potential of the first pull-down node PD1 is an effective voltage, and the pull-up node reset circuit 12 controls the pull-up node PU under the control of the potential of the first pull-down node PD1
  • the potential of the pull-up node reset circuit 12 is reset, thereby improving the noise reduction capability of the transistors included in the pull-up node reset circuit 12, preventing the drive circuit from erroneously outputting, and enabling the drive circuit to correctly output the drive signal.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes:
  • the first control circuit controls the connection between the first pull-down node and the first voltage terminal under the control of the first control signal, so that the potential of the first pull-down node is an effective voltage
  • the pull-up node reset circuit controls the connection between the pull-up node and the second voltage terminal to reset the potential of the pull-up node.
  • the driving circuit further includes a second pull-down node and a second control circuit; the driving method further includes:
  • the second control circuit controls the connection between the second pull-down node and the fourth voltage terminal under the control of the second control signal, so that the potential of the second pull-down node is an effective voltage
  • the pull-up node reset circuit controls the connection between the pull-up node and the second voltage terminal to reset the potential of the pull-up node.
  • the display device includes the above-mentioned driving circuit.
  • the display device includes a driving module
  • the driving module includes a plurality of cascaded driving circuits
  • the first input voltage terminal of the last-stage drive circuit included in the drive module is not connected to the corresponding first input voltage, and the last-stage drive circuit is a pseudo drive circuit;
  • the display device further includes multiple rows and columns of pixel circuits disposed in the display area, and the last row of pixel circuits included in the display device may be a pseudo pixel driving circuit;
  • the last stage driving circuit is used to provide corresponding driving signals to the last row of pixel circuits, and the last row of pixel circuits does not emit light.
  • multi-level driving circuits cascaded with each other form a driving module
  • the last-level drive circuit can be a dummy (pseudo) drive circuit.
  • the dummy drive circuit can provide drive signals for the dummy pixel circuit.
  • the dummy pixel circuit is not used for show.
  • the display device may include a first driving module located on the left side of the display panel and a second driving module located on the right side of the display panel;
  • the first driving module includes a multi-level driving circuit cascaded with each other;
  • the second driving module includes mutually cascaded multi-level driving circuits
  • the second driving module is electrically connected to the second clock signal terminal K12, the fourth clock signal terminal K14, the sixth clock signal terminal K16 and the eighth clock signal terminal K18 respectively;
  • the first driving module is electrically connected to the first clock signal terminal K11, the third clock signal terminal K13, the fifth clock signal terminal K15 and the seventh clock signal terminal K17 respectively;
  • Figure 23 shows the potential of the initial reset signal provided by STV0, the first start signal STV1, the second start signal STV2, the third start signal STV3, the fourth start signal STV4, and the first clock provided by the first clock signal terminal K11 signal, the second clock signal provided by the second clock signal terminal K12, the third clock signal provided by the third clock signal terminal K13, the fourth clock signal provided by the fourth clock signal terminal K14, and the third clock signal provided by the fifth clock signal terminal K15.
  • SN is the Nth frame time
  • SN+1 is the N+1th frame time
  • B0 is the blank time period between SN and SN+1.
  • the display device provided in the embodiment of the present disclosure can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

本公开提供一种驱动电路、驱动方法和显示装置。驱动电路包括第一下拉节点、第一控制电路和上拉节点复位电路；第一控制电路在第一控制信号的控制下，控制第一下拉节点与第一电压端之间连通，以使得第一下拉节点的电位为有效电压；上拉节点复位电路在第一下拉节点的电位为有效电压时，控制上拉节点与第二电压端之间连通，以对上拉节点的电位进行复位。本公开能够提升所述上拉节点复位电路包括的晶体管的降噪能力，防止所述驱动电路误输出，使得所述驱动电路能够正确输出驱动信号。

Description

驱动电路、驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动方法和显示装置。
背景技术
在相关技术中，所述驱动电路可以仅包括一个下拉节点和一个下拉节点控制电路以实现窄边框，然而由于只有一个下拉节点来控制电位，在高温高湿信赖性过程中，晶体管特性均会发生一定程度的漂移，输入电路包括的晶体管在负偏压作用下，阈值电压负向漂移，漏电流增大，第二输入电压端向上拉节点漏电产生noise(噪声)，加之上拉节点复位电路包括的晶体管的特性和第一下拉节点控制电路包括的栅极与第一下拉控制节点电连接的晶体管的特性正向漂移，导致第一下拉节点的电位下降，所述上拉节点复位电路包括的晶体管的降噪能力下降，无法将上拉节点的电位下拉为低电压，从而使得所述驱动电路误输出，产生多驱动信号输出。
发明内容
在一个方面中，本公开实施例提供一种驱动电路，包括第一下拉节点、第一控制电路和上拉节点复位电路；
所述第一控制电路分别与第一下拉节点、第一控制端和第一电压端电连接，用于在所述第一控制端提供的第一控制信号的控制下，控制所述第一下拉节点与所述第一电压端之间连通，以使得所述第一下拉节点的电位为有效电压；
所述上拉节点复位电路分别与所述第一下拉节点、上拉节点和第二电压端电连接，用于在所述第一下拉节点的电位为有效电压时，控制所述上拉节点与所述第二电压端之间连通，以对所述上拉节点的电位进行复位。
可选的，所述第一控制端为复位端、第一下拉节点或第一下拉控制节点。
可选的，所述第一控制电路包括第一晶体管；
所述第一晶体管的栅极与所述第一控制端电连接，所述第一晶体管的第一极与所述第一下拉节点电连接，所述第一晶体管的第二极与所述第一电压端电连接；
所述上拉节点复位电路包括第二晶体管；
所述第二晶体管的栅极与所述第一下拉节点电连接，所述第二晶体管的第一极与所述上拉节点电连接，所述第二晶体管的第二极与所述第二电压端电连接。
可选的，本公开至少一实施例所述的驱动电路还包括复位电路；
所述复位电路分别与所述复位端、所述上拉节点和第一输入电压电连接，用于在所述复位端提供的复位信号的控制下，控制将所述第一输入电压端提供提供的第一输入电压写入所述上拉节点。
可选的，本公开至少一实施例所述的驱动电路还包括第一下拉节点控制电路；
所述第一下拉节点控制电路分别与所述第一下拉节点、所述第一下拉控制节点、所述上拉节点、第一控制电压端和第三电压端电连接，用于在所述第一控制电压端提供的第一控制电压的控制下，控制所述第一控制电压端与所述第一下拉控制节点之间连通，在所述上拉节点的电位的控制下，控制所述第一下拉控制节点与所述第三电压端之间连通，并用于在所述第一下拉控制节点的电位的控制下，控制所述第一下拉节点与所述第一控制电压端之间连通，在所述上拉节点的电位的控制下，控制所述第一下拉节点与所述第三电压端之间连通；
所述第一电压端为所述第一控制电压端。
可选的，本公开至少一实施例所述的驱动电路还包括输出电路；
所述输出电路分别与所述上拉节点、第一下拉节点、输出时钟信号端、第四电压端和驱动信号输出端电连接，用于在所述上拉节点的电位的控制下，控制将所述输出时钟信号端提供的输出时钟信号写入所述驱动信号输出端，在所述第一下拉节点的电位的控制下，控制所述驱动信号输出端与所述第四电压端之间连通。
可选的，本公开至少一实施例所述的驱动电路还包括第二下拉节点和第 二控制电路；
所述第二控制电路分别与第二下拉节点、第二控制端和第五电压端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第二下拉节点与所述第五电压端之间连通，以使得所述第二下拉节点的电位为有效电压；
所述上拉节点复位电路还与所述第二下拉节点电连接，用于在所述第二下拉节点的电位为有效电压时，控制所述上拉节点与所述第二电压端之间连通，以对所述上拉节点的电位进行复位。
可选的，所述第二控制端为复位端、第二下拉节点或第二下拉控制节点。
可选的，所述第二控制电路包括第三晶体管；所述上拉节点复位电路还包括第四晶体管；
所述第三晶体管的栅极与所述第二控制端电连接，所述第三晶体管的第一极与所述第二下拉节点电连接，所述第三晶体管的第二极与所述第五电压端电连接；
所述第四晶体管的栅极与所述第二下拉节点电连接，所述第四晶体管的第一极与所述上拉节点电连接，所述第四晶体管的第二极与所述第二电压端电连接。
可选的，本公开至少一实施例所述的驱动电路还包括第二下拉节点控制电路；
所述第二下拉节点控制电路分别与所述第二下拉节点、所述第二下拉控制节点、所述上拉节点、第二控制电压端和第三电压端电连接，用于在所述第二控制电压端提供的第二控制电压的控制下，控制所述第二控制电压端与所述第二下拉控制节点之间连通，在所述上拉节点的电位的控制下，控制所述第二下拉控制节点与所述第三电压端之间连通，并用于在所述第二下拉控制节点的电位的控制下，控制所述第二下拉节点与所述第二控制电压端之间连通，在所述上拉节点的电位的控制下，控制所述第二下拉节点与所述第三电压端之间连通；
所述第五电压端为所述第二控制电压端。
可选的，本公开至少一实施例所述的驱动电路还包括输入电路、输出复 位电路、初始复位电路和储能电路；
所述输入电路分别与输入端、第二输入电压端和所述上拉节点电连接，用于在所述输入端提供的输入信号的控制下，控制将所述第二输入电压端提供的第二输入电压写入所述上拉节点；
所述输出复位电路分别与帧复位端、所述驱动信号输出端和第四电压端电连接，用于在所述帧复位端提供的帧复位信号的控制下，控制所述驱动信号输出端与所述第四电压端之间连通；
所述初始复位电路分别与初始复位端、所述上拉节点和所述第四电压端电连接，用于在所述初始复位端提供的初始复位信号的控制下，控制所述上拉节点与所述第四电压端之间连通；
所述储能电路的第一端与所述上拉节点电连接，所述储能电路的第二端与所述驱动信号输出端电连接，所述储能电路用于储存电能。
可选的，所述复位电路包括第五晶体管；
所述第五晶体管的栅极与所述复位端电连接，所述第五晶体管的第一极与所述上拉节点电连接，所述第五晶体管的第二极与所述第一输入电压端电连接。
可选的，所述第一下拉节点控制电路包括第六晶体管、第七晶体管、第八晶体管和第九晶体管；
所述第六晶体管的栅极与所述第六晶体管的第一极都与所述第一控制电压端电连接，所述第六晶体管的第二极与所述第一下拉控制节点电连接；
所述第七晶体管的栅极与所述上拉节点电连接，所述第七晶体管的第一极与所述第一下拉控制节点电连接，所述第七晶体管的第二极与所述第三电压端电连接；
所述第八晶体管的栅极与所述第一下拉控制节点电连接，所述第八晶体管的第一极与所述第一控制电压端电连接，所述第八晶体管的第二极与所述第一下拉节点电连接；
所述第九晶体管的栅极与所述上拉节点电连接，所述第九晶体管的第一极与所述第一下拉节点电连接，所述第九晶体管的第二极与所述第三电压端电连接。
可选的，所述第二下拉节点控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
所述第十晶体管的栅极与所述第十晶体管的第一极都与所述第二控制电压端电连接，所述第十晶体管的第二极与所述第二下拉控制节点电连接；
所述第十一晶体管的栅极与所述上拉节点电连接，所述第十一晶体管的第一极与所述第二下拉控制节点电连接，所述第十一晶体管的第二极与所述第三电压端电连接；
所述第十二晶体管的栅极与所述第二下拉控制节点电连接，所述第十二晶体管的第一极与所述第二控制电压端电连接，所述第十二晶体管的第二极与所述第二下拉节点电连接；
所述第十三晶体管的栅极与所述上拉节点电连接，所述第十三晶体管的第一极与所述第二下拉节点电连接，所述第十三晶体管的第二极与所述第三电压端电连接。
可选的，所述输入电路包括第十四晶体管；
所述第十四晶体管的栅极与所述输入端电连接，所述第十四晶体管的第一极与所述第二输入电压端电连接，所述第十四晶体管的第二极与所述上拉节点电连接；
所述输出电路包括第十五晶体管和第十六晶体管；
所述第十五晶体管的栅极与所述上拉节点电连接，所述第十五晶体管的第一极与所述输出时钟信号端电连接，所述第十五晶体管的第二极与所述驱动信号输出端电连接；
所述第十六晶体管的栅极与所述第一下拉节点电连接，所述第十六晶体管的第一极与所述驱动信号输出端电连接，所述第十六晶体管的第二极与所述第四电压端电连接；
所述输出复位电路包括第十七晶体管；
所述第十七晶体管的栅极与所述帧复位端电连接，所述第十七晶体管的第一极与所述驱动信号输出端电连接，所述第十七晶体管的第二极与所述第四电压端电连接；
所述初始复位电路包括第十八晶体管；
所述第十八晶体管的栅极与所述初始复位端电连接，所述第十八晶体管的第一极与所述上拉节点电连接，所述第十八晶体管的第二极与所述第四电压端电连接；
所述储能电路包括存储电容；
所述存储电容的第一端与所述上拉节点电连接，所述存储电容的第二端与所述驱动信号输出端电连接。
可选的，本公开至少一实施例所述的驱动电路还包括第二下拉节点；
所述输出电路还与所述第二下拉节点电连接，用于在所述第二下拉节点的电位的控制下，控制所述驱动信号输出端与第四电压端之间连通。
可选的，所述输出电路还包括第十九晶体管；
所述第十九晶体管的栅极与所述第二下拉节点电连接，所述第十九晶体管的第一极与所述驱动信号输出端电连接，所述第十九晶体管的第二极与所述第四电压端电连接。
在第二个方面中，本公开实施例提供一种驱动方法，应用于上述的驱动电路，所述驱动方法包括：
第一控制电路在第一控制信号的控制下，控制第一下拉节点与第一电压端之间连通，以使得所述第一下拉节点的电位为有效电压；
在所述第一下拉节点的电位为有效电压时，上拉节点复位电路控制上拉节点与第二电压端之间连通，以对所述上拉节点的电位进行复位。
可选的，所述驱动电路还包括第二下拉节点和第二控制电路；所述驱动方法还包括：
所述第二控制电路在第二控制信号的控制下，控制所述第二下拉节点与第五电压端之间连通，以使得所述第二下拉节点的电位为有效电压；
在所述第二下拉节点的电位为有效电压时，所述上拉节点复位电路控制所述上拉节点与第二电压端之间连通，以对所述上拉节点的电位进行复位。
在第三个方面中，本公开实施例还提供一种显示装置，包括上述的驱动电路。
可选的，所述显示装置包括驱动模组；
所述驱动模组包括多个级联的所述驱动电路；
所述驱动模组包括的最后一级驱动电路的第一输入电压端不接入相应的第一输入电压，所述最后一级驱动电路为伪驱动电路；
所述显示装置还包括设置于显示区域的多行多列像素电路，所述显示装置包括的最后一行像素电路为伪像素驱动电路；
所述最后一级驱动电路用于为所述最后一行像素电路提供相应的驱动信号，所述最后一行像素电路不发光。
附图说明
图1是本公开实施例所述的驱动电路的结构图；
图2是本公开至少一实施例所述的驱动电路的结构图；
图3是本公开至少一实施例所述的驱动电路的结构图；
图4是本公开至少一实施例所述的驱动电路的结构图；
图5是本公开至少一实施例所述的驱动电路的结构图；
图6是本公开至少一实施例所述的驱动电路的结构图；
图7是本公开至少一实施例所述的驱动电路的结构图；
图8是本公开至少一实施例所述的驱动电路的电路图；
图9是本公开如图8所示的驱动电路的至少一实施例的工作时序图；
图10是相邻两级驱动电路的工作时序图；
图11A是相关的驱动电路在信赖性测试下的仿真波形；
图11B是图8所示的驱动电路的至少一实施例在相同的信赖性条件下的仿真波形对比；
图12A是相关的驱动电路在信赖性测试后的M2的电流I1和M16的电流I16的波形图；
图12B是本公开图8所示的驱动电路的至少一实施例在信赖性测试后的M2的电流I2和M16的电流I16的波形图。
图13A是相关的驱动电路在信赖性测试后，PU的电位、PD1的电位和O1输出的驱动信号的波形图；
图13B是本公开图8所示的驱动电路的至少一实施例在信赖性测试后，PU的电位、PD1的电位和O1输出的驱动信号的波形图；
图14是本公开至少一实施例所述的驱动电路的电路图；
图15A是相关的驱动电路在信赖性测试下的仿真波形；
图15B是图8所示的驱动电路的至少一实施例在相同的信赖性条件下的仿真波形对比；
图16A是相关的驱动电路在信赖性测试后的M2的电流I1和M16的电流I16的波形图；
图16B是本公开图14所示的驱动电路的至少一实施例在信赖性测试后的M2的电流I2和M16的电流I16的波形图；
图17A是相关的驱动电路在信赖性测试后，PU的电位、PD1的电位和O1输出的驱动信号的波形图；
图17B是本公开图14所示的驱动电路的至少一实施例在信赖性测试后，PU的电位、PD1的电位和O1输出的驱动信号的波形图；
图18是本公开至少一实施例所述的驱动电路的电路图；
图19是本公开至少一实施例所述的驱动电路的结构图；
图20是本公开至少一实施例所述的驱动电路的电路图；
图21是本公开至少一实施例所述的驱动电路的电路图；
图22是本公开至少一实施例所述的驱动电路的电路图；
图23是STV0提供的初始复位信号的电位、第一起始信号STV1、第二起始信号STV2、第三起始信号STV3、第四起始信号STV4、第一时钟信号端K11提供的第一时钟信号、第二时钟信号端K12提供的第二时钟信号、第三时钟信号端K13提供的第三时钟信号、第四时钟信号端K14提供的第四时钟信号、第五时钟信号端K15提供的第五时钟信号、第六时钟信号端K16提供的第六时钟信号、第七时钟信号端K17提供的第七时钟信号、第八时钟信号端K18提供的第八时钟信号、第一输入电压端VSD接入的第一输入电压，第二输入电压端VDS提供的第二输入电压、第一控制电压端GCH提供的一控制电压、帧复位端GCL提供的帧复位信号和低电压端VGL提供的低电压信号的波形图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，本公开实施例所述的驱动电路包括第一下拉节点PD1、第一控制电路11和上拉节点复位电路12；
所述第一控制电路11分别与第一下拉节点PD1、第一控制端Tr1和第一电压端V1电连接，用于在所述第一控制端Tr1提供的第一控制信号的控制下，控制所述第一下拉节点PD1与所述第一电压端V1之间连通，以使得所述第一下拉节点PD1的电位为有效电压；
所述上拉节点复位电路12分别与所述第一下拉节点PD1、上拉节点PU和第二电压端V2电连接，用于在所述第一下拉节点PD1的电位为有效电压时，控制所述上拉节点PU与所述第二电压端V2之间连通，以对所述上拉节点PU的电位进行复位。
在本公开至少一实施例中，当所述上拉节点复位电路12包括的晶体管为n型晶体管时，所述有效电压可以为高电压，当所述上拉节点复位电路12包括的晶体管为p型晶体管时，所述有效电压可以为低电压。
在本公开至少一实施例中，所述第一电压端可以为第一控制电压端GCH，或者，所述第一电压端可以为高电压端，但不以此为限。
可选的，所述第二电压端V2可以为低电压端。
本公开实施例所述的驱动电路增设第一控制电路11，当所述第一控制信号的电位为有效电压时，第一控制电路11控制所述第一下拉节点PD1与第一电压端V1之间连通，以使得所述第一下拉节点PD1的电位为有效电压，所述上拉节点复位电路12在所述第一下拉节点PD1的电位的控制下，控制对所述上拉节点PU的电位进行复位，提升所述上拉节点复位电路12包括的晶体管的降噪能力，防止所述驱动电路误输出，使得所述驱动电路能够正确输出驱动信号。
在本公开至少一实施例中，所述第一控制端为复位端、第一下拉节点或 第一下拉控制节点。
如图2所示，本公开至少一实施例所述的驱动电路包括第一下拉节点PD1、第一控制电路11和上拉节点复位电路12；
所述第一控制电路11分别与第一下拉节点PD1、复位端R1和第一电压端V1电连接，用于在所述复位端R1提供的复位控制信号的控制下，控制所述第一下拉节点PD1与所述第一电压端V1之间连通，以使得所述第一下拉节点PD1的电位为有效电压；
所述上拉节点复位电路12分别与所述第一下拉节点PD1、上拉节点PU和第二电压端V2电连接，用于在所述第一下拉节点PD1的电位为有效电压时，控制所述上拉节点PU与所述第二电压端V2之间连通，以对所述上拉节点PU的电位进行复位。
在图2所示的驱动电路的至少一实施例中，所述第一控制端为所述复位端R1；在所述复位端R1提供高电压信号时，通过所述第一电压端V1提高信赖性后第一下拉节点PD1的电位，使得所述上拉节点复位电路12包括的晶体管的电流增大，所述驱动电路不会Multi(多)输出。
在本公开至少一实施例中，所述复位端可以为控制将第一输入电压写入上拉节点，以对所述上拉节点的电位进行复位的端子。
如图3所示，本公开至少一实施例所述的驱动电路包括第一下拉节点PD1、第一控制电路11和上拉节点复位电路12；
所述第一控制电路11分别与第一下拉节点PD1和第一电压端V1电连接，用于在所述第一下拉节点PD1的电位的控制下，控制所述第一下拉节点PD1与所述第一电压端V1之间连通，以使得所述第一下拉节点PD1的电位为有效电压；
所述上拉节点复位电路12分别与所述第一下拉节点PD1、上拉节点PU和第二电压端V2电连接，用于在所述第一下拉节点PD1的电位为有效电压时，控制所述上拉节点PU与所述第二电压端V2之间连通，以对所述上拉节点PU的电位进行复位。
在图3所示的驱动电路的至少一实施例中，所述第一控制端为所述第一下拉节点PD1；在所述第一下拉节点PD1的电位为高电压时，通过所述第一 电压端V1提高信赖性后第一下拉节点PD1的电位，使得所述上拉节点复位电路12包括的晶体管的电流增大，增强所述上拉节点复位电路12包括的晶体管的降噪能力，使得所述驱动电路不会Multi(多)输出。
如图4所示，本公开至少一实施例所述的驱动电路包括第一下拉节点PD1、第一控制电路11和上拉节点复位电路12；
所述第一控制电路11分别与第一下拉节点PD1、第一下拉控制节点PD_CN1和第一电压端V1电连接，用于在所述第一下拉控制节点PD_CN1的电位的控制下，控制所述第一下拉节点PD1与所述第一电压端V1之间连通，以使得所述第一下拉节点PD1的电位为有效电压；
所述上拉节点复位电路12分别与所述第一下拉节点PD1、上拉节点PU和第二电压端V2电连接，用于在所述第一下拉节点PD1的电位为有效电压时，控制所述上拉节点PU与所述第二电压端V2之间连通，以对所述上拉节点PU的电位进行复位。
在图4所示的驱动电路的至少一实施例中，所述第一控制端为所述第一下拉控制节点PD_CN1；在所述第一下拉控制节点PD_CN1的电位为高电压时，通过所述第一电压端V1提高信赖性后第一下拉节点PD1的电位，使得所述上拉节点复位电路12包括的晶体管的电流增大，增强所述上拉节点复位电路12包括的晶体管的降噪能力，使得所述驱动电路不会Multi(多)输出。
可选的，所述第一控制电路包括第一晶体管；
所述第一晶体管的栅极与所述第一控制端电连接，所述第一晶体管的第一极与所述第一下拉节点电连接，所述第一晶体管的第二极与所述第一电压端电连接；
所述上拉节点复位电路包括第二晶体管；
所述第二晶体管的栅极与所述第一下拉节点电连接，所述第二晶体管的第一极与所述上拉节点电连接，所述第二晶体管的第二极与所述第二电压端电连接。
本公开至少一实施例所述的驱动电路还可以包括复位电路；
所述复位电路分别与所述复位端、所述上拉节点和第一输入电压端电连接，用于在所述复位端提供的复位信号的控制下，控制将所述第一输入电压 端提供提供的第一输入电压写入所述上拉节点。
在本公开至少一实施例中，所述驱动电路还可以包括复位电路，复位电路在复位信号的控制下，将第一输入电压写入上拉节点。
本公开至少一实施例所述的驱动电路还可以包括第一下拉节点控制电路；
所述第一下拉节点控制电路分别与所述第一下拉节点、所述第一下拉控制节点、所述上拉节点、第一控制电压端和第三电压端电连接，用于在所述第一控制电压端提供的第一控制电压的控制下，控制所述第一控制电压端与所述第一下拉控制节点之间连通，在所述上拉节点的电位的控制下，控制所述第一下拉控制节点与所述第三电压端之间连通，并用于在所述第一下拉控制节点的电位的控制下，控制所述第一下拉节点与所述第一控制电压端之间连通，在所述上拉节点的电位的控制下，控制所述第一下拉节点与所述第三电压端之间连通；
所述第一电压端为所述第一控制电压端。
在具体实施时，所述驱动电路还可以包括第一下拉节点控制电路，所述第一下拉节点控制电路在上拉节点的电位和第一控制电压的控制下，控制第一下拉节点的电位和第一下拉控控制节点的电位。
在本公开至少一实施例中，所述第三电压端可以为低电压端；所述第二电压端与所述第三电压端可以为同一电压端，但不以此为限。
本公开至少一实施例所述的驱动电路还可以包括输出电路；
所述输出电路分别与所述上拉节点、第一下拉节点、输出时钟信号端、第四电压端和驱动信号输出端电连接，用于在所述上拉节点的电位的控制下，控制将所述输出时钟信号端提供的输出时钟信号写入所述驱动信号输出端，在所述第一下拉节点的电位的控制下，控制所述驱动信号输出端与所述第四电压端之间连通。
在本公开至少一实施例中，所述驱动电路还可以包括输出电路，输出电路在上拉节点的电位的控制下，将输出时钟信号写入驱动信号输出端，并在第一下拉节点的电位的控制下，控制所述驱动信号输出端与所述第四电压端之间连通，以对所述驱动信号输出端进行降噪。
可选的，所述第四电压端为低电压端，所述第二电压端、所述第三电压 端和所述第四电压端可以为同一电压端，但不以此为限。
本公开至少一实施例所述的驱动电路还可以包括第二下拉节点和第二控制电路；
所述第二控制电路分别与第二下拉节点、第二控制端和第五电压端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第二下拉节点与所述第五电压端之间连通，以使得所述第二下拉节点的电位为有效电压；
所述上拉节点复位电路还与所述第二下拉节点电连接，用于在所述第二下拉节点的电位为有效电压时，控制所述上拉节点与所述第二电压端之间连通，以对所述上拉节点的电位进行复位。
可选的，所述第五电压端可以为第二控制电压端或高电压端，但不以此为限。
本公开至少一实施例所述的驱动电路增设第二控制电路，当所述第一控制信号的电位为有效电压时，第二控制电路控制所述第二下拉节点与第五电压端之间连通，以使得所述第二下拉节点的电位为有效电压，所述上拉节点复位电路在所述第二下拉节点的电位的控制下，控制对所述上拉节点的电位进行复位，提升所述上拉节点复位电路包括的晶体管的降噪能力，防止所述驱动电路误输出，使得所述驱动电路能够正确输出驱动信号。
可选的，所述第二控制端为复位端、第二下拉节点或第二下拉控制节点，但不以此为限。
如图5所示，在图1所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括第二下拉节点PD2和第二控制电路51；
所述第二控制电路51分别与第二下拉节点PD2、第二控制端Tr2和第五电压端V5电连接，用于在所述第二控制端Tr2提供的第二控制信号的控制下，控制所述第二下拉节点PD2与所述第五电压端V5之间连通，以使得所述第二下拉节点PD2的电位为有效电压；
所述上拉节点复位电路12还与所述第二下拉节点PD2电连接，用于在所述第二下拉节点PD2的电位为有效电压时，控制所述上拉节点PU与所述 第二电压端V2之间连通，以对所述上拉节点PU的电位进行复位。
可选的，所述第二控制电路包括第三晶体管；所述上拉节点复位电路还包括第四晶体管；
所述第三晶体管的栅极与所述第二控制端电连接，所述第三晶体管的第一极与所述第二下拉节点电连接，所述第三晶体管的第二极与所述第五电压端电连接；
所述第四晶体管的栅极与所述第二下拉节点电连接，所述第四晶体管的第一极与所述上拉节点电连接，所述第四晶体管的第二极与所述第二电压端电连接。
如图6所示，在图5所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括第二下拉节点控制电路61；
所述第二下拉节点控制电路61分别与所述第二下拉节点PD2、所述第二下拉控制节点PD_CN2、所述上拉节点PU、第二控制电压端GCH2和第三电压端V3电连接，用于在所述第二控制电压端GCH2提供的第二控制电压的控制下，控制所述第二控制电压端GCH2与所述第二下拉控制节点PD_CN2之间连通，在所述上拉节点PU的电位的控制下，控制所述第二下拉控制节点PD_CN2与所述第三电压端V3之间连通，并用于在所述第二下拉控制节点PD_CN2的电位的控制下，控制所述第二下拉节点PD2与所述第二控制电压端GCH2之间连通，在所述上拉节点PU的电位的控制下，控制所述第二下拉节点PD2与所述第三电压端V3之间连通。
在图6所示的驱动电路的至少一实施例中，所述第五电压端为所述第二控制电压端GCH2，但不以此为限。
本公开如图6所述的驱动电路的至少一实施例在工作时，所述第二下拉节点控制电路61在上拉节点PU的电位和第二控制电压的控制下，控制第二下拉节点PD2的电位和第二下拉控制节点PD_CN2的电位。
本公开至少一实施例所述的驱动电路还可以包括输入电路、输出复位电路、初始复位电路和储能电路；
所述输入电路分别与输入端、第二输入电压端和所述上拉节点电连接，用于在所述输入端提供的输入信号的控制下，控制将所述第二输入电压端提 供的第二输入电压写入所述上拉节点；
所述输出复位电路分别与帧复位端、所述驱动信号输出端和第四电压端电连接，用于在所述帧复位端提供的帧复位信号的控制下，控制所述驱动信号输出端与所述第四电压端之间连通；
所述初始复位电路分别与初始复位端、所述上拉节点和所述第四电压端电连接，用于在所述初始复位端提供的初始复位信号的控制下，控制所述上拉节点与所述第四电压端之间连通；
所述储能电路的第一端与所述上拉节点电连接，所述储能电路的第二端与所述驱动信号输出端电连接，所述储能电路用于储存电能。
在本公开至少一实施例中，所述第四电压端可以为低电压端，所述第二电压端、所述第三电压端和所述第四电压端可以为同一电压端，但不以此为限。
本公开至少一实施例所述的驱动电路在工作时，输入电路在输入信号的控制下，将第二输入电压写入上拉节点，输出复位电路在帧复位信号的控制下，对所述驱动信号输出端提供的驱动信号进行复位，初始复位电路在初始复位信号的控制下，对所述上拉节点的电位进行复位。
如图7所示，在图1所述的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括复位电路71、第一下拉节点控制电路72、输出电路73、输入电路74、输出复位电路75、初始复位电路76和储能电路70；第二电压端为低电压端VGL，第一电压端为第一控制电压端GCH；
所述复位电路71分别与所述复位端R1、所述上拉节点PU和第一输入电压端VSD电连接，用于在所述复位端R1提供的复位信号的控制下，控制将所述第一输入电压端VSD提供提供的第一输入电压写入所述上拉节点PU；
所述第一下拉节点控制电路72分别与所述第一下拉节点PD1、所述第一下拉控制节点PD_CN1、所述上拉节点PU、第一控制电压端GCH和低电压端VGL电连接，用于在所述第一控制电压端GCH提供的第一控制电压的控制下，控制所述第一控制电压端GCH与所述第一下拉控制节点PD_CN1之间连通，在所述上拉节点PU的电位的控制下，控制所述第一下拉控制节点PD_CN1与所述低电压端VGL1之间连通，并用于在所述第一下拉控制节点 PD_CN1的电位的控制下，控制所述第一下拉节点PD1与所述第一控制电压端GCH之间连通，在所述上拉节点PU的电位的控制下，控制所述第一下拉节点PD1与所述低电压端VGL之间连通；
所述输出电路73分别与所述上拉节点PU、第一下拉节点PD1、输出时钟信号端K1、低电压端VGL和驱动信号输出端O1电连接，用于在所述上拉节点PU的电位的控制下，控制将所述输出时钟信号端K1提供的输出时钟信号写入所述驱动信号输出端O1，在所述第一下拉节点PD1的电位的控制下，控制所述驱动信号输出端O1与所述低电压端VGL之间连通；
所述输入电路74分别与输入端I1、第二输入电压端VDS和所述上拉节点PU电连接，用于在所述输入端I1提供的输入信号的控制下，控制将所述第二输入电压端VDS提供的第二输入电压写入所述上拉节点PU；
所述输出复位电路75分别与帧复位端GCL、所述驱动信号输出端O1和低电压端VGL电连接，用于在所述帧复位端GCL提供的帧复位信号的控制下，控制所述驱动信号输出端O1与所述低电压端VGL之间连通；
所述初始复位电路76分别与初始复位端STV0、所述上拉节点PU和所述低电压端VGL电连接，用于在所述初始复位端STV0提供的初始复位信号的控制下，控制所述上拉节点PU与所述低电压端VGL之间连通；
所述储能电路70的第一端与所述上拉节点PU电连接，所述储能电路70的第二端与所述驱动信号输出端O1电连接，所述储能电路70用于储存电能。
可选的，所述复位电路包括第五晶体管；
所述第五晶体管的栅极与所述复位端电连接，所述第五晶体管的第一极与所述上拉节点电连接，所述第五晶体管的第二极与所述第一输入电压端电连接。
可选的，所述第一下拉节点控制电路包括第六晶体管、第七晶体管、第八晶体管和第九晶体管；
所述第六晶体管的栅极与所述第六晶体管的第一极都与所述第一控制电压端电连接，所述第六晶体管的第二极与所述第一下拉控制节点电连接；
所述第七晶体管的栅极与所述上拉节点电连接，所述第七晶体管的第一极与所述第一下拉控制节点电连接，所述第七晶体管的第二极与所述第三电 压端电连接；
所述第八晶体管的栅极与所述第一下拉控制节点电连接，所述第八晶体管的第一极与所述第一控制电压端电连接，所述第八晶体管的第二极与所述第一下拉节点电连接；
所述第九晶体管的栅极与所述上拉节点电连接，所述第九晶体管的第一极与所述第一下拉节点电连接，所述第九晶体管的第二极与所述第三电压端电连接。
可选的，所述第二下拉节点控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
所述第十晶体管的栅极与所述第十晶体管的第一极都与所述第二控制电压端电连接，所述第十晶体管的第二极与所述第二下拉控制节点电连接；
所述第十一晶体管的栅极与所述上拉节点电连接，所述第十一晶体管的第一极与所述第二下拉控制节点电连接，所述第十一晶体管的第二极与所述第三电压端电连接；
所述第十二晶体管的栅极与所述第二下拉控制节点电连接，所述第十二晶体管的第一极与所述第二控制电压端电连接，所述第十二晶体管的第二极与所述第二下拉节点电连接；
所述第十三晶体管的栅极与所述上拉节点电连接，所述第十三晶体管的第一极与所述第二下拉节点电连接，所述第十晶体管的第二极与所述第三电压端电连接。
可选的，所述输入电路包括第十四晶体管；
所述第十四晶体管的栅极与所述输入端电连接，所述第十四晶体管的第一极与所述第二输入电压端电连接，所述第十四晶体管的第二极与所述上拉节点电连接；
所述输出电路包括第十五晶体管和第十六晶体管；
所述第十五晶体管的栅极与所述上拉节点电连接，所述第十五晶体管的第一极与所述输出时钟信号端电连接，所述第十五晶体管的第二极与所述驱动信号输出端电连接；
所述第十六晶体管的栅极与所述第一下拉节点电连接，所述第十六晶体 管的第一极与所述驱动信号输出端电连接，所述第十六晶体管的第二极与所述第四电压端电连接；
所述输出复位电路包括第十七晶体管；
所述第十七晶体管的栅极与所述帧复位端电连接，所述第十七晶体管的第一极与所述驱动信号输出端电连接，所述第十七晶体管的第二极与所述第四电压端电连接；
所述下拉节点复位电路包括第十八晶体管；
所述第十八晶体管的栅极与所述上拉节点电连接，所述第十八晶体管的第一极与所述第一下拉节点电连接，所述第十八晶体管的第二极与所述第三电压端电连接；
所述初始复位电路包括第十九晶体管；
所述第十九晶体管的栅极与所述初始复位端电连接，所述第十九晶体管的第一极与所述上拉节点电连接，所述第十九晶体管的第二极与所述第四电压端电连接；
所述储能电路包括存储电容；
所述存储电容的第一端与所述上拉节点电连接，所述存储电容的第二端与所述驱动信号输出端电连接。
如图8所示，在图7所示的驱动电路的至少一实施例的基础上，所述第一控制电路11包括第一晶体管M1；第一控制端为复位端R1电连接，需要说明的是，这里的复位端R1指的是：当包括多个级联在一起的驱动电路时，如果本级驱动电路是第n级，在对于正向扫描而言，则复位端连接的是n+i级驱动电路的输出端，这里i可以是大于等于1的正整数，当然，对于驱动电路中级联输出端和栅极扫描输出端分开输出的驱动电路而言，复位端可以是和级联输出端连接的信号端；
所述第一晶体管M1的栅极与复位端R1电连接，所述第一晶体管M1的源极与所述第一下拉节点PD1电连接，所述第一晶体管M1的漏极与第一控制电压端GCH电连接；
所述上拉节点复位电路12包括第二晶体管M2；
所述第二晶体管M2的栅极与所述第一下拉节点PD1电连接，所述第二 晶体管M2的源极与所述上拉节点PU电连接，所述第二晶体管M2的漏极与所述低电压端VGL电连接；
所述复位电路71包括第五晶体管M5；
所述第五晶体管M5的栅极与所述复位端R1电连接，所述第五晶体管M5的源极与所述上拉节点PU电连接，所述第五晶体管M5的漏极与所述第一输入电压端VSD电连接；
所述第一下拉节点控制电路72包括第六晶体管M6、第七晶体管M7、第八晶体管M8和第九晶体管M9；
所述第六晶体管M6的栅极与所述第六晶体管M6的源极都与所述第一控制电压端GCH电连接，所述第六晶体管M6的漏极与所述第一下拉控制节点PD_CN1电连接；
所述第七晶体管M7的栅极与所述上拉节点PU电连接，所述第七晶体管M7的源极与所述第一下拉控制节点PD_CN1电连接，所述第七晶体管M7的漏极与所述低电压端VGL电连接；
所述第八晶体管M8的栅极与所述第一下拉控制节点PD_CN1电连接，所述第八晶体管M8的源极与所述第一控制电压端GCH电连接，所述第八晶体管M8的漏极与所述第一下拉节点PD1电连接；
所述第九晶体管M9的栅极与所述上拉节点PU电连接，所述第九晶体管M9的源极与所述第一下拉节点PD1电连接，所述第九晶体管M9的漏极与所述低电压端VGL电连接；
所述输入电路74包括第十四晶体管M14；
所述第十四晶体管M14的栅极与所述输入端I1电连接，所述第十四晶体管M14的源极与所述第二输入电压端VDS电连接，所述第十四晶体管M14的漏极与所述上拉节点PU电连接；
所述输出电路73包括第十五晶体管M15和第十六晶体管M16；
所述第十五晶体管M15的栅极与所述上拉节点PU电连接，所述第十五晶体管M15的源极与所述输出时钟信号端K1电连接，所述第十五晶体管M15的漏极与所述驱动信号输出端O1电连接；
所述第十六晶体管M16的栅极与所述第一下拉节点PD1电连接，所述第 十六晶体管M16的源极与所述驱动信号输出端O1电连接，所述第十六晶体管M16的漏极与所述低电压端VGL电连接；
所述输出复位电路75包括第十七晶体管M17；
所述第十七晶体管M17的栅极与所述帧复位端GCL电连接，所述第十七晶体管M17的源极与所述驱动信号输出端O1电连接，所述第十七晶体管M17的漏极与所述低电压端VGL电连接；
所述初始复位电路76包括第十八晶体管M18；
所述第十八晶体管M18的栅极与所述初始复位端STV0电连接，所述第十八晶体管M18的源极与所述上拉节点PU电连接，所述第十八晶体管M18的漏极与所述低电压端VGL电连接；
所述储能电路70包括存储电容C1；
所述存储电容C1的第一端与所述上拉节点PU电连接，所述存储电容C1的第二端与所述驱动信号输出端O1电连接。
在图8所示的驱动电路的至少一实施例的基础上，所有的晶体管都为n型薄膜晶体管，但不此为限。
本公开如图8所示的驱动电路的至少一实施例能够进行双向扫描；
当VDS提供高电压信号，VSD提供低电压信号时，所述驱动电路能够进行正向扫描；
当VDS提供低电压信号，VSD提供高电压信号时，所述驱动电路能够进行反向扫描。
如图9所示，本公开图8所示的驱动电路的至少一实施例在工作时，以VDS提供高电压信号，VSD提供低电压信号为例进行说明；显示周期可以包括先后设置的输入阶段S1、输出阶段S2和复位阶段S3；
在所述输入阶段S1，K1提供低电压信号，I1提供高电压信号，R1提供低电压信号，GCH提供高电压信号，M1关断，M14打开，将VDS提供的高电压信号写入上拉节点PU，使得PU的电位一阶抬升，M15打开，O1输出低电压信号；
在所述输入阶段S1，M6和M7打开，以控制PD_CN1的电位为低电压，M8关断，M9打开，以控制PD1的电位为低电压；
在所述输出阶段S2，K1提供高电压信号，I1提供低电压信号，R1提供高电压信号，GCH提供高电压信号，PU的电位由于C1的耦合作用二阶抬升，M15继续打开，O1输出高电压信号，并为相邻下一级驱动电路提供输入信号；
在所述复位阶段S3，K1提供低电压信号，I1提供低电压信号，R1提供高电压信号，GCH提供高电压信号，M5打开，以对PU的电位进行复位，拉低PU的电位；
在所述复位阶段S3，M6打开，M7关断，PD_CN1的电位为高电压，M8打开，M9关断，PD1的电位为高电压，M2和M16打开，使得PU与VGL之间连通，并使得O1输出低电压信号。
在图9中，标号为S0的为输出截止保持阶段，在输出截止保持阶段S0，O1持续输出低电压信号。
本公开图8所示的驱动电路的至少一实施例在工作时，在复位阶段S3，R1提供高电压信号，GCH提供高电压信号，M1打开，以将PD1的电位拉高。
图10是相邻两级驱动电路的工作时序图，在图10中，K11为第一级驱动电路接入的时钟信号，K12为第二级驱动电路接入的时钟信号，PU1为第一级驱动电路中的上拉节点，I11为第一级驱动电路中的输入端接入的输入信号，O11为第一级驱动电路的动信号输出端；
K12为第二级驱动电路接入的时钟信号，PU2为第二级驱动电路中的上拉节点，I12为第二级驱动电路中的输入端接入的输入信号，O12为第二级驱动电路的驱动信号输出端，R11为第一级驱动电路的复位端接入的复位信号。
本公开图8所示的驱动电路的至少一实施例增设了第一晶体管M1，能够在复位信号到来时打开M1，通过GCH提供的高电平进一步拉高PD1的电位。图11A是相关的驱动电路在信赖性测试下的仿真波形，图11B是图8所示的驱动电路的至少一实施例在相同的信赖性条件下的仿真波形对比。
本公开图8所示的驱动电路的至少一实施例在工作时，PD1的高电位由相关技术中的1V提高至9V，在复位信号到来后，PU的电位和O1输出的驱动信号的噪声减小。
图12A是相关的驱动电路在信赖性测试后的M2的电流I1和M16的电流I16的波形图，图12B是本公开图8所示的驱动电路的至少一实施例在信 赖性测试后的M2的电流I2和M16的电流I16的波形图。
相关的驱动电路在信赖性测试后，I2和I16很小，而本公开如图8所示的驱动电路的至少一实施例在复位信号到来后的PD1的电位为高电压的时间内，M2有明显大电流，M2的降噪能力增强。
图13A是相关的驱动电路在信赖性测试后，PU的电位、PD1的电位和O1输出的驱动信号的波形图。图13B是本公开图8所示的驱动电路的至少一实施例在信赖性测试后，PU的电位、PD1的电位和O1输出的驱动信号的波形图。
在本公开至少一实施例中，所述信赖性测试可以为高温高湿信赖性测试；例如，所述信赖性测试可以为大于等于60℃时的高温信赖性测试；可选的，所述信赖性测试可以为85℃时的高温信赖性测试；但不以此为限。
在信赖性测试后，在M14的阈值电压负偏增大相同程度时，相关的驱动电路输出的驱动信号出现Multi(多)输出，而本公开图8所示的驱动电路的至少一实施例能够正确输出驱动信号，并且在复位信号带来后仍保持很小的噪声。
在本公开至少一实施例中，当相关的驱动电路正常输出时，在一显示周期(所述一显示周期例如可以为一帧时间)内，相关的驱动电路输出的驱动信号仅存在一个向上的脉冲；然而，当相关的驱动电路输出的驱动信号出现多输出时，在一显示周期中，相关的驱动电路输出的驱动信号具有多个向上的脉冲。如图13A所示，在一显示周期内，O1输出的驱动信号具有多个向上的脉冲，以出现多输出现象。
图14所示的驱动电路的至少一实施例与图8所示的驱动电路的至少一实施例的区别仅在于：M1的栅极与第一下拉节点PD1电连接。
图14所示的驱动电路的至少一实施例在工作时，当PU的电位为低电压，PD1的电位为高电压时，M1打开，进一步通过GCH提供的第一控制电压拉升PD1的电位。
本公开图14所示的驱动电路的至少一实施例增设了第一晶体管M1，能够在PD1的电位为高电压时打开M1，通过GCH提供的高电平进一步拉高PD1的电位。
图15A是相关的驱动电路在信赖性测试下的仿真波形，图15B是图8所示的驱动电路的至少一实施例在相同的信赖性条件下的仿真波形对比。
本公开图14所示的驱动电路的至少一实施例在工作时，PD1的高电位由相关技术中的1V提高至11.5V，在复位信号到来后，PU的电位和O1输出的驱动信号的噪声减小。
图16A是相关的驱动电路在信赖性测试后的M2的电流I1和M16的电流I16的波形图，图16B是本公开图14所示的驱动电路的至少一实施例在信赖性测试后的M2的电流I2和M16的电流I16的波形图。
相关的驱动电路在信赖性测试后，I2和I16很小，而本公开如图14所示的驱动电路的至少一实施例在复位信号到来后的PD1的电位为高电压的时间内，M2有明显大电流，M2的降噪能力增强。
图17A是相关的驱动电路在信赖性测试后，PU的电位、PD1的电位和O1输出的驱动信号的波形图。图17B是本公开图14所示的驱动电路的至少一实施例在信赖性测试后，PU的电位、PD1的电位和O1输出的驱动信号的波形图。
在信赖性测试后，在M14的阈值电压负偏增大相同程度时，相关的驱动电路输出的驱动信号出现Multi(多)输出，而本公开图14所示的驱动电路的至少一实施例能够正确输出驱动信号，并且在复位信号带来后仍保持很小的噪声。
图18所示的驱动电路的至少一实施例与图11所示的驱动电路的至少一实施例的区别仅在于：M1的栅极与第一下拉控制节点PD_CN1电连接。
图18所示的驱动电路的至少一实施例在工作时，当PU的电位为低电压，PD_CN1的电位为高电压时，M1打开，通过GCH提供的第一控制电压拉升PD1的电位。
图18所示的驱动电路的至少一实施例在工作时，PD1的电位和PD_CN1的电位同时为高电压，但是PD_CN1的高电压值大于PD1的高电压值，因此相较于图14所示的驱动电路的至少一实施例，M1的尺寸可以设置为较小，由于管子尺寸较小，所以可以进一步实现显示面板窄边框的技术效果。
在本公开图18所示的至少一实施例中，仅设置一个下拉节点(第一下拉 节点PD1)，不仅能够减少采用的晶体管的数目，利于实现显示面板的窄边框，并且能够在仅采用一个下拉节点的前提下，通过第一控制电路，控制当所述第一控制信号的电位为有效电压时，所述第一下拉节点的电位为有效电压，所述上拉节点复位电路能够在所述第一下拉节点的电位的控制下，控制对所述上拉节点的电位进行复位，提升所述上拉节点复位电路包括的晶体管的降噪能力，防止所述驱动电路误输出，使得所述驱动电路能够正确输出驱动信号。如图19所示，在图6所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括复位电路71、第一下拉节点控制电路72、输出电路73、输入电路74、输出复位电路75、初始复位电路76和储能电路70；第二电压端为低电压端VGL，第一电压端为第一控制电压端GCH；
所述复位电路71分别与所述复位端R1、所述上拉节点PU和第一输入电压端VSD电连接，用于在所述复位端R1提供的复位信号的控制下，控制将所述第一输入电压端VSD提供提供的第一输入电压写入所述上拉节点PU；
所述第一下拉节点控制电路72分别与所述第一下拉节点PD1、所述第一下拉控制节点PD_CN1、所述上拉节点PU、第一控制电压端GCH和低电压端VGL电连接，用于在所述第一控制电压端GCH提供的第一控制电压的控制下，控制所述第一控制电压端GCH与所述第一下拉控制节点PD_CN1之间连通，在所述上拉节点PU的电位的控制下，控制所述第一下拉控制节点PD_CN1与所述低电压端VGL1之间连通，并用于在所述第一下拉控制节点PD_CN1的电位的控制下，控制所述第一下拉节点PD1与所述第一控制电压端GCH之间连通，在所述上拉节点PU的电位的控制下，控制所述第一下拉节点PD1与所述低电压端VGL之间连通；
所述输出电路73分别与所述上拉节点PU、第一下拉节点PD1、第二下拉节点PD2、输出时钟信号端K1、低电压端VGL和驱动信号输出端O1电连接，用于在所述上拉节点PU的电位的控制下，控制将所述输出时钟信号端K1提供的输出时钟信号写入所述驱动信号输出端O1，在所述第一下拉节点PD1的电位的控制下，控制所述驱动信号输出端O1与所述低电压端VGL之间连通，在所述第二下拉节点PD2的电位的控制下，控制所述驱动信号输出端O1与所述低电压端VGL之间连通；
所述输入电路74分别与输入端I1、第二输入电压端VDS和所述上拉节点PU电连接，用于在所述输入端I1提供的输入信号的控制下，控制将所述第二输入电压端VDS提供的第二输入电压写入所述上拉节点PU；
所述输出复位电路75分别与帧复位端GCL、所述驱动信号输出端O1和低电压端VGL电连接，用于在所述帧复位端GCL提供的帧复位信号的控制下，控制所述驱动信号输出端O1与所述低电压端VGL之间连通；
所述初始复位电路76分别与初始复位端STV0、所述上拉节点PU和所述低电压端VGL电连接，用于在所述初始复位端STV0提供的初始复位信号的控制下，控制所述上拉节点PU与所述低电压端VGL之间连通；
所述储能电路70的第一端与所述上拉节点PU电连接，所述储能电路70的第二端与所述驱动信号输出端O1电连接，所述储能电路70用于储存电能。
如图20所示，在本公开图8所示的驱动电路的至少一实施例的基础上，所述第一控制电路11包括第一晶体管M1；第一控制端和第二控制端都为复位端R1；
所述第一晶体管M1的栅极与复位端R1电连接，所述第一晶体管M1的源极与所述第一下拉节点PD1电连接，所述第一晶体管M1的漏极与第一控制电压端GCH电连接；
所述上拉节点复位电路12包括第二晶体管M2；
所述第二晶体管M2的栅极与所述第一下拉节点PD1电连接，所述第二晶体管M2的源极与所述上拉节点PU电连接，所述第二晶体管M2的漏极与所述低电压端VGL电连接；
所述第二控制电路51包括第三晶体管M3；所述上拉节点复位电路12还包括第四晶体管M4；
所述第三晶体管M3的栅极与所述复位端R1电连接，所述第三晶体管M3的源极与第二下拉节点PD2电连接，所述第三晶体管M3的漏极与所述第二控制电压端GCH2电连接；
所述第四晶体管M4的栅极与所述第二下拉节点PD2电连接，所述第四晶体管M4的源极与所述上拉节点PU电连接，所述第四晶体管M4的漏极与所述低电压端VGL电连接；
所述复位电路71包括第五晶体管M5；
所述第五晶体管M5的栅极与所述复位端R1电连接，所述第五晶体管M5的源极与所述上拉节点PU电连接，所述第五晶体管M5的漏极与所述第一输入电压端VSD电连接；
所述第一下拉节点控制电路72包括第六晶体管M6、第七晶体管M7、第八晶体管M8和第九晶体管M9；
所述第六晶体管M6的栅极与所述第六晶体管M6的源极都与所述第一控制电压端GCH电连接，所述第六晶体管M6的漏极与所述第一下拉控制节点PD_CN1电连接；
所述第七晶体管M7的栅极与所述上拉节点PU电连接，所述第七晶体管M7的源极与所述第一下拉控制节点PD_CN1电连接，所述第七晶体管M7的漏极与所述低电压端VGL电连接；
所述第八晶体管M8的栅极与所述第一下拉控制节点PD_CN1电连接，所述第八晶体管M8的源极与所述第一控制电压端GCH电连接，所述第八晶体管M8的漏极与所述第一下拉节点PD1电连接；
所述第九晶体管M9的栅极与所述上拉节点PU电连接，所述第九晶体管M9的源极与所述第一下拉节点PD1电连接，所述第九晶体管M9的漏极与所述低电压端VGL电连接；
所述第二下拉节点控制电路61包括第十晶体管M10、第十一晶体管M11、第十二晶体管M12和第十三晶体管M13；
所述第十晶体管M10的栅极与所述第十晶体管M10的源极都与所述第二控制电压端GCH2电连接，所述第十晶体管M10的漏极与第二下拉控制节点PD_CN2电连接；
所述第十一晶体管M11的栅极与所述上拉节点PU电连接，所述第十一晶体管M11的源极与所述第二下拉控制节点PD_CN2电连接，所述第十一晶体管M11的漏极与所述低电压端VGL电连接；
所述第十二晶体管M12的栅极与所述第二下拉控制节点PD_CN2电连接，所述第十二晶体管M12的源极与所述第二控制电压端GCH2电连接，所述第十二晶体管M12的漏极与所述第二下拉节点PD2电连接；
所述第十三晶体管M13的栅极与所述上拉节点PU电连接，所述第十三晶体管M13的源极与所述第二下拉节点PD2电连接，所述第十晶体管的第二极与所述第三电压端电连接；
所述输入电路74包括第十四晶体管M14；
所述第十四晶体管M14的栅极与所述输入端I1电连接，所述第十四晶体管M14的源极与所述第二输入电压端VDS电连接，所述第十四晶体管M14的漏极与所述上拉节点PU电连接；
所述输出电路73包括第十五晶体管M15和第十六晶体管M16；
所述第十五晶体管M15的栅极与所述上拉节点PU电连接，所述第十五晶体管M15的源极与所述输出时钟信号端K1电连接，所述第十五晶体管M15的漏极与所述驱动信号输出端O1电连接；
所述第十六晶体管M16的栅极与所述第一下拉节点PD1电连接，所述第十六晶体管M16的源极与所述驱动信号输出端O1电连接，所述第十六晶体管M16的漏极与所述低电压端VGL电连接；
所述输出复位电路75包括第十七晶体管M17；
所述第十七晶体管M17的栅极与所述帧复位端GCL电连接，所述第十七晶体管M17的源极与所述驱动信号输出端O1电连接，所述第十七晶体管M17的漏极与所述低电压端VGL电连接；
所述初始复位电路76包括第十八晶体管M18；
所述第十八晶体管M18的栅极与所述初始复位端STV0电连接，所述第十八晶体管M18的源极与所述上拉节点PU电连接，所述第十八晶体管M18的漏极与所述低电压端VGL电连接；
所述储能电路70包括存储电容C1；
所述存储电容C1的第一端与所述上拉节点PU电连接，所述存储电容C1的第二端与所述驱动信号输出端O1电连接。
所述输出电路73还包括第十九晶体管M19；
所述第十九晶体管M19的栅极与所述第二下拉节点PD2电连接，所述第十九晶体管M19的源极与所述驱动信号输出端O1电连接，所述第十九晶体管M19的漏极与所述低电压端VGL电连接。
在图20所示的驱动电路的至少一实施例中，所有晶体管可以都为n型薄膜晶体管，但不以此为限。
本公开如图20所示的驱动电路的至少一实施例能够进行双向扫描；
当VDS提供高电压信号，VSD提供低电压信号时，所述驱动电路能够进行正向扫描；
当VDS提供低电压信号，VSD提供高电压信号时，所述驱动电路能够进行反向扫描。
本公开图14所示的驱动电路的至少一实施例采用两个下拉节点：第一下拉节点PD1和第二下拉节点PD2；
每隔若干显示周期(例如每隔2秒-3秒)，GCH提供的第一控制电压的电位、GCH2提供的第二控制电压的电位交替为高电压；
当所述第一控制电压的电位为高电压时，所述第二控制电压的电位可以为低电压；当所述第二控制电压的电位为低电压时，所述第一控制电压的电位可以为高电压；但不以此为限。
本公开图20所示的驱动电路的至少一实施例在工作时，当第一控制电压的电位为高电压时，在显示周期包括的输出阶段，以及，设置于所述输出阶段之后的输出截止保持阶段，PD1的电位为高电压；
当第二控制电压的电位为高电压时，在显示周期包括的复位阶段，以及，设置于所述复位阶段之后的输出截止保持阶段，PD2的电位为高电压；
PD1控制的晶体管、PD2控制的晶体管交替打开，从而改善该晶体管的阈值电压漂移现象。
本公开图20所示的驱动电路的至少一实施例在工作时，当第一控制电压的电位为高电压时，在所述显示周期包括的复位阶段，R1提供高电压信号，M1打开，以将PD1的电位拉升；
当第二控制电压的电位为高电压时，在所述显示周期包括的复位阶段，R1提供高电压信号，M3打开，以将PD2的电位拉升。
图21所示的驱动电路的至少一实施例与图20所示的驱动电路的至少一实施例的区别仅在于：M1的栅极与第一下拉节点PD1电连接，M3的栅极与第二下拉节点PD2电连接。
图21所示的驱动电路的至少一实施例在工作时，当第一控制电压为高电压时，在PU的电位为低电压，PD1的电位为高电压时，M1打开，进一步通过GCH提供的第一控制电压拉升PD1的电位；
当第二控制电压为高电压时，在PU的电位为低电压，PD2的电位为高电压时，M3打开，进一步通过GCH2提供的第二控制电压拉升PD1的电位。
图22所示的驱动电路的至少一实施例与图20所示的驱动电路的至少一实施例的区别仅在于：M1的栅极与第一下拉控制节点PD_CN1电连接，M2的栅极与第二下拉控制节点PD_CN2电连接。
图22所示的驱动电路的至少一实施例在工作时，当第一控制电压为高电压时，在PU的电位为低电压，PD_CN1的电位为高电压时，M1打开，通过GCH提供的第一控制电压拉升PD1的电位；
当第二控制电压为高电压时，在PU的电位为低电压，PD_CN2的电位为高电压时，M3打开，通过GCH2提供的第二控制电压拉升PD2的电位。
图22所示的驱动电路的至少一实施例在工作时，当第一控制电压为高电压时，PD1的电位和PD_CN1的电位同时为高电压，但是PD_CN1的高电压值大于PD1的高电压值，因此相较于图20所示的驱动电路的至少一实施例，M1的尺寸可以设置为较小；
当第二控制电压为高电压时，PD2的电位和PD_CN2的电位同时为高电压，但是PD_CN2的高电压值大于PD2的高电压值，因此相较于图20所示的驱动电路的至少一实施例，M3的尺寸可以设置为较小。
在相关技术中，在对驱动电路进行高温高湿信赖性测试时，会出现抖动横纹不良的现象。在信赖性测试后，M14的阈值电压负向漂移，M14的漏电流增大(直接因素)，并且M2和M16的降噪能力下降(间接因素)，共同导致本级驱动电路的上拉节点和驱动信号端的噪声增大，驱动输出信号端的噪声会导致下一级驱动电路的上拉节点具有更大的噪声，因此下一级驱动电路的驱动信号输出端的噪声更严重，因此噪声逐级积累，导致设置于较后的驱动电路的驱动信号输出端严重Multi(多)输出。M14的阈值电压的负漂程度越严重，噪声积累越快导致驱动信号输出端的多输出。针对2.0寸模拟结果，当M14的阈值电压漂移到-0.6V时，会产生多输出，当M14的阈值电压大于 -0.5V时，不会产生多输出。在信赖性测试后切换进行反向扫描，在85摄氏度下，M14的阈值电压漂移严重，在反向扫描时，M14作为复位单元漏电流增大，导致上拉节点的电位无二阶抬升，驱动信号输出端无法正常输出。在70摄氏度下，M14的漂移较小，M14的漏电流较小，因此上拉节点的电位能够二阶抬升，驱动信号输出端能够正常输出。
在相关技术中，在进行正向扫描时，由于扫描尾行，不会通过M5对上拉节点的电位进行复位(M5的漏极不接入相应的第一输入电压)，驱动信号输出端输出完整的时钟信号，直至帧后复位。而中间行受复位以及M14的漏电噪声影响，驱动信号输出端Multi输出周期没有明显规律。
在对相关技术进行改进时，初步怀疑是由于信赖性后PD1的电位下降，M2的特性漂移，对上拉节点PU的降噪能力降低，PU的电位出现Multi波形，造成抖动横纹。但是其他型号产品在信赖性测试后PD1的电位也降至1V-2V，实测2.0寸衍生向信赖性后M2的阈值电压为14V，也为信赖性后正常水平，通过模拟说明PD1的电位的降低和M2的阈值电压漂移不会导致驱动信号输出端严重Multi输出。
在相关技术中，在信赖性测试后，当晶体管的特性正常漂移(M1的阈值电压为0.29V，M8的阈值电压为6.92V，M2的阈值电压为14.79V)时，PU的电位、PD1的电位，和驱动信号输出端输出的驱动信号的波形；PD1的高电压值为1.33V，PU的低电压值为-11V，并且PU的电位为低电压时，会多次向上波动1.7V，但是驱动信号能够正常输出。
在信赖性测试后，加重M2的特性漂移(将M2的阈值电压增大至25V)时，PU的电位、PD1的电位，和驱动信号输出端输出的驱动信号的波形；PU的低电压值为-11V，并且PU的电位为低电压时，会多次向上波动2V，但是驱动信号能够正常输出。
在信赖性测试后，M2的阈值电压的漂移之后导致PU的电位一定程度上波动，但是PU的电位仍为低电压，不会导致驱动信号误输出，PU的电位的抬升有其他原因。
在相关技术中，根据高温闪屏不良分析，双向扫描由于M14在信赖性后阈值电压负向漂移，导致漏电流增大，PU的噪声增大，搭配单下拉节点易出 现闪屏现象。在增大信赖性测试后M14的负向漂移程度(M14的阈值电压为-3V，其他晶体管的阈值电压为信赖性测试后正常水平)，模拟结果证明PU的电位和驱动信号端确实会产生严重Multi输出，导致显示异常。
基于以上测试，本公开实施例增设第一控制电路11，当所述第一控制信号的电位为有效电压时，第一控制电路11控制所述第一下拉节点PD1与第一电压端V1之间连通，以使得所述第一下拉节点PD1的电位为有效电压，所述上拉节点复位电路12在所述第一下拉节点PD1的电位的控制下，控制对所述上拉节点PU的电位进行复位，提升所述上拉节点复位电路12包括的晶体管的降噪能力，防止所述驱动电路误输出，使得所述驱动电路能够正确输出驱动信号。
本公开实施例所述的驱动方法，应用于上述的驱动电路，所述驱动方法包括：
第一控制电路在第一控制信号的控制下，控制第一下拉节点与第一电压端之间连通，以使得所述第一下拉节点的电位为有效电压；
在所述第一下拉节点的电位为有效电压时，上拉节点复位电路控制上拉节点与第二电压端之间连通，以对所述上拉节点的电位进行复位。
在本公开至少一实施例中，所述驱动电路还包括第二下拉节点和第二控制电路；所述驱动方法还包括：
所述第二控制电路在第二控制信号的控制下，控制所述第二下拉节点与第四电压端之间连通，以使得所述第二下拉节点的电位为有效电压；
在所述第二下拉节点的电位为有效电压时，所述上拉节点复位电路控制所述上拉节点与第二电压端之间连通，以对所述上拉节点的电位进行复位。
本公开实施例所述的显示装置包括上述的驱动电路。
本公开至少一实施例所述的显示装置包括驱动模组；
所述驱动模组包括多个级联的所述驱动电路；
所述驱动模组包括的最后一级驱动电路的第一输入电压端不接入相应的第一输入电压，所述最后一级驱动电路为伪驱动电路；
所述显示装置还包括设置于显示区域的多行多列像素电路，所述显示装置包括的最后一行像素电路可以为伪像素驱动电路；
所述最后一级驱动电路用于为所述最后一行像素电路提供相应的驱动信号，所述最后一行像素电路不发光。
在本公开至少一实施例所述的显示装置中，相互级联的多级驱动电路组成驱动模组；
在对所述驱动模组进行正向扫描时，最后一级驱动电路包括的复位电路不接入相应的第一输入电压，因此在复位阶段，所述复位电路包括的晶体管不会导通，不会对最后一级驱动电路中的上拉节点的电位进行复位，所述最后一级驱动电路可以为dummy(伪)驱动电路，伪驱动电路可以为dummy像素电路提供驱动信号，dummy像素电路不用于显示。
在具体实施时，所述显示装置可以包括位于显示面板左侧边的第一驱动模组和位于显示面板右侧边的第二驱动模组；
所述第一驱动模组包括相互级联的多级驱动电路；
所述第二驱动模组包括相互级联的多级驱动电路；
所述第二驱动模组分别与第二时钟信号端K12、第四时钟信号端K14、第六时钟信号端K16和第八时钟信号端K18电连接；
所述第一驱动模组分别与第一时钟信号端K11、第三时钟信号端K13、第五时钟信号端K15和第七时钟信号端K17电连接；
图23是STV0提供的初始复位信号的电位、第一起始信号STV1、第二起始信号STV2、第三起始信号STV3、第四起始信号STV4、第一时钟信号端K11提供的第一时钟信号、第二时钟信号端K12提供的第二时钟信号、第三时钟信号端K13提供的第三时钟信号、第四时钟信号端K14提供的第四时钟信号、第五时钟信号端K15提供的第五时钟信号、第六时钟信号端K16提供的第六时钟信号、第七时钟信号端K17提供的第七时钟信号、第八时钟信号端K18提供的第八时钟信号、第一输入电压端VSD接入的第一输入电压，第二输入电压端VDS提供的第二输入电压、第一控制电压端GCH提供的一控制电压、帧复位端GCL提供的帧复位信号和低电压端VGL提供的低电压信号的波形图。
在图23中，SN为第N帧时间，SN+1为第N+1帧时间，B0为SN与SN+1之间的空白时间段。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (21)

  1. 一种驱动电路，包括第一下拉节点、第一控制电路和上拉节点复位电路；
    所述第一控制电路分别与第一下拉节点、第一控制端和第一电压端电连接，用于在所述第一控制端提供的第一控制信号的控制下，控制所述第一下拉节点与所述第一电压端之间连通，以使得所述第一下拉节点的电位为有效电压；
    所述上拉节点复位电路分别与所述第一下拉节点、上拉节点和第二电压端电连接，用于在所述第一下拉节点的电位为有效电压时，控制所述上拉节点与所述第二电压端之间连通，以对所述上拉节点的电位进行复位。
  2. 如权利要求1所述的驱动电路，其中，所述第一控制端为复位端、第一下拉节点或第一下拉控制节点。
  3. 如权利要求1所述的驱动电路，其中，所述第一控制电路包括第一晶体管；
    所述第一晶体管的栅极与所述第一控制端电连接，所述第一晶体管的第一极与所述第一下拉节点电连接，所述第一晶体管的第二极与所述第一电压端电连接；
    所述上拉节点复位电路包括第二晶体管；
    所述第二晶体管的栅极与所述第一下拉节点电连接，所述第二晶体管的第一极与所述上拉节点电连接，所述第二晶体管的第二极与所述第二电压端电连接。
  4. 如权利要求2所述的驱动电路，其中，还包括复位电路；
    所述复位电路分别与所述复位端、所述上拉节点和第一输入电压电连接，用于在所述复位端提供的复位信号的控制下，控制将所述第一输入电压端提供的第一输入电压写入所述上拉节点。
  5. 如权利要求2所述的驱动电路，其中，还包括第一下拉节点控制电路；
    所述第一下拉节点控制电路分别与所述第一下拉节点、所述第一下拉控制节点、所述上拉节点、第一控制电压端和第三电压端电连接，用于在所述 第一控制电压端提供的第一控制电压的控制下，控制所述第一控制电压端与所述第一下拉控制节点之间连通，在所述上拉节点的电位的控制下，控制所述第一下拉控制节点与所述第三电压端之间连通，并用于在所述第一下拉控制节点的电位的控制下，控制所述第一下拉节点与所述第一控制电压端之间连通，在所述上拉节点的电位的控制下，控制所述第一下拉节点与所述第三电压端之间连通；
    所述第一电压端为所述第一控制电压端。
  6. 如权利要求5所述的驱动电路，其中，还包括输出电路；
    所述输出电路分别与所述上拉节点、第一下拉节点、输出时钟信号端、第四电压端和驱动信号输出端电连接，用于在所述上拉节点的电位的控制下，控制将所述输出时钟信号端提供的输出时钟信号写入所述驱动信号输出端，在所述第一下拉节点的电位的控制下，控制所述驱动信号输出端与所述第四电压端之间连通。
  7. 如权利要求1至6中任一权利要求所述的驱动电路，其中，还包括第二下拉节点和第二控制电路；
    所述第二控制电路分别与第二下拉节点、第二控制端和第五电压端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第二下拉节点与所述第五电压端之间连通，以使得所述第二下拉节点的电位为有效电压；
    所述上拉节点复位电路还与所述第二下拉节点电连接，用于在所述第二下拉节点的电位为有效电压时，控制所述上拉节点与所述第二电压端之间连通，以对所述上拉节点的电位进行复位。
  8. 如权利要求7所述的驱动电路，其中，所述第二控制端为复位端、第二下拉节点或第二下拉控制节点。
  9. 如权利要求7所述的驱动电路，其中，所述第二控制电路包括第三晶体管；所述上拉节点复位电路还包括第四晶体管；
    所述第三晶体管的栅极与所述第二控制端电连接，所述第三晶体管的第一极与所述第二下拉节点电连接，所述第三晶体管的第二极与所述第五电压端电连接；
    所述第四晶体管的栅极与所述第二下拉节点电连接，所述第四晶体管的第一极与所述上拉节点电连接，所述第四晶体管的第二极与所述第二电压端电连接。
  10. 如权利要求8所述的驱动电路，其中，还包括第二下拉节点控制电路；
    所述第二下拉节点控制电路分别与所述第二下拉节点、所述第二下拉控制节点、所述上拉节点、第二控制电压端和第三电压端电连接，用于在所述第二控制电压端提供的第二控制电压的控制下，控制所述第二控制电压端与所述第二下拉控制节点之间连通，在所述上拉节点的电位的控制下，控制所述第二下拉控制节点与所述第三电压端之间连通，并用于在所述第二下拉控制节点的电位的控制下，控制所述第二下拉节点与所述第二控制电压端之间连通，在所述上拉节点的电位的控制下，控制所述第二下拉节点与所述第三电压端之间连通；
    所述第五电压端为所述第二控制电压端。
  11. 如权利要求6所述的驱动电路，其中，还包括输入电路、输出复位电路、初始复位电路和储能电路；
    所述输入电路分别与输入端、第二输入电压端和所述上拉节点电连接，用于在所述输入端提供的输入信号的控制下，控制将所述第二输入电压端提供的第二输入电压写入所述上拉节点；
    所述输出复位电路分别与帧复位端、所述驱动信号输出端和第四电压端电连接，用于在所述帧复位端提供的帧复位信号的控制下，控制所述驱动信号输出端与所述第四电压端之间连通；
    所述初始复位电路分别与初始复位端、所述上拉节点和所述第四电压端电连接，用于在所述初始复位端提供的初始复位信号的控制下，控制所述上拉节点与所述第四电压端之间连通；
    所述储能电路的第一端与所述上拉节点电连接，所述储能电路的第二端与所述驱动信号输出端电连接，所述储能电路用于储存电能。
  12. 如权利要求4所述的驱动电路，其中，所述复位电路包括第五晶体管；
    所述第五晶体管的栅极与所述复位端电连接，所述第五晶体管的第一极与所述上拉节点电连接，所述第五晶体管的第二极与所述第一输入电压端电连接。
  13. 如权利要求5所述的驱动电路，其中，所述第一下拉节点控制电路包括第六晶体管、第七晶体管、第八晶体管和第九晶体管；
    所述第六晶体管的栅极与所述第六晶体管的第一极都与所述第一控制电压端电连接，所述第六晶体管的第二极与所述第一下拉控制节点电连接；
    所述第七晶体管的栅极与所述上拉节点电连接，所述第七晶体管的第一极与所述第一下拉控制节点电连接，所述第七晶体管的第二极与所述第三电压端电连接；
    所述第八晶体管的栅极与所述第一下拉控制节点电连接，所述第八晶体管的第一极与所述第一控制电压端电连接，所述第八晶体管的第二极与所述第一下拉节点电连接；
    所述第九晶体管的栅极与所述上拉节点电连接，所述第九晶体管的第一极与所述第一下拉节点电连接，所述第九晶体管的第二极与所述第三电压端电连接。
  14. 如权利要求10所述的驱动电路，其中，所述第二下拉节点控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
    所述第十晶体管的栅极与所述第十晶体管的第一极都与所述第二控制电压端电连接，所述第十晶体管的第二极与所述第二下拉控制节点电连接；
    所述第十一晶体管的栅极与所述上拉节点电连接，所述第十一晶体管的第一极与所述第二下拉控制节点电连接，所述第十一晶体管的第二极与所述第三电压端电连接；
    所述第十二晶体管的栅极与所述第二下拉控制节点电连接，所述第十二晶体管的第一极与所述第二控制电压端电连接，所述第十二晶体管的第二极与所述第二下拉节点电连接；
    所述第十三晶体管的栅极与所述上拉节点电连接，所述第十三晶体管的第一极与所述第二下拉节点电连接，所述第十三晶体管的第二极与所述第三电压端电连接。
  15. 如权利要求11所述的驱动电路，其中，所述输入电路包括第十四晶体管；
    所述第十四晶体管的栅极与所述输入端电连接，所述第十四晶体管的第一极与所述第二输入电压端电连接，所述第十四晶体管的第二极与所述上拉节点电连接；
    所述输出电路包括第十五晶体管和第十六晶体管；
    所述第十五晶体管的栅极与所述上拉节点电连接，所述第十五晶体管的第一极与所述输出时钟信号端电连接，所述第十五晶体管的第二极与所述驱动信号输出端电连接；
    所述第十六晶体管的栅极与所述第一下拉节点电连接，所述第十六晶体管的第一极与所述驱动信号输出端电连接，所述第十六晶体管的第二极与所述第四电压端电连接；
    所述输出复位电路包括第十七晶体管；
    所述第十七晶体管的栅极与所述帧复位端电连接，所述第十七晶体管的第一极与所述驱动信号输出端电连接，所述第十七晶体管的第二极与所述第四电压端电连接；
    所述初始复位电路包括第十八晶体管；
    所述第十八晶体管的栅极与所述初始复位端电连接，所述第十八晶体管的第一极与所述上拉节点电连接，所述第十八晶体管的第二极与所述第四电压端电连接；
    所述储能电路包括存储电容；
    所述存储电容的第一端与所述上拉节点电连接，所述存储电容的第二端与所述驱动信号输出端电连接。
  16. 如权利要求15所述的驱动电路，其中，还包括第二下拉节点；
    所述输出电路还与所述第二下拉节点电连接，用于在所述第二下拉节点的电位的控制下，控制所述驱动信号输出端与第四电压端之间连通。
  17. 如权利要求16所述的驱动电路，其中，所述输出电路还包括第十九晶体管；
    所述第十九晶体管的栅极与所述第二下拉节点电连接，所述第十九晶体 管的第一极与所述驱动信号输出端电连接，所述第十九晶体管的第二极与所述第四电压端电连接。
  18. 一种驱动方法，应用于如权利要求1至17中任一权利要求所述的驱动电路，所述驱动方法包括：
    第一控制电路在第一控制信号的控制下，控制第一下拉节点与第一电压端之间连通，以使得所述第一下拉节点的电位为有效电压；
    在所述第一下拉节点的电位为有效电压时，上拉节点复位电路控制上拉节点与第二电压端之间连通，以对所述上拉节点的电位进行复位。
  19. 如权利要求18所述的驱动方法，其中，所述驱动电路还包括第二下拉节点和第二控制电路；所述驱动方法还包括：
    所述第二控制电路在第二控制信号的控制下，控制所述第二下拉节点与第五电压端之间连通，以使得所述第二下拉节点的电位为有效电压；
    在所述第二下拉节点的电位为有效电压时，所述上拉节点复位电路控制所述上拉节点与第二电压端之间连通，以对所述上拉节点的电位进行复位。
  20. 一种显示装置，包括如权利要求1至17中任一权利要求所述的驱动电路。
  21. 如权利要求20所述的显示装置，所述显示装置包括驱动模组；
    所述驱动模组包括多个级联的所述驱动电路；
    所述驱动模组包括的最后一级驱动电路的第一输入电压端不接入相应的第一输入电压，所述最后一级驱动电路为伪驱动电路；
    所述显示装置还包括设置于显示区域的多行多列像素电路，所述显示装置包括的最后一行像素电路为伪像素驱动电路；
    所述最后一级驱动电路用于为所述最后一行像素电路提供相应的驱动信号，所述最后一行像素电路不发光。
PCT/CN2022/089825 2022-04-28 2022-04-28 驱动电路、驱动方法和显示装置 WO2023206219A1 (zh)

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