WO2023203765A1 - 半導体装置の製造方法、及び、半導体装置 - Google Patents

半導体装置の製造方法、及び、半導体装置 Download PDF

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Publication number
WO2023203765A1
WO2023203765A1 PCT/JP2022/018581 JP2022018581W WO2023203765A1 WO 2023203765 A1 WO2023203765 A1 WO 2023203765A1 JP 2022018581 W JP2022018581 W JP 2022018581W WO 2023203765 A1 WO2023203765 A1 WO 2023203765A1
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Prior art keywords
insulating film
semiconductor
hybrid bonding
electrode
semiconductor device
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Ceased
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PCT/JP2022/018581
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English (en)
French (fr)
Japanese (ja)
Inventor
志津 福住
恵子 上野
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Resonac Corp
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Resonac Corp
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Priority to PCT/JP2022/018581 priority Critical patent/WO2023203765A1/ja
Priority to JP2024516045A priority patent/JPWO2023203765A1/ja
Priority to US18/857,185 priority patent/US20250279392A1/en
Priority to CN202280095052.4A priority patent/CN119054059A/zh
Publication of WO2023203765A1 publication Critical patent/WO2023203765A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
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    • H10W74/00—Encapsulations, e.g. protective coatings
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H10W72/07338—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/355—Materials of die-attach connectors of outermost layers of multilayered die-attach connectors, e.g. material of a coating
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
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    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
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    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/331—Bonding techniques, e.g. hybrid bonding characterised by the application of energy for connecting
    • H10W80/333—Compression bonding
    • H10W80/334—Thermocompression bonding
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Definitions

  • the present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device.
  • connection method FC connection method
  • FC connection methods include methods of joining the joints to metals using solder, tin, gold, silver, copper, etc., methods of joining the joints to metals by applying ultrasonic vibration, and mechanical contact using the contractile force of resin. There are known methods for holding the . From the viewpoint of reliability of the connection part, it is common to use solder, tin, gold, silver, copper, or the like to join the connection part with metal.
  • the COB (Chip On Board) type connection method which is widely used in BGA (Ball Grid Array), CSP (Chip Size Package), etc.
  • the FC connection method is also widely used in the COC (Chip On Chip) type connection method, which connects semiconductor chips by forming connection parts (bumps or wiring) on the semiconductor chips (for example, patented (See Reference 1).
  • Patent Document 1 when manufacturing a semiconductor device by stacking a large number of semiconductor chips by flip-chip bonding, the height of each connection bump is accumulated, resulting in the semiconductor device becoming thick. In particular, when semiconductor chips are multi-staged, the influence of the height of the connection bumps on the thickness of the semiconductor device cannot be ignored. Therefore, a manufacturing method that can realize a reduction in the height of a semiconductor device is desired.
  • An object of the present disclosure is to provide a method for manufacturing a semiconductor device and a semiconductor device that can reduce the height of the semiconductor device.
  • the present disclosure relates, as one aspect, to a method for manufacturing a semiconductor device.
  • This method for manufacturing a semiconductor device includes preparing a first semiconductor substrate having a first substrate body including a plurality of first semiconductor elements, a first insulating film provided on the first substrate body, and a plurality of first electrodes.
  • a hybrid bonding structure to obtain a hybrid bonding structure; forming a plurality of connection bumps on a surface of the second substrate body opposite to the second insulating film; and forming a hybrid bonding structure on which the plurality of connection bumps are formed.
  • a plurality of diced hybrid bonding structures each comprising at least one first semiconductor element, at least one first electrode, at least one second semiconductor element, at least one second electrode, and at least one connection bump; a step of mounting a first hybrid bonding structural component among the plurality of hybrid bonding structural components on another member, and a step of applying a curable first liquid to a gap between the first hybrid bonding structural component and the other member.
  • the method includes a step of injecting a material and a step of curing the first liquid material.
  • a first hybrid bonding structure is manufactured using a hybrid bonding technique in which semiconductor chips (or semiconductor wafers, etc.) are bonded together and connected without using connection bumps, and a first hybrid Connecting bumps are formed on the bonding structure, which is then diced to obtain a plurality of hybrid bonding structure components. Then, mounting is performed using such a first hybrid bonding structure component with connection bumps, and a first liquid material is injected into the gap between the components and other components to be mounted and hardened.
  • this manufacturing method because hybrid bonding technology is used to connect some semiconductor chips to each other, the thickness of the semiconductor device can be reduced compared to the case where all the connections between semiconductor chips are made using connection bumps. This makes it possible to reduce the height.
  • the manufacturing process was long because the stacked semiconductor chips were connected one by one by flip-chip, but according to the above semiconductor device manufacturing method, some semiconductor chips are connected to each other by hybrid bonding. Since it becomes possible to perform the process all at once using technology, it becomes possible to shorten the manufacturing process and improve productivity.
  • the method for manufacturing a semiconductor device described above includes a step of mounting a second hybrid bonding structural component among a plurality of hybrid bonding structural components on a first hybrid bonding structural component, and a step of mounting the second hybrid bonding structural component and the first hybrid bonding structural component. It is preferable to further include the steps of injecting a curable second liquid material into the gap between the two and hardening the second liquid material. According to this manufacturing method, even when stacked semiconductor chips are multi-staged, it is possible to reduce the height of the semiconductor device. Furthermore, the manufacturing process of semiconductor devices can be shortened and productivity can be improved.
  • the step of injecting the first liquid material and the step of injecting the second liquid material may be performed separately. According to this manufacturing method, it is possible to more reliably inject the first liquid material and the second liquid material, and easily manufacture a highly reliable semiconductor device.
  • the method for manufacturing a semiconductor device described above may further include the step of sealing the first hybrid bonding structural component and the second hybrid bonding structural component, and the step of injecting the first liquid material and the step of injecting the second liquid material.
  • a step may be performed during this sealing step.
  • the other member may be a substrate provided with wiring electrodes on the surface, and in the step of mounting the first hybrid bonding structure component, the connection bump of the first hybrid bonding structure component
  • the first hybrid bonding structure component may be mounted on the substrate such that the first hybrid bonding structure component is connected to the wiring electrode. According to this manufacturing method, it is possible to reduce the height of a semiconductor device in which a semiconductor chip is mounted on a substrate.
  • At least one of the first insulating film of the first semiconductor substrate and the second insulating film of the second semiconductor substrate may contain an inorganic insulating material. According to this manufacturing method, it is possible to manufacture a semiconductor device with a finer structure. Further, since the bond between inorganic materials can be easily made strong, it is possible to increase the adhesive strength between semiconductor chips and further improve the connection reliability as a semiconductor device.
  • At least one of the first insulating film of the first semiconductor substrate and the second insulating film of the second semiconductor substrate may contain an organic insulating material. According to this manufacturing method, debris generated when a semiconductor substrate is diced into semiconductor chips is absorbed (incorporated) into the insulating film portion made of the organic material using an organic material that is relatively soft, and the debris is bonded using hybrid bonding. It is possible to reduce connection failures between semiconductor chips that are connected to each other.
  • the organic insulating material included in at least one of the first insulating film and the second insulating film is polyimide, a polyimide precursor, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO ), or a PBO precursor.
  • the first insulating film etc. can be easily formed by spin coating or the like, and a thin film can be easily formed. Further, since these materials have high heat resistance, they can withstand high temperatures when bonding is performed by hybrid bonding, and it becomes possible to bond semiconductor chips together more reliably.
  • the first liquid material may be a liquid epoxy resin composition containing at least an epoxy resin and a curing agent.
  • This semiconductor device includes a first semiconductor component including a first semiconductor chip, a first insulating film provided on the first semiconductor chip, and a first electrode, a second semiconductor chip, and a first semiconductor component provided on a first surface of the second semiconductor chip.
  • a second semiconductor component including a second insulating film and a second electrode provided on the second semiconductor chip; and a first connection bump provided on the second surface of the second semiconductor chip and connected to the electrode of the second semiconductor chip.
  • a first hybrid bonding structure component in which a first insulating film and a second insulating film are bonded together and a first electrode and a second electrode are bonded; and another component on which the first hybrid bonding structure component is mounted. and a cured product of a first liquid material injected between the first hybrid bonding structural component and another member so as to cover the first connection bump and cured.
  • This semiconductor device uses a first hybrid bonding structure component that uses a hybrid bonding technique in which semiconductor chips (or semiconductor wafers, etc.) are bonded together and connected without using connection bumps. Therefore, compared to a semiconductor device in which all connections between semiconductor chips are made using connection bumps, the thickness of the semiconductor device can be reduced and the height of the semiconductor device can be reduced.
  • the above semiconductor device is a second hybrid bonding structure component mounted on the first hybrid bonding structure component, and the third semiconductor chip, a third insulating film provided on the third semiconductor chip, and a third electrode.
  • a fourth semiconductor component including a fourth semiconductor chip and a fourth insulating film and a fourth electrode provided on the first surface of the fourth semiconductor chip; a second connection bump provided on two surfaces and connected to the electrode of the fourth semiconductor chip, the third insulating film and the fourth insulating film are bonded together, and the third electrode and the fourth electrode are bonded together.
  • a cured product of a second liquid material injected between the joined second hybrid bonding structural component and the first hybrid bonding structural component so as to cover the second connection bump and hardening. may further be provided. According to this semiconductor device, even when stacked semiconductor chips are multi-staged, it is possible to reduce the height of the semiconductor device.
  • the other member may be a substrate having a wiring electrode, and the first connection bump may be connected to the wiring electrode. According to this semiconductor device, it is possible to reduce the height of the semiconductor device in which the semiconductor chip is mounted on the substrate.
  • At least one of the first insulating film and the second insulating film may include an inorganic insulating material. According to this configuration, it is possible to manufacture a semiconductor device with a finer configuration. Further, since the bond between inorganic materials can be easily made strong, it is possible to increase the adhesive strength between semiconductor chips and further improve the connection reliability as a semiconductor device.
  • At least one of the first insulating film and the second insulating film may include an organic insulating material. According to this configuration, the debris from dicing into semiconductor chips is absorbed (incorporated) into the insulating film portion made of the organic material by the organic material, which is a relatively soft material, and the semiconductors are bonded by hybrid bonding. Connection defects between chips can be reduced.
  • the cured product of the first liquid material may be a cured product of a liquid epoxy resin composition containing at least an epoxy resin and a curing agent.
  • the height of the semiconductor device can be reduced.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present disclosure.
  • FIGS. 2A and 2B are cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG. 3A and 3B are cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG. 1, and are diagrams showing a process subsequent to the process shown in FIG. 2.
  • FIGS. 4A and 4B are cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG. 1, and are diagrams showing a process subsequent to the process shown in FIG. 3.
  • FIGS. 5A and 5B are cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG.
  • FIG. 1 1, and are diagrams showing a process subsequent to the process shown in FIG. 4.
  • 6A and 6B are cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG. 1, and are diagrams showing steps subsequent to the step shown in FIG. 5.
  • FIGS. 7A and 7B are cross-sectional views showing another example of a method for manufacturing the semiconductor device shown in FIG.
  • the term “layer” includes a structure that is formed on the entire surface as well as a structure that is formed on a part of the layer when observed as a plan view.
  • the term “process” does not only refer to an independent process, but also refers to a process that cannot be clearly distinguished from other processes, as long as the intended effect of the process is achieved. included.
  • a numerical range indicated using “ ⁇ ” indicates a range that includes the numerical values written before and after " ⁇ " as the minimum and maximum values, respectively.
  • FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device according to this embodiment.
  • the semiconductor device 1 is an example of a semiconductor package, and includes a substrate 10, a set of first hybrid bonding structural components 40A and a first connecting body 55A arranged on the substrate 10, and Another set of a second hybrid bonding structural component 40B and a second connecting body 55B are further arranged on the first hybrid bonding structural component 40A.
  • a first connection body 55A, a first hybrid bonding structure component 40A, a second connection body 55B, and a second hybrid bonding structure component 40B are stacked in this order on the substrate 10.
  • the substrate 10 has a plurality of wiring electrodes 12 on the surface 11.
  • the substrate 10 is not particularly limited as long as it is a printed circuit board, and there is no need for a metal layer formed on the surface of an insulating substrate whose main component is glass epoxy, polyimide, polyester, ceramic, epoxy, bismaleimide triazine, polyimide, etc.
  • a circuit board or the like on which wiring (wiring pattern) is formed by printing can be used.
  • the wiring electrode 12 includes, for example, gold, silver, and copper.
  • the first hybrid bonding structure component 40A includes a first semiconductor component 26A including a first semiconductor chip 20A, a first insulating film 22A provided on the first semiconductor chip 20A, and a plurality of first electrodes 24A, and a second semiconductor component 26A.
  • a second semiconductor component 36A including a chip 30A, a second insulating film 32A provided on a first surface 30a of the second semiconductor chip 30A, and a plurality of second electrodes 34A, and a second surface 30b of the second semiconductor chip 30A. It has a first connection bump 50A provided thereon and connected to the terminal electrode 31a of the second semiconductor chip 30A.
  • a first hybrid bonding structure component 40A disposed on the substrate 10 is attached to the substrate 10 by a first connection bump 50A.
  • the terminal electrode 31a of the first hybrid bonding structure component 40A is connected to the wiring electrode 12 of the substrate 10 by the first connection bump 50A.
  • a cured product of an adhesive liquid resin composition (first liquid material) constituting the first connection body 55A is filled around the first connection bump 50A.
  • the first hybrid bonding structure component 40A the first insulating film 22A and the second insulating film 32A are bonded together, and the plurality of first electrodes 24A and the plurality of second electrodes 34 are respectively bonded.
  • the first electrode 24A is electrically connected to wiring formed by a semiconductor element included in the first semiconductor chip 20A.
  • the second electrode 34A is electrically connected to wiring formed by a semiconductor element included in the second semiconductor chip 30A. Note that various conventional methods can be used for the method of forming the plurality of first electrodes 24A in the first insulating film 22A and the direction of forming the plurality of second electrodes 34A in the second insulating film 32A. , a detailed explanation will be omitted here.
  • the first semiconductor chip 20A and the second semiconductor chip 30A are not particularly limited, and various semiconductors such as elemental semiconductors made of the same type of elements such as silicon and germanium, and compound semiconductors such as gallium arsenide and indium phosphide. can be used.
  • the first semiconductor chip 20A and the second semiconductor chip 30A may have terminal electrodes 21a, 31a for connecting the semiconductor chips to the outside, and through electrodes 21b, 31b penetrating the semiconductor chips.
  • the terminal electrode 21a of the first semiconductor chip 20A is connected to the terminal electrode 31a of the fourth semiconductor chip 30B via a second connection bump 50B, which will be described later.
  • the through electrode 21b of the first semiconductor chip 20A is connected to the terminal electrode 21a and the first electrode 24A.
  • the terminal electrode 31a of the second semiconductor chip 30A is connected to the wiring electrode 12 of the substrate 10 via the first connection bump 50A.
  • the through electrode 31b of the second semiconductor chip 30A is connected to the terminal electrode 31a and the second electrode 34A.
  • the thickness of the first semiconductor chip 20A and the second semiconductor chip 30A is, for example, in the range of 0.2 mm to 2.0 mm.
  • the first insulating film 22A and the second insulating film 32A are configured to include an inorganic insulating material or an organic insulating material.
  • the first insulating film 22A and the second insulating film 32A may be configured to include both an inorganic insulating material and an organic insulating material.
  • the inorganic insulating material used for the insulating film is, for example, silicon oxide (SiO 2 ).
  • SiO 2 silicon oxide
  • an inorganic insulating material such as silicon oxide is used for the insulating film, a semiconductor device with a finer structure can be manufactured. Further, since the bond between inorganic insulating materials can be easily made strong, it is possible to increase the adhesive strength between semiconductor chips and improve the connection reliability as a semiconductor device.
  • the organic insulating material used for the first insulating film 22A and the second insulating film 32A is, for example, polyimide, polyimide precursor (for example, polyimiamic ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), polybenzoxazole ( PBO) or PBO precursor.
  • These organic insulating materials have a lower elastic modulus than inorganic insulating materials such as silicon oxide (SiO 2 ), and are soft materials.
  • the elastic modulus of the organic material constituting the first insulating film 22A and the second insulating film 32A may be, for example, 7.0 GPa or less, 5.0 GPa or less, or 3.0 GPa or less. It may be 2.0 GPa or less, or 1.5 GPa or less.
  • the elastic modulus here means Young's modulus.
  • the organic insulating material constituting the first insulating film 22A and the second insulating film 32A preferably has a coefficient of thermal expansion of 70 ppm/K or less, and more preferably 50 ppm/K or less.
  • the thickness of the first insulating film 22A and the second insulating film 32A is preferably 10 ⁇ m or less, more preferably 5 ⁇ m or less, and even more preferably 3 ⁇ m or less.
  • the first electrode 24A and the second electrode 34A formed in the first insulating film 22A and the second insulating film 32A can be The semiconductor device 1 can be miniaturized and the thickness of the semiconductor device 1 can be reduced.
  • the thickness of the first insulating film 22A and the second insulating film 32A is preferably 1 ⁇ m or more from the viewpoint of ensuring electrical reliability.
  • the first electrode 24A and the second electrode 34A are terminal electrodes provided on the inner surfaces 20a and 30a of the first semiconductor chip 20A and the second semiconductor chip 30A, and are made of copper or aluminum, for example.
  • the first electrode 24A penetrates the first insulating film 22A and is exposed on the surface of the first insulating film 22A that is opposite to the surface 20a to which the first semiconductor chip 20A is connected.
  • the second electrode 34A penetrates the second insulating film 32A and is exposed on the surface of the second insulating film 32A that is opposite to the surface 30a to which the second semiconductor chip 30A is connected.
  • the first electrode 24A and the second electrode 34A are bonded to each other.
  • the first connection bump 50A is a connection member provided on the surface 30b of the second semiconductor chip 30A and connected to the terminal electrode 31a of the second semiconductor chip 30A.
  • the first connection bump 50A contains gold, silver, copper, solder (main components are, for example, tin-silver, tin-lead, tin-bismuth, tin-copper), nickel, tin, lead, etc. as main components. and may contain multiple metals.
  • the first connection bump 50A is connected to the wiring electrode 12 of the substrate 10 at the other end.
  • the first connection body 55A located between the substrate 10 and the first hybrid bonding structural component 40A is a cured product of a liquid adhesive resin composition, and covers the first connection bump 50A.
  • the liquid adhesive resin composition used to form the first connector 55A is, for example, an adhesive resin composition containing an epoxy resin and a curing agent.
  • the curing agent is, for example, an amine curing agent.
  • the liquid resin composition used to form the first connector 55A may contain an inorganic filler, a curing accelerator, rubber particles, or the like.
  • a second hybrid bonding structural component 40B is arranged on the first hybrid bonding structural component 40A.
  • the second hybrid bonding structure component 40B is attached to the first semiconductor chip 20A by a second connection bump 50B.
  • the second hybrid bonding structural component 40B has the same configuration as the first hybrid bonding structural component 40A, and the following description may be made with some overlapping parts omitted.
  • the second hybrid bonding structure component 40B includes a third semiconductor component 26B including a third semiconductor chip 20B, a third insulating film 22B provided on the third semiconductor chip 20B, and a plurality of third electrodes 24B, and a fourth semiconductor component 26B.
  • a fourth semiconductor component 36B including a chip 30B, a fourth insulating film 32B provided on a first surface 30a of the fourth semiconductor chip 30B, and a plurality of fourth electrodes 34B, and a second surface 30b of the fourth semiconductor chip 30B. It has a second connection bump 50B provided thereon and connected to the terminal electrode 31a of the fourth semiconductor chip 30B.
  • a second hybrid bonding structure 40B disposed on the first hybrid bonding structure 40A is attached to the first hybrid bonding structure 40A by a second connection bump 50B. More specifically, the terminal electrode 31a of the second hybrid bonding structural component 40B is connected to the terminal electrode 21a of the first hybrid bonding structural component 40A by a second connection bump 50B. The area around the second connection bump 50B is filled with a cured product of an adhesive resin composition (second liquid material) constituting the second connection body 55B. Further, in the second hybrid bonding structure component 40B, the third insulating film 22B and the fourth insulating film 32B are bonded together, and the plurality of third electrodes 24B and the plurality of fourth electrodes 34B are respectively bonded.
  • the third semiconductor chip 20B and the fourth semiconductor chip 30B are the same semiconductor chips as the first semiconductor chip 20A and the second semiconductor chip 30A.
  • the third semiconductor chip 20B and the fourth semiconductor chip 30B may have terminal electrodes 21a, 31a for connecting the semiconductor chips to the outside, and through electrodes 21b, 31b penetrating the semiconductor chips.
  • the terminal electrode 31a of the fourth semiconductor chip 30B is connected to the terminal electrode 21a of the first semiconductor chip 20A via the second connection bump 54B.
  • the through electrode 31b of the fourth semiconductor chip 30B is connected to the terminal electrode 31a and the fourth electrode 34B.
  • the thickness of the third semiconductor chip 20B and the fourth semiconductor chip 30B is, for example, in the range of 0.2 mm to 2.0 mm, similarly to the first semiconductor chip 20A and the like.
  • the third insulating film 22B and the fourth insulating film 32B are configured to include an inorganic insulating material or an organic insulating material, similarly to the first insulating film 22A and the second insulating film 32A.
  • the third insulating film 22B and the fourth insulating film 32B may be configured to include both an inorganic insulating material and an organic insulating material.
  • the inorganic insulating material or organic insulating material used for the insulating film is the same as that for the first insulating film 22A.
  • the thicknesses of the third insulating film 22B and the fourth insulating film 32B are similarly preferably 10 ⁇ m or less, more preferably 5 ⁇ m or less, and even more preferably 3 ⁇ m or less.
  • the thickness of the third insulating film 22B and the fourth insulating film 32B is preferably 1 ⁇ m or more from the viewpoint of ensuring electrical reliability.
  • the third electrode 24B and the fourth electrode 34B are terminal electrodes provided on the inner surfaces 20a and 30a of the third semiconductor chip 20B and the fourth semiconductor chip 30B, and are made of copper or aluminum, for example.
  • the third electrode 24B penetrates the third insulating film 22B and is exposed on the surface of the third insulating film 22B that is opposite to the surface 20a to which the third semiconductor chip 20B is connected.
  • the fourth electrode 34B penetrates the fourth insulating film 32B and is exposed on a surface of the fourth insulating film 32B opposite to the surface 30a to which the fourth semiconductor chip 30B is connected.
  • the third electrode 24B and the fourth electrode 34B are bonded to each other.
  • the second connection bump 50B is a connection member provided on the surface 30b of the fourth semiconductor chip 30B and connected to the terminal electrode 31a of the fourth semiconductor chip 30B.
  • the second connection bump 50B like the first connection bump 50A, has gold, silver, copper, solder as main components (the main components are, for example, tin-silver, tin-lead, tin-bismuth, tin-copper), nickel. , tin, lead, etc., and may contain multiple metals.
  • the second connection bump 50B is connected at the other end to the terminal electrode 21a of the first semiconductor chip 20A.
  • the second connecting body 55B located between the first hybrid bonding structural component 40A and the second hybrid bonding structural component 40B is a cured product of a liquid adhesive resin composition, similar to the first connecting body 55A. and covers the second connection bump 50B.
  • the connection configuration in the semiconductor device 1 having the above-described configuration will be described.
  • the first hybrid bonding structure component 40A is arranged on the substrate 10, and the wiring electrode 12 of the substrate 10 is connected to the terminal electrode 31a of the second semiconductor chip 30A via the first connection bump 50A. It is connected.
  • This terminal electrode 31a is connected to the terminal electrode 21a of the first semiconductor chip 20A via the second electrode 34A, the first electrode 24A, and the through electrode 21b of the first semiconductor chip 20A.
  • a second hybrid bonding structure component 40B is further arranged on the first hybrid bonding structure component 40A, and the terminal electrode 21a of the first semiconductor chip 20A is connected to the first hybrid bonding structure component 40B via the second connection bump 50B.
  • Such a semiconductor device 1 may have a configuration in which hybrid bonding structural components having a similar configuration are further stacked and connected therebetween by connection bumps.
  • FIGS. 2A and 2B are cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG. 3A and 3B are cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG. 1, and are diagrams showing a process subsequent to the process shown in FIG. 2.
  • FIGS. 4A and 4B are cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG. 1, and are diagrams showing a process subsequent to the process shown in FIG. 3.
  • FIGS. 5A and 5B are cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG. 1, and are diagrams showing a process subsequent to the process shown in FIG. 4.
  • 6A and 6B are cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG. 1, and are diagrams showing steps subsequent to the step shown in FIG. 5.
  • the semiconductor device 1 can be manufactured, for example, through at least the following steps (a) to (h).
  • the first insulating film of the first semiconductor substrate and the second insulating film of the second semiconductor substrate are bonded to each other, and the plurality of first electrodes of the first semiconductor substrate and the second semiconductor A step of bonding the plurality of second electrodes of the substrate to obtain a hybrid bonding structure.
  • Step (a) corresponds to a plurality of semiconductor components including the first semiconductor component 26A and the third semiconductor component 26B, and is a first silicon substrate on which an integrated circuit including semiconductor elements and wiring connecting them is formed.
  • This is a step of preparing the semiconductor substrate 70.
  • a plurality of first electrodes 74 made of copper, aluminum, etc. are provided at predetermined intervals on one surface 72a of the first substrate body 72 made of silicon etc.
  • a first insulating film 76 made of an inorganic or organic material is provided.
  • the first substrate body 72 may be, for example, a circular or rectangular semiconductor wafer.
  • the first electrode 74 is an end face electrode for penetrating the first insulating film 76 and exposing the integrated circuit formed on the first semiconductor substrate 70 to the outside.
  • the plurality of first electrodes 74 may be provided after the first insulating film 76 is provided on the one surface 72a of the first substrate main body 72, or the plurality of first electrodes 74 may be provided on the one surface 72a of the first substrate main body 72.
  • the first insulating film 76 may be provided after that.
  • the first substrate body 72 may be provided with a terminal electrode 72b connected to an integrated circuit or the like and a through electrode 72c penetrating the substrate body.
  • Step (b) corresponds to a plurality of semiconductor components including the second semiconductor component 36A and the fourth semiconductor component 36B, and is a second silicon substrate on which an integrated circuit including semiconductor elements and wiring connecting them is formed.
  • This is a step of preparing the semiconductor substrate 80.
  • a plurality of second electrodes 84 made of copper, aluminum or the like are provided at predetermined intervals on one surface 82a of the second substrate body 82 made of silicon or the like.
  • a second insulating film 86 made of an inorganic or organic material is provided.
  • the second substrate body 82 may be, for example, a circular or rectangular semiconductor wafer.
  • the second electrode 84 is an end face electrode for penetrating the second insulating film 86 and exposing the integrated circuit formed on the second semiconductor substrate 80 to the outside.
  • the plurality of second electrodes 84 may be provided after the second insulating film 86 is provided on the one surface 82a of the second substrate main body 82, or the plurality of second electrodes 84 may be provided on the one surface 82a of the second substrate main body 82. Alternatively, the second insulating film 86 may be provided.
  • the second substrate body 82 may be provided with a terminal electrode 82b connected to an integrated circuit or the like and a through electrode 82c penetrating the substrate body. Note that (a) in FIG. 2 shows only a part of the first semiconductor substrate 70 and the second semiconductor substrate 80 in the planar direction, and the other parts have the same structure, but are not shown. . The same applies to FIGS. 2(b) and 3.
  • the first insulating film 76 and the second insulating film 86 used in the step (a) and the step (b) are the first insulating film 22A, the second insulating film 32A, the third insulating film 22B, and the third insulating film 22B of the semiconductor device 1 described above. 4 insulating film 32B, and includes an inorganic material or an organic material.
  • the inorganic material used for the insulating film is, for example, silicon oxide (SiO 2 ).
  • SiO 2 silicon oxide
  • a semiconductor device with a finer structure can be manufactured.
  • step (c) described below since the bond between inorganic materials is easy to strengthen, the adhesive strength between semiconductor substrates is increased and the connection reliability as a semiconductor device is improved. becomes possible.
  • the organic material used for the insulating film is, for example, polyimide, a polyimide precursor (eg, polyimiamic ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or a PBO precursor.
  • These organic materials have a lower elastic modulus than inorganic materials such as silicon oxide (SiO 2 ), and are soft materials.
  • the elastic modulus of the organic material constituting the first insulating film 76 and the second insulating film 86 may be, for example, 7.0 GPa or less, 5.0 GPa or less, or 3.0 GPa or less. It may be 2.0 GPa or less, or 1.5 GPa or less.
  • the elastic modulus here means Young's modulus.
  • the organic material constituting the first insulating film 76 and the second insulating film 86 preferably has a coefficient of thermal expansion of 70 ppm/K or less, and more preferably 50 ppm/K or less.
  • each insulating film can be easily formed as a thin film by spin coating or the like. Furthermore, since these organic materials have heat resistance, they can withstand the temperature (for example, a high temperature of 300° C. or higher) when the first electrode 74 and the second electrode 84 are bonded in step (c) described later. This prevents the bond between the insulating films from deteriorating due to high temperatures.
  • the first insulating film 76 and the second insulating film 86 may be insulating films containing both an inorganic material and an organic material.
  • the thickness of the first insulating film 76 and the second insulating film 86 may be 20 ⁇ m or less. By sufficiently reducing the thickness of the first insulating film 76 and the second insulating film 86, the wiring formed from the first electrode 74 and the second electrode 84 can have a finer structure. Note that the thickness of the first insulating film 76 and the second insulating film 86 may be thicker than 20 ⁇ m. In this case, when the insulating films are bonded together, more debris can be embedded in the resin insulating film, and the insulating films can be bonded together more reliably. Further, the thickness of the first insulating film 76 and the second insulating film 86 may be 4 ⁇ m or more. In this case, by embedding minute debris in the resin insulating film, even if minute debris remains, it is possible to maintain a good connection between the first insulating film 76 and the second insulating film 86. It becomes possible.
  • step (c) the first insulating film 76 of the first semiconductor substrate 70 and the second insulating film 86 of the second semiconductor substrate 80 are bonded together, and the plurality of first electrodes 74 of the first semiconductor substrate 70 and the first insulating film 86 of the second semiconductor substrate 80 are bonded together.
  • the bonding surface 70a of the first semiconductor substrate 70 and the bonding surface 80a of the second semiconductor substrate 80 are polished using a CMP (Chemical Mechanical Polishing) method.
  • CMP Chemical Mechanical Polishing
  • the first semiconductor substrate 70 may be polished by a CMP method under the condition that the first electrode 74 made of copper or the like is selectively and deeply removed, or each surface of the first electrode 74 is aligned with the surface of the first insulating film 76. It may be polished by CMP method. The same applies to the polishing of the second semiconductor substrate 80. Such polishing also removes debris on the surfaces of the first semiconductor substrate 70 and the second semiconductor substrate 80.
  • step (c) after removing the organic substances or metal oxides attached to the surfaces of the bonding surface 70a of the first semiconductor substrate 70 and the bonding surface 80a of the second semiconductor substrate 80, the steps shown in FIGS. 2A and 2B are performed. , the bonding surface 70a of the first semiconductor substrate 70 and the bonding surface 80a of the second semiconductor substrate 80 are made to face each other, and the first electrode 74 and the second electrode 84 of the first semiconductor substrate 70 are aligned. conduct. At this positioning stage, the first insulating film 76 of the first semiconductor substrate 70 and the second insulating film 86 of the second semiconductor substrate 80 are separated from each other and are not bonded.
  • the first insulating film 76 of the first semiconductor substrate 70 and the second insulating film 86 of the second semiconductor substrate 80 are bonded.
  • the first insulating film 76 and the second insulating film 86 may be uniformly heated before joining.
  • the heating temperature when bonding the first insulating film 76 and the second insulating film 86 may be, for example, 30° C. or more and 400° C. or less, and the pressure may be 0.1 MPa or more and 1 MPa or less.
  • the first insulating film 76 and the second insulating film 86 are bonded to form an insulating bonded portion, and the first semiconductor substrate 70 and the second semiconductor substrate 80 are mechanically strengthened to each other. It is attached.
  • a predetermined heat, pressure, or both are applied to bond the first electrode 74 of the first semiconductor substrate 70 and the second electrode 84 of the second semiconductor substrate 80.
  • the heating temperature is 150°C or more and 400°C or less, and may be 200°C or more and 300°C or less, and the pressure is 0.1 MPa or more and 1 MPa or more. It may be the following.
  • the first electrode 74 and the corresponding second electrode 84 are bonded to form an electrode bonding portion, and the first electrode 74 and the second electrode 84 are mechanically and electrically bonded firmly.
  • Ru Note that electrode bonding may be performed after bonding the insulating film, but electrode bonding and bonding of the insulating film may be performed simultaneously. Through the above steps, a hybrid bonding structure S is obtained.
  • connection bumps 50 are formed on the surface 82d of the second substrate main body 82 of the hybrid bonding structure S opposite to the second insulating film 86.
  • the connection bump 50 contains gold, silver, copper, solder (main components are, for example, tin-silver, tin-lead, tin-bismuth, tin-copper), nickel, tin, lead, etc. as main components. It may contain multiple metals.
  • such connection bumps 50 are formed so as to be connected to the plurality of terminal electrodes 82b of the second substrate main body 82. Conventional methods can be used to manufacture the bumps.
  • step (e) the hybrid bonding structure S provided with the connection bumps 50 is diced into a plurality of individual pieces, and at least one first semiconductor element, at least one first electrode 74, and at least one second semiconductor element are diced. , at least one second electrode 84 and at least one connection bump 50 are obtained.
  • step (e) the hybrid bonding structure S is diced into individual pieces using plasma dicing, stealth dicing, laser dicing, or the like. As a result, individual hybrid bonding structural components 40 are obtained, as shown in FIG. 4(a). This hybrid bonding structural component 40 corresponds to the first hybrid bonding structural component 40A and the second hybrid bonding structural component 40B described above.
  • step (f) the first hybrid bonding structural component 40A out of the plurality of individualized hybrid bonding structural components 40 is mounted on the substrate 10, which is another member.
  • step (f) first, as shown in FIG. 4B, the first hybrid bonding structure component 40A is picked up by the bonding tool P and moved toward the substrate 10. Thereafter, after arranging the first hybrid bonding structural component 40A on the substrate 10, the first hybrid bonding structural component 40A is pressed while being heated. At this time, as shown in FIG. 5A, each of the first connection bumps 50A and the corresponding wiring electrode 12 are connected. In other words, the terminal electrode 31a of the second semiconductor chip 30A is connected to the wiring electrode 12 via the first connection bump 50A. At this time, a gap V is formed between the first hybrid bonding structural component 40A and the substrate 10, except for the first connection bump 50A.
  • step (g) as shown in FIG. 5B, a first liquid material made of a curable resin composition is injected into the gap V between the first hybrid bonding structural component 40A and the substrate 10 using a syringe or the like. Furthermore, in step (h), the injected first liquid material is cured by heat or ultraviolet light (light). Such a first liquid material protects the first connection bump 50A and protects the connection between the first hybrid bonding structure component 40A and the substrate 10.
  • Such a first liquid material may be an underfill agent (CUF), which is a type of semiconductor encapsulant, and is, for example, a liquid epoxy resin composition containing an epoxy resin and a curing agent. .
  • the curing agent contained in the first liquid material is, for example, an amine curing agent.
  • the first liquid material may contain an inorganic filler. The average particle size of the inorganic filler may be within the range of 0.3 to 5 ⁇ m.
  • the epoxy resin used for the first liquid material is not particularly limited, and examples include glycidyl ether type epoxy resins obtained by reacting bisphenol A, bisphenol F, bisphenol AD, bisphenol S, naphthalene diol, hydrogenated bisphenol A, etc. with epichlorohydrin. , epoxidized novolac resins obtained by condensing or co-condensing phenols and aldehydes, including ortho-cresol novolac-type epoxy resins, and epoxidized novolac resins obtained by the reaction of polybasic acids such as phthalic acid and dimer acid with epichlorohydrin.
  • aminoglycidyl ether type epoxy resin obtained by reacting polyamines such as diaminodiphenylmethane and isocyanuric acid with epichlorohydrin, and linear aliphatic epoxy resins obtained by oxidizing olefin bonds with peracid such as peracetic acid. , alicyclic epoxy resin, etc. can be used.
  • the epoxy resin used in the first liquid material examples include bisphenol A epoxy resin, bisphenol F epoxy resin, bisphenol AD epoxy resin, bisphenol S epoxy resin, naphthalene diol epoxy resin, and hydrogenated bisphenol A epoxy resin. It is desirable to contain at least one liquid epoxy resin selected from resins and aminoglycidyl ether type epoxy resins, and it is more preferable to use at least one of liquid bisphenol F type epoxy resins and aminoglycidyl ether type epoxy resins. In addition, these may be used individually or in combination of 2 or more types.
  • a reactive diluent having an epoxy group may be mixed to adjust the viscosity.
  • the reactive diluent having an epoxy group include n-butyl glycidyl ether, versatic acid glycidyl ether, styrene oxide, ethylhexyl glycidyl ether, phenyl glycidyl ether, butylphenyl glycidyl ether, 1,6-hexanediol diglycidyl ether, Examples include neopentyl glycol diglycidyl ether, diethylene glycol diglycidyl ether, and trimethylolpropane triglycidyl ether, and one or more of these may be used in combination.
  • These epoxy resins are preferably sufficiently purified and contain few ionic impurities.
  • the content of free Na ions and free Cl ions is preferably 500 ppm or less.
  • the curing agent used in the first liquid material is not particularly limited, and acid anhydrides, phenol resins, aromatic amines, various imidazole derivatives, etc. that are commonly used as curing agents for epoxy resins can be used. From the viewpoint of lowering the viscosity, it is preferable to use an acid anhydride. From the viewpoint of storage stability, it is preferable to use phenol resins and imidazole derivatives. From the viewpoint of moisture-resistant adhesion, it is preferable to use aromatic amines. Among these, it is particularly preferable to contain at least one compound selected from liquid acid anhydrides, liquid phenol resins, and liquid aromatic amines as a curing agent, and more preferably to contain a liquid aromatic amine as a curing agent. Note that if the composition is liquid, a solid compound may be used as the curing agent, or a combination of liquid and solid compounds may be used.
  • acid anhydrides examples include phthalic anhydride, tetrahydrophthalic anhydride, 3-methyltetrahydrophthalic anhydride, himic anhydride, succinic anhydride, trimellitic anhydride, pyromellitic anhydride, etc. It may be used alone or in combination of two or more types.
  • the phenolic resin is not particularly limited as long as it has two or more phenolic hydroxyl groups in its molecule, and examples include phenols such as phenol, cresol, resorcinol, catechol, bisphenol A, bisphenol F, phenylphenol, and aminophenol.
  • Novolac type phenol resin allylated bisphenol A obtained by condensing or co-condensing naphthols such as ⁇ -naphthol, ⁇ -naphthol, dihydroxynaphthalene, etc. and a compound having an aldehyde group such as formaldehyde under an acidic catalyst.
  • allylated bisphenol F allylated naphthalene diol
  • phenol novolac phenol/aralkyl resin synthesized from phenols such as phenol and/or naphthols and dimethoxyparaxylene or bis(methoxymethyl)biphenyl, naphthol/aralkyl resin, etc. These may be used alone or in combination of two or more.
  • aromatic amines examples include Epicure W, Epicure Z (all trade names manufactured by Japan Epoxy Resin Co., Ltd.), Kayahard AA, Kayahard AB, and Kayahard AS (all manufactured by Nippon Kayaku Co., Ltd.). (trade name), Totoamine HM-205 (manufactured by Toto Kasei Co., Ltd., trade name), ADEKA Hardener EH-101 (manufactured by Asahi Denka Kogyo Co., Ltd., trade name), Epomic Q-640, Epomic Q-643 (all manufactured by Mitsui) (manufactured by Kagaku Co., Ltd., trade name), DETDA80 (manufactured by Lonza, trade name), etc., and these may be used alone or in combination of two or more kinds.
  • Imidazole derivatives include 2-methylimidazole, 2-undecylimidazole, 2-heptadecyl imidazole, 1,2-dimethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-phenyl-4-methyl Imidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-methylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, 1-cyanoethyl-2-undecylimidazole, 1-cyanoethyl-2-pheno limidazole, 1-cyanoethyl-2-ethyl-4-methylimidazolium trimellitate, 1-cyanoethyl-2-undecylimidazolium trimellitate, 1-cyanoethyl-2-phenylimidazolium trimellitate, 2,4 -Diamino-6-[2'-methylimidazoly
  • the equivalent ratio of the epoxy resin and the curing agent in the first liquid material is not particularly limited, but in order to reduce the amount of unreacted components, the amount of the curing agent relative to the epoxy resin should be in the range of 0.6 to 1.6 equivalents. It is preferable to set an equivalent amount, more preferably 0.7 to 1.4 equivalents, and even more preferably 0.8 to 1.2 equivalents. 0.6. If the amount is outside the range of 1.6 equivalents, unreacted components tend to increase and reliability tends to decrease.
  • the equivalent of phenolic resin is calculated assuming that one phenolic hydroxyl group reacts with one epoxy group, and the equivalent of aromatic amine is calculated as one active hydrogen of amino group reacts with one epoxy group.
  • the equivalent weight of acid anhydride is calculated assuming that one acid anhydride group reacts with one epoxy group. Since the imidazole derivative acts as a polymerization catalyst for the epoxy resin, the amount of the imidazole derivative to be added is determined in consideration of the curing speed and pot life of the composition.
  • the first liquid material may contain an inorganic filler.
  • Inorganic fillers are added to the epoxy resin composition for the purpose of reducing thermal expansion, providing rigidity, and thermal conductivity, and are usually fused silica, crystalline silica, alumina, silicon nitride, boron nitride, silicon carbide, etc. or the like can be used. By including an inorganic filler, the viscosity of the liquid epoxy resin composition can be adjusted.
  • the inorganic filler for example, spherical fused silica can be used.
  • substantially spherical fused silica As the spherical fused silica, it is preferable to use substantially spherical fused silica produced by heat-treating natural or synthetic silica by a thermal spraying method or the like.
  • substantially spherical means the following. That is, when natural or synthetic silica is heat-treated to make it spherical, particles that are not completely melted may not have a true spherical shape. In addition, a plurality of fused particles may coexist. Furthermore, the evaporated silica vapor may adhere to and solidify on the surfaces of other particles, resulting in spherical silica particles having fine particles attached thereto.
  • Substantially spherical means that particles with such shapes are allowed to coexist, but for example, the sphericity of a particle can be expressed as Wardell's sphericity [(diameter of a circle equal to the projected area of the particle)/(projected area of the particle) It is desirable that particles having this value of 0.9 or more account for 90% by weight or more of the entire inorganic filler.
  • the average particle size of the inorganic filler used in the liquid epoxy resin composition is preferably within the range of 0.3 ⁇ m to 5 ⁇ m.
  • the resin composition of the first liquid material may contain a curing accelerator, if necessary. Further, the resin composition of the first liquid material may contain a coupling agent, a flexibilizing agent, a coloring agent, and the like.
  • the curing accelerator is not particularly limited as long as it accelerates the curing reaction between the epoxy resin and the curing agent, which is commonly used in epoxy resin compositions, and various amine compounds, 2-ethyl-4- Imidazole compounds such as methylimidazole, organophosphine compounds, quaternary ammonium or phosphonium compounds, etc. can be used.
  • Cyclamidine compounds such as undecene-7 and these compounds include maleic anhydride, 1,4-benzoquinone, 2,5-torquinone, 1,4-naphthoquinone, 2,3-dimethylbenzoquinone, 2,6-dimethyl ⁇ of quinone compounds such as benzoquinone, 2,3-dimethoxy-5-methyl-1,4benzoquinone, 2,3-dimethoxy-1,4-benzoquinone, phenyl-1,4-benzoquinone, diazophenylmethane, phenol resin, etc.
  • tertiary amines such as benzyldimethylamine, triethanolamine, dimethylaminoethanol, tris(dimethylaminomethyl)phenol, and derivatives thereof, 2-methylimidazole , 2-phenylimidazole, 2-phenyl-4-methylimidazole, 2-heptadecylimidazole and other imidazoles and derivatives thereof, tributylphosphine, methyldiphenylphosphine, triphenylphosphine, tris(4-methylphenyl)phosphine, diphenyl Phosphine compounds such as organic phosphines such as phosphine and phenylphosphine, and intramolecular polarization obtained by adding compounds with ⁇ bonds such as the above quinone compounds, maleic anhydride, diazophenylmethane, and phenol resins to these phosphine compounds
  • phosphorus compounds such as tetra-substituted phosphonium/tetra-substituted borates such as tetraphenylphosphonium tetraphenylborate, tetraphenylphosphonium ethyltriphenylborate, tetrabutylphosphonium tetrabutylborate, 2-ethyl-4-methylimidazole/tetraphenylborate, N- Examples include tetraphenylboron salts such as methylmorpholine/tetraphenylborate and derivatives thereof, and one of these may be used alone or two or more may be used in combination.
  • Coupling agents have the effect of improving wetting of the inorganic filler with the resin and adhesion with the adherend, and specifically include ⁇ -(2-aminoethyl)aminopropyltrimethoxysilane, ⁇ -(2-aminoethyl ) Aminopropyldimethoxysilane, ⁇ -glycidoxypropyltrimethoxysilane, ⁇ -mercaptopropyltrimethoxysilane, ⁇ -anilinopropyltrimethoxysilane, ⁇ -ureidotrimethoxysilane, ⁇ -dibutylaminopropyltrimethoxysilane, imidazole Silane or the like can be used. Silicone and polyolefin elastomers or their powders can be used as the flexibilizing agent, and carbon black, organic dyes, organic pigments, titanium oxide, red lead, red iron oxide, and the like can be used as the coloring agents.
  • step (h) the curable first liquid material injected into the gap V between the first hybrid bonding structural component 40A and the substrate 10 in step (g) is cured in step (h), and as shown in FIG.
  • the second hybrid bonding structural component 40B is picked up by the bonding tool P and placed on top of the first hybrid bonding structural component 40A.
  • the second hybrid bonding structure component 40B is placed and pressed while being heated. Thereby, the second hybrid bonding structural component 40B is mounted.
  • the terminal electrode 31a of the fourth semiconductor chip 30B is connected to the terminal electrode 21a of the first semiconductor chip 20A via the second connection bump 50B.
  • a gap V is formed between the second hybrid bonding structural component 40B and the first hybrid bonding structural component 40A, except for the second connection bump 50B.
  • the semiconductor device shown in FIG. 1 can be obtained.
  • the second hybrid bonding structural component 40B is picked up by the bonding tool P without injecting the first liquid material, and the first hybrid
  • the second hybrid bonding structural component 40B is placed on the bonding structural component 40A and is pressed while being heated. Thereby, as shown in FIG. 7(a), the second hybrid bonding structure component 40B is mounted. At this time, no resin or the like is injected into any of the gaps V.
  • a step is performed to collectively seal the multiple stacked semiconductor chips.
  • the gap V between the substrate 10 and the first hybrid bonding structural component 40A, and the gap between the first hybrid bonding structural component 40A and the second hybrid bonding structural component 40B are A sealant is injected into the gap V between the two and hardened.
  • Such a sealant is also called MUF (Mold Underfill), and is, for example, a liquid resin containing a liquid epoxy resin, a curing agent containing a liquid aromatic amine, rubber particles, and an inorganic filler. Compositions can be used.
  • the rubber particles may be, for example, acrylic rubber.
  • a hybrid bonding structure S is manufactured using a hybrid bonding technique in which semiconductor chips (or semiconductor wafers, etc.) are bonded together and connected without using connection bumps.
  • connection bumps are formed on the hybrid bonding structure S, and this is diced to obtain a plurality of hybrid bonding structure components 40.
  • mounting is performed using the first hybrid bonding structural component 40A with such connection bumps, and the first liquid material is injected into the gap between it and other components to be mounted and hardened.
  • the manufacturing method because hybrid bonding technology is used to connect some semiconductor chips to each other, the thickness of the semiconductor device can be reduced compared to the case where all the connections between semiconductor chips are made using connection bumps. This makes it possible to reduce the height.
  • the manufacturing process was long because the stacked semiconductor chips were connected one by one by flip-chip, but according to the above semiconductor device manufacturing method, some semiconductor chips are connected to each other by hybrid bonding. Since it becomes possible to perform the process all at once using technology, it becomes possible to shorten the manufacturing process and improve productivity.
  • the method for manufacturing a semiconductor device includes a step of mounting the second hybrid bonding structural component 40B on the first hybrid bonding structural component 40A, and a step of mounting the second hybrid bonding structural component 40B and the first hybrid bonding structural component 40A.
  • the method further includes the steps of injecting a curable second liquid material into the gap V and curing the second liquid material. According to this manufacturing method, even when stacked semiconductor chips are multi-staged, it is possible to reduce the height of the semiconductor device. Furthermore, the manufacturing process of semiconductor devices can be shortened and productivity can be improved.
  • the step of injecting the first liquid material and the step of injecting the second liquid material may be performed separately. According to this manufacturing method, it is possible to more reliably inject the first liquid material and the second liquid material, and easily manufacture a highly reliable semiconductor device.
  • the method for manufacturing a semiconductor device may further include a step of sealing the first hybrid bonding structural component 40A and the second hybrid bonding structural component 40B, and a step of injecting the first liquid material and a second A step of injecting a liquid material may be performed during this sealing step.
  • a step of sealing the first hybrid bonding structural component 40A and the second hybrid bonding structural component 40B may further include a step of injecting the first liquid material and a second A step of injecting a liquid material may be performed during this sealing step.
  • the sealing material is used as an underfill material to protect the connection bumps all at once. It can be done by Therefore, according to this manufacturing method, the productivity of semiconductor devices can be further improved.
  • the other member is the substrate 10 on which the wiring electrode 12 is provided, and in the step of mounting the first hybrid bonding structure component 40A, the first hybrid bonding structure component The first hybrid bonding structure component 40A is mounted on the substrate 10 such that the first connection bump 50A of 40A is connected to the wiring electrode 12. According to this manufacturing method, it is possible to reduce the height of a semiconductor device in which a semiconductor chip is mounted on a substrate.
  • At least one of the first insulating film 76 of the first semiconductor substrate 70 and the second insulating film 86 of the second semiconductor substrate 80 may contain an inorganic insulating material. According to this manufacturing method, it is possible to manufacture a semiconductor device with a finer structure. Further, since the bond between inorganic materials can be easily made strong, it is possible to increase the adhesive strength between semiconductor chips and further improve the connection reliability as a semiconductor device.
  • At least one of the first insulating film 76 of the first semiconductor substrate 70 and the second insulating film 86 of the second semiconductor substrate 80 may contain an organic insulating material. According to this manufacturing method, debris generated when a semiconductor substrate is diced into semiconductor chips is absorbed (incorporated) into the insulating film portion made of the organic material using an organic material that is relatively soft, and the debris is bonded using hybrid bonding. It is possible to reduce connection failures between semiconductor chips that are connected to each other.
  • the organic insulating material included in at least one of the first insulating film 76 and the second insulating film 86 is polyimide, a polyimide precursor, polyamideimide, benzocyclobutene (BCB), It may also contain polybenzoxazole (PBO) or a PBO precursor.
  • PBO polybenzoxazole
  • the first insulating film etc. can be easily formed by spin coating or the like, and a thin film can be easily formed. Further, since these materials have high heat resistance, they can withstand high temperatures when bonding is performed by hybrid bonding, and it becomes possible to bond semiconductor chips together more reliably.
  • SYMBOLS 1 Semiconductor device, 10... Substrate (other parts), 12... Wiring electrode, 20A... First semiconductor chip, 20B... Third semiconductor chip, 21a... Terminal electrode, 21b... Through electrode, 22A... First insulating film, 22B... Third insulating film, 24A... First electrode, 24B... Third electrode, 26A... First semiconductor component, 26B... Third semiconductor component, 30A... Second semiconductor chip, 30B... Fourth semiconductor chip, 31a...
  • Second connection body 70...first semiconductor substrate, 72...first substrate body, 74...first electrode, 76...first insulating film, 80...second semiconductor substrate, 82...second substrate body, 84...second Electrode, 86...Second insulating film, S...Hybrid bonding structure, V...Gap.

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  • Wire Bonding (AREA)
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US18/857,185 US20250279392A1 (en) 2022-04-22 2022-04-22 Method for producing semiconductor device, and semiconductor device
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JP2015176958A (ja) * 2014-03-14 2015-10-05 株式会社東芝 半導体装置及びその製造方法
JP2020191334A (ja) * 2019-05-20 2020-11-26 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置及び電子機器

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