WO2023201649A1 - 多时隙收发信机和多时隙通信方法 - Google Patents

多时隙收发信机和多时隙通信方法 Download PDF

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Publication number
WO2023201649A1
WO2023201649A1 PCT/CN2022/088275 CN2022088275W WO2023201649A1 WO 2023201649 A1 WO2023201649 A1 WO 2023201649A1 CN 2022088275 W CN2022088275 W CN 2022088275W WO 2023201649 A1 WO2023201649 A1 WO 2023201649A1
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Prior art keywords
local oscillator
frequency
signal
oscillator signal
time slot
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PCT/CN2022/088275
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English (en)
French (fr)
Inventor
崔建伟
张宜成
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Hytera Communications Corp Ltd
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Hytera Communications Corp Ltd
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Priority to PCT/CN2022/088275 priority Critical patent/WO2023201649A1/zh
Publication of WO2023201649A1 publication Critical patent/WO2023201649A1/zh
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits

Definitions

  • the present application relates to the field of communication technology, and in particular to a multi-slot transceiver and a multi-slot communication method.
  • TDMA Time Division Multiple Address, Time Division Multiple Access
  • the frequency generating circuit is turned on and its frequency is in a locked state. Since the frequency generation circuit of the next time slot is opened in advance and the corresponding working link is initialized, the transmit frequency output by the frequency generation circuit in advance will be conducted to the RF (Radio Frequency, radio frequency) switch through the working link, thus interfering with the working receiving frequency. , or interfere with the receiving circuit working at the same frequency through the spatial coupling path, causing the bit error rate to increase and the sensitivity to decrease.
  • RF Radio Frequency, radio frequency
  • the main technical problem solved by this application is to provide a multi-time slot transceiver and a multi-time slot communication method, which can avoid the problem of co-channel interference of the multi-time slot transceiver.
  • the first aspect of this application provides a multi-slot transceiver, including a transmitter, a receiver and a frequency generation circuit.
  • the frequency generation circuit is connected to the transmitter and used to provide the transmitter with orthogonal local frequency.
  • the frequency generation circuit is used to generate the first orthogonal local oscillator signal, and at the beginning of the transmission time slot, the frequency generation circuit is used to generate the second orthogonal local oscillator signal signal;
  • the transmitter is configured to generate a first transmission signal based on the first orthogonal local oscillator signal, and generate a second transmission signal based on the second orthogonal local oscillator signal; wherein the frequency of the first transmission signal is different from the receiving frequency of the receiver , the frequency of the second transmitted signal is the same as the receiving frequency of the receiver.
  • the second aspect of this application provides a multi-time slot communication method, which is applied to a multi-time slot transceiver.
  • the multi-time slot transceiver includes a transmitter, a receiver and a frequency generation circuit.
  • the multi-time slot communication method includes: The frequency generation circuit generates a first orthogonal local oscillator signal at the first moment before the start of the transmission time slot, and inputs the first orthogonal local oscillator signal into the transmitter; the transmitter generates a first transmission signal based on the first orthogonal local oscillator signal ; The frequency generation circuit generates a second orthogonal local oscillator signal at the beginning of the transmission time slot, and inputs the second orthogonal local oscillator signal into the transmitter; the transmitter generates a second transmission signal based on the second orthogonal local oscillator signal; wherein, The frequency of the first transmitted signal is different from the receiving frequency of the receiver, and the frequency of the second transmitted signal is the same as the receiving frequency of the receiver.
  • the multi-slot transceiver in this application includes a transmitter, a receiver and a frequency generation circuit.
  • the frequency generation circuit is connected to the transmitter and is used to provide the transmitter with correct orthogonal local oscillator signal; wherein, at the first moment before the start of the transmission time slot, the frequency generation circuit is used to generate the first orthogonal local oscillator signal, and at the beginning of the transmission time slot, the frequency generation circuit is used to generate the second orthogonal local oscillator signal.
  • the transmitter is configured to generate a first transmit signal based on the first orthogonal local oscillator signal, and generate a second transmit signal based on the second orthogonal local oscillator signal; wherein the frequency of the first transmit signal is consistent with the reception frequency of the receiver.
  • the frequency is different, and the frequency of the second transmitted signal is the same as the receiving frequency of the receiver.
  • the frequency of the transmitter's transmit signal is controlled by changing the orthogonal local oscillator signal generated by the frequency generation circuit, so that the frequency of the first transmit signal generated in the receiving time slot is different from the receiving frequency of the receiver.
  • the frequency of the second transmission signal generated in the time slot is the same as the receiving frequency of the receiver, which not only ensures that the transmission circuit can operate normally at the beginning of the transmission time slot, but also solves the problem of interference with the receiving frequency due to the frequency generation circuit being turned on in advance. .
  • the frequency generation circuit is directly improved to avoid interference from the source.
  • the circuit structure is simple and the layout area of the circuit board is saved.
  • Figure 1 is a working sequence diagram of an existing multi-slot transceiver
  • Figure 2 is an interaction diagram of an existing multi-slot transceiver relay
  • FIG. 3 is a working sequence diagram of an existing multi-slot transceiver relay
  • Figure 4 is a working sequence diagram of a multi-slot transceiver
  • Figure 5 is a logic diagram of a multi-slot transceiver
  • Figure 6 is a schematic structural diagram of an embodiment of the multi-slot transceiver of the present application.
  • Figure 7 is a schematic structural diagram of another embodiment of the multi-slot transceiver of the present application.
  • Figure 8 is a schematic structural diagram of another embodiment of the multi-slot transceiver of the present application.
  • Figure 9 is a schematic structural diagram of a multi-slot transceiver according to another embodiment of the present application.
  • Figure 10 is a logical schematic diagram of yet another embodiment of the multi-slot transceiver of the present application.
  • Figure 11 is a working sequence diagram of a multi-slot transceiver
  • Figure 12 is a schematic flow chart of an embodiment of the multi-slot communication method of the present application.
  • FIG. 13 is a schematic flowchart of an implementation of step S11 in Figure 12;
  • FIG. 14 is a schematic flowchart of another implementation of step S11 in FIG. 12 .
  • first and second in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • plural means at least two, such as two, three, etc., unless otherwise clearly and specifically limited.
  • the terms “including” and “having” and any variations thereof are intended to cover non-exclusive inclusion.
  • a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.
  • Figure 1 is a working sequence diagram of the existing multi-slot transceiver.
  • Figure 2 is an interaction diagram of the relay of the existing multi-slot transceiver.
  • Figure 3 is a diagram of the existing multi-slot transceiver. The following working sequence diagram.
  • Tetra Trans European Trunked Radio
  • Tetra digital trunking communication system is a professional mobile communication system based on TDMA technology. The general system consists of base stations and mobile terminals.
  • Tetra terminal working modes can be divided into DMO (Direct Mode Operation, direct working mode) and TMO (Trunked Mode Operation, cluster working mode), which are four-time slot working modes.
  • Tetra terminal is a multi-slot transceiver. As shown in Figure 1, the first time slot T1 transmits a signal, the third time slot T3 receives a signal, the second time slot T2 and the fourth time slot T4 are in idle mode, each time slot can be 14.167ms, so that it can be Each working time slot leaves ample preparation time so that the hardware circuit can prepare for work in advance.
  • Tetra terminals can have repeater functions (referred to as relay terminals). As shown in Figure 2, the relay terminal is used to connect two Tetra terminals working normally in DMO mode, thereby doubling the communication distance of the Tetra terminals working in DMO mode. For the relay terminal, all four time slots need to be occupied to transfer the signals transmitted by the two DMO call terminals, so as to increase the call distance and realize the forwarding function.
  • the working sequence diagram is shown in Figure 3. Show. Since the four time slots are occupied, the receiving time slot RX or the transmitting time slot TX does not have time to provide the locking time of the frequency generating circuit 13, so the frequency generating circuit 13 needs to be opened in advance in the previous time slot to perform pre-locking.
  • Figure 4 is a working sequence diagram of a multi-time slot transceiver
  • Figure 5 is a logic diagram of a multi-time slot transceiver.
  • three adjacent time slots are taken as an example for explanation. From left to right, they are the first time slot, the second time slot and the third time slot.
  • the frequency generation circuit 13 of the next working time slot is turned on, and at time t1, the initialization of the working link (such as the modulator of the transmitter or the demodulator of the receiver) of the next working time slot is turned on.
  • the initialization of the working link such as the modulator of the transmitter or the demodulator of the receiver
  • the third time slot is working in the transmitting state
  • the frequency generation circuit 13 of the transmitter needs to be turned on to ensure that it is in a locked state before the arrival of the third time slot.
  • the t1 moment before the start of the third time slot is the initialization time for the transmitter to open some channels (such as modulators) in advance.
  • some channels such as modulators
  • the frequency generation circuit 13 of the transmitter needs to be turned on to ensure that it is in the second time slot. It is locked before the gap arrives.
  • the t1 moment before the start of the second time slot is the initialization time for the transmitter to open some channels in advance.
  • the frequency generation circuit of the transmitter (such as the phase-locked loop shown in Figure 5 TX PLL and voltage controlled oscillator TXVCO) are turned on at the t0 moment of the receiving time slot.
  • the transmitting circuit is opened for initialization (such as the modulator is turned on) at the t1 moment of the receiving time slot.
  • the modulator outputs the transmitting frequency TX_F through the radio frequency power amplifier.
  • Receiver circuits working at the same frequency increase their bit error rate and reduce their sensitivity.
  • FIG. 6 is a schematic structural diagram of an embodiment of a multi-slot transceiver of the present application.
  • the multi-slot transceiver of the present application can be applied to TDMA systems and can support relay functions.
  • the multi-slot transceiver 10 includes at least a transmitter 11, a receiver 12 and a frequency generation circuit 13.
  • the frequency generation circuit 13 is connected to the transmitter 11 and is used to provide the transmitter 11 with an orthogonal local oscillator signal.
  • the frequency generation circuit 13 is used to generate the first orthogonal local oscillator signal Z1
  • the frequency generation circuit 13 is used to generate the second Quadrature local oscillator signal Z2.
  • the first orthogonal local oscillator signal Z1 and the second orthogonal local oscillator signal Z2 have different frequencies.
  • the transmitting time slot is the time slot operating in the transmitting state
  • the receiving time slot is the time slot operating in the receiving state.
  • the transmitter 11 is configured to generate a first transmission signal F1 based on the first orthogonal local oscillator signal Z1, and to generate a second transmission signal F2 based on the second orthogonal local oscillator signal Z2.
  • the frequency of the transmission signal of the transmitter 11 can be controlled by controlling the frequency of the orthogonal local oscillator signal generated by the frequency generation circuit 13, so that The frequency of the first transmission signal F1 generated in the reception time slot is different from the reception frequency of the receiver 12, and the frequency of the second transmission signal F2 generated in the transmission time slot is the same as the reception frequency of the receiver 12, so not only This ensures that the transmitting circuit can operate normally at the beginning of the transmitting time slot, and can also solve the problem of interfering with the receiving frequency due to the frequency generation circuit 13 being turned on in advance. Secondly, the frequency generation circuit 13 is directly improved to avoid interference from the source. The circuit structure is simple and the layout area of the circuit board is saved.
  • FIG. 7 is a schematic structural diagram of a multi-slot transceiver according to another embodiment of the present application.
  • the frequency generation circuit 13 may include a local oscillator 131 (Local Oscillator, LO) and a frequency divider 132.
  • the local oscillator 131 is used to generate a local oscillator signal.
  • the frequency divider 132 is connected to the local oscillator 131 and the transmitter 11 respectively, and is used to convert the local oscillator signal into a quadrature local oscillator signal according to a preset frequency division ratio.
  • the preset frequency division ratio includes a first frequency division ratio and a second frequency division ratio, and the first frequency division ratio and the second frequency division ratio are different.
  • the frequency divider 132 is used to convert the local oscillator signal into a first orthogonal local oscillator signal according to the first frequency division ratio at the first moment before the start of the transmission time slot; Initially, the frequency divider 132 converts the local oscillator signal into a second quadrature local oscillator signal according to the second frequency division ratio.
  • the local oscillator 131 may be a voltage-controlled oscillator, which is an oscillation circuit whose output frequency has a corresponding relationship with the input control voltage.
  • the working state of the voltage-controlled oscillator or the component parameters of the oscillation circuit are controlled by the input control voltage, and its output The frequency changes with the change of the external control voltage.
  • the frequency divider 132 may be a division circuit, such as a divide-by-two circuit, used to divide the local oscillator signal by two. Through research by the inventor of the present application, it is found that the frequency divider 132 can quickly switch the frequency division ratio. Based on this, a frequency division ratio different from that at t0 time to t2 time can be set. When the transmitter 11 switches the frequency division ratio between t0 time and t2 time, The frequency ratio can change the frequency of the transmitted signal, thereby avoiding the problem of co-channel interference in adjacent time slots.
  • the frequency of the local oscillator signal generated by the local oscillator 131 is a first number of times the frequency of the second transmission signal F2.
  • the second frequency division ratio is 2.
  • the purpose is that after frequency division, the local oscillator signal can generate an orthogonal local oscillator signal with the same frequency as the second transmission signal. Since the first frequency division ratio is different from the second frequency division ratio, when the second frequency division ratio is 2, the first frequency division ratio may be 1, 4, 8, etc.
  • the frequency of the local oscillator signal generated by the local oscillator 131 is 1 times the frequency of the first transmission signal F1; when the first frequency division ratio is 4, the local oscillator 131 generates The frequency of the local oscillator signal is 4 times the frequency of the first transmission signal F1; when the first frequency division ratio is 8, the frequency of the local oscillator signal generated by the local oscillator 131 is 8 times the frequency of the first transmission signal F1 .
  • the frequency of the first transmission signal F1 corresponding to the frequency division ratio is 1 is 800M, and the frequency of the first transmission signal F1 corresponding to the frequency division ratio is 4.
  • the frequency of F1 is 200M, and the frequency of the first transmission signal F1 corresponding to the frequency division ratio of 8 is 100M.
  • FIG. 8 is a schematic structural diagram of a multi-slot transceiver according to another embodiment of the present application.
  • the multi-slot transceiver also includes a frequency multiplier 133.
  • the frequency multiplier 133 is connected to the local oscillator 131 and is used to increase the frequency of the local oscillator signal.
  • the frequency divider 132 is connected to the frequency multiplier 133 and the transmitter 11 respectively, and is used to convert the frequency-raised local oscillator signal into a first orthogonal local oscillator signal according to the first frequency division ratio at the first moment before the start of the transmission time slot.
  • the first frequency division ratio and the second frequency division ratio different.
  • the frequency of the local oscillator signal generated by the local oscillator 131 is a second number multiple of the frequency of the second transmission signal, and the second number is smaller than the first number.
  • the frequency multiplier 133 is used to increase the frequency of the local oscillator signal generated by the local oscillator 131 to a first multiple of the frequency of the second transmission signal before inputting it into the frequency divider 132 .
  • the frequency multiplier 133 may be a frequency tripler, used to increase the frequency of the input signal by three times.
  • the local oscillator signal can be increased to twice the frequency of the second transmission signal through the frequency multiplier 133 .
  • the second quantity multiple can also be times, the frequency multiplier 133 can be a quadruple frequency multiplier, or the second number of times can also be times, the frequency multiplier 133 can be a five-fold frequency multiplier, which is not limited here.
  • orthogonal modulation requires that the frequency at which the local oscillator itself oscillates (that is, the frequency of the local oscillator signal) is twice the frequency of the antenna port. For example: if the frequency transmitted by the antenna port is 400M, then the oscillation frequency is 800M. The antenna port will generate harmonics when transmitting frequency. The frequency of harmonics is, for example, 400M, 800M or 1200M, and 800M is the same frequency as the local oscillator signal, which will interfere with the phase noise of the local oscillator.
  • the frequency of the local oscillator signal can be After the local oscillator signal passes through the frequency tripler, it can be The frequency is increased to 800M, so that the frequency transmitted by the antenna port is still 400M, but the harmonics at this time are different from the frequency of the local oscillator signal, so that they will not interfere with the phase noise of the local oscillator.
  • the frequency generation circuit 13 may also include a register, which is used to register a preset frequency division ratio, including a first frequency division ratio and a second frequency division ratio.
  • the type of register is not limited, for example, it can be an 8-bit register, a 16-bit register, a 32-bit register, etc.
  • the 8-bit register includes 8 bits (bits), namely b0 ⁇ b7.
  • the fifth bit b4 is selected to register the variable DIV corresponding to the preset frequency division ratio. This variable is controlled by the frequency divider 132 .
  • the divide-by-4 mode will be started.
  • the divide-by-2 mode will be started.
  • the variables f1 and f2 of bits b0 and b1 are used to register other data, such as user flags. Bits b2-b3 and b5-b7 are set to 0 and reserved for future use.
  • FIG. 9 is a schematic structural diagram of a multi-slot transceiver according to another embodiment of the present application.
  • the transmitter 11 includes a Cartesian loop circuit 111, an amplifier 112 and a coupler 113 connected in sequence, and the Cartesian loop circuit 111, the amplifier 112 and the coupler 113 form a Cartesian negative feedback loop.
  • the Cartesian loop circuit 111 is connected to the frequency generation circuit 13 for receiving the baseband signal (I, Q signals) and the orthogonal local oscillator signal.
  • the signal I and the signal Q are in an orthogonal relationship, and the signal I and the signal Q are analog time domain signals.
  • the Cartesian loop circuit 111 uses the quadrature local oscillator signal to modulate and up-convert the baseband signal and then sends it to the amplifier 112.
  • the amplifier 112 amplifies the received signal and sends it to the coupler 113.
  • the coupler 113 amplifies the received signal.
  • the transmit signal and feedback signal are obtained through processing, and the coupler 113 sends the feedback signal to the Cartesian loop circuit 111 for demodulation.
  • the coupler 113 obtains the first transmit signal
  • the coupler 113 obtains the second orthogonal local oscillator signal
  • the coupler 113 obtains the third 2. Transmit signal.
  • the coupler 113 is connected to the antenna and is used to transmit the first transmission signal and the second transmission signal output by the amplifier 112 through the antenna.
  • the receiver 12 and the transmitter 11 may share one antenna.
  • the feedback signal in the Cartesian negative feedback loop is coupled through the coupler 113 and restored to two orthogonal baseband signals (recorded as restored baseband signals).
  • the Cartesian loop circuit 111 compares the two baseband signals and restores The difference value of the baseband signal is subjected to forward I/Q signal pre-distortion processing and then up-converted, and is synthesized into a signal and sent to the amplifier 112 to achieve the purpose of compensating for the nonlinear distortion of the radio frequency transmitter 11.
  • the amplifier 112 may include a power amplifier, which is connected to the Cartesian loop circuit 111 and is used for current amplification of the signal output by the Cartesian loop circuit 111 .
  • the amplifier 112 may also include a signal amplifier.
  • the signal amplifier is connected to the Cartesian loop circuit 111 and the power amplifier, and is used to amplify the voltage of the signal output by the Cartesian loop circuit 111 and then input it into the power amplifier.
  • the amplifier 112 may also be a three-stage amplifier, but is not limited thereto.
  • the Cartesian loop circuit 111 is composed of two uplink and downlink paths.
  • the uplink path modulates the baseband signal and sends it to the amplifier 112.
  • the downlink path couples part of the uplink signal through the coupler 113, and then sends it to the Cartesian loop circuit 111 for demodulation.
  • the downlink path couples one hundredth or one thousandth of the uplink signal through the coupler 113.
  • the Cartesian loop circuit 111 compares the difference between the transmitted baseband signal and the demodulated baseband signal, and then performs pre-distortion processing on the uplink baseband signal to achieve the purpose of linearization.
  • transmitter 11 may include at least part of the circuitry of frequency generation circuit 13 .
  • the built-in division circuit in the Cartesian loop circuit 111 can be used as the frequency divider 132 .
  • the local oscillator signal generated by the local oscillator 131 is input to the division circuit in the transmitter 11 for frequency division processing to obtain an orthogonal local oscillator signal, which is then input to the up modulator 1113 and down modulator 1116 in Figure 10 for orthogonal modulation. deal with.
  • FIG. 10 is a logical schematic diagram of yet another embodiment of the multi-slot transceiver of the present application.
  • the Cartesian loop circuit 111 includes an uplink path and a downlink path.
  • the uplink path includes an input amplifier 1111, an upper error amplifier 1112, an up modulator 1113 and a first upper attenuator 1114 that are connected in sequence.
  • the downlink path includes a first lower attenuator that is connected in sequence. 1115, down modulator 1116 and down error amplifier 1117.
  • the upper error amplifier 1112 is connected to the lower error amplifier 1117, the upper modulator 1113 and the lower modulator 1116 are respectively connected to the frequency generation circuit 13, the first upper attenuator 1114 is connected to the amplifier 112, and the first lower attenuator 1115 is connected to the coupler 113.
  • the first down attenuator 1115 inputs the feedback signal, attenuates the feedback signal and outputs it to the down modulator 1116 .
  • the down modulator 1116 is used to modulate the attenuated feedback signal and the quadrature local oscillator signal output by the frequency generation circuit 13 to obtain a restored baseband signal and output the restored baseband signal to the lower error amplifier 1117 .
  • the input amplifier 1111 is used to amplify the baseband signal and output it to the upper error amplifier 1112 .
  • the upper error amplifier 1112 is used to compare the restored baseband signal with the amplified baseband signal to obtain a difference signal.
  • the upper modulator 1113 is used to modulate the difference signal and the orthogonal local oscillator signal output by the frequency generation circuit 13, and output the modulated signal to the first upper attenuator 1114.
  • the first upper attenuator 1114 modulates the The processed signal is subjected to attenuation processing, and the attenuated signal is output to the amplifier 112 .
  • the baseband signal is amplified by the input amplifier 1111 and then input to the upper error amplifier 1112.
  • the feedback signal coupled from the coupler 113 in the downstream path is attenuated by the first lower attenuator 1115 and then input to the lower modulator 1116.
  • the modulator 1116 restores it to two orthogonal baseband signals (recorded as restored baseband signals), and then inputs the upper error amplifier 1112 through the lower error amplifier 1117 for signal comparison, and uses the obtained difference signal as a forward I/Q signal.
  • the signal is up-converted and synthesized into one signal, which is then attenuated by the first upper attenuator 1114 and then sent to the amplifier 112 to achieve the purpose of compensating the non-linear distortion of the transmitter 11 .
  • the first upper attenuator 1114 controls the output power of the Cartesian loop circuit 111
  • the first lower attenuator 1115 is used to control the input power of the Cartesian loop circuit 111 to accurately attenuate the signal, and its accuracy is Can reach 1dB.
  • the transmitter 11 may also include a second upper attenuator 114 and/or a second lower attenuator 115 to play a matching role.
  • Appropriate models and other parameters may be selected according to the actual circuit structure.
  • the second upper attenuator 114 is connected to the first upper attenuator 1114 and the amplifier 112, and is used to assist in attenuating the signal to ensure better reflection coefficients of the front and rear stages of the amplifier and prevent mutual influence between stages.
  • the second lower attenuator 115 is connected to the coupler 113 and the first lower attenuator 1115, and is used to pre-attenuate the feedback signal coupled by the coupler 113 to prevent the feedback signal from being strong and burning the Cartesian loop circuit 111 or downlink. Front-end circuitry in the path.
  • the second upper attenuator 114 and/or the second lower attenuator 115 may include resistors.
  • the transmitter 11 may also include a filter 116 connected to the first lower attenuator 1115 and the second lower attenuator 115 for filtering out harmonics generated by the amplifier 112 .
  • the filter 116 is, for example, a low-pass filter.
  • Figure 11 is an operating timing diagram of a multi-slot transceiver.
  • the time period between time t2 and t3 the size of the guard time period is approximately equal to 0.94ms.
  • the actual test method of modifying the frequency division ratio was 90% shorter than the response time of modifying the frequency division ratio in the simulation test.
  • the modification of the frequency division ratio can be achieved within 100us, which is far less than the protection time of 0.94ms. It is also That is to say, when the guard time ends, the transmitting circuit is ready, and when the receiving time slot changes to the transmitting time slot, the signal can be transmitted promptly and accurately without co-channel interference, so this solution is feasible.
  • the frequency multiplier when the frequency multiplier is tested in repeater mode, based on this solution, there is no interference between the receiving time slot and the transmitting time slot, that is, the transmission preparation affects the receiver's bit error rate to 0, which can reduce
  • the current consumption of the frequency multiplier is approximately 6mA average current.
  • FIG 12 is a schematic flow chart of an embodiment of the multi-slot communication method of the present application.
  • the multi-slot communication method is applied to the multi-slot transceiver in the above embodiment.
  • the multi-slot transceiver includes a transmitter, a receiver and a frequency generation circuit. The method may include the following steps:
  • the frequency generation circuit generates the first orthogonal local oscillator signal at the first moment before the start of the transmission time slot, and inputs the first orthogonal local oscillator signal into the transmitter.
  • the transmitter generates a first transmission signal based on the first orthogonal local oscillator signal.
  • the frequency generation circuit generates the second orthogonal local oscillator signal at the beginning of the transmission time slot, and inputs the second orthogonal local oscillator signal into the transmitter.
  • the transmitter generates a second transmission signal based on the second orthogonal local oscillator signal; wherein the frequency of the first transmission signal is different from the reception frequency of the receiver, and the frequency of the second transmission signal is the same as the reception frequency of the receiver.
  • Step S11 is a schematic flowchart of an implementation of step S11 in FIG. 12 .
  • the frequency generation circuit includes a local oscillator and a frequency divider.
  • Step S11 may include sub-steps S1111 and S1112:
  • the local oscillator generates a local oscillator signal.
  • the frequency divider converts the local oscillator signal into the first orthogonal local oscillator signal according to the first frequency division ratio at the first moment before the start of the transmission time slot, and inputs the first orthogonal local oscillator signal into the transmitter.
  • the first frequency division ratio is a multiple of the frequency of the local oscillator signal generated by the local oscillator and the frequency of the first transmission signal.
  • the above step S13 may be: the frequency divider converts the local oscillator signal into a second orthogonal local oscillator signal according to the second frequency division ratio at the beginning of the transmission time slot, and inputs the second orthogonal local oscillator signal into the transmitter. .
  • the second frequency division ratio is a multiple of the frequency of the local oscillator signal generated by the local oscillator and the frequency of the second transmission signal, and the second frequency division ratio is different from the first frequency division ratio.
  • the first frequency division ratio is 1, 4, or 8, and the second frequency division ratio is 2.
  • the local oscillator generates a local oscillator signal with a frequency that is a first number of times the frequency of the second transmit signal.
  • the frequency generation circuit includes a local oscillator, a frequency multiplier and a frequency divider.
  • the frequency multiplier is connected to the local oscillator and is used to increase the frequency of the local oscillator signal.
  • the frequency divider is connected to the frequency multiplier and the transmitter respectively.
  • Step S11 may include sub-steps S1121 to S1123:
  • the local oscillator generates a local oscillator signal.
  • the frequency multiplier increases the frequency of the local oscillator signal.
  • the frequency divider converts the frequency-raised local oscillator signal into the first orthogonal local oscillator signal according to the first frequency division ratio at the first moment before the start of the transmission time slot, and inputs the first orthogonal local oscillator signal into the transmission machine.
  • the above step S13 may be: the frequency divider converts the frequency-raised local oscillator signal into a second orthogonal local oscillator signal according to the second frequency division ratio at the beginning of the transmission time slot, and converts the second orthogonal local oscillator signal into The signal is input to the transmitter, and the first frequency division ratio and the second frequency division ratio are different.
  • the frequency of the local oscillator signal generated by the local oscillator is a second number times the frequency of the second transmission signal, and the second number is smaller than the first number.
  • the frequency multiplier may increase the frequency of the local oscillator signal generated by the local oscillator to a second multiple of the frequency of the second transmitted signal.
  • the frequency multiplier increases the frequency of the local oscillator signal generated by the local oscillator to a first multiple of the frequency of the second transmission signal and then inputs it into the frequency divider.
  • the scheme of switching the frequency division ratio of this application is simple in principle and highly feasible. It can not only theoretically avoid co-channel interference in transmitting and receiving time slots, but also save current consumption. In addition, it can also save PCB layout area and production costs. Compared with other methods of blocking signals through switches, the interference isolation effect of this application is better.
  • the disclosed methods and devices can be implemented in other ways.
  • the device implementation described above is only illustrative.
  • the division of modules or units is only a logical function division.
  • there may be other division methods for example, multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • a unit described as a separate component may or may not be physically separate.
  • a component shown as a unit may or may not be a physical unit, that is, it may be located in one place, or it may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software functional units.
  • Integrated units may be stored in a computer-readable storage medium if they are implemented in the form of software functional units and sold or used as independent products.
  • the technical solution of the present application is essentially or contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including a number of instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the various implementation methods of this application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code. .

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Abstract

本申请公开了一种多时隙收发信机和多时隙通信方法。其中，多时隙收发信机包括发射机、接收机和频率产生电路，频率产生电路，与发射机连接，用于为发射机提供正交本振信号；其中，在发射时隙开始前的第一时刻，频率产生电路用于产生第一正交本振信号，以及在发射时隙开始时，频率产生电路用于产生第二正交本振信号；发射机用于基于第一正交本振信号产生第一发射信号，以及基于第二正交本振信号产生第二发射信号；其中，第一发射信号的频率与接收机的接收频率不同，第二发射信号的频率与接收机的接收频率相同。通过上述方式，本申请能够避免多时隙收发信机的同频干扰问题。

Description

多时隙收发信机和多时隙通信方法 【技术领域】
本申请涉及通信技术领域，特别是涉及一种多时隙收发信机和多时隙通信方法。
【背景技术】
随着科技日益发展，无线通信飞速发展，TDMA(Time Division MultipleAddress，时分多址)系统的发展应用机遇与挑战并存，稳定TDMA系统应用产品的性能可为TDMA系统价值最大化提供一臂之力。
对于TDMA系统而言，当相邻两个时隙都处于发射或者接收状态时，由于FGU(Frequency Generate Unit，频率产生单元)电路(又可以称为频率产生电路)锁定时间的限制，需要在工作时隙到来之前打开频率产生电路并使其频率处于锁定状态。由于下一时隙的频率产生电路提前打开和对应工作链路初始化，频率产生电路提前输出的发射频率会通过工作链路传导至RF(Radio Frequency，射频)开关处，从而干扰到正在工作的接收频率，或者通过空间耦合的路径，干扰到处于同一频率工作的接收电路，使其误码率升高，灵敏度降低。
【发明内容】
本申请主要解决的技术问题是提供一种多时隙收发信机和多时隙通信方法，能够避免多时隙收发信机的同频干扰问题。
为解决上述技术问题，本申请第一方面提供了一种多时隙收发信机，包括发射机、接收机和频率产生电路，频率产生电路，与发射机连接，用于为发射机提供正交本振信号；其中，在发射时隙开始前的第一时刻，频率产生电路用于产生第一正交本振信号，以及在发射时隙开始时，频率产生电路用于产生第二正交本振信号；发射机用于基于第一正交本振信号产生第一发射信号，以及基于第二正交本振信号产生第二发射信号；其中，第一发射信号的频率与接收机的接收频率不同，第二发射信号的频率与接收机的接收频率相同。
为解决上述技术问题，本申请第二方面提供了一种多时隙通信方法，应用于多时隙收发信机，多时隙收发信机包括发射机、接收机和频率产生电路，多时隙通信方法包括：频率产生电路在发射时隙开始前的第一时刻产生第一正交 本振信号，并将第一正交本振信号输入发射机；发射机基于第一正交本振信号产生第一发射信号；频率产生电路在发射时隙开始时产生第二正交本振信号，并将第二正交本振信号输入发射机；发射机基于第二正交本振信号产生第二发射信号；其中，第一发射信号的频率与接收机的接收频率不同，第二发射信号的频率与接收机的接收频率相同。
本申请的有益效果是：区别于现有技术的情况，本申请中的多时隙收发信机包括发射机、接收机和频率产生电路，频率产生电路与发射机连接，用于为发射机提供正交本振信号；其中，在发射时隙开始前的第一时刻，频率产生电路用于产生第一正交本振信号，以及在发射时隙开始时，频率产生电路用于产生第二正交本振信号；发射机用于基于第一正交本振信号产生第一发射信号，以及基于第二正交本振信号产生第二发射信号；其中，第一发射信号的频率与接收机的接收频率不同，第二发射信号的频率与接收机的接收频率相同。以上，通过改变频率产生电路产生的正交本振信号以控制发射机的发射信号的频率，使其在接收时隙中产生的第一发射信号的频率与接收机的接收频率不同，而在发射时隙中产生的第二发射信号的频率与接收机的接收频率相同，从而不仅保证发射电路可以在发射时隙开始时可以正常运行，还可以解决由于频率产生电路提前开启而干扰接收频率的问题。其次，直接对频率产生电路进行改进，从源头规避干扰，电路结构简单，节省了电路板的布局面积。
【附图说明】
为了更清楚地说明本申请中的技术方案，下面将对实施例描述中所需要的附图作简单的介绍，显而易见地，下面描述的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来说，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有多时隙收发信机的工作时序图；
图2是现有多时隙收发信机中继的交互图；
图3是现有多时隙收发信机中继的工作时序图；
图4是一种多时隙收发信机的工作时序图；
图5是一种多时隙收发信机的逻辑图；
图6是本申请多时隙收发信机一实施例的结构示意图；
图7为本申请多时隙收发信机另一实施例的结构示意图；
图8为本申请多时隙收发信机又一实施例的结构示意图；
图9为本申请多时隙收发信机再一实施例的结构示意图；
图10是本申请多时隙收发信机的再又一实施例的逻辑示意图；
图11为一种多时隙收发信机的工作时序图；
图12是本申请多时隙通信方法一实施例的流程示意图；
图13是图12中步骤S11的一实施方式的流程示意图；
图14是图12中步骤S11的另一实施方式的流程示意图。
【具体实施方式】
在本申请中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
本申请中的术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1至图3，图1是现有多时隙收发信机的工作时序图，图2是现有多时隙收发信机中继的交互图，图3是现有多时隙收发信机中继的工作时序图。
Tetra(Trans European Trunked Radio，泛欧集群无线电)是一种面向下一代数字式移动通信的开放式标准；它的主要优点是兼容性好、开放性好、频谱利用率高以及保密性强，它是参与厂商最多的数字集群通信系统。Tetra数字集群 通信系统是基于TDMA技术的专业移动通信系统，一般系统由基站和移动终端组成。
Tetra终端工作模式可以分为DMO(Direct Mode Operation，直接工作方式)和TMO(Trunked Mode Operation，集群工作方式)，它们是四时隙工作方式。Tetra终端属于一种多时隙收发信机。如图1所示，第一时隙T1发射信号，第三时隙T3接收信号，第二时隙T2和第四时隙T4处于空闲模式，每个时隙可以为14.167ms，以便能够在每个工作时隙留有充裕的准备时间，使得硬件电路提前做好工作准备。
Tetra终端可以具有中继器功能(简称中继终端)。如图2所示，中继终端用于连接两个正常工作的DMO模式的Tetra终端，进而将工作于DMO模式下的Tetra终端通信距离增加一倍。对中继终端而言，需要将所有四个时隙占满来实现对两个DMO通话终端的所发射信号进行转接，以达增加通话距离实现转发的功能，其工作时序图如图3所示。由于四个时隙被占满，接收时隙RX或发射时隙TX没有时间来提供频率产生电路13的锁定时间，所以需要在前一个时隙提前打开频率产生电路13，进行预锁定。
请参阅图4，图4是一种多时隙收发信机的工作时序图，图5是一种多时隙收发信机的逻辑图。如图4所示，以相邻的三个时隙为例进行说明，从左至右依次为第一时隙、第二时隙和第三时隙。
在每一时隙的t0时刻打开下一工作时隙的频率产生电路13，t1时刻打开下一工作时隙的工作链路(例如发射机的调制器或接收机的解调器)的初始化。例如，当第二时隙工作在接收状态(即第二时隙作为接收时隙)，第三时隙工作在发射状态(即第三时隙作为发射时隙)时，在第三时隙到来之前的t0时刻，需要打开发射机的频率产生电路13，确保其在第三时隙到来之前已经处于锁定状态。第三时隙开始前的t1时刻，是发射机提前打开部分通道(例如调制器)的初始化时间。而当第二时隙工作在发射状态，第一时隙处于接收状态时，同理，在第二时隙到来之前的t0时刻，需要打开发射机的频率产生电路13，确保其在第二时隙到来之前已经处于锁定状态。而第二时隙开始前的t1时刻，是发射机提前打开部分通道的初始化时间。
如图5所示，在多时隙收发信机中，当连续两个工作时隙有接收转发射，且接收和发射同频时，发射机的频率产生电路(例如图5所示的锁相环TX PLL和压控振荡器TXVCO组成)在接收时隙的t0时刻就已打开，发射电路在接收 时隙的t1时刻打开初始化(如调制器打开)，调制器输出发射频率TX_F，通过射频功率放大器PA传导至RF开关处，但是此时接收器正输入接收频率RX_F，发射频率与接收频率相同(即TX_F＝RX_F)，从而干扰到正在工作的接收频率RX_F；或者通过空间耦合的路径，干扰到处于同一频率工作的接收电路，使其误码率升高，灵敏度降低。
请参阅图6，图6是本申请多时隙收发信机一实施例的结构示意图。本申请的多时隙收发信机可以应用于TDMA系统，且可以支持中继功能。多时隙收发信机10至少包括发射机11、接收机12和频率产生电路13。
结合图4和图6，频率产生电路13与发射机11连接，用于为发射机11提供正交本振信号。其中，在发射时隙TX开始前的第一时刻t0，频率产生电路13用于产生第一正交本振信号Z1，以及在发射时隙RX开始时t2，频率产生电路13用于产生第二正交本振信号Z2。可以理解的，第一正交本振信号Z1和第二正交本振信号Z2的频率不同。在本实施例中，发射时隙即工作于发射状态的时隙，接收时隙即工作于接收状态的时隙。
发射机11用于基于第一正交本振信号Z1产生第一发射信号F1，以及基于第二正交本振信号Z2产生第二发射信号F2。其中，第一发射信号F1的频率与接收机12的接收频率F0不同，第二发射信号F2的频率与接收机12的接收频率F0相同，即F1≠F0，F2＝F0。
由此，在连续两个工作时隙有接收转发射，且接收和发射同频时，通过控制频率产生电路13产生的正交本振信号的频率可以控制发射机11的发射信号的频率，使其在接收时隙中产生的第一发射信号F1的频率与接收机12的接收频率不同，而在发射时隙中产生的第二发射信号F2的频率与接收机12的接收频率相同，从而不仅保证发射电路可以在发射时隙开始时可以正常运行，还可以解决由于频率产生电路13提前开启而干扰接收频率的问题。其次，直接对频率产生电路13进行改进，从源头规避干扰，电路结构简单，节省了电路板的布局面积。
请参阅图7，图7为本申请多时隙收发信机另一实施例的结构示意图。
频率产生电路13可以包括本地振荡器131(Local Oscillator，LO)和分频器132。本地振荡器131用于产生本振信号。分频器132分别与本地振荡器131和发射机11连接，用于按照预设分频比将本振信号转换为正交本振信号。预设分频比包括第一分频比和第二分频比，第一分频比与第二分频比不同。其中， 分频器132用于在发射时隙开始前的第一时刻，分频器132按照第一分频比将本振信号转换为第一正交本振信号；以及用于在发射时隙开始时，分频器132按照第二分频比将本振信号转换为第二正交本振信号。
本地振荡器131可以为压控振荡器，其为输出频率与输入的控制电压有对应关系的振荡电路，压控振荡器的工作状态或振荡回路的元件参数受输入的控制电压的控制，其输出频率随外加控制电压的变化而变化。分频器132可以为除法电路，例如除二电路，用于将本振信号进行二分频。经过本申请发明人的研究发现，分频器132能够快速切换分频比，基于此，可以在t0时刻设置与t2时刻不同的分频比，当发射机11在t0时刻和t2时刻通过切换分频比，可以改变发射信号的频率，从而可以避免相邻时隙的同频干扰问题。
在一些实施方式中，本地振荡器131产生的本振信号的频率为第二发射信号F2的频率的第一数量倍。当第一数量倍为两倍时，第二分频比为2，其目的是本振信号经过分频后能够产生与第二发射信号相同频率的正交本振信号。由于第一分频比与第二分频比不同，当第二分频比为2时，第一分频比可以为1、4或8等。
其中，当第一分频比为1时，本地振荡器131产生的本振信号的频率为第一发射信号F1的频率的1倍；当第一分频比为4时，本地振荡器131产生的本振信号的频率为第一发射信号F1的频率的4倍；当第一分频比为8时，本地振荡器131产生的本振信号的频率为第一发射信号F1的频率的8倍。
在一个具体例子中，当本地振荡器131产生的本振信号的频率为800M时，分频比为1对应的第一发射信号F1的频率为800M，分频比为4对应的第一发射信号F1的频率为200M，分频比为8对应的第一发射信号F1的频率为100M。
请参阅图8，图8为本申请多时隙收发信机又一实施例的结构示意图。
区别于上述实施例，多时隙收发信机还包括倍频器133。倍频器133与本地振荡器131连接，用于将本振信号的频率提升。分频器132分别与倍频器133和发射机11连接，用于在发射时隙开始前的第一时刻，按照第一分频比将频率提升后的本振信号转换为第一正交本振信号Z1；以及用于在发射时隙开始时，按照第二分频比将频率提升后的本振信号转换为第二正交本振信号Z2，第一分频比与第二分频比不同。
其中，本地振荡器131产生的本振信号的频率为第二发射信号的频率的第二数量倍，第二数量小于第一数量。倍频器133用于将本地振荡器131产生的 本振信号的频率提升至第二发射信号的频率的第一数量倍后输入分频器132。
一个示例，第二数量倍可以为
Figure PCTCN2022088275-appb-000001
倍，倍频器133可以为三倍频器，用于将输入信号的频率提升3倍。本振信号经过倍频器133可以提升至第二发射信号的频率的2倍。另一个示例，第二数量倍也可以为
Figure PCTCN2022088275-appb-000002
倍，倍频器133可以为四倍频器，或者，第二数量倍也可以为
Figure PCTCN2022088275-appb-000003
倍，倍频器133可以为五倍频器，此处不作限定。
在一应用场景中，正交调制需要本地振荡器本身振荡的频率(即本振信号的频率)是天线口频率的两倍。比如：天线口发射的频率为400M，则振荡的频率为800M。天线口在发射频率时会产生谐波，谐波的频率例如为400M、800M或1200M，而800M与本振信号的频率相同，从而会干扰本地振荡器的相位噪声。但是，当多时隙收发信机还包括倍频器133时，本振信号的频率可以为
Figure PCTCN2022088275-appb-000004
本振信号通过三倍频器后可以将
Figure PCTCN2022088275-appb-000005
的频率，提升至800M，以使得天线口发射的频率仍为400M，但是此时的谐波与本振信号的频率不同，从而不会干扰本地振荡器的相位噪声。
在一些实施方式中，频率产生电路13还可以包括寄存器，寄存器用于寄存预设分频比，包括第一分频比和第二分频比。寄存器的种类不作限制，例如可以为8位元寄存器、16位元寄存器、32位元寄存器等。
表1 8位元寄存器的寄存状态
7 6 5 4 3 2 1 0
0 0 0 DIV 0 0 f2 f1
如上表1所示，8位元寄存器包括8个位元(bit)，即b0～b7，这里选择第5位元b4寄存预设分频比对应的变量DIV，该变量由分频器132控制。例如，当变量DIV写入b4＝1时，将启动4分频模式，当DIV写入b4＝2时，将启动2分频模式，或者，还可以将DIV写入b4＝4，则可以启动1分频模式，此处不作限制。位元b0和b1的变量f1和f2用于其他数据的寄存，例如用户标志位。位元b2-b3和b5-b7设置为0，以保留供将来使用。
请参阅图9，图9为本申请多时隙收发信机再一实施例的结构示意图。
在一些实施例中，发射机11包括依次连接的笛卡尔环路电路111、放大器112和耦合器113，笛卡尔环路电路111、放大器112和耦合器113形成笛卡尔负反馈环路。笛卡尔环路电路111连接频率产生电路13，用于接收基带信号(I、Q信号)和正交本振信号，信号I和信号Q为正交关系，信号I和信号Q为模拟时域信号。笛卡尔环路电路111利用正交本振信号对基带信号进行调制和上变频后发送给放大器112，放大器112对接收到的信号进行放大后传送给耦合器113，耦合器113对接收到的信号进行处理得到发射信号和反馈信号，耦合器113将反馈信号发送给笛卡尔环路电路111进行解调。其中，当笛卡尔环路电路111接收第一正交本振信号时，耦合器113得到第一发射信号，当笛卡尔环路电路111接收第二正交本振信号时，耦合器113得到第二发射信号。
其中，耦合器113与天线连接，用于将放大器112输出的第一发射信号和第二发射信号通过天线发射出去。本实施例中，接收机12和发射机11可以共用一根天线。
笛卡尔负反馈环路中的反馈信号通过耦合器113耦合得到，并将其还原为两路正交基带信号(记为还原基带信号)，笛卡尔环路电路111通过比较两路基带信号以及还原基带信号，对其差值进行前向I/Q信号预失真处理后进行上变频，并合成一路信号输送给放大器112，达到补偿射频发射机11非线性失真的目的。
放大器112可以包括功率放大器，功率放大器与笛卡尔环路电路111连接，用于对笛卡尔环路电路111输出的信号进行电流放大。此外，放大器112还可以包括信号放大器，信号放大器连接笛卡尔环路电路111和功率放大器，用于将笛卡尔环路电路111输出的信号进行电压放大后输入功率放大器。放大器112也可以为三级放大器，并不限于此。
笛卡尔环路电路111由上行和下行两条通路组成，上行通路把基带信号进行调制并发送给放大器112。下行通路是通过耦合器113耦合部分上行信号，再送给笛卡尔环路电路111进行解调，例如，下行通路通过耦合器113耦合百分之一或千分之一的上行信号。笛卡尔环路电路111通过比较发送过来的基带信号和解调下来的基带信号的差值，然后对上行基带信号做预失真处理，以达到线性化的目的。
在一些实施方式中，发射机11可以包括频率产生电路13中的至少部分电路。例如，可以将笛卡尔环路电路111中自带的除法电路作为分频器132。本地振荡器131产生的本振信号输入发射机11中的除法电路进行分频处理，得到正 交本振信号，然后再输入给图10中的上调制器1113和下调制器1116进行正交调制处理。
请参阅图10，图10是本申请多时隙收发信机的再又一实施例的逻辑示意图。
笛卡尔环路电路111包括上行通路和下行通路，上行通路包括依次连接的输入放大器1111、上误差放大器1112、上调制器1113和第一上衰减器1114，下行通路包括依次连接的第一下衰减器1115、下调制器1116和下误差放大器1117。上误差放大器1112连接下误差放大器1117，上调制器1113和下调制器1116分别连接频率产生电路13，第一上衰减器1114连接放大器112，第一下衰减器1115连接耦合器113。
第一下衰减器1115输入反馈信号，并将反馈信号衰减后输出至下调制器1116。下调制器1116用于将衰减后的反馈信号和频率产生电路13输出的正交本振信号进行调制处理，以得到还原基带信号并将还原基带信号输出至下误差放大器1117。
输入放大器1111用于将基带信号放大处理后输出至上误差放大器1112。上误差放大器1112用于将还原基带信号和放大处理后的基带信号进行比较，得到差值信号。上调制器1113用于将差值信号和频率产生电路13输出的正交本振信号进行调制处理，并将调制处理后的信号输出至第一上衰减器1114，第一上衰减器1114对调制处理后的信号进行衰减处理，并将衰减处理后的信号输出至放大器112。
具体地，基带信号由输入放大器1111进行信号放大后输入上误差放大器1112，下行通路中从耦合器113耦合得到的反馈信号，经过第一下衰减器1115进行衰减处理后输入下调制器1116，下调制器1116将其还原为正交两路基带信号(记为还原基带信号)，然后通过下误差放大器1117输入上误差放大器1112进行信号比较，并将得到的差值信号进行前向I/Q信号预失真处理后进行上变频，并合成一路信号，然后经过第一上衰减器1114进行衰减处理后输送给放大器112，达到补偿发射机11非线性失真的目的。其中，第一上衰减器1114控制笛卡尔环路电路111输出功率的大小，第一下衰减器1115用于控制笛卡尔环路电路111输入功率的大小，用于对信号进行精确衰减，其精度可以达到1dB。
发射机11还可以包括第二上衰减器114和/或第二下衰减器115，起到匹配作用，可以根据实际电路结构选择合适型号等参数。第二上衰减器114连接第一上衰减器1114和放大器112，用于对信号辅助衰减，以保证放大器前后级本 身的反射系数更好，防止级间相互影响。第二下衰减器115连接耦合器113和第一下衰减器1115，用于对耦合器113耦合的反馈信号进行预衰减处理，以避免反馈信号较强而烧坏笛卡尔环路电路111或下行通路中的前端电路。第二上衰减器114和/或第二下衰减器115可以包括电阻。
发射机11还可以包括滤波器116，滤波器116连接第一下衰减器1115和第二下衰减器115，用于滤除放大器112产生的谐波。滤波器116例如为低通滤波器。
请参阅图11，图11为多时隙收发信机的工作时序图。
按照陆地集群通信协议规定，每个时隙开始后都有一个保护时间段，如图11所示的时刻t2与t3之间的时间段，该保护时间段的大小约等于0.94ms。经过实际测验发现，实际测试本申请修改分频比的方式，比模拟测试修改分频比的响应时间减少了90％，可以在100us内实现分频比的修改，远小于保护时间0.94ms，也就是说，当保护时间结束时，发射电路都已经准备好，而且在接收时隙转发射时隙时，无同频干扰的情况下及时准确的发射信号，所以本方案是切实可行的。另外，测试在中继(Repeater)模式下存在倍频器时，基于本方案，接收时隙和发送时隙之间不存在干扰，即发射准备影响接收机的误码率为0，从而可以减少倍频器的电流消耗，大约为6mA的平均电流。
请参阅图12，图12是本申请多时隙通信方法一实施例的流程示意图。本实施例中，多时隙通信方法应用于上述实施例中的多时隙收发信机，多时隙收发信机包括发射机、接收机和频率产生电路，该方法可以包括以下步骤：
S11：频率产生电路在发射时隙开始前的第一时刻产生第一正交本振信号，并将第一正交本振信号输入发射机。
S12：发射机基于第一正交本振信号产生第一发射信号。
S13：频率产生电路在发射时隙开始时产生第二正交本振信号，并将第二正交本振信号输入发射机。
S14：发射机基于第二正交本振信号产生第二发射信号；其中，第一发射信号的频率与接收机的接收频率不同，第二发射信号的频率与接收机的接收频率相同。
请参阅图13，图13是图12中步骤S11的一实施方式的流程示意图。其中，频率产生电路包括本地振荡器和分频器。步骤S11可以包括子步骤S1111和S1112：
S1111：本地振荡器产生本振信号。
S1112：分频器在发射时隙开始前的第一时刻按照第一分频比将本振信号转换为第一正交本振信号，并将第一正交本振信号输入发射机。
在一些实施方式中，第一分频比为本地振荡器产生的本振信号的频率与第一发射信号的频率的倍数。
对应地，上述步骤S13可以为：分频器在发射时隙开始时按照第二分频比将本振信号转换为第二正交本振信号，并将第二正交本振信号输入发射机。
在一些实施方式中，第二分频比为本地振荡器产生的本振信号的频率与第二发射信号的频率的倍数，第二分频比与第一分频比不同。
在一个示例中，第一分频比为1、4或8，第二分频比为2。
在一些实施方式中，本地振荡器产生的本振信号的频率为第二发射信号的频率的第一数量倍。
请参阅图14，图14是图12中步骤S11的另一实施方式的流程示意图。其中，频率产生电路包括本地振荡器、倍频器和分频器。倍频器与本地振荡器连接，用于将本振信号的频率提升。分频器分别与倍频器和发射机连接。步骤S11可以包括子步骤S1121～S1123：
S1121：本地振荡器产生本振信号。
S1122：倍频器将本振信号的频率提升。
S1123：分频器在发射时隙开始前的第一时刻按照第一分频比将频率提升后的本振信号转换为第一正交本振信号，并将第一正交本振信号输入发射机。
对应地，上述步骤S13可以为：分频器在发射时隙开始时按照第二分频比将频率提升后的本振信号转换为第二正交本振信号，并将第二正交本振信号输入发射机，第一分频比与第二分频比不同。
本地振荡器产生的本振信号的频率为第二发射信号的频率的第二数量倍，第二数量小于第一数量。倍频器可以将本地振荡器产生的本振信号的频率提升为第二发射信号的频率的第二数量倍。
倍频器将本地振荡器产生的本振信号的频率提升至第二发射信号的频率的第一数量倍后输入分频器。
可以理解的，本申请的各个实施例之间可以相互结合，关于上述步骤的说明可以参见前述实施例中的对应位置，此处不再赘述。
以上，本申请的切换分频比的方案原理简单、可行性高，不仅可以从原理 上规避收发时隙的同频干扰，还节省电流消耗，此外，还可以节省PCB布局面积和生产成本。相比于其他通过开关阻断信号的方式，本申请的隔离干扰的效果更好。
在本申请所提供的几个实施例中，应该理解到，所揭露的方法和装置，可以通过其它的方式实现。例如，以上所描述的装置实施方式仅仅是示意性的，例如，模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性、机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施方式方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本申请各个实施方式方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

  1. 一种多时隙收发信机，其特征在于，包括发射机、接收机和频率产生电路，
    所述频率产生电路，与所述发射机连接，用于为所述发射机提供正交本振信号；其中，在发射时隙开始前的第一时刻，所述频率产生电路用于产生第一正交本振信号，以及在发射时隙开始时，所述频率产生电路用于产生第二正交本振信号；
    所述发射机用于基于所述第一正交本振信号产生第一发射信号，以及基于所述第二正交本振信号产生第二发射信号；
    其中，所述第一发射信号的频率与所述接收机的接收频率不同，所述第二发射信号的频率与所述接收机的接收频率相同。
  2. 根据权利要求1中所述的多时隙收发信机，其特征在于，所述频率产生电路包括本地振荡器和分频器，
    所述本地振荡器，用于产生本振信号；
    所述分频器，分别与所述本地振荡器和所述发射机连接，用于在发射时隙开始前的第一时刻，按照第一分频比将所述本振信号转换为所述第一正交本振信号；以及用于在发射时隙开始时，按照第二分频比将所述本振信号转换为所述第二正交本振信号，所述第一分频比与所述第二分频比不同。
  3. 根据权利要求2中所述的多时隙收发信机，其特征在于，所述第一分频比为1、4或8，所述第二分频比为2。
  4. 根据权利要求2中所述的多时隙收发信机，其特征在于，所述频率产生电路还包括寄存器，所述寄存器用于寄存所述第一分频比和所述第二分频比。
  5. 根据权利要求1中所述的多时隙收发信机，其特征在于，所述频率产生电路包括本地振荡器、倍频器和分频器，
    所述本地振荡器，用于产生本振信号；
    所述倍频器，与所述本地振荡器连接，用于将所述本振信号的频率提升；
    所述分频器，分别与所述倍频器和所述发射机连接，用于在发射时隙开始前的第一时刻，按照第一分频比将频率提升后的本振信号转换为所述第一正交本振信号；以及用于在发射时隙开始时，按照第二分频比将频率提升后的本振信号转换为所述第二正交本振信号，所述第一分频比与所述第二分频比不同。
  6. 根据权利要求1中所述的多时隙收发信机，其特征在于，所述发射机包括依次连接的笛卡尔环路电路、放大器和耦合器，所述笛卡尔环路电路、放大器和所述耦合器形成笛卡尔负反馈环路，
    所述笛卡尔环路电路连接所述频率产生电路，用于接收基带信号和所述正交本振信号，并利用所述正交本振信号对所述基带信号进行调制和上变频后发送给所述放大器，所述放大器对接收到的信号进行放大后传送给所述耦合器，所述耦合器将接收到的信号进行处理得到发射信号和反馈信号，所述耦合器将所述反馈信号发送给所述笛卡尔环路电路进行解调；
    其中，当所述笛卡尔环路电路接收所述第一正交本振信号时，所述耦合器得到所述第一发射信号，当所述笛卡尔环路电路接收所述第二正交本振信号时，所述耦合器得到所述第二发射信号。
  7. 根据权利要求6中所述的多时隙收发信机，其特征在于，所述笛卡尔环路电路包括上行通路和下行通路，所述上行通路包括依次连接的输入放大器、上误差放大器、上调制器和第一上衰减器，所述下行通路包括依次连接的第一下衰减器、下调制器和下误差放大器，所述上误差放大器连接所述下误差放大器，所述上调制器和所述下调制器分别连接所述频率产生电路，所述第一上衰减器连接所述放大器，所述第一下衰减器连接所述耦合器；
    所述第一下衰减器输入所述反馈信号，并将所述反馈信号衰减后输出至所述下调制器；所述下调制器用于将衰减后的所述反馈信号和所述频率产生电路输出的正交本振信号进行调制处理，以得到还原基带信号并将所述还原基带信号输出至所述下误差放大器；
    所述输入放大器用于将所述基带信号放大处理后输出至所述上误差放大器；所述上误差放大器用于将所述还原基带信号和放大处理后的所述基带信号进行比较，得到差值信号；所述上调制器用于将所述差值信号和所述频率产生电路输出的正交本振信号进行调制处理，并将所述调制处理后的信号输出至第一上衰减器，所述第一上衰减器对所述调制处理后的信号进行衰减处理，并将所述衰减处理后的信号输出至所述放大器。
  8. 一种多时隙通信方法，其特征在于，应用于多时隙收发信机，所述多时隙收发信机包括发射机、接收机和频率产生电路，所述多时隙通信方法包括：
    所述频率产生电路在发射时隙开始前的第一时刻产生第一正交本振信号，并将所述第一正交本振信号输入所述发射机；
    所述发射机基于所述第一正交本振信号产生第一发射信号；
    所述频率产生电路在发射时隙开始时产生第二正交本振信号，并将所述第二正交本振信号输入所述发射机；
    所述发射机基于所述第二正交本振信号产生第二发射信号；
    其中，所述第一发射信号的频率与所述接收机的接收频率不同，所述第二发射信号的频率与所述接收机的接收频率相同。
  9. 根据权利要求8中所述的多时隙通信方法，其特征在于，所述频率产生电路包括本地振荡器和分频器，所述频率产生电路在发射时隙开始前的第一时刻产生第一正交本振信号，并将所述第一正交本振信号输入所述发射机，包括：
    所述本地振荡器产生本振信号；
    所述分频器在发射时隙开始前的第一时刻按照第一分频比将所述本振信号转换为所述第一正交本振信号，并将所述第一正交本振信号输入所述发射机；
    所述频率产生电路在发射时隙开始时产生第二正交本振信号，并将所述第二正交本振信号输入所述发射机，包括：
    所述分频器在发射时隙开始时按照第二分频比将所述本振信号转换为所述第二正交本振信号，并将所述第二正交本振信号输入所述发射机，所述第一分频比与所述第二分频比不同。
  10. 根据权利要求8中所述的多时隙通信方法，其特征在于，所述频率产生电路包括本地振荡器、倍频器和分频器，所述频率产生电路在发射时隙开始前的第一时刻产生第一正交本振信号，并将所述第一正交本振信号输入所述发射机，包括：
    所述本地振荡器产生本振信号；
    所述倍频器将所述本振信号的频率提升；
    所述分频器在发射时隙开始前的第一时刻按照第一分频比将频率提升后的本振信号转换为所述第一正交本振信号，并将所述第一正交本振信号输入所述发射机；
    所述频率产生电路在发射时隙开始时产生第二正交本振信号，并将所述第二正交本振信号输入所述发射机，包括：
    所述分频器在发射时隙开始时按照第二分频比将频率提升后的本振信号转换为所述第二正交本振信号，并将所述第二正交本振信号输入所述发射机，所述第一分频比与所述第二分频比不同。
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CN103209004A (zh) * 2013-04-07 2013-07-17 海能达通信股份有限公司 一种多时隙收发信机
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CN1214579A (zh) * 1997-06-21 1999-04-21 三星电子株式会社 时分双工数字无线电通信系统及其操作方法
CN104160631A (zh) * 2012-03-01 2014-11-19 高通股份有限公司 用于无线设备的以时分双工模式的频率合成器架构
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