WO2023201589A1 - 发光控制电路及其控制方法、栅极驱动电路及其控制方法 - Google Patents

发光控制电路及其控制方法、栅极驱动电路及其控制方法 Download PDF

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Publication number
WO2023201589A1
WO2023201589A1 PCT/CN2022/088009 CN2022088009W WO2023201589A1 WO 2023201589 A1 WO2023201589 A1 WO 2023201589A1 CN 2022088009 W CN2022088009 W CN 2022088009W WO 2023201589 A1 WO2023201589 A1 WO 2023201589A1
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Prior art keywords
node
electrically connected
signal terminal
control
transistor
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PCT/CN2022/088009
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English (en)
French (fr)
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WO2023201589A9 (zh
Inventor
袁志东
李永谦
袁粲
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/088009 priority Critical patent/WO2023201589A1/zh
Priority to CN202280000798.2A priority patent/CN117280404A/zh
Publication of WO2023201589A1 publication Critical patent/WO2023201589A1/zh
Publication of WO2023201589A9 publication Critical patent/WO2023201589A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a light emitting control circuit and a control method thereof, a gate drive circuit and a control method thereof.
  • OLED display panels have the advantages of active light-emitting, wide viewing angle, high contrast, fast response, low power consumption, ultra-thin and so on, so they have received widespread attention.
  • the display panel includes multiple pixels, and the pixels include pixel driving circuits and light-emitting devices. If the pixels continue to emit light for a long time, the light-emitting devices will age, so the pixels need to be compensated.
  • the lighting control circuit includes a first lighting control sub-circuit and a second lighting control sub-circuit.
  • the first lighting control sub-circuit includes a first detection control unit and a first lighting output unit.
  • the second lighting control sub-circuit includes a second detection control unit and a second lighting output unit.
  • the first detection control unit is electrically connected to the detection control terminal, the first clock signal terminal, the first voltage signal terminal and the first node, and is configured to respond to the detection control signal from the detection control terminal and the detection control signal from the detection control terminal.
  • the first voltage signal from the first voltage signal terminal is transmitted to the first node under the control of the first clock signal of the first clock signal terminal.
  • the first light emitting output unit is electrically connected to the first node, the first voltage signal terminal and the first output signal terminal, and is configured to convert the first light source under the control of the voltage of the first node.
  • the voltage signal is transmitted to the first output signal terminal.
  • the second detection control unit is electrically connected to the detection control terminal, the second clock signal terminal, the first voltage signal terminal and the second node, and is configured to operate between the detection control signal and the second node.
  • the first voltage signal is transmitted to the second node under the control of a second clock signal at the second clock signal terminal.
  • the second light emitting output unit is electrically connected to the second node, the first voltage signal terminal and the second output signal terminal, and is configured to convert the first voltage under the voltage control of the second node.
  • the signal is transmitted to the second output signal terminal.
  • the first detection control unit includes a first detection input subunit and a first detection output subunit.
  • the first detection input subunit is electrically connected to the detection control terminal, the first clock signal terminal and the third node, and is configured to transmit the first clock signal to the detection control terminal under the control of the detection control signal.
  • the third node is electrically connected to the third node, the first voltage signal terminal and the first node, and is configured to convert the first voltage signal under the voltage control of the third node. transmitted to the first node.
  • the second detection control unit includes a second detection input subunit and a second detection output subunit.
  • the second detection input subunit is electrically connected to the detection control terminal, the second clock signal terminal and the fourth node, and is configured to transmit the second clock signal to the detection control terminal under the control of the detection control signal. Describe the fourth node.
  • the second detection output subunit is electrically connected to the fourth node, the first voltage signal terminal and the second node, and is configured to convert the first voltage signal under the voltage control of the fourth node. transmitted to the second node.
  • the first detection control unit further includes a first energy storage subunit; the first energy storage subunit is electrically connected to the first node and the third node, and is configured to maintain all Describe the voltage of the third node.
  • the second detection control unit further includes a second energy storage subunit; the second energy storage subunit is electrically connected to the second node and the fourth node, and is configured to maintain the voltage of the fourth node.
  • the first detection input subunit includes a first transistor, a control electrode of the first transistor is electrically connected to the detection control terminal, and the first electrode is electrically connected to the second clock signal terminal, The second pole is electrically connected to the third node.
  • the first detection output subunit includes a second transistor, a control electrode of the second transistor is electrically connected to the third node, a first electrode is electrically connected to the first voltage signal terminal, and a second electrode is electrically connected to the The first node is electrically connected.
  • the first energy storage subunit includes a first capacitor, a first plate of the first capacitor is electrically connected to the third node, and a second plate is electrically connected to the first node.
  • the second detection input subunit includes a third transistor, a control pole of the third transistor is electrically connected to the detection control terminal, a first pole is electrically connected to the fourth clock signal terminal, and a second pole is electrically connected to the The fourth node is electrically connected.
  • the second detection output subunit includes a fourth transistor, a control electrode of the fourth transistor is electrically connected to the fourth node, a first electrode is electrically connected to the first voltage signal terminal, and a second electrode is electrically connected to the The second node is electrically connected.
  • the second energy storage subunit includes a second capacitor, a first plate of the second capacitor is electrically connected to the fourth node, and a second plate is electrically connected to the second node.
  • the first lighting control sub-circuit further includes a first pulse width modulation unit.
  • the first pulse width modulation unit is electrically connected to the first input signal terminal, the third clock signal terminal and the first node, and is configured to control the signal from the third clock signal terminal under the control of the third clock signal from the third clock signal terminal.
  • the first input signal from the first input signal terminal is transmitted to the first node.
  • the second lighting control sub-circuit also includes a second pulse width modulation unit.
  • the second pulse width modulation unit is electrically connected to the second input signal terminal, the fourth clock signal terminal and the second node, and is configured to control the fourth clock signal from the fourth clock signal terminal.
  • the second input signal from the second input signal terminal is transmitted to the second node.
  • the first pulse width modulation unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a third capacitor.
  • the control electrode of the fifth transistor is electrically connected to the third clock signal terminal, the first electrode is electrically connected to the first input signal terminal, and the second electrode is electrically connected to the first node.
  • the control electrode of the sixth transistor is electrically connected to the first node, the first electrode is electrically connected to the second voltage signal terminal, and the second electrode is electrically connected to the fifth node.
  • the control electrode of the seventh transistor is electrically connected to the fifth node, the first electrode is electrically connected to the third voltage signal terminal, and the second electrode is electrically connected to the first output signal terminal.
  • the control electrode of the eighth transistor is electrically connected to the fifth clock signal terminal, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the sixth node.
  • the control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode is electrically connected to the third clock signal terminal, and the second electrode is electrically connected to the seventh node.
  • the control electrode of the tenth transistor is electrically connected to the first input signal terminal, the first electrode is electrically connected to the seventh node, and the second electrode is electrically connected to the fifth node.
  • the first plate of the third capacitor is electrically connected to the sixth node, and the second plate of the third capacitor is electrically connected to the seventh node.
  • the second pulse width modulation unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a fourth capacitor.
  • the control electrode of the eleventh transistor is electrically connected to the fourth clock signal terminal, the first electrode is electrically connected to the second input signal terminal, and the second electrode is electrically connected to the second node.
  • the control electrode of the twelfth transistor is electrically connected to the second node, the first electrode is electrically connected to the second voltage signal terminal, and the second electrode is electrically connected to the eighth node.
  • the control electrode of the thirteenth transistor is electrically connected to the eighth node, the first electrode is electrically connected to the third voltage signal terminal, and the second electrode is electrically connected to the second output signal terminal.
  • the control electrode of the fourteenth transistor is electrically connected to the sixth clock signal terminal, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the ninth node.
  • the control electrode of the fifteenth transistor is electrically connected to the ninth node, the first electrode is electrically connected to the fourth clock signal terminal, and the second electrode is electrically connected to the tenth node.
  • the control electrode of the sixteenth transistor is electrically connected to the second input signal terminal, the first electrode is electrically connected to the tenth node, and the second electrode is electrically connected to the eighth node.
  • the first plate of the fourth capacitor is electrically connected to the ninth node, and the second plate is electrically connected to the tenth node.
  • the first light emitting output unit includes a seventeenth transistor, a control electrode of the seventeenth transistor is electrically connected to the first node, a first electrode is electrically connected to the first voltage signal terminal, and a second electrode is electrically connected to the first voltage signal terminal.
  • the first output signal terminal is electrically connected.
  • the second light emitting output unit includes an eighteenth transistor, a control electrode of the eighteenth transistor is electrically connected to the second node, a first electrode is electrically connected to the first voltage signal terminal, and a second electrode is electrically connected to the second node.
  • the second output signal terminal is electrically connected.
  • the gate driving circuit includes a random detection circuit, a shift register circuit, and the light emission control circuit described in any of the above embodiments.
  • the random detection circuit is electrically connected to the random detection signal terminal, the third input signal terminal, the seventh clock signal terminal and the eleventh node, and is configured to operate between the random detection signal from the random detection signal terminal and the random detection signal from the third Under the control of the third input signal at the input signal terminal, the seventh clock signal from the seventh clock signal terminal is transmitted to the eleventh node to select a row of pixels for the compensation shift register circuit of the light-emitting device and the third
  • the eleventh node is electrically connected and configured to output a scanning signal to the corresponding row of pixels under the voltage control of the eleventh node to turn on the corresponding row of pixels.
  • the detection control end of the light emission control circuit is electrically connected to a circuit node in the random detection circuit or a circuit node in the shift register circuit.
  • the random detection circuit includes a random detection control subcircuit and a detection output subcircuit.
  • the random detection control subcircuit is electrically connected to the random detection signal terminal, the third input signal terminal and the twelfth node, and is configured to transmit the third input signal to The twelfth node.
  • the detection output subcircuit is electrically connected to the twelfth node, the seventh clock signal terminal and the eleventh node, and is configured to convert the seventh clock under the voltage control of the twelfth node. The signal is transmitted to the eleventh node.
  • the detection control terminal is electrically connected to the twelfth node.
  • the random detection circuit further includes a first energy storage sub-circuit and a first anti-leakage electronic circuit.
  • the first energy storage sub-circuit is electrically connected to the fourth voltage signal terminal and the twelfth node, and is configured to maintain the voltage of the twelfth node.
  • the first anti-leakage electronic circuit is electrically connected to the random detection control sub-circuit, the random detection signal terminal, the twelfth node and the fourth voltage signal terminal, and is configured to operate between the random detection signal and the Under the control of the voltage of the twelfth node, the fourth voltage signal is transmitted to the eleventh node.
  • the random detection control sub-circuit is electrically connected to the twelfth node through the first anti-leakage electronic circuit.
  • the random detection control sub-circuit includes a nineteenth transistor, a control electrode of the nineteenth transistor is electrically connected to the random detection signal terminal, and a first electrode is electrically connected to the third input signal terminal. connection, the second pole is electrically connected to the thirteenth node.
  • the detection output sub-circuit includes a twentieth transistor, a control electrode of the twentieth transistor is electrically connected to the twelfth node, a first electrode is electrically connected to the seventh clock signal terminal, and a second electrode is electrically connected to the twelfth node. The eleventh node is electrically connected.
  • the first energy storage sub-circuit includes a fifth capacitor, a first plate of the fifth capacitor is electrically connected to the fourth voltage signal terminal, and a second pole is electrically connected to the twelfth node.
  • the first anti-leakage electronic circuit includes a twenty-first transistor and a twenty-second transistor. The control electrode of the twenty-first transistor is electrically connected to the random detection signal terminal, and the first electrode is electrically connected to the thirteenth node. connection, the second pole is electrically connected to the twelfth node; the control pole of the twenty-second transistor is electrically connected to the twelfth node, the first pole is electrically connected to the fourth voltage signal terminal, and the The second pole is electrically connected to the thirteenth node.
  • the shift register circuit includes a first shift register sub-circuit and a second shift register sub-circuit.
  • the first shift register sub-circuit includes a first compensation input unit and a first scan output unit.
  • the second shift register subcircuit includes a second compensation input unit and a second scan output unit.
  • the first compensation input unit is electrically connected to the eleventh node, the seventh clock signal terminal and the fourteenth node, and is configured to control the first compensation input unit under the control of the seventh clock signal. The voltage of the eleventh node is transmitted to the fourteenth node.
  • the first scan output unit is electrically connected to the fourteenth node, the eighth clock signal terminal and a third output signal terminal, and the third output signal terminal is configured to be electrically connected to odd rows of pixels; the first The scan output unit is configured to transmit the eighth clock signal from the eighth clock signal terminal to the third output signal terminal under the control of the voltage of the fourteenth node to turn on the corresponding odd-numbered row pixels. .
  • the second compensation input unit is electrically connected to the eleventh node, the seventh clock signal terminal and the fifteenth node, and is configured to convert the eleventh node under the control of the seventh clock signal. The voltage of the node is transmitted to the fifteenth node.
  • the second scan output unit is electrically connected to the fifteenth node, the ninth clock signal terminal and the fourth output signal terminal, and the fourth output signal terminal is configured to be electrically connected to the even row pixels; the second The scan output unit is configured to transmit the ninth clock signal from the ninth clock signal terminal to the fourth output signal terminal under the control of the voltage of the fifteenth node to turn on the corresponding even row pixels.
  • the detection control terminal is electrically connected to the fourteenth node or the fifteenth node.
  • the first compensation input unit includes a twenty-third transistor, a control electrode of the twenty-third transistor is electrically connected to the seventh clock signal terminal, and a first electrode is connected to the eleventh transistor.
  • the node is electrically connected
  • the second pole is electrically connected to the fourteenth node.
  • the first scan output unit includes a twenty-fourth transistor, a control electrode of the twenty-fourth transistor is electrically connected to the fourteenth node, a first terminal is electrically connected to the eighth clock signal terminal, and a second terminal of the transistor is electrically connected to the eighth clock signal terminal.
  • the pole is electrically connected to the third output signal terminal.
  • the second compensation input unit includes a twenty-fifth transistor, a control electrode of the twenty-fifth transistor is electrically connected to the seventh clock signal terminal, a first electrode is electrically connected to the eleventh node, and a second electrode of the transistor is electrically connected to the eleventh node.
  • the pole is electrically connected to the fifteenth node.
  • the second scan output unit includes a twenty-sixth transistor, a control electrode of the twenty-sixth transistor is electrically connected to the fifteenth node, a first electrode is electrically connected to the ninth clock signal terminal, and a second The pole is electrically connected to the fourth output signal terminal.
  • the first shift register sub-circuit further includes a first scan input unit, a first inverter and a first reset unit.
  • the first scan input unit is electrically connected to the third input signal terminal, the fourth voltage signal terminal and the fourteenth node, and is configured to control the third input signal under the control of the third input signal.
  • the third voltage signal is transmitted to the fourteenth node.
  • One end of the first inverter is electrically connected to the fourteenth node, and the other end is electrically connected to the sixteenth node.
  • the first reset unit is electrically connected to the first reset signal terminal, the sixteenth node, the fifth voltage signal terminal, the fourteenth node and the third output signal terminal, and is configured to receive a signal from the first reset unit. Under the control of the first reset signal at the reset signal terminal and the voltage of the sixteenth node, the fifth voltage signal at the fifth voltage signal terminal is transmitted to the fourteenth node and the third output signal terminal.
  • the second shift register sub-circuit further includes a second scan input unit, a second inverter and a second reset unit.
  • the second scan input unit is electrically connected to the third input signal terminal, the fourth voltage signal terminal and the fifteenth node, and is configured to control the third input signal under the control of the third input signal.
  • the third voltage signal is transmitted to the fifteenth node.
  • One end of the second inverter is electrically connected to the fifteenth node, and the other end is electrically connected to the seventeenth node.
  • the second reset unit is electrically connected to the second reset signal terminal, the fifth voltage signal terminal, the fifteenth node, the seventeenth node and the fourth output signal terminal, and is configured to receive a signal from the second reset signal.
  • the fifth voltage signal is transmitted to the fifteenth node and the fourth output signal terminal under the control of the second reset signal at the terminal and the voltage of the seventeenth node.
  • the first scan input unit includes a twenty-seventh transistor, a control electrode of the twenty-seventh transistor is electrically connected to the third input signal terminal, and a first electrode is connected to the fourth voltage The signal terminal is electrically connected, and the second pole is electrically connected to the fourteenth node.
  • the first reset unit includes a twenty-eighth transistor, a twenty-ninth transistor and a thirtieth transistor.
  • the control electrode of the twenty-eighth transistor is electrically connected to the first reset signal terminal, and the first electrode is connected to the first reset signal terminal.
  • the fifth voltage signal terminal is electrically connected, and the second pole is electrically connected to the fourteenth node; the control pole of the twenty-ninth transistor is electrically connected to the sixteenth node, and the first pole is electrically connected to the fifth node.
  • the voltage signal terminal is electrically connected, the second pole is electrically connected to the third output signal terminal; the control pole of the thirtieth transistor is electrically connected to the sixteenth node, and the first pole is electrically connected to the fifth voltage signal terminal.
  • the second pole is electrically connected to the fourteenth node.
  • the second scan input unit includes a thirty-first transistor, a control electrode of the thirty-first transistor is electrically connected to the third input signal terminal, a first electrode is electrically connected to the fourth voltage signal terminal, and the The two poles are electrically connected to the fourteenth node.
  • the second reset unit includes a thirty-second transistor, a thirty-third transistor, and a thirty-fourth transistor.
  • the control electrode of the thirty-second transistor is electrically connected to the second reset signal terminal, and the first electrode is connected to the second reset signal terminal.
  • the fifth voltage signal terminal is electrically connected, and the second pole is electrically connected to the fifteenth node; the control pole of the thirty-third transistor is electrically connected to the seventeenth node, and the first pole is electrically connected to the fifteenth node.
  • the five voltage signal terminals are electrically connected, and the second pole is electrically connected to the fourth output signal terminal; the control pole of the thirty-fourth transistor is electrically connected to the seventeenth node, and the first pole is electrically connected to the fifth voltage The signal terminal is electrically connected, and the second pole is electrically connected to the fifteenth node.
  • a method for controlling a light-emitting control circuit is also provided, which is used to drive the light-emitting control circuit in any of the above embodiments.
  • the first output signal terminal of the light-emitting control circuit is electrically connected to the pixels in the odd rows, and the second output signal terminal of the light-emitting control circuit is electrically connected to the pixels in the even rows.
  • a frame cycle includes a display phase and a blank phase.
  • the control method includes: during the blank phase, the first detection of the first light-emitting control subcircuit of the light-emitting control circuit
  • the control unit transmits the first voltage signal to the first node
  • the first output unit of the first lighting control sub-circuit transmits the first voltage signal to the first output under the control of the voltage of the first node. signal terminal, so that the operating current flows through the light-emitting device of the odd-numbered row pixels or the even-numbered rows of pixels; or, the second detection control unit of the second lighting control sub-circuit of the lighting control circuit transmits the first voltage signal to the third lighting device.
  • the second output unit of the second lighting control sub-circuit transmits the first voltage signal to the second output signal terminal under the control of the voltage of the second node, so that the operating current flows through the odd number row pixels or the light-emitting devices of the even row pixels.
  • the first lighting control sub-circuit includes a first pulse width modulation unit
  • the second lighting control sub-circuit includes a second pulse width modulation unit
  • the control method includes: during the display phase, the first pulse width modulation unit transmits a first input signal to the first node under the control of a third clock signal; the first luminescence output unit Under the control of the voltage of the first node, the first voltage signal is transmitted to the first output signal terminal to modulate the light emitting time of the pixels in the odd rows and the pixels in the even rows.
  • the second detection control unit transmits the first voltage signal to the second node
  • the second light-emitting output unit transmits the first voltage signal to the second output signal terminal under the control of the voltage of the second node, so that the operating current flows through the light-emitting device of the odd-numbered row pixels or the even-numbered rows of pixels.
  • control method includes: during the display phase, the second pulse width modulation unit transmits a second input signal to the second node under the control of a fourth clock signal; the second luminescence output unit Under the control of the voltage of the second node, the first voltage signal is transmitted to the second output signal terminal to modulate the light emitting time of the pixels in the odd rows and the pixels in the even rows.
  • the first detection control unit transmits the first voltage signal to the first node
  • the first light-emitting output unit transmits the first voltage signal to the second output signal terminal under the control of the voltage of the first node, so that the operating current flows through the odd-numbered row pixels or the even-numbered rows of pixels.
  • control method includes: in the same frame period, the first clock signal terminal, the second input signal terminal and the fourth clock signal terminal output pulse signals, and the second clock signal terminal, the first input signal terminal terminal and the third clock signal terminal do not output a voltage signal. Or, in the same frame period, the second clock signal terminal, the first input signal terminal and the third clock signal terminal output pulse signals, and the first clock signal terminal, the second input signal terminal terminal and the fourth clock signal terminal do not output a voltage signal.
  • a method for controlling a gate driving circuit is provided.
  • the control method is configured to drive the gate driving circuit described in any of the above embodiments.
  • the first output signal terminal of the light-emitting control circuit of the gate driving circuit is electrically connected to the pixels in the odd rows, and the second output signal terminal of the light-emitting control circuit is electrically connected to the pixels in the even rows.
  • a frame cycle includes a display phase and a blank phase.
  • the control method includes:
  • the random detection circuit of the gate drive circuit transmits the third input signal to the circuit node in the random detection circuit under the control of the random detection signal, and maintains the corresponding circuit node voltage until the blank phase. .
  • the random detection circuit transmits the seventh clock signal to the shift register circuit of the gate drive circuit under the control of the voltage of the corresponding circuit node; the shift register circuit transmits the signal to the corresponding row of pixels.
  • the first voltage signal is transmitted to the first output signal terminal or the second output signal terminal, so that the operating current flows through the light-emitting devices of the odd row pixels or the even row pixels.
  • the shift register circuit includes a first shift register sub-circuit and a second shift register sub-circuit
  • the first shift register sub-circuit includes a first scan input unit and a first scan output unit
  • the second shift register sub-circuit includes a second scan input unit and a second scan output unit
  • the first light-emitting control sub-circuit of the light-emitting control circuit includes a first pulse width modulation unit
  • the second light-emitting control sub-circuit includes Second pulse width modulation unit.
  • the control method includes:
  • the first scan input unit inputs a fourth voltage signal to the fourteenth node under the control of the third input signal; the first scan output unit inputs the eighth voltage signal under the control of the voltage of the fourteenth node.
  • the clock signal is transmitted to the third output signal terminal to turn on the corresponding odd-numbered rows of pixels.
  • the second scan input unit inputs the fourth voltage signal to the fifteenth node under the control of the third input signal; the second scan output unit inputs the fourth voltage signal to the fifteenth node under the control of the voltage of the fifteenth node.
  • the ninth clock signal is transmitted to the fourth output signal terminal to turn on the corresponding even row pixels.
  • the first pulse width modulation unit transmits the first input signal to the first node under the control of the third clock signal, or the second pulse width modulation unit transmits the first input signal to the first node under the control of the fourth clock signal.
  • a second input signal is transmitted to the second node to modulate the lighting time of the odd row pixels and the even row pixels.
  • a method for controlling a display panel includes the gate driving circuit, the data driving circuit, odd-numbered row pixels and even-numbered row pixels described in any of the above embodiments.
  • the first light-emitting control sub-circuit of the gate driving circuit is electrically connected to the odd-numbered row pixels
  • the second light-emitting control sub-circuit is electrically connected to the even-numbered row pixels.
  • One frame period includes a display phase and a blank phase, and the blank phase includes a first data writing phase, a second data writing phase, and a sensing phase.
  • the control method includes:
  • the data driving circuit In the first data writing stage, the data driving circuit writes zero grayscale data to one of the odd row pixels and the even row pixels that is not selected for external compensation. In the second data writing stage, the data driving circuit writes sensing grayscale data to one of the odd row pixels and the even row pixels that is selected for compensation of the light emitting device. In the sensing stage, the first light-emitting control sub-circuit or the second light-emitting control sub-circuit outputs a first voltage signal to cause operating current to flow through the light-emitting devices of the odd-numbered row pixels and the even-numbered row pixels. ; The pixel circuit of the odd row pixels or the even row pixels detects the voltage of the light emitting device.
  • the blank phase further includes a first data write-back phase and a second data write-back phase.
  • the control method further includes: during the first data write-back stage, one of the odd row pixels and the even row pixels that is not selected for compensation of the light emitting device writes first initial grayscale data.
  • the second data write-back stage one of the odd-numbered row pixels and the even-numbered row pixels that is selected for compensation of the light-emitting device writes second initial grayscale data.
  • the first initial grayscale data is the grayscale data written into the corresponding row of pixels before the first data writing stage.
  • the second initial grayscale data is the grayscale data written into the corresponding row of pixels before the second data writing stage.
  • a display device in yet another aspect, includes the gate driving circuit described in any of the above embodiments.
  • Figure 1 is a structural diagram of a display device according to an embodiment of the present disclosure
  • Figure 2 is a structural diagram of a display panel according to an embodiment of the present disclosure
  • Figure 3 is an equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure.
  • Figure 4 is a timing control diagram of the pixel driving circuit according to an embodiment of the present disclosure.
  • Figure 5 is another equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure.
  • Figure 6 is an equivalent circuit diagram of a two-row pixel driving circuit according to an embodiment of the present disclosure.
  • Figure 7 is a cascade relationship diagram of a gate drive circuit according to an embodiment of the present disclosure.
  • Figure 8 is a connection diagram of a gate driving circuit and a pixel driving circuit according to an embodiment of the present disclosure
  • Figure 9 is a structural diagram of a lighting control circuit according to an embodiment of the present disclosure.
  • Figure 10 is another structural diagram of a light emission control circuit according to an embodiment of the present disclosure.
  • Figure 11 is another structural diagram of the light emitting control circuit according to an embodiment of the present disclosure.
  • Figure 12 is an equivalent circuit diagram of the first detection control unit and the second detection control unit according to the embodiment of the present disclosure
  • Figure 13 is another structural diagram of a light emission control circuit according to an embodiment of the present disclosure.
  • Figure 14A is an equivalent circuit diagram of the first lighting control sub-circuit according to the embodiment of the present disclosure.
  • Figure 14B is an equivalent circuit diagram of the second lighting control subcircuit according to the embodiment of the present disclosure.
  • Figure 15 is another structural diagram of the light emission control circuit according to an embodiment of the present disclosure.
  • Figure 16A is another equivalent circuit diagram of the first lighting control sub-circuit according to the embodiment of the present disclosure.
  • Figure 16B is another equivalent circuit diagram of the second lighting control sub-circuit according to the embodiment of the present disclosure.
  • Figure 17A is another equivalent circuit diagram of the first lighting control sub-circuit according to the embodiment of the present disclosure.
  • Figure 17B is another equivalent circuit diagram of the second lighting control sub-circuit according to the embodiment of the present disclosure.
  • Figure 18 is a control sequence control diagram of the light emitting control circuit according to an embodiment of the present disclosure.
  • Figure 19A is a structural diagram of a gate drive circuit according to an embodiment of the present disclosure.
  • Figure 19B is another structural diagram of a gate drive circuit according to an embodiment of the present disclosure.
  • Figure 20 is a structural diagram of a random detection circuit according to an embodiment of the present disclosure.
  • Figure 21 is an equivalent circuit diagram of the random detection circuit according to the embodiment of the present disclosure.
  • Figure 22 is another structural diagram of a random detection circuit according to an embodiment of the present disclosure.
  • Figure 23 is another equivalent circuit diagram of the random detection circuit according to the embodiment of the present disclosure.
  • Figure 24A is a structural diagram of a shift register circuit according to an embodiment of the present disclosure.
  • Figure 24B is an equivalent circuit diagram of the shift register circuit according to the embodiment of the present disclosure.
  • Figure 25A is a structural diagram of the first shift register subcircuit according to an embodiment of the present disclosure.
  • Figure 25B is a structural diagram of the second shift register subcircuit according to the embodiment of the present disclosure.
  • Figure 26A is an equivalent circuit diagram of the first shift register subcircuit according to an embodiment of the present disclosure.
  • FIG. 26B is an equivalent circuit diagram of the second shift register subcircuit according to the embodiment of the present disclosure.
  • Figure 27 is a timing control diagram of the gate drive circuit according to an embodiment of the present disclosure.
  • FIG. 28 is a timing control diagram of the display panel according to the embodiment of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • the transistors used in all embodiments of the present disclosure can be thin film transistors (Thin Film Transistor, TFT for short), field effect transistors (Metal Oxide Semiconductor, MOS for short), or other devices with the same characteristics.
  • TFT Thin Film Transistor
  • MOS Metal Oxide Semiconductor
  • the embodiments of the present disclosure are suitable for This is not limited.
  • the transistor may be a TFT.
  • TFT can be prepared using a-Si process, oxide (Oxide) semiconductor process, low temperature polysilicon (Low Temperature Poly-silicon, abbreviation: LTPS) process, and high temperature polysilicon (High Temperature Poly-silicon, abbreviation: HTPS) process.
  • LTPS Low Temperature Poly-silicon
  • HTPS High Temperature Poly-silicon
  • the embodiments of the present disclosure do not limit the type of transistor.
  • the transistor can be an N-type transistor or a P-type transistor, an enhancement-mode transistor, or a depletion-mode transistor.
  • all transistors are N-type transistors as an example to illustrate the present application.
  • the N-type transistor is turned on under the action of a high-level voltage signal and turned off under the action of a low-level voltage signal; that is, the operating voltage of the N-type transistor is a high-level voltage and the turn-off voltage is a low-level voltage.
  • the gate of the transistor is the control electrode.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the first electrode of the transistor may be one of the source electrode and the drain electrode of the transistor, and the second electrode may be the other one of the source electrode and the drain electrode of the transistor. Since the source and drain of a transistor may be symmetrical in structure, there may be no structural difference between the source and drain of the transistor.
  • the capacitor in the embodiment of the present disclosure may be a capacitor device manufactured separately through a process.
  • the capacitor device may be realized by manufacturing special capacitor electrodes.
  • Each capacitor electrode (first plate and second plate) of the capacitor may be made of metal. layer, semiconductor layer (such as doped polysilicon), etc.
  • Capacitance can also be the parasitic capacitance between transistors, or it can be realized by the transistor itself and other devices and circuits, or it can be realized by using the parasitic capacitance between the circuit's own circuits.
  • Each of the above-mentioned transistors may further include at least one switch transistor connected in parallel with each transistor.
  • the embodiments of the disclosure are only examples of the pixel driving circuit and the gate driving circuit. Other structures with the same functions as the pixel driving circuit and the gate driving circuit will not be described one by one, but they should all fall within the protection scope of the disclosure.
  • first node do not represent actual existing components, but represent the meeting points of relevant electrical connections in the circuit diagram. That is to say, these nodes are formed by the relevant electrical connections in the circuit diagram. A node equivalent to the meeting point of .
  • FIG. 1 is a structural diagram of a display device.
  • the display device 1000 can display either motion (eg, video) or fixed (eg, still image). Any device, whether text or image.
  • the display device 1000 can be a television, a laptop, a tablet, a mobile phone, a personal digital assistant (Personal Digital Assistant, PDA for short), a navigator, a wearable device, or an augmented reality (Augmented Reality, AR for short) device. , virtual reality (Virtual Realit, VR) equipment and any other products or components with display functions.
  • PDA Personal Digital Assistant
  • AR Augmented Reality
  • VR Virtual Realit
  • the display device 1000 includes a display panel 1100 , a data driving circuit 1200 disposed on the display panel 1100 , and a circuit board 1300 (such as Source PCB) electrically connected to the display panel 1100 and the data driving circuit 1200 .
  • the data driver circuit 1200 can be a driver chip (Source Driver IC)
  • the circuit board 1300 can be a Source PCB.
  • the display panel 1100 has a display area AA and a peripheral area BB located at least on one side of the display area AA.
  • the display panel 1100 has a display area AA and a peripheral area BB surrounding the display area AA.
  • the data driving circuit 1200 is disposed in the peripheral area BB of the display panel 1100.
  • the display panel 1100 includes a plurality of pixels (SubPixel) P, a plurality of data lines DL, a plurality of first gate lines GL1 , a plurality of second gate lines GL2 , a plurality of sensing signal lines SL (not shown in FIG. 2 ), and A plurality of gate drive circuits 1120.
  • Each pixel P may include a pixel driving circuit 1110 and a light emitting device EL.
  • the plurality of light-emitting devices EL of the plurality of pixels P can emit at least three primary colors, such as red (Red, R), green (Green, G) and blue (Blue, B) light.
  • a plurality of pixels P are arranged in multiple columns along the first direction X (the pixels P in the multiple columns are arranged along the first direction
  • Each row of pixels P includes a plurality of pixels P arranged along the first direction X
  • each column of pixels P includes a plurality of pixels P arranged along the second direction Y.
  • the first direction X and the second direction Y intersect, for example, the second direction Y is perpendicular to the first direction X.
  • the multiple rows of pixels P include alternately arranged odd-numbered rows of pixels P1 and even-numbered rows of pixels P2.
  • the second row, the fourth row, the sixth row, ..., and the Nth row are all even row pixels P2.
  • N is a positive integer
  • N is an even number.
  • the gate driving circuit 1120 is disposed in the peripheral area BB. Each group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 respectively passes through a first gate line GL1 and a second gate line GL2 and a gate driver. Circuit 1120 is electrically connected. A plurality of gate driving circuits 1120 are arranged in cascade. Each column of pixels P is electrically connected to the data driving circuit 1200 through a data line DL, and each column of pixels P is electrically connected to a sensing signal line SL (the sensing signal line SL is not shown in FIG. 2 ).
  • a group of adjacent odd-numbered row pixels and even-numbered row pixels refers to a row electrically connected to the same gate driving circuit 1120 (electrically connected to the same light-emitting control circuit 100).
  • FIG. 3 is an equivalent circuit diagram of a pixel driving circuit 1110 provided by an embodiment of the present disclosure.
  • the pixel driving circuit 1110 may include a driving transistor T101, a data writing transistor T102, a sensing transistor T103, and a storage capacitor Cst.
  • the control electrode of the data writing transistor T102 is electrically connected to the first gate line GL1, the first electrode is electrically connected to the data line DL, and the second electrode is electrically connected to the control electrode of the driving transistor T101.
  • the first electrode of the driving transistor T101 is electrically connected to the power supply voltage signal terminal VDD, and the second electrode is electrically connected to the anode of the light emitting device EL.
  • the control electrode of the sensing transistor T103 is electrically connected to the second gate line GL2, the first electrode is electrically connected to the anode of the light-emitting device EL, and the second electrode is electrically connected to the sensing signal line SL.
  • the first plate of the energy storage capacitor Cst is electrically connected to the control electrode of the driving transistor T101, and the second plate is electrically connected to the anode of the light emitting device EL.
  • the light-emitting device EL Since the light-emitting device EL will age when working (emitting light) for a long time, the light-emitting device EL needs to be compensated so that the light-emitting device EL can display the required grayscale data.
  • FIG. 4 is a timing control diagram of the pixel driving circuit 1110 shown in FIG. 3 .
  • a frame period (Frame) F includes a blank phase (Blank) B and a display phase (Display) D.
  • the blank phase B includes a sensing data writing phase B1, a sensing phase B2 and a display data writing back phase B3.
  • the gate driving circuit 1120 controls the data writing transistor T102 to turn on through the first gate line GL1, and the data driving circuit 1200 writes sensing grayscale data to the control electrode of the driving transistor T101 through the data line DL. VGm.
  • the sensing grayscale data VGm turns on the driving transistor T101, and the power supply voltage signal terminal VDD charges the anode of the light-emitting device EL through the driving transistor T101.
  • the data writing transistor T102 is turned off, and the second gate line GL2 controls the sensing transistor T103 to be turned on, and the sensing signal line SL senses the voltage of the anode of the light emitting device EL.
  • the gate driving circuit 1120 can control the data writing transistor T102 to turn on through the first gate line GL1, and the data driving circuit 1200 writes the display grayscale data Dn to the control electrode of the driving transistor T101 through the data line DL; display grayscale Data Dn controls the driving transistor T101 to turn on, the power supply voltage signal terminal CDD is connected to the anode of the light-emitting device EL, the driving current flows through the light-emitting device EL, and the light-emitting device EL works.
  • the light-emitting device EL may be an organic light-emitting diode (OLED).
  • OLED organic light-emitting diode
  • the luminous efficiency of the light-emitting device EL is positively related to the current size (or current density) flowing through the light-emitting device EL. That is, when the current flowing through the light-emitting device EL is small, the luminous efficiency of the light-emitting device EL is low; when the current flowing through the light-emitting device EL is large, the luminous efficiency of the light-emitting device EL is high.
  • some embodiments of the present disclosure also provide a pixel driving circuit 1110.
  • Figure 5 is a pixel driving circuit shown in Figure 3 that adds light emission.
  • the light-emitting control transistor T104 is used to modulate the light-emitting time of the light-emitting device EL (i.e., pulse width modulation: Pulse Width Modulation; abbreviation: PWM) to change the light-emitting duty ratio of the light-emitting device EL within one frame, thereby shortening the light-emitting device EL
  • pulse width modulation Pulse Width Modulation
  • PWM Pulse Width Modulation
  • control electrode of the light-emitting control transistor T104 is electrically connected to the gate drive circuit 1120 through the light-emitting control scan line EM.
  • the first electrode is electrically connected to the power supply voltage signal terminal VDD, and the second electrode is electrically connected to the first electrode of the driving transistor T101. connect.
  • the light emission control transistor T104 may be an oxide thin-film transistor (oxide TFT for short). Oxide thin-film transistors have high electron mobility and good turn-off characteristics. In this way, it is beneficial to completely turn on or turn off the light emission control transistor T104 during the modulation of the light emission time of the light emitting device EL.
  • FIG. 6 is an equivalent circuit diagram of a group of adjacent odd-numbered row pixels P1 and even-numbered rows of pixels P2, wherein each row exemplarily shows only one pixel P.
  • the second electrode of the light emission control transistor T104(1) of the pixel P1 in the odd row is electrically connected to the second electrode of the light emission control transistor T104(2) of the pixel P2 in the even row through a connection line L0.
  • a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 share the light emission control transistor T104.
  • one of the light-emitting control transistor T104(1) of the pixel P1 in the odd row and the light-emitting control transistor T104(2) of the pixel P2 in the even row controls the two light-emitting devices EL corresponding to the pixel P in the two rows.
  • the lighting time of one is modulated, and the other rests (always in the off state during the corresponding frame period). In this way, the risk of damage or threshold voltage drift of the light-emitting control transistor T104 due to long-term operation can be reduced, and the reliability of the light-emitting control transistor T104 can be improved.
  • the light-emitting control transistor T104(1) of the pixel P1 in the odd row and the light-emitting control transistor T104(2) of the pixel P2 in the even row alternately control the light-emitting time of the two light-emitting devices EL of the pixel P corresponding to the two rows. Adjust and alternate with rest.
  • the luminescence control of a row of pixels P electrically connected to the corresponding luminescence control scan line EM Transistor T104 may also be off.
  • the sensing data writing stage B1 when the light-emitting control transistors T104 of a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 are both in the off state, and the group of adjacent odd-numbered row pixels P1 and even-numbered rows are selected
  • the light-emitting control transistor T104 of the corresponding row pixel P cannot be turned on.
  • the anode of the light-emitting device EL is electrically insulated from the power supply voltage VDD, so the light-emitting device EL cannot be completed. charging, so the light-emitting device EL cannot be compensated.
  • the gate driving circuit 1120 includes a lighting control circuit 100, a random detection circuit 200 and a shift register circuit 300.
  • the random detection circuit 200 can also be called a random Sense unit.
  • the random detection circuit 200 is configured to randomly select a row of pixels P in each frame period F, and compensate the light-emitting devices EL of the selected row of pixels P.
  • a plurality of shift register circuits 300 are cascaded in sequence. Each shift register circuit 300 is electrically connected to the first gate line GL1 and the second gate line GL2, and is configured to output the first scan signal to the first gate line GL1 and to the second gate line GL1. The second gate line GL2 outputs the second scanning signal. Among them, a random detection circuit 200 is electrically connected to two shift register circuits 300 (as shown in Figure 8).
  • the shift register circuit 300 includes a first shift register sub-circuit GL1GOA and a second shift register sub-circuit GL2GOA; a plurality of first shift register sub-circuits GL1GOA of the plurality of shift register circuits 300
  • the plurality of second shift register sub-circuits GL2GOA of the plurality of shift register circuits 300 are cascaded in sequence. It should be noted that FIG. 7 only illustrates the first shift register sub-circuit GL1GOA.
  • FIG. 9 is a structural diagram of the light emitting control circuit 100 .
  • the lighting control circuit 100 includes a first lighting control sub-circuit 110 and a second lighting control sub-circuit 120 .
  • multiple light emission control circuits 100 of multiple gate driving circuits 1120 are arranged in cascade in sequence.
  • the first lighting control sub-circuits 110 of each gate driving circuit 1120 are cascaded with each other, wherein the first cascade output signal terminal CR1 of the first lighting control sub-circuit 110 of the upper stage is connected to the first cascading output signal terminal CR1 of the lower stage.
  • the first input signal terminal IN1 of the lighting control sub-circuit 110 is electrically connected.
  • the second light-emitting control sub-circuit 120 of each gate driving circuit 1120 is cascaded in sequence, wherein the second cascade output signal terminal CR2 of the upper-level second light-emitting control sub-circuit 120 is connected to the next-level second light-emitting control sub-circuit.
  • the second input signal terminal IN2 of 120 is electrically connected.
  • Each light emission control circuit 100 is electrically connected to a first light emission control scan line EM1 and a second light emission control scan line EM2, and is configured to output a light emission control signal through the first light emission control scan line EM1 and the second light emission control scan line EM2. , to modulate the emission duration of a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 that are electrically connected thereto.
  • each light emission control circuit 100 is electrically connected to a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2.
  • the first light-emitting control sub-circuit 110 of the light-emitting control circuit 100 is electrically connected to the odd-numbered row pixels P1
  • the second light-emitting control sub-circuit 120 is electrically connected to the even-numbered row pixels P2.
  • the first output signal terminal EM1 is electrically connected to the control electrode of the light emission control transistor T104 of the pixel P1 in the odd row
  • the second output signal terminal EM2 is electrically connected to the control electrode of the light emission control transistor T104 of the pixel P2 in the even row.
  • the first output signal terminal and the first light-emitting control signal line use the same label EM1 to indicate that the first output signal terminal is electrically connected to the first light-emitting control signal line;
  • the second output The signal terminal and the second light-emitting control signal line use the same label EM2 to indicate that the second output signal terminal and the second light-emitting control signal line are electrically connected.
  • the first lighting control sub-circuit 110 includes a first detection control unit 111 and a first lighting output unit 112 .
  • the second lighting control sub-circuit 120 includes a second detection control unit 121 and a second lighting output unit 122 .
  • the first detection control unit 111 is electrically connected to the detection control terminal VH, the first clock signal terminal CKA1, the first voltage signal terminal VGH and the first node N1, and is configured to operate between the detection control signal from the detection control terminal VH and the first node N1. Under the control of the first clock signal of the clock signal terminal CKA1, the first voltage signal from the first voltage signal terminal VGH is transmitted to the first node N1.
  • the first light emitting output unit 112 is electrically connected to the first node N1, the first voltage signal terminal VGH and the first output signal terminal EM1, and is configured to transmit the first voltage signal to the first node N1 under the control of the voltage of the first node N1.
  • the second detection control unit 121 is electrically connected to the detection control terminal VH, the second clock signal terminal CKA2, the first voltage signal terminal VGH and the second node N2, and is configured to detect the control signal and the second voltage signal from the second clock signal terminal CKLB. Under the control of the two clock signals, the first voltage signal is transmitted to the second node N2.
  • the second light emitting output unit 122 is electrically connected to the second node N2, the first voltage signal terminal VGH and the second output signal terminal EM2, and is configured to transmit the first voltage signal to the second voltage signal under the voltage control of the second node N2.
  • the detection control terminal VH can output an operating voltage (high) to the light-emitting control circuit 100 electrically connected to the row of pixels P. level voltage signal).
  • the second light emitting control subcircuit 120 electrically connected to the Nth row pixel
  • the detection control terminal VH and the detection control terminal VH in the first light emitting control sub-circuit 110 that are electrically connected to the N-1th row pixels simultaneously generate an operating voltage (high-level voltage signal).
  • the first voltage signal terminal VGH may be a voltage signal terminal that continuously outputs a high level, so that the first voltage signal is a high level voltage signal.
  • one of the first clock signal terminal CKA1 and the second clock signal terminal CKA2 outputs a pulse signal in the blank phase B, and the other outputs a continuous low-level voltage signal in different frame periods.
  • the first clock signal terminal CKA1 and the second clock signal terminal CKA2 alternately output pulse signals in the blank phase B (as shown in Figure 18). In this way, in the blank phase B of the same frame period F, only one of the first clock signal terminal CKA1 and the second clock signal terminal CKA2 outputs a pulse signal.
  • the first clock signal terminal CKA1 and the second clock signal terminal CKA2 switch to output pulse signals every other frame period F. That is, in the blank phase B of the odd-numbered (such as 1, 3, 5, etc.) frame period, one of the first clock signal terminal CKA1 and the second clock signal terminal CKA2 outputs a pulse signal; in the even-numbered (such as 2, 4, etc.) frame period , 6, etc.) frame periods, the other one of the first clock signal terminal CKA1 and the second clock signal terminal CKA2 outputs a pulse signal.
  • the first clock signal terminal CKA1 and the second clock signal terminal CKA2 switch to output pulse signals. That is, within the first, third, fifth, ..., N-1th "two frame periods", one of the first clock signal terminal CKA1 and the second clock signal terminal CKA2 is During the blank phase, One outputs a pulse signal during the blank phase B. where N is an even number.
  • the light-emitting control transistor T104 When a row of pixels P is selected for compensation, one of a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2, the light-emitting control transistor T104 is turned on.
  • the power supply voltage signal terminal VDD can be transmitted to the first pole of the two driving transistors T101 through the turned-on light-emitting control transistor T104 and the connection line L0, and according to the open state of the two driving transistors T101 (the driving transistor T101 of the selected row pixel P is in the sense It is turned on under the control of the measured grayscale data VGm, and the driving transistor T101 of the pixel P in another row is turned off during the sensing data writing phase B1) to charge the anode of the light-emitting device EL of the pixel P in the selected row.
  • the lighting control circuit 100 includes a first detection control unit 111 and a second detection control unit 122.
  • the driving transistor T101 of the selected row pixel P can be electrically connected to the power supply voltage signal terminal VDD through the first detection control unit 111 and the second detection control unit 122, and then during the driving When the transistor T101 is turned on, the anode of the light-emitting device EL of the selected row pixel P is charged, thereby realizing compensation for the light-emitting device EL of the selected row pixel P.
  • the selected row of pixels P refers to a row of pixels P that compensate for the light-emitting device EL.
  • Some embodiments of the present disclosure also provide a control method for the lighting control circuit 100, which is used to drive the lighting control circuit 100 in any of the above embodiments.
  • one frame period F includes a display phase D and a blank phase B.
  • the control methods include:
  • the first detection control unit 111 of the first lighting control sub-circuit 110 of the lighting control circuit 100 transmits the first voltage signal to the first node N1, and the first output unit 112 of the first lighting control sub-circuit 110 Under the control of the voltage of the first node N1, transmit the first voltage signal to the first output signal terminal EM1, so that the operating current flows through the light-emitting device EL of the odd-numbered row pixels P1 or the even-numbered rows of pixels P2;
  • the second detection control unit 121 of the second lighting control sub-circuit 120 of the lighting control circuit 100 transmits the first voltage signal to the second node N2, and the second output unit 122 of the second lighting control sub-circuit 120 is at the second node N2.
  • the first voltage signal is transmitted to the second output signal terminal EM2, so that the operating current flows through the light-emitting device EL of the odd-numbered row pixels P1 or the even-numbered rows of pixels P2.
  • the detection control terminal VH outputs an operating voltage signal to the light emitting control circuit 100 electrically connected to the selected row pixel P.
  • the first detection control unit 111 controls the first voltage from the first voltage signal terminal VGH under the control of the detection signal (operating voltage signal) from the detection control terminal VH and the first clock signal from the first clock signal terminal CKA1 The signal is transmitted to the first node N1.
  • the first light emitting output unit 112 transmits the first voltage signal from the first voltage signal terminal VGH to the first output signal terminal EM1 under the control of the voltage of the first node N1 (first voltage signal).
  • the second detection control unit 121 controls the first voltage from the first voltage signal terminal VGH under the control of the detection signal from the detection control terminal VH and the second clock signal from the second clock signal terminal CKA2. The signal is transmitted to the second node N2.
  • the second light emitting output unit 122 transmits the first voltage signal from the first voltage signal terminal VGH to the second output signal terminal EM2 under the control of the voltage of the second node N2 (first voltage signal).
  • the first voltage signal is output to turn on the light emission control transistor T104 of the corresponding row of pixels P.
  • the first output signal terminal EM1 of the light emission control circuit 100 outputs a first voltage signal, and the first voltage signal is transmitted from the first output signal terminal EM1 along the light emission control scan line EM1 to the light emission control transistor T104 ( 1), the light-emitting control transistor T104(1) is turned on, and the power supply voltage signal from the power supply voltage signal terminal VDD is transmitted to the odd-numbered row pixel P1 through the light-emitting control transistor T104(1) of the odd-numbered pixel P1 and the connecting line L0.
  • the driving transistor T101 of the selected row pixel P is turned on and charges the anode of the light-emitting device 120 of the selected row pixel P, so that the row pixel P can realize the compensation function of the light-emitting device EL.
  • the first detection control unit 111 includes a first detection input subunit 1111 and a first detection output subunit 1112 .
  • the first detection input subunit 1111 is electrically connected to the detection control terminal VH, the first clock signal terminal CKA1 and the third node N3, and is configured to transmit the first clock signal to the third node under the control of the detection control signal. N3.
  • the first detection output subunit 1112 is electrically connected to the third node N3, the first voltage signal terminal VGH and the first node N1, and is configured to control the first voltage under the control of the voltage of the third node N3 (first clock signal). The signal is transmitted to the first node N1.
  • the first detection input sub-unit 1111 includes a first transistor T1.
  • the control electrode of the first transistor T1 is electrically connected to the detection control terminal VH, the first electrode is electrically connected to the first clock signal terminal CKA1, and the second electrode is electrically connected to the third node N3.
  • the second detection output subunit 1112 includes a second transistor T2.
  • the control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the first node N1.
  • the second detection control unit 121 includes a second detection input subunit 1211 and a second detection output subunit 1212 .
  • the second detection input subunit 1211 is electrically connected to the detection control terminal VH, the second clock signal terminal CKA2 and the fourth node N4, and is configured to transmit the second clock signal to the fourth node N4 under the control of the detection control signal.
  • the second detection output subunit 1212 is electrically connected to the fourth node N4, the first voltage signal terminal VGH and the second node N2, and is configured to control the first voltage under the control of the voltage of the fourth node N4 (second clock signal). The signal is transmitted to the second node N2.
  • the second detection input sub-unit 1211 includes a third transistor T3.
  • the control electrode of the third transistor T3 is electrically connected to the detection control terminal VH, the first electrode is electrically connected to the second clock signal terminal CKA2, and the second electrode is electrically connected to the fourth node N4.
  • the second detection output subunit 1212 includes a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the first electrode is electrically connected to the first voltage signal terminal VGH.
  • the two poles are electrically connected to the second node N2.
  • the first detection control unit 111 further includes a first energy storage subunit 1113 .
  • the first energy storage subunit 1113 is electrically connected to the first node N1 and the third node N3, and is configured to maintain the voltage of the third node N3.
  • the first clock signal input to the third node N3 by the first clock signal terminal CKA1 may be a pulse signal.
  • the first energy storage subunit 1113 can enable the third node N3 to maintain the voltage value of the first clock signal within a certain period of time, and in the first When the voltage of one node N1 transitions (increases or decreases), the third node N3 transitions accordingly.
  • the first energy storage subunit 1113 includes a first capacitor C1 , a first plate of the first capacitor C1 is electrically connected to the third node N3 , and a second plate is electrically connected to the first node N1 .
  • the first energy storage subunit 1113 can cause the third transistor T3 to continue to turn off for a certain period of time.
  • the first node N1 inputs a first voltage signal, thereby causing the first output signal terminal EM1 to output a continuous operating voltage signal, which is beneficial to the power supply voltage signal terminal VDD charging the anode of the light-emitting device EL.
  • the second detection control unit 121 further includes a second energy storage subunit 1213.
  • the second energy storage subunit 1213 is electrically connected to the second node N2 and the fourth node N4, and is configured to maintain The voltage of the fourth node N4.
  • the second clock signal input to the fourth node N4 by the second clock signal terminal CKA2 may be a pulse signal.
  • the second energy storage subunit 1213 can enable the fourth node N3 to maintain the voltage value of the first clock signal within a certain period of time, and in the first When the voltage of the second node N2 transitions (increases or decreases), the fourth node N4 transitions accordingly.
  • the second energy storage subunit 1213 includes a second capacitor C2, the first plate of the second capacitor C2 is electrically connected to the fourth node N4, and the second plate is electrically connected to the second node N2.
  • the effects that can be achieved by the second energy storage subunit 1213 are the same as those that can be achieved by the first energy storage subunit 1113, which will not be described again here.
  • the first detection input sub-unit 1111 includes a first transistor T1; the first detection output sub-unit 1112 includes a second transistor T2; the first energy storage sub-unit 1113 includes a first capacitor C1;
  • the second detection input subunit 1211 includes a third transistor T3; the second detection output subunit 1212 includes a fourth transistor T4; and the second energy storage subunit 1213 includes a second capacitor C2.
  • the control electrode of the first transistor T1 is electrically connected to the detection control terminal VH, the first electrode is electrically connected to the first clock signal terminal CKA1, and the second electrode is electrically connected to the third node N3.
  • the control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the first node N1.
  • the first plate of the first capacitor C1 is electrically connected to the third node N3, and the second plate is electrically connected to the first node N1.
  • the control electrode of the third transistor T3 is electrically connected to the detection control terminal VH, the first electrode is electrically connected to the second clock signal terminal CKA2, and the second electrode is electrically connected to the fourth node N4.
  • the control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the second node N2.
  • the first plate of the second capacitor C2 is electrically connected to the fourth node N4, and the second plate is electrically connected to the second node N2.
  • the first lighting output unit 112 may include a first cascade signal output subunit 1121 and a first lighting control signal output subunit 1122 .
  • the first cascade signal output subunit 1121 is electrically connected to the first node N1, the first voltage signal terminal VGH and the first cascade output signal terminal CR1, and is configured to control the voltage of the first node N1.
  • the first voltage signal from the first voltage signal terminal VGH is transmitted to the first cascade output signal terminal CR1 and outputs the first level to the first input signal terminal IN1 of the first lighting control sub-circuit 110 of the next lighting control circuit 100 link signal.
  • the first cascade signal output subunit 1121 includes a thirty-fifth transistor T35 and a seventh capacitor C7.
  • the control electrode of the thirty-fifth transistor T35 is electrically connected to the first node N1, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the first cascade output signal terminal CR1.
  • the first plate of the seventh capacitor C7 is electrically connected to the first node N1, and the second plate is electrically connected to the first cascade output signal terminal CR1.
  • the first cascade output signal terminal CR1 of the first light-emitting control circuit 110 of the upper stage and the first light-emitting control circuit 110 of the lower stage are The first input signal terminal IN1 is electrically connected.
  • the first lighting control signal output subunit 1122 is electrically connected to the first node N1, the first voltage signal terminal VGH and the first output signal terminal EM1, and is configured to convert the voltage from the first voltage under the control of the voltage of the first node N1.
  • the first voltage signal of the signal terminal VGH is transmitted to the first output signal terminal EM1, and a light emission control signal is output to the first light emission control scan line EM1 of the odd row pixel P1 to turn on or off the light emission control transistor T104 of the odd row pixel P1 ( 1).
  • the first light-emitting control signal output sub-unit 1122 of the first light-emitting output unit 112 includes a seventeenth transistor T17.
  • the control electrode of the seventeenth transistor T17 is electrically connected to the first node N1, and the first electrode is connected to the first voltage.
  • the signal terminal VGH is electrically connected, and the second pole is electrically connected to the first output signal terminal EM1.
  • the second lighting output unit 122 may include a second cascade signal output subunit 1221 and a second lighting control signal output subunit 1222 .
  • the second cascade signal output subunit 1221 is electrically connected to the second node N2, the first voltage signal terminal VGH and the second cascade output signal terminal CR2, and is configured to control the voltage of the second node N2.
  • the first voltage signal from the first voltage signal terminal VGH is transmitted to the second cascade output signal terminal CR2, and the second cascade signal is output to the second lighting control sub-circuit 120 of the next lighting control circuit 100.
  • the second cascade signal output subunit 1221 includes a thirty-sixth transistor T36 and an eighth capacitor C8.
  • the control electrode of the thirty-sixth transistor T36 is electrically connected to the second node N2, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the second cascade output signal terminal CR2.
  • the first plate of the eighth capacitor C8 is electrically connected to the second node N2, and the second plate is electrically connected to the second cascade output signal terminal CR2.
  • the second cascade output signal terminal CR2 of the first light-emitting control circuit 120 of the upper stage and the second light-emitting control circuit 120 of the lower stage are The second input signal terminal IN2 is electrically connected.
  • the second light emitting control signal output sub-unit 1222 is electrically connected to the second node N2, the first voltage signal terminal VGH and the second output signal terminal EM2, and is configured to control the voltage of the second node N2.
  • the first voltage signal from the first voltage signal terminal VGH is transmitted to the second output signal terminal EM2, and a lighting control signal is output to the second lighting control scan line EM2 of the even row pixels P2 to turn on or off the lighting control of the even row pixels.
  • Transistor T104 Transistor T104.
  • the second light-emitting control signal output sub-unit 1222 of the second light-emitting output unit 122 includes an eighteenth transistor T18.
  • the control electrode of the eighteenth transistor T18 is electrically connected to the second node N2, and the first electrode It is electrically connected to the first voltage signal terminal VGH, and the second pole is electrically connected to the second output signal terminal EM2.
  • the first lighting control sub-circuit 110 of the lighting control circuit 100 further includes a first pulse width modulation unit 113
  • the second lighting control sub-circuit 120 further includes a second pulse width modulation unit 123 .
  • the first pulse width modulation unit 113 may include a first input subunit 1131.
  • the first input subunit 1131 of the first pulse width modulation unit 113 is electrically connected to the first input signal terminal IN1, the third clock signal terminal CKB1 and the first node N1.
  • the connection is configured to transmit the first input signal from the first input signal terminal IN1 to the first node N1 under the control of the third clock signal from the third clock signal terminal CKB1.
  • the first input subunit 1131 may include a fifth transistor T5, the control electrode of the fifth transistor T5 is electrically connected to the third clock signal terminal CKB1, and the first electrode is electrically connected to the first input signal terminal IN1. , the second pole is electrically connected to the first node N1.
  • the first input signal terminal IN1 may be electrically connected to the first cascade output signal terminal CR1 in the upper-level lighting control circuit 100, and the first input signal is the first cascade signal output by the upper-level lighting control circuit 100.
  • the first input signal terminal IN1 in the first-stage lighting control circuit 100 may be electrically connected to the first start signal terminal STU1 (as shown in FIG. 7 ).
  • the first pulse width modulation unit 113 may also include a sixth transistor T6 , a seventh transistor T7 , and an eighth transistor. T8, the ninth transistor T9, the tenth transistor T10, the thirty-seventh transistor T37 and the third capacitor C3.
  • control electrode of the sixth transistor T6 is electrically connected to the first node N1
  • the first electrode is electrically connected to the second voltage signal terminal LVGL
  • the second electrode is electrically connected to the fifth node N5.
  • the sixth transistor T6 is configured to transmit the second voltage signal from the second voltage signal terminal LVGL to the fifth node N5 under the control of the voltage of the first node N1.
  • the second voltage signal terminal LVGL may continuously output the turn-off voltage signal.
  • the control electrode of the seventh transistor T7 is electrically connected to the fifth node N5, the first electrode is electrically connected to the third voltage signal terminal VGL, and the second electrode is electrically connected to the first output signal terminal EM1.
  • the seventh transistor T7 is configured to transmit the second voltage signal from the third voltage signal terminal VGL to the first output signal terminal EM1 under the control of the voltage of the fifth node N5.
  • the third voltage signal terminal VGL may continuously output a turn-off voltage signal.
  • both the second voltage signal terminal LVGL and the third voltage signal terminal VGL can continuously output the shutdown voltage signal.
  • the level voltages output by the third voltage signal terminal VGL and the second voltage signal terminal LVGL may be the same, or the voltage of the voltage signal output by the third voltage signal terminal VGL is higher than the voltage of the voltage signal output by the second voltage signal terminal LVGL. .
  • the voltage of the voltage signal output by the third voltage signal terminal VGL is higher than the voltage of the voltage signal output by the second voltage signal terminal LVGL.
  • the control electrode of the eighth transistor T8 is electrically connected to the fifth clock signal terminal CKC1, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the sixth node N6.
  • the control electrode of the ninth transistor T9 is electrically connected to the sixth node N6, the first electrode is electrically connected to the third clock signal terminal CKB1, and the second electrode is electrically connected to the seventh node N7.
  • the control electrode of the tenth transistor T10 is electrically connected to the first input signal terminal IN1, the first electrode is electrically connected to the seventh node N7, and the second electrode is electrically connected to the fifth node N7.
  • the first plate of the third capacitor C3 is electrically connected to the sixth node N6, and the second plate is electrically connected to the seventh node N7.
  • the eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the third capacitor C3 are configured to operate when the fifth clock signal from the fifth clock signal terminal CKC1, the third clock signal from the third clock signal terminal CKB1 and Under the control of the first voltage signal of the first voltage signal terminal VGH, the first voltage signal is transmitted to the fifth node N5.
  • the control electrode of the thirty-seventh transistor T37 is electrically connected to the fifth node N5, the first electrode is electrically connected to the second voltage signal terminal LVGL, and the second electrode is electrically connected to the first cascade output signal terminal CR1, and is configured to be at the fifth node Under the control of the voltage of N5, the second voltage signal from the second voltage signal terminal LVGL is transmitted to the first cascade output signal terminal CR1.
  • the first pulse width modulation unit 113 may further include a thirty-eighth transistor T38, a thirty-ninth transistor T39, a fortieth transistor T40, a forty-first transistor T41, a forty-third The second transistor T42, the forty-third transistor T43 and the ninth capacitor C9.
  • the control electrode of the thirty-eighth transistor T38 is electrically connected to the start reset control terminal TRS, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the first node N1. It is configured to start from Under the control of the reset signal of the reset control terminal TRS, the first voltage signal from the first voltage signal terminal VGH is transmitted to the first node N1.
  • the initial reset control terminal TRS is usually turned on for a few lines before the first frame of power-on for circuit initialization, and remains constant low during the display period.
  • the control electrode of the thirty-ninth transistor T39 is electrically connected to the third clock signal segment CKB1, the first end is electrically connected to the eighteenth node N18, and the second electrode is electrically connected to the first node N1.
  • the control electrode of the fortieth transistor T40 is electrically connected to the first node N1, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the eighteenth node N18.
  • the second pole of the fifth transistor T5 is electrically connected to the eighteenth node N18.
  • the second pole of the fifth transistor T5 is electrically connected to the first node N1 through the thirty-ninth transistor T39.
  • the thirty-ninth transistor T39 and the fortieth transistor T40 form an anti-leakage circuit of the fifth transistor T5 and are configured to reduce the leakage current of the fifth transistor T5 in the off state.
  • the control electrode of the forty-first transistor T41 is electrically connected to the first input signal terminal IN1, the first electrode is electrically connected to the fifth clock signal terminal CKC1, and the second electrode is electrically connected to the nineteenth node N19.
  • the forty-first transistor T41 is configured to transmit the fifth clock signal from the fifth clock signal terminal CKC1 to the nineteenth node N19 under the control of the first input signal from the first input signal terminal IN1.
  • the control electrode of the forty-second transistor T42 is electrically connected to the first input signal terminal IN1, the first electrode is electrically connected to the nineteenth node N19, and the second electrode is electrically connected to the seventh node N7.
  • the forty-second transistor T42 is configured to transmit the voltage from the nineteenth node N19 to the seventh node N7 under the control of the first input signal from the first input signal terminal IN1.
  • the control electrode of the forty-third transistor T43 is electrically connected to the seventh node N7, the first electrode is electrically connected to the first voltage signal terminal VGH, the second electrode is electrically connected to the nineteenth node N19, and is configured to be at the seventh node N7 Under the control of the voltage, the first voltage signal from the first voltage signal terminal VGH is transmitted to the nineteenth node N19.
  • the first plate of the ninth capacitor C9 is electrically connected to the second voltage signal terminal LVGL, and the second plate is electrically connected to the fifth node N5.
  • the first pulse width modulation unit 113 may only include the thirty-eighth transistor T38, the thirty-ninth transistor T39, the fortieth transistor T40, the forty-first transistor T41, the forty-second transistor T42, Some of the forty-third transistors T43.
  • the first pulse width modulation unit 113 may include a thirty-seventh transistor T37, a thirty-eighth transistor T38, and a forty-first transistor T41.
  • the first pulse width modulation unit 113 further includes a thirty-ninth transistor T39 and a fortieth transistor T40.
  • the embodiments of the present disclosure can realize the above-mentioned thirty-eighth transistor T38, thirty-ninth transistor T39, fortieth transistor T40, forty-first transistor T41, forty-second transistor T42, and forty-third transistor T43. The functions and functions will not be described again.
  • the second pulse width modulation unit 123 may include a second input subunit 1231 , and the second input subunit 1231 of the second pulse width modulation unit 123 is connected to the second input signal terminal IN2 and the fourth input signal terminal IN2 .
  • the clock signal terminal CKB2 and the second node N2 are electrically connected and configured to transmit the second input signal from the second input signal terminal IN2 to the second node under the control of the fourth clock signal from the fourth clock signal terminal CKB2 N2.
  • the second input subunit 1231 may include an eleventh transistor T11.
  • the control electrode of the eleventh transistor T11 is electrically connected to the fourth clock signal terminal CKB2, and the first electrode is connected to the second input signal terminal IN2. Electrically connected, the second pole is electrically connected to the second node N2.
  • the second input signal terminal IN2 may be electrically connected to the second cascade output signal terminal CR2 in the upper-level lighting control circuit 100, and the second input signal is the second cascade signal output by the upper-level lighting control circuit 100.
  • the first input signal terminal IN1 in the first-stage lighting control circuit 100 may be electrically connected to the second start signal terminal STU2 (as shown in FIG. 7 ).
  • the second pulse width modulation unit 123 may further include a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a forty-sixth transistor T46, and a fourth capacitor. C4.
  • the control electrode of the twelfth transistor T12 is electrically connected to the second node N2, the first electrode is electrically connected to the second voltage signal terminal LVGL, and the second electrode is electrically connected to the eighth node N8.
  • the twelfth transistor T12 is configured to transmit the second voltage signal from the second voltage signal terminal LVGL to the eighth node N8 under the control of the voltage of the second node N2.
  • the control electrode of the thirteenth transistor T13 is electrically connected to the eighth node N8, the first electrode is electrically connected to the third voltage signal terminal VGL, and the second electrode is electrically connected to the second output signal terminal EM2.
  • the thirteenth transistor T13 is configured to transmit the third voltage signal from the third voltage signal terminal VGL to the second output signal terminal EM2 under the control of the voltage of the eighth node N8.
  • the control electrode of the forty-sixth transistor T46 is electrically connected to the eighth node N8, the first electrode is electrically connected to the second voltage signal terminal LVGL, and the second electrode is electrically connected to the second cascade output signal terminal CR2.
  • the forty-sixth transistor T46 is configured to transmit the second voltage signal from the second voltage signal terminal LVGL to the second cascade output signal terminal CR2 under the control of the voltage of the eighth node N8.
  • the control electrode of the fourteenth transistor T14 is electrically connected to the sixth clock signal terminal CKC2, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the ninth node N9.
  • the control electrode of the fifteenth transistor T15 is electrically connected to the ninth node N9, the first electrode is electrically connected to the fourth clock signal terminal CKB2, and the second electrode is electrically connected to the tenth node N10.
  • the control electrode of the sixteenth transistor T16 is electrically connected to the second input signal terminal IN2, the first electrode is electrically connected to the tenth node N10, and the second electrode is electrically connected to the eighth node N8.
  • the first plate of the fourth capacitor C4 is electrically connected to the ninth node N9, and the second plate is electrically connected to the tenth node N10.
  • the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the fourth capacitor C4 are configured to operate when the sixth clock signal from the sixth clock signal terminal CKC2, the fourth clock signal from the fourth clock signal terminal CKB2
  • the first voltage signal is transmitted to the eighth node N8 under the control of the clock signal and the first voltage signal from the first voltage signal terminal VGH.
  • the second pulse width modulation unit 123 may further include a forty-fifth transistor T45, a forty-sixth transistor T46, a forty-seventh transistor T47, a forty-eighth transistor T48, a fourth Nineteenth transistor T49, fiftieth transistor T50 and tenth capacitor C10.
  • the control electrode of the forty-fifth transistor T45 is electrically connected to the start reset control terminal TRS, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the second node N2. Under the control of the reset signal of the reset control terminal TRS, the first voltage signal from the first voltage signal terminal VGH is transmitted to the second node N2.
  • the control electrode of the forty-sixth transistor T46 is electrically connected to the fourth clock signal terminal CKB2, the first electrode is electrically connected to the twentieth node N20, and the second electrode is electrically connected to the second node N2.
  • the control electrode of the forty-seventh transistor T47 is electrically connected to the second node N2, the first electrode is electrically connected to the twentieth node N20, and the second electrode is electrically connected to the second node N2.
  • the forty-sixth transistor T46 and the forty-seventh transistor T47 together form an anti-leakage circuit of the eleventh transistor T11 and are configured to reduce the leakage current of the eleventh transistor T11 in the off state.
  • the control electrode of the forty-eighth transistor T48 is electrically connected to the second input signal terminal IN2, the first electrode is electrically connected to the sixth clock signal terminal CKC2, and the second electrode is electrically connected to the twenty-first node N21.
  • the forty-eighth transistor T48 is configured to transmit the sixth clock signal from the sixth clock signal terminal CKC2 to the twenty-first node N21 under the control of the second input signal from the second input signal terminal IN2.
  • the control electrode of the forty-ninth transistor T49 is electrically connected to the second input signal terminal IN2, the first electrode is electrically connected to the twenty-first node N21, and the second electrode is electrically connected to the ninth node N9.
  • the forty-ninth transistor T49 is configured to transmit the voltage of the twenty-first node N21 to the ninth node N9 under the control of the second input signal from the second input signal terminal IN2.
  • the control electrode of the fiftieth transistor T50 is electrically connected to the ninth node N9, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the twenty-first node N21.
  • the fiftieth transistor T50 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the twenty-first node N21 under the control of the voltage of the ninth node N9.
  • the first plate of the tenth capacitor C10 is electrically connected to the second voltage signal terminal LVGL, and the second plate is electrically connected to the eighth node N8.
  • the light emitting control circuit 100 includes the first pulse width modulation unit 113 and the second pulse width modulation unit 123 described in any of the above embodiments, and selects a group of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 to pair the light-emitting device EL In case of compensation.
  • one of the first lighting control sub-circuit 110 and the second lighting control sub-circuit 120 that is electrically connected to the corresponding group of odd-numbered row pixels P1 and even-numbered row pixels P outputs a pulse width modulation signal, To modulate the light-emitting time of odd-numbered row pixels P1 and even-numbered row pixels P2; the other outputs a pulse signal during the blank phase B to make the operating current flow through odd-numbered row pixels P1 or even-numbered row pixels P2 (selected row pixel P) Light emitting device EL.
  • control method of the lighting control circuit 100 also includes:
  • the first pulse width modulation unit 113 transmits the first input signal from the first input signal terminal IN1 to the first node N1 under the control of the third clock signal CKB1.
  • the first light-emitting output unit 112 transmits the first voltage signal to the first output signal terminal EM1 under the control of the voltage of the first node N1 to modulate the light-emitting time of the odd-numbered row pixels P1 and the even-numbered rows of pixels P2.
  • the second detection control unit 123 transmits the first voltage signal to the second node N2.
  • the second light-emitting output unit 122 transmits the first voltage signal to the second output signal terminal EM2 under the control of the voltage of the second node N2, so that the operating current flows through the light-emitting device EL of the odd-numbered row pixels P1 or the even-numbered rows of pixels P2.
  • the operating current flowing through the light-emitting device EL of the odd-numbered row pixel P1 or the even-numbered row pixel P2 means charging the anode of the light-emitting device EL of the pixel row P selected for compensation.
  • FIG. 18 is a timing control diagram of the lighting control circuit 100 .
  • the first start signal terminal Stu1 outputs a pulse signal
  • the first input signal terminal IN1 of the first lighting control sub-circuit 110 receives the pulse signal.
  • the first pulse width modulation unit 113 of the first lighting control sub-circuit 110 turns on the fifth transistor T5 and the thirty-ninth transistor T39 to receive the first input signal from the first input signal terminal IN1. The signal is transmitted to the first node N1.
  • the first light-emitting output unit 112 (the seventeenth transistor T17) transmits the first voltage signal to the first output signal terminal EM1 under the control of the voltage of the first node N1, so as to control the pixels P1 in the odd rows and the pixels P2 in the even rows.
  • the luminescence time is modulated.
  • the thirty-fifth transistor T35 transmits the first voltage signal to the first cascade signal output signal terminal CR1 under the control of the voltage of the first node N1 to the first lighting control sub-circuit 110 of the next lighting control circuit 100
  • the first input signal terminal IN1 outputs the first cascade signal.
  • blank phase B see Figure 17A, Figure 17B and Figure 18.
  • a group of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting device EL.
  • the detection control terminal VH turns on the first transistor T1 and the third transistor T3.
  • the first clock signal terminal CKA1 continues to output a shutdown voltage signal (ie does not output a pulse signal), and the third node N3 has no signal input, so the voltage of the third node N3 remains unchanged (at the shutdown voltage).
  • the second clock signal terminal CKA2 outputs a pulse signal, which is written into the fourth node N4 through the third transistor T3, and the potential of the fourth node N3 rises to the operating voltage.
  • the fourth transistor T4 is turned on under the voltage control of the fourth node N4, and the first voltage signal of the first voltage signal terminal VGH is transmitted to the second node N2. That is, the second detection control unit 121 transmits the first voltage signal to the second node N2.
  • the eighteenth transistor T18 (the second light emitting output unit 122) is turned on under the control of the second node N2, and the first voltage signal of the first voltage signal terminal VGH is transmitted to the second output signal terminal EM2 through the eighteenth transistor T18.
  • control method of the lighting control circuit 100 further includes:
  • the second pulse width modulation unit 123 transmits the second input signal to the second node N2 under the control of the fourth clock signal CKB2; the second light emitting output unit 122 is under the control of the voltage of the second node N2 , transmitting the first voltage signal to the second output signal terminal EM2 to modulate the light emitting time of the pixels P1 in the odd rows and the pixels P2 in the even rows.
  • the first detection control unit 111 transmits the first voltage signal to the first node N1
  • the first light-emitting output unit 112 transmits the first voltage signal to the second output signal terminal EM2 under the control of the voltage of the first node N1, so that the operating current flows through the light-emitting device EL of the odd-numbered row pixels P1 or the even-numbered rows of pixels P2. .
  • the second start signal terminal Stu2 outputs a pulse signal
  • the second input signal terminal IN2 of the second lighting control sub-circuit 110 can Pulse signal received.
  • the second pulse width modulation unit 123 of the second light emitting control sub-circuit 120 turns on the eleventh transistor T5 and the forty-sixth transistor T46 to transmit the first signal from the second input signal terminal IN2.
  • the input signal is transmitted to the second node N2.
  • the second light emitting output unit 122 (the eighteenth transistor T18 ) transmits the first voltage signal to the second output signal terminal EM2 under the control of the voltage of the second node N2 to control the pixels P1 in the odd rows and the pixels P2 in the even rows.
  • the luminescence time is modulated.
  • the thirty-sixth transistor T36 transmits the first voltage signal to the second cascade signal output signal terminal CR2 under the control of the voltage of the second node N2 to the second lighting control sub-circuit 120 of the next lighting control circuit 100
  • the second input signal terminal IN2 outputs a second cascade signal.
  • blank phase B see Figure 17A, Figure 17B and Figure 18.
  • blank phase B of the last two frame periods F when a group of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting device EL.
  • the detection control terminal VH turns on the first transistor T1 and the third transistor T3.
  • the first clock signal terminal CKA1 outputs a pulse signal, which is written into the third node N3, and the potential of the third node N3 rises to the operating voltage.
  • the second clock signal terminal CKA2 continues to output the shutdown voltage, and the potential of the fourth node N3 continues to be the shutdown voltage.
  • the second transistor T2 is turned on under the voltage control of the third node N3, and the first voltage signal of the first voltage signal terminal VGH is transmitted to the first node N1. That is, the first detection control unit 111 transmits the first voltage signal to the first node N1.
  • the seventeenth transistor T17 (first light emitting output unit 112) is turned on under the control of the first node N1, and the first voltage signal of the first voltage signal terminal VGH is transmitted to the first output signal terminal EM1 through the seventeenth transistor T17.
  • control method of the lighting control circuit 100 further includes:
  • the first clock signal terminal CKA1, the second input signal terminal IN2 and the fourth clock signal terminal CKB2 output pulse signals, and the second clock signal terminal CKA2, the first input signal terminal CR1 and the third clock signal Terminal CKB1 does not output a voltage signal.
  • control method of the lighting control circuit 100 further includes:
  • the second clock signal terminal CKA2 In the same frame period F, the second clock signal terminal CKA2, the first input signal terminal CR1 and the third clock signal terminal CKB1 output pulse signals, and the first clock signal terminal CKA1, the second input signal terminal IN2 and the fourth clock signal Terminal CKB2 does not output a voltage signal.
  • the random detection circuit (random Sense unit) 200 is electrically connected to the random detection signal terminal OE, the third input signal terminal IN3, the seventh clock signal terminal CKD and the eleventh node N11 , is configured to transmit the seventh clock signal from the seventh clock signal terminal CKD to the eleventh under the control of the random detection signal from the random detection signal terminal OE and the third input signal from the third input signal terminal IN3 Node N11 is used to select a row of pixels for compensation of the EL of the light-emitting device.
  • the random detection circuit 200 can generate a random detection signal, and then select pixels in different rows in each frame to compensate the light-emitting devices of the pixels P in different rows, thereby achieving the purpose of random compensation.
  • the shift register circuit 300 is electrically connected to the eleventh node N11 and is configured to output a scanning signal to the corresponding row of pixels P under the voltage control of the eleventh node N11 to turn on the corresponding row of pixels P.
  • the detection control terminal VH of the light emission control circuit 100 in any of the above embodiments is electrically connected to a circuit node in the random detection circuit 200 or a circuit node in the shift register circuit 300 . In this way, there is no need to set up an additional signal control terminal to provide a signal to the detection control terminal VH, thereby simplifying the gate drive circuit 1120.
  • the random detection circuit 200 includes a random detection control subcircuit 210 and a detection output subcircuit 220 .
  • the random detection control subcircuit 210 is electrically connected to the random detection signal terminal OE, the third input signal terminal IN3 and the twelfth node N12, and is configured to control the random detection signal from the third input signal under the control of the random detection signal terminal OE.
  • the third input signal of the signal terminal IN3 is transmitted to the twelfth node N12.
  • the third input signal terminal IN3 can be a cascade input signal terminal, and the third input signal terminal IN3 is connected with the third cascade output signal terminal or the fourth cascade output signal of the shift register circuit 300 in the upper gate drive circuit 1120 terminal electrical connection.
  • the detection output sub-circuit 220 is electrically connected to the twelfth node N12, the seventh clock signal terminal CKD and the eleventh node N11, and is configured to convert the seventh clock signal under the voltage control of the twelfth node N12. Transmitted to the eleventh node N11.
  • the detection control terminal VH of the light emission control circuit 100 is electrically connected to the twelfth node N12.
  • the random detection control sub-circuit 210 includes a nineteenth transistor T19.
  • the control electrode of the nineteenth transistor T19 is electrically connected to the random detection signal terminal OE, and the first electrode is electrically connected to the third input signal terminal IN3.
  • the second pole is electrically connected to the twelfth node N12.
  • the detection output sub-circuit 220 includes a twentieth transistor T20.
  • the control electrode of the twentieth transistor T20 is electrically connected to the twelfth node N12, the first electrode is electrically connected to the seventh clock signal terminal CKD, and the second electrode is electrically connected to the eleventh node. N11 electrical connection.
  • the random detection circuit 200 further includes a first energy storage sub-circuit 230 and a first anti-leakage electronic circuit 240 .
  • the first energy storage sub-circuit 230 is electrically connected to the fourth voltage signal terminal VDD and the twelfth node N12, and is configured to maintain the voltage of the twelfth node N12.
  • the fourth voltage signal terminal VDD may be the same as the power supply voltage signal terminal VDD in the pixel driving circuit 1110. Therefore, the same label "VDD" is used for both. In this way, the number of voltage signal terminals can be reduced, thereby simplifying the circuit structure of the display panel 1000 .
  • the first anti-leakage electronic circuit 240 is electrically connected to the random detection control sub-circuit 210, the random detection signal terminal OE, the twelfth node N12 and the fourth voltage signal terminal VDD, and is configured to respond to the random detection signal from the random detection signal terminal OE. Under the control of the voltage of the twelfth node and the fourth voltage signal terminal VDD, the fourth voltage signal from the fourth voltage signal terminal VDD is transmitted to the eleventh node N11.
  • the first energy storage sub-circuit 230 includes a fifth capacitor C5.
  • the first plate of the fifth capacitor C5 is electrically connected to the fourth voltage signal terminal VDD, and the second pole is electrically connected to the twelfth node N12. connect.
  • the first anti-leakage electronic circuit 240 includes a twenty-first transistor T21 and a twenty-second transistor T22.
  • the control electrode of the twenty-first transistor T21 is electrically connected to the random detection signal terminal OE.
  • the first The first pole is electrically connected to the thirteenth node N13, and the second pole is electrically connected to the twelfth node N12.
  • the control electrode of the twenty-second transistor T22 is electrically connected to the twelfth node N12, the first electrode is electrically connected to the fourth voltage signal terminal VDD, and the second electrode is electrically connected to the thirteenth node N13.
  • the random detection control sub-circuit 210 is electrically connected to the twelfth node N12 through the first anti-leakage electronic circuit 240 . That is, the second pole of the nineteenth transistor T19 is electrically connected to the twelfth node N12 through the twenty-first transistor T21.
  • the second electrode of the nineteenth transistor T19 is electrically connected to the first electrode of the twenty-first transistor T21, and the control electrode of the nineteenth transistor T19 and the control electrode of the twenty-first transistor T21 are both connected to the random detection
  • the signal terminal OE is electrically connected, so that when the working level of the signal terminal OE is randomly detected, the control electrode of the nineteenth transistor T19 and the twenty-first transistor T21 are turned on at the same time, and the third input signal from the third input signal terminal IN3
  • the input signal can be transmitted to the twelfth node N12 through the control electrode of the nineteenth transistor T19 and the twenty-first transistor T21 in sequence.
  • Control methods include:
  • the random detection circuit 200 of the gate driving circuit 1120 transmits the third input signal from the third input signal terminal IN3 to the random detection circuit under the control of the random detection signal (from the random detection signal terminal OE).
  • the circuit node NX (the twelfth node N12) in 200 is maintained at the corresponding circuit node NX voltage to the blank phase B.
  • the random detection circuit 200 transmits the seventh clock signal from the seventh clock signal terminal CKD to the shift register circuit 300 of the gate driving circuit 1120 under the control of the voltage of the circuit node NX.
  • the shift register circuit outputs a scan signal to the corresponding row pixel P (a row of pixels P selected for light emitting device EL compensation) to turn on the corresponding row pixel P (turn on the data writing transistor T102 of the corresponding row pixel P).
  • the light emission control circuit 1000 of the gate drive circuit 1120 controls the voltage of the circuit node NX in the random detection circuit 200 or the voltage of the circuit node NY (the fourteenth node N14 or the fifteenth node N15) in the shift register circuit 300 Next, the first voltage signal is transmitted to the first output signal terminal EM1 or the second output signal terminal EM2, so that the operating current flows through the light-emitting devices of the odd-numbered row pixels P1 or the even-numbered rows of pixels P2.
  • the circuit node NX of the random detection circuit 200 and the circuit node NY in the shift register circuit 300 can both output operating voltages to the detection control terminal VH of the light emitting control circuit 100 .
  • the light emission control circuit 100 transmits the first voltage signal to the first output signal terminal EM1 or the second output signal terminal EM2 under the control of the detection control signal from the detection control terminal VH. Please refer to the control method of the light emitting control circuit 100 mentioned above, which will not be described again here.
  • shift register circuit 300 includes first shift register sub-circuit 310 and second shift register sub-circuit 320.
  • the first shift register sub-circuit 310 includes a first compensation input unit 311 and a first scan output unit 312.
  • the second shift register sub-circuit 320 includes a second compensation input unit 321 and a second scan output unit 322.
  • the first compensation input unit 311 is electrically connected to the eleventh node N11, the seventh clock signal terminal CKD and the fourteenth node N14, and is configured to be under the control of the seventh clock signal from the seventh clock signal terminal CKD, The voltage of the eleventh node N11 is transmitted to the fourteenth node N14.
  • the first scan output unit 312 is electrically connected to the fourteenth node N14, the eighth clock signal terminal CKE1 and the third output signal terminal GL1.
  • the third output signal terminal GL1 is configured to be electrically connected to the odd-numbered row pixel P1 (with the odd-numbered row pixel
  • the data of P1 is written into the transistor T102 (the control electrode of 1 is electrically connected).
  • the first scan output unit 312 is configured to transmit the eighth clock signal from the eighth clock signal terminal CKE1 to the third output signal terminal GL1 under the control of the voltage of the fourteenth node N14 to turn on the corresponding odd-numbered row pixels. P1 (turn on data writing transistor T102(1)).
  • the third output signal terminal GL1 is electrically connected to the first gate line GL1.
  • the same label "GL1" is used for both.
  • the fourth output signal terminal GL2 is electrically connected to the second gate line GL2.
  • the same label "GL2" is used for both.
  • the second compensation input unit 321 is electrically connected to the eleventh node N11, the seventh clock signal terminal CKD and the fifteenth node N15, and is configured to transmit the voltage of the eleventh node N11 under the control of the seventh clock signal CKD. to the fifteenth node N15.
  • the second scan output unit 322 is electrically connected to the fifteenth node N15, the ninth clock signal terminal CKE2 and the fourth output signal terminal GL2.
  • the fourth output signal terminal GL2 is configured to be electrically connected to the even row pixels P2 (with the even row pixels P2).
  • the data of P2 is written to the control electrode of transistor T102 (2) is electrically connected).
  • the second scan output unit 322 is configured to transmit the ninth clock signal from the ninth clock signal terminal CKE2 to the fourth output signal terminal GL2 under the control of the voltage of the fifteenth node N15 to turn on the corresponding even row pixels. P2 (turn on data writing transistor T102(2)).
  • the first compensation input unit 311 includes a twenty-third transistor T23, the control electrode of the twenty-third transistor T23 is electrically connected to the seventh clock signal terminal CKD, and the first electrode is electrically connected to the eleventh node, The second pole is electrically connected to the fourteenth node N14.
  • the first scan output unit 312 includes a twenty-fourth transistor T24.
  • the control electrode of the twenty-fourth transistor T24 is electrically connected to the fourteenth node N14, the first electrode is electrically connected to the eighth clock signal terminal CKE1, and the second electrode is electrically connected to the eighth clock signal terminal CKE1.
  • the three output signal terminals GL1 are electrically connected.
  • the second compensation input unit 321 includes a twenty-fifth transistor T25.
  • the control electrode of the twenty-fifth transistor T25 is electrically connected to the seventh clock signal terminal CKD, the first electrode is electrically connected to the eleventh node N11, and the second electrode is electrically connected to the eleventh node N11. Fifteen nodes N15 are electrically connected.
  • the second scan output unit 322 includes a twenty-sixth transistor T26.
  • the control electrode of the twenty-sixth transistor T26 is electrically connected to the fifteenth node N15, the first electrode is electrically connected to the ninth clock signal terminal CKE2, and the second electrode is electrically connected to the ninth clock signal terminal CKE2.
  • the four output signal terminals GL2 are electrically connected.
  • the detection control terminal VH of the lighting control circuit 100 in any of the above embodiments is electrically connected to the fourteenth node N14 or the fifteenth node N15.
  • the first shift register sub-circuit 310 further includes a first scan input unit 313, a first inverter 314 and a first reset unit 315.
  • the first scan input unit 313 is electrically connected to the third input signal terminal IN3, the fourth voltage signal terminal VDD and the fourteenth node N14, and is configured to control the third input signal from the third input signal terminal IN3.
  • the fourth voltage signal from the fourth voltage signal terminal VDD is transmitted to the fourteenth node N14.
  • One end of the first inverter 314 is electrically connected to the fourteenth node N14, and the other end is electrically connected to the sixteenth node N16.
  • first inverter 314 and the second inverter 324 are common techniques in the art, and will not be described again in this application.
  • the first reset unit is electrically connected to the first reset signal terminal Std1, the sixteenth node N16, the fifth voltage signal terminal LVGL, the fourteenth node N14 and the third output signal terminal GL1, and is configured to receive a signal from the first reset signal terminal. Under the control of the first reset signal of Std1 and the voltage of the sixteenth node N16, the fifth voltage signal of the fifth voltage signal terminal LVGL is transmitted to the fourteenth node N14 and the third output signal terminal GL1.
  • both the fifth voltage signal LVGL and the second voltage signal terminal LVGL can continuously output low-level voltage signals.
  • the two can be the same or different.
  • the fifth voltage signal terminal LVGL and the second voltage signal terminal LVGL are the same as an example for exemplary explanation.
  • the first scan input unit 313 includes a twenty-seventh transistor T27.
  • the control electrode of the twenty-seventh transistor T27 is electrically connected to the third input signal terminal IN3, and the first electrode is connected to the fourth voltage signal terminal.
  • VDD is electrically connected, and the second pole is electrically connected to the fourteenth node N14.
  • the first reset unit 315 may include a twenty-eighth transistor T28, a twenty-ninth transistor T29, and a thirtieth transistor T30.
  • the control electrode of the twenty-eighth transistor T28 is electrically connected to the first reset signal terminal Std1, the first electrode is electrically connected to the fifth voltage signal terminal LVGL, and the second electrode is electrically connected to the fourteenth node N14.
  • the control electrode of the twenty-ninth transistor T29 is electrically connected to the sixteenth node N16, the first electrode is electrically connected to the fifth voltage signal terminal LVGL, and the second electrode is electrically connected to the third output signal terminal GL1.
  • the control electrode of the thirtieth transistor T30 is electrically connected to the sixteenth node N16, the first electrode is electrically connected to the fifth voltage signal terminal LVGL, and the second electrode is electrically connected to the fourteenth node N14.
  • the first shift register sub-circuit may further include a fifty-first transistor T51, a fifty-second transistor T52, a fifty-third transistor T53, a fifty-fourth transistor T54, and a tenth transistor. a capacitor C11.
  • the control electrode of the fifty-first transistor T51 is electrically connected to the first reset signal terminal Std1
  • the first electrode is electrically connected to the twenty-second node N22 (the second electrode of the twenty-eighth transistor T28)
  • the second electrode is electrically connected to the tenth Four nodes are electrically connected.
  • the second pole of the twenty-eighth transistor T28 is electrically connected to the fourteenth node N14 through the fiftieth transistor T51.
  • the control electrode of the fifty-second transistor T52 is electrically connected to the sixteenth node N16, the first electrode is electrically connected to the twenty-second node N22 (the second electrode of the thirtieth transistor T30), and the second electrode is electrically connected to the fourteenth node N14 electrical connection.
  • the second electrode of the thirtieth transistor T30 is electrically connected to the fourteenth node N14 through the fifty-second transistor T52.
  • the control electrode of the fifty-third transistor T53 is electrically connected to the seventh clock signal terminal CKD, the first electrode is electrically connected to the twenty-second node N22, and the second electrode is electrically connected to the fourteenth node N14.
  • the second pole of the twenty-third transistor T23 is electrically connected to the fourteenth node N14 through the fifty-third transistor T53.
  • the control electrode of the fifty-fourth transistor T54 is electrically connected to the fourteenth node N14, the first electrode is electrically connected to the fourth voltage signal terminal VDD, and the second electrode is electrically connected to the twenty-second node N22.
  • the second shift register sub-circuit 320 further includes a second scan input unit 323 , a second inverter 324 and a second reset unit 325 .
  • the second scan input unit 323 is electrically connected to the third input signal terminal IN3, the fourth voltage signal terminal VDD and the fifteenth node N15, and is configured to transmit the third voltage signal to the tenth node under the control of the third input signal. Five nodes N15.
  • One end of the second inverter 324 is electrically connected to the fifteenth node N15, and the other end is electrically connected to the seventeenth node N17.
  • the second reset unit 325 is electrically connected to the second reset signal terminal Std2, the fifth voltage signal terminal LVGL, the fifteenth node N16, the seventeenth node N17 and the fourth output signal terminal GL2, and is configured to receive a signal from the second reset signal. Under the control of the second reset signal at terminal Std2 and the voltage of the seventeenth node N17, the fifth voltage signal from the fifth voltage signal terminal LVGL is transmitted to the fifteenth node N15 and the fourth output signal terminal GL2.
  • the second scan input unit 323 includes a thirty-first transistor T31.
  • the control electrode of the thirty-first transistor T31 is electrically connected to the third input signal terminal IN3, and the first electrode is connected to the fourth voltage signal terminal.
  • VDD is electrically connected, and the second pole is electrically connected to the fifteenth node N15.
  • the second reset unit 325 includes a thirty-second transistor T32, a thirty-third transistor T33, and a thirty-fourth transistor T34.
  • the control electrode of the thirty-second transistor T32 is electrically connected to the second reset signal terminal Std2, the first electrode is electrically connected to the fifth voltage signal terminal LVGL, and the second electrode is electrically connected to the fifteenth node N15.
  • the control electrode of the thirty-third transistor T33 is electrically connected to the seventeenth node N17, the first electrode is electrically connected to the fifth voltage signal terminal VLGL, and the second electrode is electrically connected to the fourth output signal terminal GL2.
  • the control electrode of the thirty-fourth transistor T34 is electrically connected to the seventeenth node N17, the first electrode is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode is electrically connected to the fifteenth node N15.
  • the second shift register sub-circuit 320 further includes a fifty-fifth transistor T55, a fifty-sixth transistor T56, a fifty-seventh transistor T57, and a fifty-eighth transistor T58.
  • the control electrode of the fifty-fifth transistor T55 is electrically connected to the second reset signal terminal Std2, the first electrode is electrically connected to the twenty-third node N23 (the second electrode of the thirty-second transistor T32), and the second electrode is electrically connected to the tenth node N23. Five node N15 electrical connections.
  • the second electrode of the thirty-second transistor T32 is electrically connected to the fifteenth transistor through the fifty-fifth transistor T55.
  • the control electrode of the fifty-sixth transistor T56 is electrically connected to the seventeenth node N17, the first electrode is electrically connected to the twenty-third node N23 (the second electrode of the thirty-fourth transistor T34), and the second electrode is electrically connected to the fifteenth node N17. Node N15 is electrically connected.
  • the second pole of the thirty-fourth transistor T34 is electrically connected to the fifteenth node N15 through the fifty-sixth transistor T56.
  • the control electrode of the fifty-seventh transistor T57 is electrically connected to the seventh clock signal terminal CKD, the first electrode is electrically connected to the twenty-third N23 node (the second electrode of the twenty-fifth transistor T25), and the second electrode is electrically connected to the tenth Five node N15 electrical connections.
  • the second pole of the twenty-fifth transistor T25 is electrically connected to the fifteenth node N15 through the fifty-seventh transistor T57.
  • the control electrode of the fifty-eighth transistor T58 is electrically connected to the fifteenth node, the first electrode is electrically connected to the fourth voltage signal terminal VDD, and the second terminal is electrically connected to the twenty-third node N23.
  • Some embodiments of the present disclosure also provide a gate driving circuit control method for driving the gate driving circuit 1120 in any of the above embodiments.
  • Control methods include:
  • the random detection circuit 200 of the gate driving circuit 1120 transmits the third input signal from the third input signal terminal IN3 to the random detection circuit under the control of the random detection signal (from the random detection signal terminal OE).
  • the circuit node NX (the twelfth node N12) in 200 is maintained at the corresponding circuit node NX voltage to the blank phase B.
  • the random detection signal terminal OE and the third input signal terminal IN3 output high-level signals, and the nineteenth transistor T19 and the twenty-first transistor T21 are in It is turned on under the control of the random detection signal from the random detection signal terminal OE, and the third input signal (high level signal) from the third input signal terminal IN3 is transmitted to the twelfth node N12 in the random detection circuit 200 .
  • the twentieth transistor T20 is turned on.
  • the random detection signal terminal OE and the third input signal terminal IN3 output a low-level signal
  • the twenty-first transistor T21 is turned off, and the voltage of the twelfth node N12 remains unchanged under the action of the fifth capacitor C5.
  • the random detection circuit 200 transmits the seventh clock signal from the seventh clock signal terminal CKD to the shift register circuit of the gate driving circuit 1120 under the control of the voltage of the circuit node NX (twelfth node). 300.
  • the voltage of the twelfth node N12 remains unchanged under the action of the fifth capacitor C5, and the twentieth transistor T20 remains open.
  • the seventh clock signal terminal CKD outputs a high-level seventh clock signal, and the seventh clock signal is transmitted to the eleventh node N11 through the twentieth transistor T20.
  • the shift register circuit outputs a scan signal to the corresponding row pixel P (a row of pixels P selected for light emitting device EL compensation) to turn on the corresponding row pixel P (turn on the data writing transistor T102 of the corresponding row pixel P).
  • the twenty-third transistor T23 and the fifty-third transistor T53 are turned on at the same time, and the seventh clock signal at the eleventh node N11 The signal is transmitted to the fourteenth node N14.
  • the twenty-fourth transistor T24 is turned on.
  • the seventh clock signal at the eleventh node N11 can also be transmitted to the fifteenth node N15.
  • the voltage of the fifteenth node N15 controls the twenty-sixth transistor T26 to turn on.
  • One of the seventh clock signal terminal CKE1 and the eighth clock signal terminal CKE2 outputs a high-level voltage signal and transmits it to the third output signal terminal GL1 or the fourth output signal terminal GL2.
  • the seventh clock signal terminal CKE1 when the odd-numbered row pixel P1 is selected for EL compensation of the light-emitting device, the seventh clock signal terminal CKE1 outputs a high-level voltage signal, and the high-level voltage signal output by the seventh clock signal terminal CKE1 passes through the twenty-fourth
  • the transistor T24 is transmitted to the third output signal terminal GL1 and outputs a scanning signal to the odd row pixels P1, and the data writing transistor T102(1) of the odd row pixels P1 is turned on.
  • the eighth clock signal terminal CKE2 when the even-numbered row pixel P2 is selected for EL compensation of the light-emitting device, the eighth clock signal terminal CKE2 outputs a high-level voltage signal, and the high-level voltage signal output by the eighth clock signal terminal CKE2 passes through the twenty-sixth
  • the transistor T26 transmits to the fourth output signal terminal GL2 and outputs a scanning signal to the even row pixel P2, and the data writing transistor T102(2) of the even row pixel P2 is turned on.
  • the light emission control circuit 1000 of the gate drive circuit 1120 controls the voltage of the circuit node NX in the random detection circuit 200 or the voltage of the circuit node NY (the fourteenth node N14 or the fifteenth node N15) in the shift register circuit 300 Next, the first voltage signal is transmitted to the first output signal terminal EM1 or the second output signal terminal EM2, so that the operating current flows through the light-emitting device EL of the odd-numbered row pixels P1 or the even-numbered rows of pixels P2.
  • the operating current flowing through the light-emitting device EL of the odd-numbered row pixel P1 or the even-numbered row pixel P2 means charging the anode of the light-emitting device EL of the selected row pixel P.
  • the circuit node NX of the random detection circuit 200 and the circuit node NY of the shift register circuit 300 can both output operating voltage signals to the detection control terminal VH of the light emitting control circuit 100 .
  • the light emission control circuit 100 transmits the first voltage signal to the first output signal terminal EM1 or the second output signal terminal EM2 under the control of the detection control signal from the detection control terminal VH.
  • the detection control terminal VH of the light emission control circuit 100 is electrically connected to the twelfth node in the random detection circuit 200 .
  • the twelfth node N12 outputs a high-level voltage signal, which can control the lighting control circuit 100 to transmit the first voltage signal to the first output signal terminal EM1 or the second output signal terminal EM2 to turn on Odd row pixels P1 (light emitting control transistor T104(1)) or even row pixels P2 (light emitting control transistor T104(1)).
  • the working process of the light emitting control circuit 100 is as described above and will not be described again here.
  • the detection control terminal VH of the light emission control circuit 100 is electrically connected to the fourteenth node or the fifteenth node N14 in the shift register circuit 300 .
  • both the fourteenth node N14 and the fifteenth node N152 can output high-level voltage signals, and the first voltage signal of the light-emitting control circuit 100 is transmitted to the first output signal terminal EM1 or the second output signal terminal EM2.
  • the working process of the lighting control circuit 100 will not be described again here.
  • the first output signal terminal EM1 of the light-emitting control circuit 110 of the gate driving circuit 1120 is electrically connected to the odd-numbered row pixels P1
  • the second output signal terminal EM2 of the light-emitting control circuit 100 is electrically connected to the even-numbered row pixels P2.
  • the shift register circuit 300 includes a first shift register sub-circuit 310 and a second shift register sub-circuit 320.
  • the first shift register sub-circuit 310 includes a first scan input unit 313 and a first scan output unit 312.
  • the shift register sub-circuit 320 includes a second scan input unit 323 and a second scan output unit 322;
  • the first light-emitting control sub-circuit 110 of the light-emitting control circuit 100 includes a first pulse width modulation unit 113, and the second light-emitting control sub-circuit 120 includes The second pulse width modulation unit 123.
  • the first scan input unit 313 inputs the fourth voltage signal to the fourteenth node N14 under the control of the third input signal IN3; the first scan output unit 312 inputs the fourth voltage signal to the fourteenth node N14 under the control of the voltage. , transmitting the eighth clock signal to the third output signal terminal GL1 to turn on the corresponding odd-numbered row pixels.
  • the twenty-seventh transistor T27 is turned on, and the fourth voltage signal of the fourth voltage signal terminal VDD Transmitted to the fourteenth node N14.
  • the fourth voltage signal may be a high-level voltage signal.
  • the twenty-fourth transistor T24 is turned on, and the eighth clock signal from the eighth clock signal terminal CKE1 is transmitted to the Three output signal terminal GL1.
  • the second scan input unit 323 inputs the fourth voltage signal to the fifteenth node N15 under the control of the third input signal IN3; the second scan output unit 322 inputs the ninth clock signal under the control of the voltage of the fifteenth node N15.
  • the signal is transmitted to the fourth output signal terminal GL2 to turn on the corresponding even row pixels.
  • the thirty-first transistor T31 is turned on, and the fourth voltage signal of the fourth voltage signal terminal VDD Transmitted to the fifteenth node N15.
  • the twenty-sixth transistor T26 is turned on, and the ninth clock signal from the ninth clock signal terminal CKE2 is transmitted to the third output signal terminal GL1.
  • the eighth clock signal terminal CKE1 and the ninth clock signal terminal CKE2 can output high-level voltage signals at different times, so that the third output signal terminal GL1 and the fourth output signal terminal GL2 can output scanning signals at different times. , and then clock the data writing transistor T102 of the pixels P in different rows at different times.
  • the first pulse width modulation unit 113 transmits the first input signal to the first node under the control of the third clock signal CKB1, or the second pulse width modulation unit 123 transmits the second input signal to the first node under the control of the fourth clock signal CKB2.
  • the input signal is transmitted to the second node N2 to modulate the lighting time of the pixels in the odd rows and the pixels in the even rows. That is, in the same frame period, one of the first pulse width modulation unit 113 and the second pulse width modulation unit 123 outputs a pulse width modulation signal, and in different frame periods, the first pulse width modulation unit 113 and the second pulse width modulation unit 123 output a pulse width modulation signal.
  • the wide modulation unit 123 alternately outputs pulse width modulation signals.
  • the control process of the first pulse width modulation unit 113 and the second pulse width modulation unit 123 can be referred to the above, and will not be described again here.
  • Some embodiments of the present disclosure also provide a display panel control method for controlling the display panel 1000 in the above embodiments.
  • the display panel 1000 includes a gate driving circuit 1120, a data driving circuit 1200, and a pixel driving circuit 1110.
  • the blank phase B includes a first data writing phase B11 , a second data writing phase B12 and a sensing phase B13 .
  • FIG. 28 shows an example of selecting the even-numbered row pixels P2 for complementing the light-emitting device EL.
  • the control method of the display panel 100 includes:
  • the data driving circuit 1200 writes zero grayscale data V0 to one of the pixels P1 in the odd rows and the pixels P2 in the even rows that is not selected for external compensation. In this way, the driving transistor T101 of the row of pixels P that is not selected for external compensation will not be turned on. When one of the light-emitting control transistors T104 is turned on, the anode of the light-emitting device EL of the row of pixels P that is not selected will not be charged. Ensure that one row of pixels P is directly selected in each frame for EL compensation of the light-emitting device.
  • the first gate line GL1(1) is electrically connected to the odd-numbered row pixel P1
  • the second gate line GL2(1) outputs an operating voltage signal
  • the data line DL outputs zero grayscale data V0.
  • the driving transistor T101(1) of the odd-numbered row pixel P1 is controlled to turn off the voltage signal, and the driving transistor T10 of the odd-numbered row pixel P1 is in a closed state during the subsequent compensation process.
  • the data driving circuit 1200 writes the sensing grayscale data VGm to one of the odd row pixels P1 and the even row pixels P2 that is selected for compensation of the light emitting device.
  • the first gate line GL1(2) and the second gate line GL2(2) electrically connected to the even row pixel P2 output an operating voltage signal, and the data line DL Output the sensing grayscale data VGm.
  • the control voltage of the driving transistor T101(2) of the pixel P2 in the even row is at the working voltage, and the driving transistor T101(2) of the pixel P1 in the even row can be turned on during the subsequent compensation process.
  • the first light-emitting control sub-circuit 110 or the second light-emitting control sub-circuit 120 outputs a first voltage signal (operating voltage), so that the operating current flows through the light-emitting devices EL of odd-numbered row pixels and even-numbered row pixels; odd-numbered rows of pixels
  • the pixel circuit of the row pixels or the even-numbered row pixels detects the voltage of the light-emitting device.
  • the first lighting control sub-circuit 110 outputs a first voltage signal to the first lighting control signal line EM1.
  • the operating current can flow through the drive control transistor T101 of the selected row pixel P (a row of pixels P selected for light-emitting device EL compensation), thereby causing the operating current to flow through the light-emitting device EL of the selected row pixel P, and the corresponding light-emitting device EL
  • the sensing signal line SL of the pixel driving circuit 1110 senses the voltage of the anode corresponding to the light emitting device EL.
  • the blank phase B after the sensing phase B13 , also includes a first data write-back phase B14 and a second data write-back phase B15 .
  • the first data write-back stage B14 one of a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 that is not selected for compensation of the light-emitting device EL writes the first initial grayscale data DATA1; the first initial The grayscale data DATA1 is the grayscale data written into the corresponding row of pixels P before the first data writing stage B11. In this way, the unselected row of pixels P can display the required grayscale in the next display stage D.
  • the first gate line GL1(1) and the second gate line GL2(1) electrically connected to the odd-numbered row pixel P1 output an operating voltage signal, and the data line DL
  • the first initial grayscale data DATA1 is output.
  • the second data write-back stage B15 one of the odd-numbered row pixels P1 and the even-numbered row pixels P2 selected for compensation of the light-emitting device EL writes the second initial grayscale data DATA2; the second initial grayscale data DATA2 is Before the second data writing stage B12, grayscale data of the corresponding row of pixels is written. In this way, the selected row of pixels P can display the required grayscale in the next display stage D.
  • the first gate line GL1(2) and the second gate line GL2(2) electrically connected to the even row pixel P2 output an operating voltage signal, and the data line DL
  • the second initial grayscale data DATA2 is output.

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Abstract

一种发光控制电路，第一检测控制单元与检测控制端、第一时钟信号端、第一电压信号端及第一节点电连接，被配置为在检测控制信号和第一时钟信号的控制下，将第一电压信号传输至第一节点。第一发光输出单元与第一节点、第一电压信号端和第一输出信号端电连接，被配置为在第一节点的电压的控制下，将第一电压信号传输至第一输出信号端。第二检测控制单元与检测控制端、第二时钟信号端、第一电压信号端及第二节点电连接，被配置为在检测控制信号和第二时钟信号的控制下，将第一电压信号传输至第二节点。第二发光输出单元与第二节点、第一电压信号端和第二输出信号端电连接，被配置为在第二节点的电压控制下，将第一电压信号传输至第二输出信号端。

Description

发光控制电路及其控制方法、栅极驱动电路及其控制方法 技术领域
本公开涉及显示技术领域，尤其涉及一种发光控制电路及其控制方法、栅极驱动电路及其控制方法。
背景技术
有机发光二极管(英文：Organic Light-Emitting Diode，简称OLED)显示面板具有主动发光、广视角、对比度高、响应速度快、耗电低、超轻薄等优点，因此受到广泛关注。显示面板包括多个像素，像素包括像素驱动电路和发光器件，像素长时间持续发光会造成发光器件老化，因此需要对像素进行补偿。
发明内容
一方面，提供一种发光控制电路。发光控制电路包括第一发光控制子电路和第二发光控制子电路。第一发光控制子电路包括第一检测控制单元和第一发光输出单元。第二发光控制子电路包括第二检测控制单元和第二发光输出单元。其中，所述第一检测控制单元与检测控制端、第一时钟信号端、第一电压信号端及所述第一节点电连接，被配置为在来自所述检测控制端的检测控制信号和来自所述第一时钟信号端的第一时钟信号的控制下，将来自所述第一电压信号端的第一电压信号传输至所述第一节点。所述第一发光输出单元与所述第一节点、所述第一电压信号端和第一输出信号端电连接，被配置为在所述第一节点的电压的控制下，将所述第一电压信号传输至所述第一输出信号端。所述第二检测控制单元与所述检测控制端、第二时钟信号端、所述第一电压信号端及所述第二节点电连接，被配置为在所述检测控制信号和来自所述第二时钟信号端的第二时钟信号的控制下，将所述第一电压信号传输至所述第二节点。所述第二发光输出单元与所述第二节点、所述第一电压信号端和第二输出信号端电连接，被配置为在所述第二节点的电压控制下，将所述第一电压信号传输至所述第二输出信号端。
在一些实施例中，所述第一检测控制单元包括第一检测输入子单元和第一检测输出子单元。第一检测输入子单元与所述检测控制端、所述第一时钟信号端及第三节点电连接，被配置为在所述检测控制信号的控制下，将所述第一时钟信号传输至所述第三节点。第一检测输出子单元与所述第三节点、所述第一电压信号端和所述第一节点电连接，被配置为在所述第三节点的电压控制下，将所述第一电压信号传输至所述第一节点。
所述第二检测控制单元包括第二检测输入子单元和第二检测输出子单元。第二检测输入子单元与所述检测控制端、所述第二时钟信号端及第四节点电连接，被配置为在所述检测控制信号的控制下，将所述第二时钟信号传输至所述第四节点。第二检测输出子单元与所述第四节点、所述第一电压信号端和所述第二节点电连接，被配置为在所述第四节点的电压控制下，将所述第一电压信号传输至所述第二节点。
在一些实施例中，所述第一检测控制单元还包括第一储能子单元；所述第一储能子单元与所述第一节点和所述第三节点电连接，被配置为维持所述第三节点的电压。所述第二检测控制单元还包括第二储能子单元；第二储能子单元与所述第二节点和所述第四节点电连接，被配置为维持所述第四节点的电压。
在一些实施例中，所述第一检测输入子单元包括第一晶体管，所述第一晶体管的控制极与所述检测控制端电连接，第一极与所述第二时钟信号端电连接，第二极与所述第三节点电连接。所述第一检测输出子单元包括第二晶体管，所述第二晶体管的控制极与所述第三节点电连接，第一极与所述第一电压信号端电连接，第二极与所述第一节点电连接。所述第一储能子单元包括第一电容器，所述第一电容器的第一极板与所述第三节点电连接，第二极板与所述第一节点电连接。
所述第二检测输入子单元包括第三晶体管，所述第三晶体管的控制极与所述检测控制端电连接，第一极与所述第四时钟信号端电连接，第二极与所述第四节点电连接。所述第二检测输出子单元包括第四晶体管，所述第四晶体管的控制极与所述第四节点电连接，第一极与所述第一电压信号端电连接，第二极与所述第二节点电连接。所述第二储能子单元包括第二电容器，所述第二电容器的第一极板与所述第四节点电连接，第二极板与所述第二节点电连接。
在一些实施例中，所述第一发光控制子电路还包括第一脉宽调制单元。第一脉宽调制单元与第一输入信号端、第三时钟信号端及所述第一节点电连接，被配置为在来自所述第三时钟信号端的第三时钟信号的控制下，将来自所述第一输入信号端的第一输入信号传输至所述第一节点。
所述第二发光控制子电路还包括第二脉宽调制单元。第二脉宽调制单元与第二输入信号端、第四时钟信号端及所述第二节点电连接，被配置为在来自所述第四时钟信号端的第四时钟信号的控制下，将来自所述第二输入信号端的第二输入信号传输至所述第二节点。
在一些实施例中，所述第一脉宽调制单元包括第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第三电容器。所述第五晶体管的控制极与所述第三时钟信号端电连接，第一极与所述第一输入信号端电连接，第二极与所述第一节点电连接。所述第六晶体管的控制极与所述第一节点电连接，第一极与第二电压信号端电连接，第二极与第五节点电连接。所述第七晶体管的控制极与所述第五节点电连接，第一极与第三电压信号端电连接，第二极与所述第一输出信号端电连接。所述第八晶体管的控制极与第五时钟信号端电连接，第一极与所述第一电压信号端电连接，第二极与第六节点电连接。所述第九晶体管的控制极与所述第六节点电连接，第一极与所述第三时钟信号端电连接，第二极与第七节点电连接。所述第十晶体管的控制极与所述第一输入信号端电连接，第一极与所述第七节点电连接，第二极与所述第五节点电连接。所述第三电容器的第一极板与所述第六节点电连接，第二极板与所述第七节点电连接。
所述第二脉宽调制单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管和第四电容器。所述第十一晶体管的控制极与所述第四时钟信号端电连接，第一极与所述第二输入信号端电连接，第二极与所述第二节点电连接。所述第十二晶体管的控制极与所述第二节点电连接，第一极与第二电压信号端电连接，第二极与第八节点电连接。所述第十三晶体管的控制极与所述第八节点电连接，第一极与所述第三电压信号端电连接，第二极与所述第二输出信号端电连接。所述第十四晶体管的控制极与第六时钟信号端电连接，第一极与所述第一电压信号端电连接，第二极与第九节点电连接。所述第十五晶体管的控制极与所述第九节点电连接，第一极与所述第四时钟信号端电连接，第二极与第十节点电连接。所述第十六晶体管的控制极与所述第二输入信号端电连接，第一极与所述第十节点电连接，第二极与所述第八节点电连接。所述第四电容器的第一极板与所述第九节点电连接，第二极板与所述第十节点电连接。
所述第一发光输出单元包括第十七晶体管，所述第十七晶体管的控制极与所述第一节点电连接，第一极与所述第一电压信号端电连接，第二极与所述第一输出信号端电连接。所述第二发光输出单元包括第十八晶体管，所述第十八晶体管的控制极与所述第二节点电连接，第一极与所述第一电压信号端电连接，第二极与所述第二输出信号端电连接。
另一方面，还提供了一种栅极驱动电路。栅极驱动电路包括随机检测电路、移位寄存器电路和上述任一实施例所述的发光控制电路。其中，随机检 测电路与随机检测信号端、第三输入信号端、第七时钟信号端和第十一节点电连接，被配置为在来自所述随机检测信号端的随机检测信号和来自所述第三输入信号端的第三输入信号的控制下，将来自所述第七时钟信号端的第七时钟信号传输至所述第十一节点，以选中一行像素进行发光器件的补偿移位寄存器电路与所述第十一节点电连接，被配置为在所述第十一节点的电压控制下，向对应行像素输出扫描信号，以打开对应行像素。发光控制电路的检测控制端与所述随机检测电路中的电路节点或者所述移位寄存器电路中的电路节点电连接。
在一些实施例中，所述随机检测电路包括随机检测控制子电路和检测输出子电路。随机检测控制子电路与所述随机检测信号端、所述第三输入信号端和第十二节点电连接，被配置为在所述随机检测信号的控制下，将所述第三输入信号传输至所述第十二节点。检测输出子电路与所述第十二节点、所述第七时钟信号端和所述第十一节点电连接，被配置为在所述第十二节点的电压控制下，将所述第七时钟信号传输至所述第十一节点。其中，所述检测控制端与所述第十二节点电连接。
在一些实施例中，所述随机检测电路还包括第一储能子电路和第一防漏电子电路。第一储能子电路与第四电压信号端和所述第十二节点电连接，被配置为维持所述第十二节点的电压。第一防漏电子电路与所述随机检测控制子电路、所述随机检测信号端、所述第十二节点和所述第四电压信号端电连接，被配置为在所述随机检测信号和所述第十二节点的电压的控制下，将所述第四电压信号传输至所述第十一节点。其中，所述随机检测控制子电路通过所述第一防漏电子电路与所述第十二节点电连接。
在一些实施例中，所述随机检测控制子电路包括第十九晶体管，所述第十九晶体管的控制极与所述随机检测信号端电连接，第一极与所述第三输入信号端电连接，第二极与第十三节点电连接。所述检测输出子电路包括第二十晶体管，所述第二十晶体管的控制极与所述第十二节点电连接，第一极与所述第七时钟信号端电连接，第二极与所述第十一节点电连接。所述第一储能子电路包括第五电容器，所述第五电容器的第一极板与所述第四电压信号端电连接，第二极与所述第十二节点电连接。第一防漏电子电路包括第二十一晶体管和第二十二晶体管，所述第二十一晶体管的控制极与所述随机检测信号端电连接，第一极与所述第十三节点电连接，第二极与所述第十二节点电连接；所述第二十二晶体管的控制极与所述第十二节点电连接，第一极与所述第四电压信号端电连接，第二极与所述第十三节点电连接。
在一些实施例中，所述移位寄存器电路包括第一移位寄存器子电路和第二移位寄存器子电路。第一移位寄存器子电路包括第一补偿输入单元和第一扫描输出单元。第二移位寄存器子电路，包括第二补偿输入单元和第二扫描输出单元。其中，所述第一补偿输入单元与所述第十一节点、所述第七时钟信号端和第十四节点电连接，被配置为在所述第七时钟信号的控制下，将所述第十一节点的电压传输至所述第十四节点。所述第一扫描输出单元与所述第十四节点、第八时钟信号端和第三输出信号端电连接，所述第三输出信号端被配置为与奇数行像素电连接；所述第一扫描输出单元被配置为，在所述第十四节点的电压的控制下，将来自所述第八时钟信号端的第八时钟信号传输至所述第三输出信号端，以打开对应的奇数行像素。所述第二补偿输入单元与所述第十一节点、所述第七时钟信号端和第十五节点电连接，被配置为在所述第七时钟信号的控制下，将所述第十一节点的电压传输至所述第十五节点。所述第二扫描输出单元与所述第十五节点、第九时钟信号端和第四输出信号端电连接，所述第四输出信号端被配置为与偶数行像素电连接；所述第二扫描输出单元被配置为，在所述第十五节点的电压的控制下，将来自所述第九时钟信号端的第九时钟信号传输至所述第四输出信号端，以打开对应的偶数行像素。其中，所述检测控制端与所述第十四节点或所述第十五节点电连接。
在一些实施例中，所述第一补偿输入单元包括第二十三晶体管，所述第二十三晶体管的控制极与所述第七时钟信号端电连接，第一极与所述第十一节点电连接，第二极与所述第十四节点电连接。所述第一扫描输出单元包括第二十四晶体管，所述第二十四晶体管的控制极与所述第十四节点电连接，第一端与所述第八时钟信号端电连接，第二极与所述第三输出信号端电连接。所述第二补偿输入单元包括第二十五晶体管，所述第二十五晶体管的控制极与所述第七时钟信号端电连接，第一极与所述第十一节点电连接，第二极与所述第十五节点电连接。所述第二扫描输出单元包括第二十六晶体管，所述第二十六晶体管的控制极与所述第十五节点电连接，第一极与所述第九时钟信号端电连接，第二极与所述第四输出信号端电连接。
在一些实施例中，所述第一移位寄存器子电路还包括第一扫描输入单元、第一反相器和第一复位单元。其中，所述第一扫描输入单元与所述第三输入信号端、所述第四电压信号端和所述第十四节点电连接，被配置为在所述第三输入信号的控制下，将所述第三电压信号传输至所述第十四节点。所述第一反相器的一端与所述第十四节点电连接，另一端与第十六节点电连接。所 述第一复位单元与第一复位信号端、所述第十六节点、所述第五电压信号端、第十四节点和第三输出信号端电连接，被配置为在来自所述第一复位信号端的第一复位信号和所述第十六节点的电压的控制下，将所述第五电压信号端的第五电压信号传输至所述第十四节点和所述第三输出信号端。
所述第二移位寄存器子电路还包括第二扫描输入单元、第二反相器和第二复位单元。所述第二扫描输入单元与所述第三输入信号端、所述第四电压信号端和所述第十五节点电连接，被配置为在所述第三输入信号的控制下，将所述第三电压信号传输至所述第十五节点。所述第二反相器的一端与所述第十五节点电连接，另一端与第十七节点电连接。所述第二复位单元与第二复位信号端、所述第五电压信号端、第十五节点、第十七节点和第四输出信号端电连接，被配置为在来自所述第二复位信号端的第二复位信号和所述第十七节点的电压的控制下，将所述第五电压信号传输至所述第十五节点和所述第四输出信号端。
在一些实施例中，所述第一扫描输入单元包括第二十七晶体管，所述第二十七晶体管的控制极与所述第三输入信号端电连接、第一极与所述第四电压信号端电连接，第二极与所述第十四节点电连接。
所述第一复位单元包括第二十八晶体管、第二十九晶体管和第三十晶体管，所述第二十八晶体管的控制极与所述第一复位信号端电连接，第一极与所述第五电压信号端电连接，第二极与所述第十四节点电连接；所述第二十九晶体管的控制极与所述第十六节点电连接，第一极与所述第五电压信号端电连接，第二极与所述第三输出信号端电连接；第三十晶体管的控制极与所述第十六节点电连接，第一极与所述第五电压信号端电连接，第二极与所述第十四节点电连接。
所述第二扫描输入单元包括第三十一晶体管，所述第三十一晶体管的控制极与所述第三输入信号端电连接，第一极与所述第四电压信号端电连接，第二极与所述第十四节点电连接。
所述第二复位单元包括第三十二晶体管、第三十三晶体管和第三十四晶体管，所述第三十二晶体管的控制极与所述第二复位信号端电连接，第一极与所述第五电压信号端电连接，第二极与所述第十五节点电连接；所述第三十三晶体管的控制极与所述第十七节点电连接，第一极与所述第五电压信号端电连接，第二极与所述第四输出信号端电连接；所述第三十四晶体管的控制极与所述第十七节点电连接，第一极与所述第五电压信号端电连接，第二极与所述第十五节点电连接。
又一方面，还提供了一种发光控制电路的控制方法，用于驱动上述任一实施例中的发光控制电路。所述发光控制电路的第一输出信号端与奇数行像素电连接，所述发光控制电路的第二输出信号端与偶数行像素电连接。一个帧周期包括显示阶段和空白阶段。
在一组相邻的奇数行像素或偶数行像素被选中进行发光器件的补偿的情况下，控制方法包括：在所述空白阶段，所述发光控制电路的第一发光控制子电路的第一检测控制单元将第一电压信号传输至第一节点，所述第一发光控制子电路的第一输出单元在所述第一节点的电压的控制下，将所述第一电压信号传输至第一输出信号端，以使工作电流流经奇数行像素或偶数行像素的发光器件；或者，所述发光控制电路的第二发光控制子电路的第二检测控制单元将所述第一电压信号传输至第二节点，所述第二发光控制子电路的第二输出单元在所述第二节点的电压的控制下，将第一电压信号传输至第二输出信号端，以使工作电流流经所述奇数行像素或所述偶数行像素的发光器件。
在一些实施例中，在所述第一发光控制子电路包括第一脉宽调制单元，且第二发光控制子电路包括第二脉宽调制单元的情况下。
所述控制方法包括：在所述显示阶段，所述第一脉宽调制单元在第三时钟信号的控制下，将第一输入信号传输至所述第一节点；第一发光输出单元在所述第一节点的电压的控制下，将所述第一电压信号传输至所述第一输出信号端，以对所述奇数行像素和所述偶数行像素的发光时间进行调制。在一组相邻的奇数行像素或偶数行像素被选中进行发光器件的补偿的情况下，在所述空白阶段，所述第二检测控制单元将所述第一电压信号传输至第二节点，所述第二发光输出单元在所述第二节点的电压的控制下，将所述第一电压信号传输至第二输出信号端，以使工作电流流经奇数行像素或偶数行像素的发光器件；
或者，所述控制方法包括：在所述显示阶段，所述第二脉宽调制单元在第四时钟信号的控制下，将第二输入信号传输至所述第二节点；第二发光输出单元在所述第二节点的电压的控制下，将所述第一电压信号传输至所述第二输出信号端，以对所述奇数行像素和所述偶数行像素的发光时间进行调制。在一组相邻的奇数行像素或偶数行像素被选中进行发光器件的补偿的情况下，在所述空白阶段，所述第一检测控制单元将所述第一电压信号传输至第一节点，所述第一发光输出单元在所述第一节点的电压的控制下，将所述第一电压信号传输至所述第二输出信号端，以使工作电流流经奇数行像素或偶数行像素的发光器件。
在一些实施例中，所述控制方法包括：在同一个帧周期，第一时钟信号端、第二输入信号端和第四时钟信号端输出脉冲信号，且第二时钟信号端、第一输入信号端和第三时钟信号端不输出电压信号。或者，在同一个帧周期，所述第二时钟信号端、所述第一输入信号端和所述第三时钟信号端输出脉冲信号，且所述第一时钟信号端、所述第二输入信号端和所述第四时钟信号端不输出电压信号。
又一方面，提供一种栅极驱动电路的控制方法，控制方法被配置为驱动上述任一实施例中所述的栅极驱动电路。所述栅极驱动电路的发光控制电路的第一输出信号端与奇数行像素电连接，所述发光控制电路的第二输出信号端与偶数行像素电连接。一个帧周期包括显示阶段和空白阶段。在一组相邻的奇数行像素或偶数行像素被选中进行发光器件的补偿的情况下，所述控制方法包括：
在所述显示阶段，所述栅极驱动电路的随机检测电路在随机检测信号的控制下，将第三输入信号传输至随机检测电路中的电路节点，且维持对应电路节点电压至所述空白阶段。
在所述空白阶段，所述随机检测电路在对应电路节点的电压的控制下，将第七时钟信号传输至所述栅极驱动电路的移位寄存器电路；所述移位寄存器电路向对应行像素输出扫描信号，以打开对应行像素；所述栅极驱动电路的发光控制电路在所述随机检测电路中的电路节点的电压或者所述移位寄存器电路中的电路节点的电压的控制下，将第一电压信号传输至第一输出信号端或第二输出信号端，以使工作电流流经所述奇数行像素或所述偶数行像素的发光器件。
在一些实施例中，所述移位寄存器电路包括第一移位寄存器子电路和第二移位寄存器子电路，所述第一移位寄存器子电路包括第一扫描输入单元和第一扫描输出单元，所述第二移位寄存器子电路包括第二扫描输入单元和第二扫描输出单元；所述发光控制电路的第一发光控制子电路包括第一脉宽调制单元，第二发光控制子电路包括第二脉宽调制单元。在所述显示阶段，所述控制方法包括：
所述第一扫描输入单元在第三输入信号的控制下，向第十四节点输入第四电压信号；所述第一扫描输出单元在所述第十四节点的电压的控制下，将第八时钟信号传输至所述第三输出信号端，以打开对应的奇数行像素。所述第二扫描输入单元在第三输入信号的控制下，向第十五节点输入所述第四电压信号；所述第二扫描输出单元在所述第十五节点的电压的控制下，将第九 时钟信号传输至所述第四输出信号端，以打开对应的偶数行像素。所述第一脉宽调制单元在第三时钟信号的控制下，将来第一输入信号传输至所述第一节点，或者，所述第二脉宽调制单元在第四时钟信号的控制下，将第二输入信号传输至所述第二节点，以对所述奇数行像素和所述偶数行像素的发光时间进行调制。
又一方面，提供了一种显示面板的控制方法。显示面板包括上述任一实施例中所述的栅极驱动电路，数据驱动电路，奇数行像素和偶数行像素。所述栅极驱动电路的第一发光控制子电路与所述奇数行像素电连接，第二发光控制子电路与所述偶数行像素电连接。一个帧周期包括显示阶段和空白阶段，所述空白阶段包括第一数据写入阶段、第二数据写入阶段和感测阶段。在一组相邻的奇数行像素或偶数行像素被选中进行发光器件的补偿的情况下，所述控制方法包括：
在所述第一数据写入阶段，所述数据驱动电路向所述奇数行像素和所述偶数行像素中未被选中进行外部补偿的一者，写入零灰阶数据。在所述第二数据写入阶段，所述数据驱动电路向所述奇数行像素和所述偶数行像素中被选中进行发光器件的补偿的一者，写入感测灰阶数据。在所述感测阶段，所述第一发光控制子电路或所述第二发光控制子电路输出第一电压信号，以使工作电流流经所述奇数行像素和所述偶数行像素的发光器件；所述奇数行像素或所述偶数行像素的像素电路对所述发光器件的电压进行检测。
在一些实施例中，所述空白阶段还包括第一数据写回阶段和第二数据写回阶段。所述控制方法还包括：在所述第一数据写回阶段，所述奇数行像素和所述偶数行像素中未被选中进行发光器件的补偿的一者，写入第一初始灰阶数据。在所述第二数据写回阶段，所述奇数行像素和所述偶数行像素中被选中进行发光器件的补偿的一者，写入第二初始灰阶数据。其中，所述第一初始灰阶数据为在所述第一数据写入阶段之前，写入对应行像素的灰阶数据。所述第二初始灰阶数据为在所述第二数据写入阶段之前，写入对应行像素的灰阶数据。
又一方面，提供了一种显示装置。所述显示装置包括上述任一实施例中所述的栅极驱动电路。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还 可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为本公开实施例的显示装置的结构图；
图2为本公开实施例的显示面板的结构图；
图3为本公开实施例的像素驱动电路的一种等效电路图；
图4为本公开实施例的像素驱动电路的一种时序控制图；
图5为本公开实施例的像素驱动电路的又一种等效电路图；
图6为本公开实施例的两行像素驱动电路的等效电路图；
图7为本公开实施例的栅极驱动电路的级联关系图；
图8为本公开实施例的栅极驱动电路和像素驱动电路的连接关系图；
图9为本公开实施例的发光控制电路的一种结构图；
图10为本公开实施例的发光控制电路的另一种结构图；
图11为本公开实施例的发光控制电路的又一种结构图；
图12为本公开实施例的第一检测控制单元和第二检测控制单元的等效电路图；
图13为本公开实施例的发光控制电路的又一种结构图；
图14A为本公开实施例的第一发光控制子电路的一种等效电路图；
图14B为本公开实施例的第二发光控制子电路的一种等效电路图；
图15为本公开实施例的发光控制电路的又一种结构图；
图16A为本公开实施例的第一发光控制子电路的另一种等效电路图；
图16B为本公开实施例的第二发光控制子电路的另一种等效电路图；
图17A为本公开实施例的第一发光控制子电路的又一种等效电路图；
图17B为本公开实施例的第二发光控制子电路的又一种等效电路图；
图18为本公开实施例的发光控制电路的一种控制时序控制图；
图19A为本公开实施例的栅极驱动电路的一种结构图；
图19B为本公开实施例的栅极驱动电路的另一种结构图；
图20为本公开实施例的随机检测电路的一种结构图；
图21为本公开实施例的随机检测电路的一种等效电路图；
图22为本公开实施例的随机检测电路的另一种结构图；
图23为本公开实施例的随机检测电路的另一种等效电路图；
图24A为本公开实施例的移位寄存器电路的一种结构图；
图24B为本公开实施例的移位寄存器电路的一种等效电路图；
图25A为本公开实施例的第一移位寄存器子电路的结构图；
图25B为本公开实施例的第二移位寄存器子电路的结构图；
图26A为本公开实施例的第一移位寄存器子电路的等效电路图；
图26B为本公开实施例的第二移位寄存器子电路的等效电路图；
图27为本公开实施例的栅极驱动电路的一种时序控制图；
图28为本公开实施例的显示面板的一种时序控制图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管(Thin Film Transistor，简称：TFT)，或场效应管(Metal Oxide Semiconductor，简称：MOS)，或其他特性相同的器件，本公开实施例对此不做限定。
示例性地，晶体管可以为TFT。TFT可以采用a-Si工艺，氧化物(Oxide)半导体工艺、低温多晶硅(Low Temperature Poly-silicon，简称：LTPS)工艺、高温多晶硅(High Temperature Poly-silicon，简称：HTPS)工艺制备。本公开的实施例对此不作限定。
本公开的实施例对晶体管的类型不做限定。晶体管可以为N型晶体管，也可以为P型晶体管，可以为增强型晶体管，也可以为耗尽型晶体管。在本公开的实施例中，以所有晶体管为N型晶体管为例，对本申请进行示例性地说明。N型晶体管在高电平电压信号作用下导通，在低电平电压信号作用下关断；即N型晶体管的工作电压为高电平电压，关断电压为低电平电压。
在本公开的实施例中，晶体管的栅极为控制极，同时，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此时，晶体管的第一极可以为晶体管的源极(Source)和漏极(Drain)中的一者，第二极可以为晶体管的源极和漏极中的另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。
本公开实施例中的电容器可以是通过工艺制程单独制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容器的各个电容电极(第一极板和第二极板)可以通过金属层、半导体层(例如掺杂多晶硅)等实现。电容也可以是晶体管之间的寄生电容，或者通过晶体管本身与其他器件、线路来实现，又或者利用电路自身线路之间的寄生电容来实现。
上述各个晶体管还可以包括至少一个与各个晶体管分别并联的开关管。本公开实施例中仅仅是对像素驱动电路和栅极驱动电路的举例说明，其它与像素驱动电路和栅极驱动电路功能相同的结构不再一一赘述，但都应当属于本公开的保护范围。
本公开实施例中的“第一节点”、“第二节点”等并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
本公开的一些实施例提供了一种显示装置1000，参阅图1，图1为显示装置的一种结构图，显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。
示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(Personal Digital Assistant，简称PDA)、导航仪、可穿戴设备、增强现实(Augmented Reality，简称AR)设备、虚拟现实(Virtual Realit，简称VR)设备等任何具有显示功能的产品或者部件。
参阅图2，显示装置1000包括显示面板1100，及设置于显示面板1100上的数据驱动电路1200，以及与显示面板1100和数据驱动电路1200电连接的电路板1300(比如Source PCB)。比如，数据驱动电路1200可以为驱动芯片(Source Driver IC)，电路板1300可以是Source PCB。
显示面板1100具有显示区AA和至少位于显示区AA一侧的周边区BB。示例性地，参阅图2，显示面板1100具有显示区AA和围绕显示区AA的周边区BB。其中，数据驱动电路1200设置于显示面板1100的周边区BB。
显示面板1100包括多个像素(SubPixel)P、多条数据线DL、多条第一栅线GL1、多条第二栅线GL2、多条感测信号线SL(图2中未示出)以及多个栅极驱动电路1120。
每个像素P可以包括像素驱动电路1110和发光器件EL。多个像素P的多个发光器件EL至少可以发出三基色，例如红色(Red，R)、绿色(Green，G)和蓝色(Blue，B)的光线。
多个像素P沿第一方向X排列成多列(多列像素P沿第一方向X排列)，沿第二方向Y排列成多行(多行像素P沿第二方向Y排列)。每行像素P包括沿第一方向X排布的多个像素P，每列像素P包括沿第二方向Y排布的多个像素P。其中，第一方向X和第二方向Y相交，比如，第二方向Y和第一方向X垂直。
沿第二方向Y，多行像素P包括交替排布的奇数行像素P1和偶数行像素P2。示例性地，沿第一方向X且远离数据驱动电路1200的方向，第一行、第三行、第五行、……、第N－1行均为奇数行像素P1。第二行、第四行、第六行、……、第N行均为偶数行像素P2。其中N为正整数，且N为偶数。
参阅图2，栅极驱动电路1120设置于周边区BB，每一组相邻的奇数行像素P1和偶数行像素P2各自通过一条第一栅线GL1和一条第二栅线GL2与一个栅极驱动电路1120电连接。多个栅极驱动电路1120级联设置。每列像素P通过一条数据线DL与数据驱动电路1200电连接，且每列像素P与一条感测信号线SL电连接(图2中未示出感测信号线SL)。
可以理解的是，本公开的实施例中，“一组相邻的奇数行像素和偶数行像素”是指，与同一栅极驱动电路1120电连接(与同一发光控制电路100电连接)的一行奇数行像素P1和一行偶数行像素P2。
参阅图3，图3为本公开实施例提供的一种像素驱动电路1110的等效电路图。像素驱动电路1110可以包括驱动晶体管T101、数据写入晶体管T102、感测晶体管T103和储能电容器Cst。
其中，数据写入晶体管T102的控制极与第一栅线GL1电连接，第一极与数据线DL电连接，第二极与驱动晶体管T101的控制极电连接。驱动晶体管T101的第一极与电源电压信号端VDD电连接，第二极与发光器件EL的阳极电连接。感测晶体管T103的控制极与第二栅线GL2电连接，第一极与发光器件EL的阳极电连接，第二极与感测信号线SL电连接。储能电容器Cst的第一极板与驱动晶体管T101的控制极电连接，第二极板与发光器件EL的阳极电连接。
由于发光器件EL长时间工作(发光)会发生老化，因此需要对发光器件EL进行补偿，以使发光器件EL能够显示所需要显示的灰阶数据。
参阅图4，图4为图3所示像素驱动电路1110的一种时序控制图。一个帧周期(Frame)F包括空白阶段(Blank)B和显示阶段(Display)D。空白阶段B包括感测数据写入阶段B1、感测阶段B2和显示数据写回阶段B3。
在感测数据写入阶段B1，栅极驱动电路1120通过第一栅线GL1控制数据写入晶体管T102打开，数据驱动电路1200通过数据线DL向驱动晶体管T101的控制极写入感测灰阶数据VGm。感测灰阶数据VGm将驱动晶体管T101打开，电源电压信号端VDD通过驱动晶体管T101向发光器件EL的阳极充电。
在感测阶段B2，数据写入晶体管T102关闭，且第二栅线GL2控制感测晶体管T103打开，感测信号线SL对发光器件EL的阳极的电压进行感测。
可以理解的是，对发光器件EL进行补偿的过程为本领域的常规技术，本公开的实施例对发光器件EL进行补偿的其他过程不做详细说明。
在显示阶段，栅极驱动电路1120可以通过第一栅线GL1控制数据写入晶体管T102打开，数据驱动电路1200通过数据线DL向驱动晶体管T101的控制极写入显示灰阶数据Dn；显示灰阶数据Dn控制驱动晶体管T101打开，电源电压信号端CDD与发光器件EL的阳极导通，驱动电流流经发光器件EL，发光器件EL工作。
在一些实施例中，发光器件EL可以为有机发光二极管(OLED)，这样，发光器件EL的发光效率与流经发光器件EL的电流大小(或电流密度)正相关。即流经发光器件EL的电流大小较小时，发光器件EL的发光效率较低，流经发光器件EL的电流大小较大时，发光器件EL的发光效率较高。
为了提升发光器件EL在显示低灰阶时的发光效率，本公开的一些实施例还提供了一种像素驱动电路1110，参阅图5，图5为在图3所示像素驱动电路基础上增加发光控制晶体管T104后，像素驱动电路1110的等效电路图。 发光控制晶体管T104用于对发光器件EL的发光时间进行调制(即脉冲宽度调制：Pulse Width Modulation；简称：PWM)，以改变发光器件EL在一帧内的发光空占比，进而缩短发光器件EL的发光时间，通过缩短发光器件EL的发光时间，增加发光器件EL发光过程中，流经发光器件EL的电流大小，进而提升发光器件EL的发光效率。
参阅图5，发光控制晶体管T104的控制极通过发光控制扫描线EM与栅极驱动电路1120电连接，第一极与电源电压信号端VDD电连接，第二极与驱动晶体管T101的第一极电连接。
在一些实施例中，发光控制晶体管T104可以为氧化物薄膜晶体管(oxide Thin-Film Transistor，简称：oxide TFT)，氧化物薄膜晶体管具有较高的电子迁移率及良好的关断特性。这样，有利于在对发光器件EL的发光时间调制过程中，完全打开或者完全关闭发光控制晶体管T104。
在一些实施例中，参阅图6，图6为一组相邻的奇数行像素P1和偶数行像素P2的等效电路图，其中，每行仅示例性地展示了一个像素P。奇数行像素P1的发光控制晶体管T104(1)的第二极，与偶数行像素P2的发光控制晶体管T104(2)的第二极通过一条连接线L0电连接。这样，一组相邻的奇数行像素P1和偶数行像素P2共用发光控制晶体管T104。
在同一个帧周期F内，奇数行像素P1的发光控制晶体管T104(1)和偶数行像素P2的发光控制晶体管T104(2)中的一者，对两行对应像素P的两个发光器件EL的发光时间进行调制，另一者休息(在对应帧周期内始终处于关断状态)。这样，可以降低发光控制晶体管T104因长时间工作，产生损坏或者阈值电压漂移的风险，提升发光控制晶体管T104的信赖性。
在不同的帧周期F内，奇数行像素P1的发光控制晶体管T104(1)和偶数行像素P2的发光控制晶体管T104(2)交替对两行对应的像素P的两个发光器件EL的发光时间进行调制，且交替进行休息。
在相关技术中，由于采用了上述像素驱动电路(一组相邻奇数行像素P1和偶数行像素P2共用发光控制晶体管T104)，在一个帧周期内，与一组相邻的奇数行像素P1和偶数行像素P2电连接的两条发光控制扫描线EM中的一条，持续输出关断电压(低电平电压信号)，与对应发光控制扫描线EM电连接的一行像素P的发光控制晶体管T104处于关闭状态；另一条发光控制扫描线EM输出脉冲信号，脉冲信号在感测数据写入阶段B1也可能为关断电压，这样，与对应条发光控制扫描线EM电连接的一行像素P的发光控制晶体管T104也可能处于关闭状态。但是，在感测数据写入阶段B1，当一组相 邻的奇数行像素P1和偶数行像素P2的发光控制晶体管T104都处于关闭状态，且选中该组相邻的奇数行像素P1和偶数行像素P2中的一者进行发光器件EL的补偿时，不能实现打开对应行像素P的发光控制晶体管T104，发光器件EL的阳极与电源电压VDD之间电绝缘，因此不能完成对对发光器件EL的充电，因而不能对发光器件EL进行补偿。
为了解决上述问题，本公开的一些实施例还提供了一种栅极驱动电路1120，参阅图7，栅极驱动电路1120包括发光控制电路100、随机检测电路200和移位寄存器电路300。
随机检测电路200也可以称随机Sense unit。随机检测电路200被配置为在每个帧周期F内，随机选中一行像素P，对选中的一行像素P的发光器件EL进行补偿。
多个移位寄存器电路300依次级联，每个移位寄存器电路300与第一栅线GL1和第二栅线GL2电连接，被配置为向第一栅线GL1输出第一扫描信号，向第二栅线GL2输出第二扫描信号。其中，一个随机检测电路200与两个移位寄存器电路300电连接(如图8所示)。
示例性地，参阅图8，移位寄存器电路300包括第一移位寄存器子电路GL1GOA和第二移位寄存器子电路GL2GOA；多个移位寄存器电路300的多个第一移位寄存器子电路GL1GOA依次级联，多个移位寄存器电路300的多个第二移位寄存器子电路GL2GOA依次级联。需要说明的是，图7中仅示例性地展示了第一移位寄存器子电路GL1GOA。
参阅图9，图9为发光控制电路100的一种结构图。发光控制电路100包括第一发光控制子电路110和第二发光控制子电路120。
参阅图7和图8，多个栅极驱动电路1120的多个发光控制电路100依次级联设置。示例性地，每个栅极驱动电路1120的第一发光控制子电路110相互级联，其中，上一级第一发光控制子电路110的第一级联输出信号端CR1与下一级第一发光控制子电路110的第一输入信号端IN1电连接。每个栅极驱动电路1120的第二发光控制子电路120依次级联，其中，上一级第二发光控制子电路120的第二级联输出信号端CR2与下一级第二发光控制子电路120的第二输入信号端IN2电连接。
每个发光控制电路100与一条第一发光控制扫描线EM1和一条第二发光控制扫描线EM2电连接，被配置为通过第一发光控制扫描线EM1和第二发光控制扫描线EM2输出发光控制信号，以对与之电连接的一组相邻的奇数行像素P1和偶数行像素P2的发光时长进行调制。
示例性地，参阅图8和图9，每个发光控制电路100与一组相邻的奇数行像素P1和偶数行像素P2电连接。发光控制电路100的第一发光控制子电路110与奇数行像素P1电连接，第二发光控制子电路120与偶数行像素P2电连接。这样，第一输出信号端EM1与奇数行像素P1的发光控制晶体管T104的控制极电连接，第二输出信号端EM2与偶数行像素P2的发光控制晶体管T104的控制极电连接。
本公开的实施例中，为了简化说明，第一输出信号端和第一发光控制信号线采用了相同的标号EM1，以表示第一输出信号端与第一发光控制信号线电连接；第二输出信号端和第二发光控制信号线采用了相同的标号EM2，以表示第二输出信号端和第二发光控制信号线电连接。
第一发光控制子电路110包括第一检测控制单元111和第一发光输出单元112。第二发光控制子电路120包括第二检测控制单元121和第二发光输出单元122。
第一检测控制单元111与检测控制端VH、第一时钟信号端CKA1、第一电压信号端VGH及第一节点N1电连接，被配置为在来自检测控制端VH的检测控制信号和来自第一时钟信号端CKA1的第一时钟信号的控制下，将来自第一电压信号端VGH的第一电压信号传输至第一节点N1。
第一发光输出单元112与第一节点N1、第一电压信号端VGH和第一输出信号端EM1电连接，被配置为在第一节点N1的电压的控制下，将第一电压信号传输至第一输出信号端EM1。
第二检测控制单元121与检测控制端VH、第二时钟信号端CKA2、第一电压信号端VGH及第二节点N2电连接，被配置为在检测控制信号和来自第二时钟信号端CKLB的第二时钟信号的控制下，将第一电压信号传输至第二节点N2。
第二发光输出单元122与第二节点N2、第一电压信号端VGH和第二输出信号端EM2电连接，被配置为在第二节点N2的电压控制下，将第一电压信号传输至第二输出信号端EM2。
在一些实施例中，在选中一行像素P并对该行像素P的发光器件EL进行补偿的情况下，检测控制端VH可以向与该行像素P电连接的发光控制电路100输出工作电压(高电平电压信号)。
示例性地，在选中第N行(N为偶数)像素P，并对第N行像素P的发光器件EL进行补偿的情况下，与第N行像素电连接的第二发光控制子电路120中的检测控制端VH，及与第N-1行像素电连接的第一发光控制子电路110 中的检测控制端VH，同时生成工作电压(高电平电压信号)。
第一电压信号端VGH可以为持续输出高电平的电压信号端，这样，第一电压信号为高电平电压信号。
在同一个帧周期F内，第一时钟信号端CKA1和第二时钟信号端CKA2中的一者，在空白阶段B输出脉冲信号，另一者输出持续低电平电压信号，在不同帧周期内，第一时钟信号端CKA1和第二时钟信号端CKA2交替在空白阶段B输出脉冲信号(如图18所示)。这样，在同一个帧周期F的空白阶段B，第一时钟信号端CKA1和第二时钟信号端CKA2中，只有一个输出脉冲信号。这样，可以在选中一组相邻的奇数行像素P1或偶数行像素中P2进行发光器件的补偿的情况下，奇数行像素P1和偶数行像素中P2的两个发光控制晶体管T104中的一者打开，另一者休息。
比如，每隔一个帧周期F第一时钟信号端CKA1和第二时钟信号端CKA2切换一次输出脉冲信号。即在第奇数(比如1、3、5等)个帧周期的空白阶段B，第一时钟信号端CKA1和第二时钟信号端CKA2中的一者输出脉冲信号；在第偶数(比如2、4、6等)个帧周期的空白阶段B，第一时钟信号端CKA1和第二时钟信号端CKA2中的另一者输出脉冲信号。
比如，每隔两个帧周期(如图18所示)，第一时钟信号端CKA1和第二时钟信号端CKA2切换一次输出脉冲信号。即，在第一个、第三个、第五个、……、第N-1个“两个帧周期”内，第一时钟信号端CKA1和第二时钟信号端CKA2中的一者，在空白阶段X2输出脉冲信号；在第二个、第四个、第六个、……、第N个“两个帧周期”内，第一时钟信号端CKA1和第二时钟信号端CKA2中的另一者在空白阶段B输出脉冲信号。其中N为偶数。
在选中一行像素P进行补偿的情况下，一组相邻奇数行像素P1和偶数行像素P2中的一者，发光控制晶体管T104打开。电源电压信号端VDD可以通过打开的发光控制晶体管T104和连接线L0传输至两个驱动晶体管T101的第一极，并根据两个驱动晶体管T101的打开状态(选中行像素P的驱动晶体管T101在感测灰阶数据VGm的控制下打开，另一行像素P的驱动晶体管T101在感测数据写入阶段B1关闭)，对选中行像素P的发光器件EL的阳极进行充电。
综合上述，本公开的实施例提供的发光控制电路100，包括第一检测控制单元111和第二检测控制单元122。在对选中行像素P的发光器件EL进行补偿时，可以通过第一检测控制单元111和第二检测控制单元122将选中行像素P的驱动晶体管T101与电源电压信号端VDD电连接，进而在驱动晶体管 T101打开的情况下，对选中行像素P的发光器件EL的阳极充电，实现对选中行像素P的发光器件EL的补偿。其中，选中行像素P是指，对发光器件EL进行补偿的一行像素P。
本公开的一些实施例还提供了一种发光控制电路100的控制方法，用于驱动上述任一实施例中的发光控制电路100。其中，一个帧周期F包括显示阶段D和空白阶段B。所述控制方法包括：
在一组相邻的奇数行像素P1或偶数行像素P2被选中进行发光器件EL的补偿的情况下。
在空白阶段B，发光控制电路100的第一发光控制子电路110的第一检测控制单元111将第一电压信号传输至第一节点N1，第一发光控制子电路110的第一输出单元112在第一节点N1的电压的控制下，将第一电压信号传输至第一输出信号端EM1，以使工作电流流经奇数行像素P1或偶数行像素P2的发光器件EL；
或者，发光控制电路100的第二发光控制子电路120的第二检测控制单元121将第一电压信号传输至第二节点N2，第二发光控制子电路120的第二输出单元122在第二节点N2的电压的控制下，将第一电压信号传输至第二输出信号端EM2，以使工作电流流经奇数行像素P1或偶数行像素P2的发光器件EL。
示例性地，在对选中行像素P的发光器件EL进行补偿的情况下，检测控制端VH向与选中行像素P电连接的发光控制电路100输出工作电压信号。
然后第一检测控制单元111在来自检测控制端VH的检测信号(工作电压信号)和来自第一时钟信号端CKA1的第一时钟信号的控制下，将来自第一电压信号端VGH的第一电压信号传输至第一节点N1。
接着，第一发光输出单元112在第一节点N1的电压(第一电压信号)的控制下，将来自第一电压信号端VGH的第一电压信号传输至第一输出信号端EM1。
或者，示例性地，第二检测控制单元121在来自检测控制端VH的检测信号和来自第二时钟信号端CKA2的第二时钟信号的控制下，将来自第一电压信号端VGH的第一电压信号传输至第二节点N2。
接着，第二发光输出单元122在第二节点N2的电压(第一电压信号)的控制下，将来自第一电压信号端VGH的第一电压信号传输至第二输出信号端EM2。
即，在在一组相邻的奇数行像素P1或偶数行像素P2被选中进行发光器 件EL的补偿的情况下，发光控制电路100的第一输出信号端EM1和第二输出信号端EM2的一者，输出第一电压信号，以可打开对应行像素P的发光控制晶体管T104。
比如，发光控制电路100的第一输出信号端EM1输出第一电压信号，上述第一电压信号由第一输出信号端EM1，沿发光控制扫描线EM1传输至奇数行像素P1的发光控制晶体管T104(1)的控制极，发光控制晶体管T104(1)打开，来自电源电压信号端VDD的电源电压信号，通过奇数行像素P1的发光控制晶体管T104(1)及连接线L0，传输至奇数行像素P1的驱动晶体管T101(1)的第一极及偶数行像素P2的驱动晶体管T101(2)的第一极。然后，选中行像素P的驱动晶体管T101打开，并对选中行像素P的发光器件120的阳极进行充电，进而使该行像素P能够实现对发光器件EL的补偿功能。
在一些实施例中，参阅图10，第一检测控制单元111包括第一检测输入子单元1111和第一检测输出子单元1112。
其中，第一检测输入子单元1111与检测控制端VH、第一时钟信号端CKA1及第三节点N3电连接，被配置为在检测控制信号的控制下，将第一时钟信号传输至第三节点N3。
第一检测输出子单元1112与第三节点N3、第一电压信号端VGH和第一节点N1电连接，被配置为在第三节点N3的电压(第一时钟信号)控制下，将第一电压信号传输至第一节点N1。
示例性地，参阅图12，第一检测输入子单元1111包括第一晶体管T1。第一晶体管T1的控制极与检测控制端VH电连接，第一极与第一时钟信号端CKA1电连接，第二极与第三节点N3电连接。
示例性地，参阅图12，第二检测输出子单元1112包括第二晶体管T2。第二晶体管T2的控制极与第三节点N3电连接，第一极与第一电压信号端VGH电连接，第二极与第一节点N1电连接。
在一些实施例中，参阅图10，第二检测控制单元121包括第二检测输入子单元1211和第二检测输出子单元1212。
第二检测输入子单元1211与检测控制端VH、第二时钟信号端CKA2及第四节点N4电连接，被配置为在检测控制信号的控制下，将第二时钟信号传输至第四节点N4。
第二检测输出子单元1212与第四节点N4、第一电压信号端VGH和第二节点N2电连接，被配置为在第四节点N4的电压(第二时钟信号)控制下，将第一电压信号传输至第二节点N2。
示例性地，参阅图12，第二检测输入子单元1211包括第三晶体管T3。第三晶体管T3的控制极与检测控制端VH电连接，第一极与第二时钟信号端CKA2电连接，第二极与至第四节点N4电连接。
示例性地，参阅图12，第二检测输出子单元1212包括第四晶体管T4，第四晶体管T4的控制极与第四节点N4电连接，第一极与第一电压信号端VGH电连接，第二极与第二节点N2电连接。
在一些实施例中，参阅图11，第一检测控制单元111还包括第一储能子单元1113。第一储能子单元1113与第一节点N1和第三节点N3电连接，被配置为维持第三节点N3的电压。第一时钟信号端CKA1输入第三节点N3的第一时钟信号可以为脉冲信号，第一储能子单元1113能够使第三节点N3在一定时间内维持第一时钟信号的电压值，并且在第一节点N1电压发生跃迁(升高或者降低)的情况下，第三节点N3随之跃迁。
示例性地，参阅图12，第一储能子单元1113包括第一电容器C1，第一电容器C1的第一极板与第三节点N3电连接，第二极板与第一节点N1电连接。
在传输至第三节点N3的第一时钟信号CKA1的脉宽较小，且检测控制信号控制第一晶体管T1关闭后，第一储能子单元1113可以使第三晶体管T3在一定时间内持续向第一节点N1输入第一电压信号，进而使第一输出信号端EM1输出一段持续的工作电压信号，有利于电源电压信号端VDD对发光器件EL的阳极充电。
在一些实施例中，参阅图11，第二检测控制单元121还包括第二储能子单元1213，第二储能子单元1213与第二节点N2和第四节点N4电连接，被配置为维持第四节点N4的电压。第二时钟信号端CKA2输入第四节点N4的第二时钟信号可以为脉冲信号，第二储能子单元1213能够使第四节点N3在一定时间内维持第一时钟信号的电压值，并且在第二节点N2电压发生跃迁(升高或者降低)的情况下，第四节点N4随之跃迁。
示例性地，参阅图12，第二储能子单元1213包括第二电容器C2，第二电容器C2的第一极板与第四节点N4电连接，第二极板与第二节点N2电连接。
第二储能子单元1213能够实现的效果与第一储能子单元1113能够实现的效果相同，在此不再赘述。
在一些实施例中，参阅图12，第一检测输入子单元1111包括第一晶体管T1；第一检测输出子单元1112包括第二晶体管T2；第一储能子单元1113包 括第一电容器C1；第二检测输入子单元1211包括第三晶体管T3；第二检测输出子单元1212包括第四晶体管T4；第二储能子单元1213包括第二电容器C2。
其中，第一晶体管T1的控制极与检测控制端VH电连接，第一极与第一时钟信号端CKA1电连接，第二极与第三节点N3电连接。第二晶体管T2的控制极与第三节点N3电连接，第一极与第一电压信号端VGH电连接，第二极与第一节点N1电连接。第一电容器C1的第一极板与第三节点N3电连接，第二极板与第一节点N1电连接。第三晶体管T3的控制极与检测控制端VH电连接，第一极与第二时钟信号端CKA2电连接，第二极与至第四节点N4电连接。第四晶体管T4的控制极与第四节点N4电连接，第一极与第一电压信号端VGH电连接，第二极与第二节点N2电连接。第二电容器C2的第一极板与第四节点N4电连接，第二极板与第二节点N2电连接。
在一些实施例中，参阅图13，第一发光输出单元112可以包括第一级联信号输出子单元1121和第一发光控制信号输出子单元1122。
其中，第一级联信号输出子单元1121与第一节点N1、第一电压信号端VGH和第一级联输出信号端CR1电连接，被配置为在第一节点N1的电压的控制下，将来自第一电压信号端VGH的第一电压信号传输至第一级联输出信号端CR1，并向下一发光控制电路100的第一发光控制子电路110的第一输入信号端IN1输出第一级联信号。
示例性地，参阅图14A，第一级联信号输出子单元1121包括第三十五晶体管T35和第七电容器C7。第三十五晶体管T35的控制极与第一节点N1电连接，第一极与第一电压信号端VGH电连接，第二极与第一级联输出信号端CR1电连接。第七电容器C7的第一极板与第一节点N1电连接，第二极板与第一级联输出信号端CR1电连接。
示例性地，相互级联的两个第一发光控制电路110中，上一级的第一发光控制电路110的第一级联输出信号端CR1，与下一级的第一发光控制电路110的第一输入信号端IN1电连接。
第一发光控制信号输出子单元1122与第一节点N1、第一电压信号端VGH及第一输出信号端EM1电连接，被配置为在第一节点N1的电压的控制下，将来自第一电压信号端VGH的第一电压信号传输至第一输出信号端EM1，并向奇数行像素P1的第一发光控制扫描线EM1输出发光控制信号，以打开或者关闭奇数行像素P1的发光控制晶体管T104(1)。
参阅图14A，第一发光输出单元112的第一发光控制信号输出子单元1122 包括第十七晶体管T17，第十七晶体管T17的控制极与第一节点N1电连接，第一极与第一电压信号端VGH电连接，第二极与第一输出信号端EM1电连接。
参阅图13，第二发光输出单元122可以包括第二级联信号输出子单元1221和第二发光控制信号输出子单元1222。
其中，第二级联信号输出子单元1221与第二节点N2、第一电压信号端VGH和第二级联输出信号端CR2电连接，被配置为在第二节点N2的电压的控制下，将来自第一电压信号端VGH的第一电压信号传输至第二级联输出信号端CR2，并向下一发光控制电路100的第二发光控制子电路120输出第二级联信号。
示例性地，参阅图14B，第二级联信号输出子单元1221包括第三十六晶体管T36和第八电容器C8。第三十六晶体管T36的控制极与第二节点N2电连接，第一极与第一电压信号端VGH电连接，第二极与第二级联输出信号端CR2电连接。第八电容器C8的第一极板与第二节点N2电连接，第二极板与第二级联输出信号端CR2电连接。
示例性地，相互级联的两个第二发光控制电路120中，上一级的第一发光控制电路120的第二级联输出信号端CR2，与下一级的第二发光控制电路120的第二输入信号端IN2电连接。
参阅图13，第二发光控制信号输出子单元1222与第二节点N2、第一电压信号端VGH和第二输出信号端EM2电连接，被配置为在第二节点N2的电压的控制下，将来自第一电压信号端VGH的第一电压信号传输至第二输出信号端EM2，并向偶数行像素P2的第二发光控制扫描线EM2输出发光控制信号，以打开或者关闭偶数行像素的发光控制晶体管T104。
示例性地，参阅图14B，第二发光输出单元122的第二发光控制信号输出子单元1222包括第十八晶体管T18，第十八晶体管T18的控制极与第二节点N2电连接，第一极与第一电压信号端VGH电连接，第二极与第二输出信号端EM2电连接。
在一些实施例中，参阅图15，发光控制电路100的第一发光控制子电路110还包括第一脉宽调制单元113，第二发光控制子电路120还包括第二脉宽调制单元123。
第一脉宽调制单元113可以包括第一输入子单元1131，第一脉宽调制单元113的第一输入子单元1131与第一输入信号端IN1、第三时钟信号端CKB1及第一节点N1电连接，被配置为在来自第三时钟信号端CKB1的第三时钟信 号的控制下，将来自第一输入信号端IN1的第一输入信号传输至第一节点N1。
示例性地，参阅图14A，第一输入子单元1131可以包括第五晶体管T5，第五晶体管T5的控制极与第三时钟信号端CKB1电连接，第一极与第一输入信号端IN1电连接，第二极与第一节点N1电连接。
其中，第一输入信号端IN1可以与上一级发光控制电路100中的第一级联输出信号端CR1电连接，第一输入信号为上级发光控制电路100输出的第一级联信号。第一级发光控制电路100中第一输入信号端IN1可以与第一起始信号端STU1电连接(如图7所示)。
在一些实施例中，参阅图16A，图16A为第一发光控制子电路110的一种等效电路图，第一脉宽调制单元113还可以包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第三十七晶体管T37和第三电容器C3。
其中，第六晶体管T6的控制极与第一节点N1电连接，第一极与第二电压信号端LVGL电连接，第二极与第五节点N5电连接。第六晶体管T6被配置为在第一节点N1的电压的控制下，将来自第二电压信号端LVGL的第二电压信号传输至第五节点N5。
示例性地，第二电压信号端LVGL可以持续输出关断电压信号。
第七晶体管T7的控制极与第五节点N5电连接，第一极与第三电压信号端VGL电连接，第二极与第一输出信号端EM1电连接。第七晶体管T7被配置为在第五节点N5的电压的控制下，将来自第三电压信号端VGL的第二电压信号传输至第一输出信号端EM1。
示例性地，第三电压信号端VGL可以持续输出关断电压信号。
可以理解的是，第二电压信号端LVGL和第三电压信号端VGL均可以持续输出关断电压信号。第三电压信号端VGL和第二电压信号端LVGL输出的电平电压可以相同，或者，第三电压信号端VGL输出的电压信号的电压，高于第二电压信号端LVGL输出的电压信号的电压。示例性地，第三电压信号端VGL输出的电压信号的电压，高于第二电压信号端LVGL输出的电压信号的电压。
第八晶体管T8的控制极与第五时钟信号端CKC1电连接，第一极与第一电压信号端VGH电连接，第二极与第六节点N6电连接。
第九晶体管T9的控制极与第六节点N6电连接，第一极与第三时钟信号端CKB1电连接，第二极与第七节点N7电连接。
第十晶体管T10的控制极与第一输入信号端IN1电连接，第一极与第七 节点N7电连接，第二极与第五节点N7电连接。
第三电容器C3的第一极板与第六节点N6电连接，第二极板与第七节点N7电连接。
第八晶体管T8、第九晶体管T9、第十晶体管T10和第三电容器C3被配置为，在来自第五时钟信号端CKC1的第五时钟信号、来自第三时钟信号端CKB1的第三时钟信号和第一电压信号端VGH的第一电压信号的控制下，将第一电压信号传输至第五节点N5。
第三十七晶体管T37的控制极与第五节点N5电连接，第一极与第二电压信号端LVGL，第二极与第一级联输出信号端CR1电连接，被配置为在第五节点N5的电压的控制下，将来自第二电压信号端LVGL的第二电压信号传输至第一级联输出信号端CR1。
第一脉宽调制单元113的上述各个晶体管和第三电容器C3能够实现的功能和作用在此不再一一描述。
在一些实施例中，参阅图17A，第一脉宽调制单元113还可以包括第三十八晶体管T38、第三十九晶体管T39、第四十晶体管T40、第四十一晶体管T41、第四十二晶体管T42、第四十三晶体管T43和第九电容器C9。
第三十八晶体管T38的控制极与起始复位控制端TRS电连接，第一极与第一电压信号端VGH电连接，第二极与第一节点N1电连接，被配置为在来自起始复位控制端TRS的复位信号的控制下，将来自第一电压信号端VGH的第一电压信号传输至第一节点N1。
可以理解的是，起始复位控制端TRS通常在开机首帧之前打开几行时间，用于电路的初始化，显示期间保持恒低。
第三十九晶体管T39的控制极与第三时钟信号段CKB1电连接，第一端与第十八节点N18电连接，第二极与第一节点N1电连接。第四十晶体管T40的控制极与第一节点N1电连接，第一极与第一电压信号端VGH电连接，第二极与第十八节点N18电连接。
可以理解的是，在第一脉宽调制单元113包括第三十九晶体管T39和第四十晶体管T40的情况下，参阅图17A，第五晶体管T5的第二极与第十八节点N18电连接，第五晶体管T5的第二极通过第三十九晶体管T39与第一节点N1电连接。第三十九晶体管T39和第四十晶体管T40组成第五晶体管T5的防漏电电路，被配置为降低第五晶体管T5关闭状态下的漏电流。
第四十一晶体管T41的控制极与第一输入信号端IN1电连接，第一极与第五时钟信号端CKC1电连接，第二极与第十九节点N19电连接。第四十一 晶体管T41被配置为在来自第一输入信号端IN1的第一输入信号的控制下，将来自第五时钟信号端CKC1的第五时钟信号传输至第十九节点N19。
第四十二晶体管T42的控制极与第一输入信号端IN1电连接，第一极与第十九节点N19电连接，第二极与第七节点N7电连接。第四十二晶体管T42被配置为在来自第一输入信号端IN1的第一输入信号的控制下，将来自第十九节点N19的电压传输至第七节点N7。
第四十三晶体管T43的控制极与第七节点N7电连接，第一极与第一电压信号端VGH电连接，第二极与第十九节点N19电连接，被配置为在第七节点N7的电压的控制下，将来自第一电压信号端VGH的第一电压信号传输至第十九节点N19。
第九电容器C9的第一极板与第二电压信号端LVGL电连接，第二极板与第五节点N5电连接。
可以理解的是，第一脉宽调制单元113可以仅包括上述第三十八晶体管T38、第三十九晶体管T39、第四十晶体管T40、第四十一晶体管T41、第四十二晶体管T42、第四十三晶体管T43中的部分晶体管。比如，第一脉宽调制单元113可以包括第三十七晶体管T37、第三十八晶体管T38和第四十一晶体管T41。或者，第一脉宽调制单元113还包括第三十九晶体管T39和第四十晶体管T40。本公开的实施例对上述第三十八晶体管T38、第三十九晶体管T39、第四十晶体管T40、第四十一晶体管T41、第四十二晶体管T42、第四十三晶体管T43能够实现的功能和作用不再赘述。
在一些实施例中，参阅图15，第二脉宽调制单元123可以包括第二输入子单元1231，第二脉宽调制单元123的第二输入子单元1231与第二输入信号端IN2、第四时钟信号端CKB2及第二节点N2电连接，被配置为在来自第四时钟信号端CKB2的第四时钟信号的控制下，将来自第二输入信号端IN2的第二输入信号传输至第二节点N2。
示例性地，参阅图14B，第二输入子单元1231可以包括第十一晶体管T11，第十一晶体管T11的控制极与第四时钟信号端CKB2电连接，第一极与第二输入信号端IN2电连接，第二极与第二节点N2电连接。
其中，第二输入信号端IN2可以与上一级发光控制电路100中的第二级联输出信号端CR2电连接，第二输入信号为上级发光控制电路100输出的第二级联信号。第一级发光控制电路100中第一输入信号端IN1可以与第二起始信号端STU2电连接(如图7所示)。
在一些实施例中，参阅图16B，图16B为第二发光控制子电路120的一 种等效电路图。第二脉宽调制单元123还可以包括第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第四十六晶体管T46和第四电容器C4。
其中，第十二晶体管T12的控制极与第二节点N2电连接，第一极与第二电压信号端LVGL电连接，第二极与第八节点N8电连接。第十二晶体管T12被配置为在第二节点N2的电压的控制下，将来自第二电压信号端LVGL的第二电压信号传输至第八节点N8。
第十三晶体管T13的控制极与第八节点N8电连接，第一极与第三电压信号端VGL电连接，第二极与第二输出信号端EM2电连接。第十三晶体管T13被配为在第八节点N8的电压的控制下，将来自第三电压信号端VGL的第三电压信号传输至第二输出信号端EM2。
第四十六晶体管T46的控制极与第八节点N8电连接，第一极与第二电压信号端LVGL电连接，第二极与第二级联输出信号端CR2电连接。第四十六晶体管T46被配为在第八节点N8的电压的控制下，将来自第二电压信号端LVGL的第二电压信号传输至第二级联输出信号端CR2。
第十四晶体管T14的控制极与第六时钟信号端CKC2电连接，第一极与第一电压信号端VGH电连接，第二极与第九节点N9电连接。
第十五晶体管T15的控制极与第九节点N9电连接，第一极与第四时钟信号端CKB2电连接，第二极与第十节点N10电连接。
第十六晶体管T16的控制极与第二输入信号端IN2电连接，第一极与第十节点N10电连接，第二极与第八节点N8电连接。
第四电容器C4的第一极板与第九节点N9电连接，第二极板与第十节点N10电连接。
第十四晶体管T14、第十五晶体管T15、第十六晶体管T16和第四电容器C4被配置为，在来自第六时钟信号端CKC2的第六时钟信号、来自第四时钟信号端CKB2的第四时钟信号和来自第一电压信号端VGH的第一电压信号的控制下，将第一电压信号传输至第八节点N8。
在一些实施例中，参阅图17B，第二脉宽调制单元123还可以包括第四十五晶体管T45、第四十六晶体管T46、第四十七晶体管T47、第四十八晶体管T48、第四十九晶体管T49、第五十晶体管T50和第十电容器C10。
第四十五晶体管T45的控制极与起始复位控制端TRS电连接，第一极与第一电压信号端VGH电连接，第二极与第二节点N2电连接，被配置为在来自起始复位控制端TRS的复位信号的控制下，将来自第一电压信号端VGH 的第一电压信号传输至第二节点N2。
第四十六晶体管T46的控制极与第四时钟信号端CKB2电连接，第一极与第二十节点N20电连接，第二极与第二节点N2电连接。第四十七晶体管T47的控制极与第二节点N2电连接，第一极与第二十节点N20电连接，第二极与第二节点N2电连接。
第四十六晶体管T46和第四十七晶体管T47一起构成第十一晶体管T11的防漏电电路，被配置为降低第十一晶体管T11在关闭状态下的漏电流。
第四十八晶体管T48的控制极与第二输入信号端IN2电连接，第一极与第六时钟信号端CKC2电连接，第二极与第二十一节点N21电连接。第四十八晶体管T48被配置为在来自第二输入信号端IN2的第二输入信号的控制下，将来自第六时钟信号端CKC2的第六时钟信号传输至第二十一节点N21。
第四十九晶体管T49的控制极与第二输入信号端IN2电连接，第一极与第二十一节点N21电连接，第二极与第九节点N9电连接。第四十九晶体管T49被配置为在来自第二输入信号端IN2的第二输入信号的控制下，将第二十一节点N21的电压传输至第九节点N9。
第五十晶体管T50的控制极与第九节点N9电连接，第一极与第一电压信号端VGH电连接，第二极与第二十一节点N21电连接。第五十晶体管T50被配置为在第九节点N9的电压的控制下，将来自第一电压信号端VGH的第一电压信号传输至第二十一节点N21。
第十电容器C10的第一极板与第二电压信号端LVGL电连接，第二极板与第八节点N8电连接。
在发光控制电路100包括上述任一实施例所述的第一脉宽调制单元113和第二脉宽调制单元123，且选中一组相邻的奇数行像素P1或偶数行像素P2对发光器件EL进行补偿的情况下。在同一个帧周期F内，与对应组的奇数行像素P1和偶数行像素P电连接的第一发光控制子电路110和第二发光控制子电路120中的一者，输出脉宽调制信号，以对奇数行像素P1和偶数行像素P2的发光时间进行调制；另一者在空白阶段B，输出脉冲信号，以使工作电流流经奇数行像素P1或偶数行像素P2(选中行像素P)的发光器件EL。
在上述情况下，发光控制电路100的控制方法还包括：
在显示阶段D，第一脉宽调制单元113在第三时钟信号CKB1的控制下，将来自第一输入信号端IN1的第一输入信号传输至第一节点N1。第一发光输出单元112在第一节点N1的电压的控制下，将第一电压信号传输至第一输出信号端EM1，以对奇数行像素P1和偶数行像素P2的发光时间进行调制。
在一组相邻的奇数行像素P1或偶数行像素P2被选中进行发光器件的补偿的情况下，在空白阶段B，第二检测控制单元123将第一电压信号传输至第二节点N2，第二发光输出单元122在第二节点N2的电压的控制下，将第一电压信号传输至第二输出信号端EM2，以使工作电流流经奇数行像素P1或偶数行像素P2的发光器件EL。其中，工作电流流经奇数行像素P1或偶数行像素P2的发光器件EL是指对被选中进行补偿的像素P行的发光器件EL的阳极进行充电。
示例性地，参阅图17A和图18，图18为发光控制电路100的一种时序控制图。在前两个帧周期F内，在显示阶段D，第一起始信号端Stu1输出脉冲信号，第一发光控制子电路110的第一输入信号端IN1接收脉冲信号。
第一发光控制子电路110的第一脉宽调制单元113在第三时钟信号CKB1的控制下，第五晶体管T5和第三十九晶体管T39打开，将来自第一输入信号端IN1的第一输入信号传输至第一节点N1。
第一发光输出单元112(第十七晶体管T17)在第一节点N1的电压的控制下，将第一电压信号传输至第一输出信号端EM1，以对奇数行像素P1和偶数行像素P2的发光时间进行调制。
且第三十五晶体管T35在第一节点N1的电压的控制下，将第一电压信号传输至第一级联信号输出信号端CR1，向下一发光控制电路100的第一发光控制子电路110的第一输入信号端IN1输出第一级联信号。
在空白阶段B，参阅图17A、图17B和图18。在前两个帧周期F的空白阶段B内，在一组相邻的奇数行像素P1或偶数行像素P2被选中进行发光器件EL的补偿的情况下。
检测控制端VH将第一晶体管T1和第三晶体管T3打开。第一时钟信号端CKA1持续输出关断电压信号(即不输出脉冲信号)，第三节点N3没有信号输入，因此第三节点N3的电压维持不变(处于关断电压)。第二时钟信号端CKA2输出脉冲信号，该脉冲信号通过第三晶体管T3写入第四节点N4，第四节点N3的电位升高为工作电压。
第四晶体管T4在第四节点N4的电压控制下打开，第一电压信号端VGH的第一电压信号传输至第二节点N2。即第二检测控制单元121将第一电压信号传输至第二节点N2。
第十八晶体管T18(第二发光输出单元122)在第二节点N2的控制下打开，第一电压信号端VGH的第一电压信号经第十八晶体管T18传输至第二输出信号端EM2。
或者，发光控制电路100的控制方法还包括：
在显示阶段D，第二脉宽调制单元123在第四时钟信号CKB2的控制下，将第二输入信号传输至第二节点N2；第二发光输出单元122在第二节点N2的电压的控制下，将第一电压信号传输至第二输出信号端EM2，以对奇数行像素P1和偶数行像素P2的发光时间进行调制。
在一组相邻的奇数行像素P1或偶数行像素P2被选中进行发光器件EL的补偿的情况下，在空白阶段B，第一检测控制单元111将第一电压信号传输至第一节点N1，第一发光输出单元112在第一节点N1的电压的控制下，将第一电压信号传输至第二输出信号端EM2，以使工作电流流经奇数行像素P1或偶数行像素P2的发光器件EL。
示例性地，参阅图17B和图18，在前后个帧周期F内，在显示阶段D，第二起始信号端Stu2输出脉冲信号，第二发光控制子电路110的第二输入信号端IN2能够接收到脉冲信号。
第二发光控制子电路120的第二脉宽调制单元123在第四时钟信号CKB2的控制下，第十一晶体管T5和第四十六晶体管T46打开，将来自第二输入信号端IN2的第一输入信号传输至第二节点N2。
第二发光输出单元122(第十八晶体管T18)在第二节点N2的电压的控制下，将第一电压信号传输至第二输出信号端EM2，以对奇数行像素P1和偶数行像素P2的发光时间进行调制。
且第三十六晶体管T36在第二节点N2的电压的控制下，将第一电压信号传输至第二级联信号输出信号端CR2，向下一发光控制电路100的第二发光控制子电路120的第二输入信号端IN2输出第二级联信号。
在空白阶段B，参阅图17A、图17B和图18。在后两个帧周期F的空白阶段B内，在一组相邻的奇数行像素P1或偶数行像素P2被选中进行发光器件EL的补偿的情况下。
检测控制端VH将第一晶体管T1和第三晶体管T3打开。第一时钟信号端CKA1输出脉冲信号，该脉冲信号写入第三节点N3，第三节点N3的电位升高为工作电压。第二时钟信号端CKA2持续输出关断电压，第四节点N3的电位持续为关断电压。
第二晶体管T2在第三节点N3的电压控制下打开，第一电压信号端VGH的第一电压信号传输至第一节点N1。即第一检测控制单元111将第一电压信号传输至第一节点N1。
第十七晶体管T17(第一发光输出单元112)在第一节点N1的控制下打 开，第一电压信号端VGH的第一电压信号经第十七晶体管T17传输至第一输出信号端EM1。
在一些实施例中，发光控制电路100的控制方法还包括：
在同一个帧周期F，第一时钟信号端CKA1、第二输入信号端IN2和第四时钟信号端CKB2输出脉冲信号，且第二时钟信号端CKA2、第一输入信号端CR1和第三时钟信号端CKB1不输出电压信号。示例性地，如图18中的后两个帧周期F。
或者，发光控制电路100的控制方法还包括：
在同一个帧周期F，第二时钟信号端CKA2、第一输入信号端CR1和第三时钟信号端CKB1输出脉冲信号，且第一时钟信号端CKA1、第二输入信号端IN2和第四时钟信号端CKB2不输出电压信号。示例性地，如图18中的前两个帧周期F。
在一些实施例中，参阅图19A和图19B，随机检测电路(随机Sense unit)200与随机检测信号端OE、第三输入信号端IN3、第七时钟信号端CKD和第十一节点N11电连接，被配置为在来自随机检测信号端OE的随机检测信号和来自第三输入信号端IN3的第三输入信号的控制下，将来自第七时钟信号端CKD的第七时钟信号传输至第十一节点N11，以选中一行像素进行发光器件EL的补偿。
随机检测电路200能够产生随机检测信号，进而在每一帧选中不同行像素，对不同行像素P的发光器件进行补偿，从而达到随机补偿的目的。
移位寄存器电路300与第十一节点N11电连接，被配置为在第十一节点N11的电压控制下，向对应行像素P输出扫描信号，以打开对应行像素P。
上述任一实施例中的发光控制电路100的检测控制端VH，与随机检测电路200中的电路节点或者移位寄存器电路300中的电路节点电连接。这样，不需要设置额外的信号控制端向检测控制端VH提供信号，进而简化栅极驱动电路1120。
在一些实施例中，参阅图20，随机检测电路包括200包括随机检测控制子电路210和检测输出子电路220。
随机检测控制子电路210与随机检测信号端OE、第三输入信号端IN3和第十二节点N12电连接，被配置为在来自随机检测信号端OE的随机检测信号控制下，将来自第三输入信号端IN3的第三输入信号传输至第十二节点N12。
其中，第三输入信号端IN3可以为级联输入信号端，第三输入信号端IN3与上级栅极驱动电路1120中移位寄存器电路300的第三级联输出信号端或第 四级联输出信号端电连接。
参阅图20，检测输出子电路220与第十二节点N12、第七时钟信号端CKD和第十一节点N11电连接，被配置为在第十二节点N12的电压控制下，将第七时钟信号传输至第十一节点N11。其中，发光控制电路100的检测控制端VH与第十二节点N12电连接。
示例性地，参阅图21，随机检测控制子电路210包括第十九晶体管T19，第十九晶体管T19的控制极与随机检测信号端OE电连接，第一极与第三输入信号端IN3电连接，第二极与第十二节点N12电连接。
检测输出子电路220包括第二十晶体管T20，第二十晶体管T20的控制极与第十二节点N12电连接，第一极与第七时钟信号端CKD电连接，第二极与第十一节点N11电连接。
在一些实施例中，参阅图22，随机检测电路200还包括第一储能子电路230和第一防漏电子电路240。
第一储能子电路230与第四电压信号端VDD和第十二节点N12电连接，被配置为维持第十二节点N12的电压。
其中，第四电压信号端VDD可以与像素驱动电路1110中的电源电压信号端VDD相同，因此，两者使用了相同的标号“VDD”。这样，可以减少电压信号端的数量，进而简化显示面板1000的电路结构。
第一防漏电子电路240与随机检测控制子电路210、随机检测信号端OE、第十二节点N12和第四电压信号端VDD电连接，被配置为在来自随机检测信号端OE的随机检测信号和第十二节点的电压的控制下，将来自第四电压信号端VDD的第四电压信号传输至第十一节点N11。
示例性地，参阅图23，第一储能子电路230包括第五电容器C5，第五电容器C5的第一极板与第四电压信号端VDD电连接，第二极与第十二节点N12电连接。
示例性地，参阅图23，第一防漏电子电路240包括第二十一晶体管T21和第二十二晶体管T22，第二十一晶体管T21的控制极与随机检测信号端OE电连接，第一极与第十三节点N13电连接，第二极与第十二节点N12电连接。第二十二晶体管T22的控制极与第十二节点N12电连接，第一极与第四电压信号端VDD电连接，第二极与第十三节点N13电连接。
参阅图23，随机检测控制子电路210通过第一防漏电子电路240与第十二节点N12电连接。即第十九晶体管T19的第二极通过第二十一晶体管T21与第十二节点N12电连接。
参阅图23，第十九晶体管T19的第二极与第二十一晶体管T21的第一极电连接，且第十九晶体管T19的控制极和第二十一晶体管T21的控制极均与随机检测信号端OE电连接，这样，在随机检测信号端OE输出工作电平的情况下，第十九晶体管T19的控制极和第二十一晶体管T21同时打开，来自第三输入信号端IN3的第三输入信号能够依次通过第十九晶体管T19的控制极和第二十一晶体管T21传输至第十二节点N12。
本公开的一些实施例还提供了一种上述栅极驱动电路1120的控制方法。控制方法包括：
在一组相邻的奇数行像素P1或偶数行像素P2被选中进行发光器件EL的补偿的情况下。
在显示阶段D，栅极驱动电路1120的随机检测电路200在(来自随机检测信号端OE的)随机检测信号的控制下，将来自第三输入信号端IN3的第三输入信号传输至随机检测电路200中的电路节点NX(第十二节点N12)，且维持对应电路节点NX电压至空白阶段B。
在空白阶段B，随机检测电路200在电路节点NX的电压的控制下，将来自第七时钟信号端CKD的第七时钟信号传输至栅极驱动电路1120的移位寄存器电路300。
移位寄存器电路向对应行像素P(被选中进行发光器件EL补偿的一行像素P)输出扫描信号，以打开对应行像素P(打开对应行像素P的数据写入晶体管T102)。
栅极驱动电路1120的发光控制电路1000在随机检测电路200中的电路节点NX的电压或者移位寄存器电路300中的电路节点NY(第十四节点N14或第十五节点N15)的电压的控制下，将第一电压信号传输至第一输出信号端EM1或第二输出信号端EM2，以使工作电流流经奇数行像素P1或偶数行像素P2的发光器件。
示例性地，在空白阶段B，随机检测电路200的电路节点NX，和移位寄存器电路300中的电路节点NY，均可以向发光控制电路100的检测控制端VH输出工作电压。发光控制电路100在来自检测控制端VH的检测控制信号的控制下，将第一电压信号传输至第一输出信号端EM1或第二输出信号端EM2。参见上文中发光控制电路100的控制方法，此处不再赘述。
在一些实施例中，参阅图24A，移位寄存器电路300包括第一移位寄存器子电路310和第二移位寄存器子电路320。第一移位寄存器子电路310包括第一补偿输入单元311和第一扫描输出单元312。第二移位寄存器子电路320 包括第二补偿输入单元321和第二扫描输出单元322。
其中，第一补偿输入单元311与第十一节点N11、第七时钟信号端CKD和第十四节点N14电连接，被配置为在来自第七时钟信号端CKD的第七时钟信号的控制下，将第十一节点N11的电压传输至第十四节点N14。
第一扫描输出单元312与第十四节点N14、第八时钟信号端CKE1和第三输出信号端GL1电连接，第三输出信号端GL1被配置为与奇数行像素P1电连接(与奇数行像素P1的数据写入晶体管T102(1)的控制极电连接)。第一扫描输出单元312被配置为在第十四节点N14的电压的控制下，将来自第八时钟信号端CKE1的第八时钟信号传输至第三输出信号端GL1，以打开对应的奇数行像素P1(打开数据写入晶体管T102(1))。
可以理解的是，本公开实施例中，第三输出信号端GL1与第一栅线GL1电连接，为了简化说明，两者采用了相同的标号“GL1”。第四输出信号端GL2与第二栅线GL2电连接，为了简化说明，两者采用了相同的标号“GL2”。
第二补偿输入单元321与第十一节点N11、第七时钟信号端CKD和第十五节点N15电连接，被配置为在第七时钟信号CKD的控制下，将第十一节点N11的电压传输至第十五节点N15。
第二扫描输出单元322与第十五节点N15、第九时钟信号端CKE2和第四输出信号端GL2电连接，第四输出信号端GL2被配置为与偶数行像素P2电连接(与偶数行像素P2的数据写入晶体管T102(2)的控制极电连接)。第二扫描输出单元322被配置为在第十五节点N15的电压的控制下，将来自第九时钟信号端CKE2的第九时钟信号传输至第四输出信号端GL2，以打开对应的偶数行像素P2(打开数据写入晶体管T102(2))。
示例性地，参阅图24B，第一补偿输入单元311包括第二十三晶体管T23，第二十三晶体管T23的控制极与第七时钟信号端CKD，第一极与第十一节点电连接，第二极与第十四节点N14电连接。
第一扫描输出单元312包括第二十四晶体管T24，第二十四晶体管T24的控制极与第十四节点N14电连接，第一极与第八时钟信号端CKE1电连接，第二极与第三输出信号端GL1电连接。
第二补偿输入单元321包括第二十五晶体管T25，第二十五晶体管T25的控制极与第七时钟信号端CKD电连接，第一极与第十一节点N11电连接，第二极与第十五节点N15电连接。
第二扫描输出单元322包括第二十六晶体管T26，第二十六晶体管T26的控制极与第十五节点N15电连接，第一极与第九时钟信号端CKE2电连接， 第二极与第四输出信号端GL2电连接。
在一些实施例中，上述任一实施例中的发光控制电路100的检测控制端VH与第十四节点N14或者第十五节点N15电连接。
在一些实施例中，参阅图25A，第一移位寄存器子电路310还包括第一扫描输入单元313、第一反相器314和第一复位单元315。
第一扫描输入单元313与第三输入信号端IN3、第四电压信号端VDD和第十四节点N14电连接，被配置为在来自第三输入信号端IN3的第三输入信号的控制下，将来自第第四电压信号端VDD的第四电压信号传输至第十四节点N14。
第一反相器314的一端与第十四节点N14电连接，另一端与第十六节点N16电连接。
可以理解的是，第一反相器314和第二反相器324的结构和其能够实现的功能和作用是本领域常规技术，本申请不再赘述。
第一复位单元与第一复位信号端Std1、第十六节点N16、第五电压信号端LVGL、第十四节点N14和第三输出信号端GL1电连接，被配置为在来自第一复位信号端Std1的第一复位信号和第十六节点N16的电压的控制下，将第五电压信号端LVGL的第五电压信号传输至第十四节点N14和第三输出信号端GL1。
可以理解的是，第五电压信号LVGL和第二电压信号端LVGL均可以持续输出低电平电压信号。两者可以相同或者不同。本公开的实施例中，以第五电压信号端LVGL和第二电压信号端LVGL相同为例进行示例性说明。
示例性地，参阅图26A，第一扫描输入单元313包括第二十七晶体管T27，第二十七晶体管T27的控制极与第三输入信号端IN3电连接，第一极与第四电压信号端VDD电连接，第二极与第十四节点N14电连接。
第一复位单元315可以包括包括第二十八晶体管T28、第二十九晶体管T29和第三十晶体管T30。
第二十八晶体管T28的控制极与第一复位信号端Std1电连接，第一极与第五电压信号端LVGL电连接，第二极与第十四节点N14电连接。
第二十九晶体管T29的控制极与第十六节点N16电连接，第一极与第五电压信号端LVGL电连接，第二极与第三输出信号端GL1电连接。
第三十晶体管T30的控制极与与第十六节点N16电连接，第一极与第五电压信号端LVGL电连接，第二极与第十四节点N14电连接。
在一些实施例中，参阅图26A，第一移位寄存器子电路还可以包括第五 十一晶体管T51、第五十二晶体管T52、第五十三晶体管T53、第五十四晶体管T54和第十一电容器C11。
第五十一晶体管T51的控制极与第一复位信号端Std1电连接，第一极与第二十二节点N22(第二十八晶体管T28的第二极)电连接，第二极与第十四节点电连接。其中，第二十八晶体管T28的第二极通过第五十元晶体管T51与第十四节点N14电连接。
第五十二晶体管T52的控制极与第十六节点N16电连接，第一极与第二十二节点N22(第三十晶体管T30的第二极)电连接，第二极与第十四节点N14电连接。其中，第三十晶体管T30的第二极通过第五十二晶体管T52与第十四节点N14电连接。
第五十三晶体管T53的控制极与第七时钟信号端CKD电连接，第一极与第二十二节点N22电连接，第二极与第十四节点N14电连接。第二十三晶体管T23的第二极通过第五十三晶体管T53与第十四节点N14电连接。
第五十四晶体管T54的控制极与第十四节点N14电连接，第一极与第四电压信号端VDD电连接，第二极与第二十二节点N22电连接。
在一些实施例中，参阅图25B，第二移位寄存器子电路320还包括第二扫描输入单元323、第二反相器324和第二复位单元325。
第二扫描输入单元323与第三输入信号端IN3、第四电压信号端VDD和第十五节点N15电连接，被配置为在第三输入信号的控制下，将第三电压信号传输至第十五节点N15。
第二反相器324的一端与第十五节点N15电连接，另一端与第十七节点N17电连接。
第二复位单元325与第二复位信号端Std2、第五电压信号端LVGL、第十五节点N16、第十七节点N17和第四输出信号端GL2电连接，被配置为在来自第二复位信号端Std2的第二复位信号和第十七节点N17的电压的控制下，将来自第五电压信号端LVGL的第五电压信号传输至第十五节点N15和第四输出信号端GL2。
示例性地，参阅图26B，第二扫描输入单元323包括第三十一晶体管T31，第三十一晶体管T31的控制极与第三输入信号端IN3电连接，第一极与第四电压信号端VDD电连接，第二极与第十五节点N15电连接。
第二复位单元325包括第三十二晶体管T32、第三十三晶体管T33和第三十四晶体管T34。
第三十二晶体管T32的控制极与第二复位信号端Std2电连接，第一极与 是第五电压信号端LVGL电连接，第二极与第十五节点N15电连接。
第三十三晶体管T33的控制极与第十七节点N17电连接，第一极与第五电压信号端VLGL电连接，第二极与第四输出信号端GL2电连接。
第三十四晶体管T34的控制极与第十七节点N17电连接，第一极与第四电压信号端LVGL电连接，第二极与第十五节点N15电连接。
在一些实施例中，第二移位寄存器子电路320还包括第五十五晶体管T55、第五十六晶体管T56、第五十七晶体管T57和第五十八晶体管T58。
第五十五晶体管T55的控制极与第二复位信号端Std2电连接，第一极与第二十三节点N23(第三十二晶体管T32的第二极)电连接，第二极与第十五节点N15电连接。第三十二晶体管T32的第二极通过第五十五晶体管T55与第十五晶体管电连接。
第五十六晶体管T56的控制极与第十七节点N17电连接，第一极与第二十三节点N23(第三十四晶体管T34的第二极)电连接，第二极与第十五节点N15电连接。第三十四晶体管T34的第二极通过第五十六晶体管T56与第十五节点N15电连接。
第五十七晶体管T57的控制极与第七时钟信号端CKD电连接，第一极与第二十三N23节点(第二十五晶体管T25的第二极)电连接，第二极与第十五节点N15电连接。第二十五晶体管T25的第二极通过第五十七晶体管T57与第十五节点N15电连接。
第五十八晶体管T58的控制极与第十五节点电连接，第一极与第四电压信号端VDD电连接，第二端与第二十三节点N23电连接。
本公开的一些实施例还提供了一种栅极驱动电路的控制方法，用于驱动上述任一实施例中的栅极驱动电路1120。在一组相邻的奇数行像素P1或偶数行像素P2被选中进行发光器件EL的补偿的情况下。控制方法包括：
在显示阶段D，栅极驱动电路1120的随机检测电路200在(来自随机检测信号端OE的)随机检测信号的控制下，将来自第三输入信号端IN3的第三输入信号传输至随机检测电路200中的电路节点NX(第十二节点N12)，且维持对应电路节点NX电压至空白阶段B。
示例性地，参阅图26A和图27，显示阶段D的某一时段，随机检测信号端OE和第三输入信号端IN3输出高电平信号，第十九晶体管T19和第二十一晶体管T21在来自随机检测信号端OE的随机检测信号的控制下打开，来自第三输入信号端IN3的第三输入信号(高电平信号)传输至随机检测电路200中的第十二节点N12。第二十晶体管T20打开。
然后，随机检测信号端OE和第三输入信号端IN3输出低电平信号，第二十一晶体管T21关闭，第十二节点N12在第五电容器C5的作用下电压保持不变。
在空白阶段B，随机检测电路200在电路节点NX(第十二节点)的电压的控制下，将来自第七时钟信号端CKD的第七时钟信号传输至栅极驱动电路1120的移位寄存器电路300。
示例性地，参阅图26A和图27，第十二节点N12在第五电容器C5的作用下电压保持不变，第二十晶体管T20保持打开状态。在空白阶段B的某一时段，第七时钟信号端CKD输出高电平的第七时钟信号，第七时钟信号通过第二十晶体管T20传输至第十一节点N11。
移位寄存器电路向对应行像素P(被选中进行发光器件EL补偿的一行像素P)输出扫描信号，以打开对应行像素P(打开对应行像素P的数据写入晶体管T102)。
示例性地，参阅图26A，在第七时钟信号端CKD的第七时钟信号的作用下，第二十三晶体管T23和第五十三晶体管T53同时打开，第十一节点N11处的第七时钟信号传输至第十四节点N14。在第十四节点N14的电压(第七时钟信号)的控制下，第二十四晶体管T24打开。
同理，参阅图26B，第十一节点N11处的第七时钟信号还可以传输至第十五节点N15。第十五节点N15的电压控制第二十六晶体管T26打开。
第七时钟信号端CKE1和第八时钟信号端CKE2中的一者，输出高电平电压信号，并传输至第三输出信号端GL1或第四输出信号端GL2。
示例性地，在选中奇数行像素P1进行发光器件EL补偿的情况下，第七时钟信号端CKE1输出高电平电压信号，第七时钟信号端CKE1输出的高电平电压信号通过第二十四晶体管T24传输至第三输出信号端GL1，向奇数行像素P1输出扫描信号，奇数行像素P1的数据写入晶体管T102(1)打开。
示例性地，在选中偶数行像素P2进行发光器件EL补偿的情况下，第八时钟信号端CKE2输出高电平电压信号，第八时钟信号端CKE2输出的高电平电压信号通过第二十六晶体管T26传输至第四输出信号端GL2，向偶数行像素P2输出扫描信号，偶数行像素P2的数据写入晶体管T102(2)打开。
栅极驱动电路1120的发光控制电路1000在随机检测电路200中的电路节点NX的电压或者移位寄存器电路300中的电路节点NY(第十四节点N14或第十五节点N15)的电压的控制下，将第一电压信号传输至第一输出信号端EM1或第二输出信号端EM2，以使工作电流流经奇数行像素P1或偶数行 像素P2的发光器件EL。
可以理解的是，工作电流流经奇数行像素P1或偶数行像素P2的发光器件EL是指，对被选中行像素P的发光器件EL的阳极进行充电。
在空白阶段B，随机检测电路200的电路节点NX和移位寄存器电路300中的电路节点NY，均可以向发光控制电路100的检测控制端VH输出工作电压信号。发光控制电路100在来自检测控制端VH的检测控制信号的控制下，将第一电压信号传输至第一输出信号端EM1或第二输出信号端EM2。
示例性地，发光控制电路100的检测控制端VH与随机检测电路200中的第十二节点电连接。参阅图27，在空白阶段B，第十二节点N12输出高电平电压信号，可以控制发光控制电路100将第一电压信号传输至第一输出信号端EM1或第二输出信号端EM2，以打开奇数行像素P1(发光控制晶体管T104(1))或偶数行像素P2(发光控制晶体管T104(1))。其中，发光控制电路100的工作过程参阅上文，此处不再赘述。
示例性地，发光控制电路100的检测控制端VH与移位寄存器电路300中的第十四节点或第十五节点N14电连接。参阅图27，在空白阶段B，第十四节点N14和第十五节点N152均可以输出高电平电压信号，发光控制电路100第一电压信号传输至第一输出信号端EM1或第二输出信号端EM2。发光控制电路100的工作过程此处不再赘述。
栅极驱动电路1120的发光控制电路110的第一输出信号端EM1与奇数行像素P1电连接，发光控制电路100的第二输出信号端EM2与偶数行像素P2电连接。
在一些实施例中，参阅图15和图25A。在移位寄存器电路300包括第一移位寄存器子电路310和第二移位寄存器子电路320，第一移位寄存器子电路310包括第一扫描输入单元313和第一扫描输出单元312，第二移位寄存器子电路320包括第二扫描输入单元323和第二扫描输出单元322；发光控制电路100的第一发光控制子电路110包括第一脉宽调制单元113，第二发光控制子电路120包括第二脉宽调制单元123。
在显示阶段D，第一扫描输入单元313在第三输入信号IN3的控制下，向第十四节点N14输入第四电压信号；第一扫描输出单元312在第十四节点N14的电压的控制下，将第八时钟信号传输至第三输出信号端GL1，以打开对应的奇数行像素。
示例性地，参阅图26A和图27，在显示阶段D，在第三输入信号端IN3输出高电平电压信号时，第二十七晶体管T27打开，第四电压信号端VDD的 第四电压信号传输至第十四节点N14。第四电压信号可以为高电平电压信号，在第十四节点N14的第四电压信号的控制下，第二十四晶体管T24打开，来自第八时钟信号端CKE1的第八时钟信号传输至第三输出信号端GL1。
第二扫描输入单元323在第三输入信号IN3的控制下，向第十五节点N15输入第四电压信号；第二扫描输出单元322在第十五节点N15的电压的控制下，将第九时钟信号传输至第四输出信号端GL2，以打开对应的偶数行像素。
示例性地，参阅图26B和图27，在显示阶段D，在第三输入信号端IN3输出高电平电压信号时，第三十一晶体管T31打开，第四电压信号端VDD的第四电压信号传输至第十五节点N15。在第十四节点N14的第四电压信号的控制下，第二十六晶体管T26打开，来自第九时钟信号端CKE2的第九时钟信号传输至第三输出信号端GL1。
示例性地，第八时钟信号端CKE1和第九时钟信号端CKE2可以在不同时刻输出高电平电压信号，以使第三输出信号端GL1和第四输出信号端GL2可以在不同时刻输出扫描信号，进而在不同时刻打卡不同行像素P的数据写入晶体管T102。
第一脉宽调制单元113在第三时钟信号CKB1的控制下，将来第一输入信号传输至第一节点，或者，第二脉宽调制单元123在第四时钟信号CKB2的控制下，将第二输入信号传输至第二节点N2，以对奇数行像素和偶数行像素的发光时间进行调制。即在同一个帧周期内，第一脉宽调制单元113和第二脉宽调制单元123中的一者输出脉宽调制信号，在不同帧周期内，第一脉宽调制单元113和第二脉宽调制单元123交替输出脉宽调制信号。其中，第一脉宽调制单元113和第二脉宽调制单元123的控制过程可参阅上文，此处不再赘述。
本公开的一些实施例还提供了一种显示面板的控制方法，用于控制上述实施例中的显示面板1000。显示面板1000包括栅极驱动电路1120、数据驱动电路1200和像素驱动电路1110。
在一些实施例中，参阅图28，空白阶段B包括第一数据写入阶段B11、第二数据写入阶段B12和感测阶段B13。
在一组相邻的奇数行像素P1或偶数行像素P2被选中进行发光器件的补偿的情况下，其中，图28以选中偶数行像素P2进行发光器件EL的补充为例进行展示。显示面板100的控制方法包括：
在第一数据写入阶段B11，数据驱动电路1200向奇数行像素P1和偶数行像素P2中未被选中进行外部补偿的一者，写入零灰阶数据V0。这样，未 被选中进行外部补偿的一行像素P的驱动晶体管T101不会打开，当其中一个发光控制晶体管T104打开后，不会对未被选中的一行像素P的发发光器件EL的阳极进行充电，确保每帧直选中一行像素P进行发光器件EL补偿。
示例性地，参阅图28，在偶数行像素P2被选中进行发光器件EL的补偿的情况下，在第一数据写入阶段B11，与奇数行像素P1电连接的第一栅线GL1(1)和第二栅线GL2(1)输出工作电压信号，数据线DL输出零灰阶数据V0。这样，奇数行像素P1的驱动晶体管T101(1)的控制极为关断电压信号，奇数行像素P1的驱动晶体管T10在后续补偿过程中处于关闭状态。
在第二数据写入阶段B12，数据驱动电路1200向奇数行像素P1和偶数行像素P2中被选中进行发光器件的补偿的一者，写入感测灰阶数据VGm。
示例性地，参阅图28，在第二数据写入阶段B12，与偶数行像素P2电连接的第一栅线GL1(2)和第二栅线GL2(2)输出工作电压信号，数据线DL输出感测灰阶数据VGm。这样，偶数行像素P2的驱动晶体管T101(2)的控制极为工作电压，偶数行像素P1的驱动晶体管T101(2)在后续补偿过程中处于可以打开。
在感测阶段B13，第一发光控制子电路110或第二发光控制子电路120输出第一电压信号(工作电压)，以使工作电流流经奇数行像素和偶数行像素的发光器件EL；奇数行像素或偶数行像素的像素电路对发光器件的电压进行检测。
示例性地，第一发光控制子电路110向第一发光控制信号线EM1输出第一电压信号。工作电流可以流经选中行像素P(被选中进行发光器件EL补偿的一行像素P)的驱动控制晶体管T101，进而使工作电流流经选中行像素P的发光器件EL，对对应的发光器件EL的阳极进行充电。像素驱动电路1110的感测信号线SL对对应发光器件EL的阳极的电压进行感测。
在一些实施例中，参阅图28，空白阶段B在感测感测阶段B13之后，还包括第一数据写回阶段B14和第二数据写回阶段B15。
在第一数据写回阶段B14，一组相邻的奇数行像素P1和偶数行像素P2中未被选中进行发光器件EL的补偿的一者，写入第一初始灰阶数据DATA1；第一初始灰阶数据DATA1为在第一数据写入阶段B11之前，写入对应行像素P的灰阶数据。这样，可以使未被选中的一行像素P在下一个显示阶段D显示所需显示的灰阶。
示例性地，参阅图28，在第一数据写回阶段B14，与奇数行像素P1电连接的第一栅线GL1(1)和第二栅线GL2(1)输出工作电压信号，数据线DL输出 第一初始灰阶数据DATA1。
在第二数据写回阶段B15，奇数行像素P1和偶数行像素P2中被选中进行发光器件EL的补偿的一者，写入第二初始灰阶数据DATA2；第二初始灰阶数据DATA2为在第二数据写入阶段B12之前，写入对应行像素的灰阶数据。这样，可以使被选中的一行像素P在下一个显示阶段D显示所需显示的灰阶。
示例性地，参阅图28，在第二数据写回阶段B15，与偶数行像素P2电连接的第一栅线GL1(2)和第二栅线GL2(2)输出工作电压信号，数据线DL输出第二初始灰阶数据DATA2。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种发光控制电路，包括：
    第一发光控制子电路，包括第一检测控制单元和第一发光输出单元；其中，
    所述第一检测控制单元与检测控制端、第一时钟信号端、第一电压信号端及所述第一节点电连接，被配置为在来自所述检测控制端的检测控制信号和来自所述第一时钟信号端的第一时钟信号的控制下，将来自所述第一电压信号端的第一电压信号传输至所述第一节点；
    所述第一发光输出单元与所述第一节点、所述第一电压信号端和第一输出信号端电连接，被配置为在所述第一节点的电压的控制下，将所述第一电压信号传输至所述第一输出信号端；
    第二发光控制子电路，包括第二检测控制单元和第二发光输出单元；其中，
    所述第二检测控制单元与所述检测控制端、第二时钟信号端、所述第一电压信号端及所述第二节点电连接，被配置为在所述检测控制信号和来自所述第二时钟信号端的第二时钟信号的控制下，将所述第一电压信号传输至所述第二节点；
    所述第二发光输出单元与所述第二节点、所述第一电压信号端和第二输出信号端电连接，被配置为在所述第二节点的电压控制下，将所述第一电压信号传输至所述第二输出信号端。
  2. 根据权利要求1所述的发光控制电路，其中，
    所述第一检测控制单元包括：
    第一检测输入子单元，与所述检测控制端、所述第一时钟信号端及第三节点电连接，被配置为在所述检测控制信号的控制下，将所述第一时钟信号传输至所述第三节点；
    第一检测输出子单元，与所述第三节点、所述第一电压信号端和所述第一节点电连接，被配置为在所述第三节点的电压控制下，将所述第一电压信号传输至所述第一节点；
    所述第二检测控制单元包括：
    第二检测输入子单元，与所述检测控制端、所述第二时钟信号端及第四节点电连接，被配置为在所述检测控制信号的控制下，将所述第二时钟信号传输至所述第四节点；
    第二检测输出子单元，与所述第四节点、所述第一电压信号端和所述第二节点电连接，被配置为在所述第四节点的电压控制下，将所述第一电压信 号传输至所述第二节点。
  3. 根据权利要求2所述的发光控制电路，其中，
    所述第一检测控制单元还包括第一储能子单元；所述第一储能子单元与所述第一节点和所述第三节点电连接，被配置为维持所述第三节点的电压；
    所述第二检测控制单元还包括第二储能子单元；第二储能子单元与所述第二节点和所述第四节点电连接，被配置为维持所述第四节点的电压。
  4. 根据权利要求3所述的发光控制电路，其中，
    所述第一检测输入子单元包括第一晶体管，所述第一晶体管的控制极与所述检测控制端电连接，第一极与所述第二时钟信号端电连接，第二极与所述第三节点电连接；
    所述第一检测输出子单元包括第二晶体管，所述第二晶体管的控制极与所述第三节点电连接，第一极与所述第一电压信号端电连接，第二极与所述第一节点电连接；
    所述第一储能子单元包括第一电容器，所述第一电容器的第一极板与所述第三节点电连接，第二极板与所述第一节点电连接；
    所述第二检测输入子单元包括第三晶体管，所述第三晶体管的控制极与所述检测控制端电连接，第一极与所述第四时钟信号端电连接，第二极与所述第四节点电连接；
    所述第二检测输出子单元包括第四晶体管，所述第四晶体管的控制极与所述第四节点电连接，第一极与所述第一电压信号端电连接，第二极与所述第二节点电连接；
    所述第二储能子单元包括第二电容器，所述第二电容器的第一极板与所述第四节点电连接，第二极板与所述第二节点电连接。
  5. 根据权利要求1～4中任一项所述的发光控制电路，其中，
    所述第一发光控制子电路还包括：
    第一脉宽调制单元，与第一输入信号端、第三时钟信号端及所述第一节点电连接，被配置为在来自所述第三时钟信号端的第三时钟信号的控制下，将来自所述第一输入信号端的第一输入信号传输至所述第一节点；
    所述第二发光控制子电路还包括：
    第二脉宽调制单元，与第二输入信号端、第四时钟信号端及所述第二节点电连接，被配置为在来自所述第四时钟信号端的第四时钟信号的控制下，将来自所述第二输入信号端的第二输入信号传输至所述第二节点。
  6. 根据权利要求5所述的发光控制电路，其中，
    所述第一脉宽调制单元包括：
    第五晶体管，所述第五晶体管的控制极与所述第三时钟信号端电连接，第一极与所述第一输入信号端电连接，第二极与所述第一节点电连接；
    第六晶体管，所述第六晶体管的控制极与所述第一节点电连接，第一极与第二电压信号端电连接，第二极与第五节点电连接；
    第七晶体管，所述第七晶体管的控制极与所述第五节点电连接，第一极与第三电压信号端电连接，第二极与所述第一输出信号端电连接；
    第八晶体管，所述第八晶体管的控制极与第五时钟信号端电连接，第一极与所述第一电压信号端电连接，第二极与第六节点电连接；
    第九晶体管，所述第九晶体管的控制极与所述第六节点电连接，第一极与所述第三时钟信号端电连接，第二极与第七节点电连接；
    第十晶体管，所述第十晶体管的控制极与所述第一输入信号端电连接，第一极与所述第七节点电连接，第二极与所述第五节点电连接；
    第三电容器，所述第三电容器的第一极板与所述第六节点电连接，第二极板与所述第七节点电连接；
    所述第二脉宽调制单元包括：
    第十一晶体管，所述第十一晶体管的控制极与所述第四时钟信号端电连接，第一极与所述第二输入信号端电连接，第二极与所述第二节点电连接；
    第十二晶体管，所述第十二晶体管的控制极与所述第二节点电连接，第一极与第二电压信号端电连接，第二极与第八节点电连接；
    第十三晶体管，所述第十三晶体管的控制极与所述第八节点电连接，第一极与所述第三电压信号端电连接，第二极与所述第二输出信号端电连接；
    第十四晶体管，所述第十四晶体管的控制极与第六时钟信号端电连接，第一极与所述第一电压信号端电连接，第二极与第九节点电连接；
    第十五晶体管，所述第十五晶体管的控制极与所述第九节点电连接，第一极与所述第四时钟信号端电连接，第二极与第十节点电连接；
    第十六晶体管，所述第十六晶体管的控制极与所述第二输入信号端电连接，第一极与所述第十节点电连接，第二极与所述第八节点电连接；
    第四电容器，所述第四电容器的第一极板与所述第九节点电连接，第二极板与所述第十节点电连接；
    所述第一发光输出单元包括：
    第十七晶体管，所述第十七晶体管的控制极与所述第一节点电连接，第一极与所述第一电压信号端电连接，第二极与所述第一输出信号端电连接；
    所述第二发光输出单元包括：
    第十八晶体管，所述第十八晶体管的控制极与所述第二节点电连接，第一极与所述第一电压信号端电连接，第二极与所述第二输出信号端电连接。
  7. 一种栅极驱动电路，包括：
    随机检测电路，与随机检测信号端、第三输入信号端、第七时钟信号端和第十一节点电连接，被配置为在来自所述随机检测信号端的随机检测信号和来自所述第三输入信号端的第三输入信号的控制下，将来自所述第七时钟信号端的第七时钟信号传输至所述第十一节点，以选中一行像素进行发光器件的补偿；
    移位寄存器电路，与所述第十一节点电连接，被配置为在所述第十一节点的电压控制下，向对应行像素输出扫描信号，以打开对应行像素；
    如权利要求1～6中任一项所述的发光控制电路，所述发光控制电路的检测控制端与所述随机检测电路中的电路节点或者所述移位寄存器电路中的电路节点电连接。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述随机检测电路包括：
    随机检测控制子电路，与所述随机检测信号端、所述第三输入信号端和第十二节点电连接，被配置为在所述随机检测信号的控制下，将所述第三输入信号传输至所述第十二节点；
    检测输出子电路，与所述第十二节点、所述第七时钟信号端和所述第十一节点电连接，被配置为在所述第十二节点的电压控制下，将所述第七时钟信号传输至所述第十一节点；
    其中，所述检测控制端与所述第十二节点电连接。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述随机检测电路还包括：
    第一储能子电路，与第四电压信号端和所述第十二节点电连接，被配置为维持所述第十二节点的电压；
    第一防漏电子电路，与所述随机检测控制子电路、所述随机检测信号端、所述第十二节点和所述第四电压信号端电连接，被配置为在所述随机检测信号和所述第十二节点的电压的控制下，将所述第四电压信号传输至所述第十一节点；
    其中，所述随机检测控制子电路通过所述第一防漏电子电路与所述第十二节点电连接。
  10. 根据权利要求9所述的栅极驱动电路，其中，
    所述随机检测控制子电路包括第十九晶体管，所述第十九晶体管的控制极与所述随机检测信号端电连接，第一极与所述第三输入信号端电连接，第二极与第十三节点电连接；
    所述检测输出子电路包括第二十晶体管，所述第二十晶体管的控制极与所述第十二节点电连接，第一极与所述第七时钟信号端电连接，第二极与所述第十一节点电连接；
    所述第一储能子电路包括第五电容器，所述第五电容器的第一极板与所述第四电压信号端电连接，第二极与所述第十二节点电连接；
    第一防漏电子电路包括第二十一晶体管和第二十二晶体管，所述第二十一晶体管的控制极与所述随机检测信号端电连接，第一极与所述第十三节点电连接，第二极与所述第十二节点电连接；所述第二十二晶体管的控制极与所述第十二节点电连接，第一极与所述第四电压信号端电连接，第二极与所述第十三节点电连接。
  11. 根据权利要求7所述的栅极驱动电路，其中，所述移位寄存器电路包括：
    第一移位寄存器子电路，包括第一补偿输入单元和第一扫描输出单元；其中，
    所述第一补偿输入单元与所述第十一节点、所述第七时钟信号端和第十四节点电连接，被配置为在所述第七时钟信号的控制下，将所述第十一节点的电压传输至所述第十四节点；
    所述第一扫描输出单元与所述第十四节点、第八时钟信号端和第三输出信号端电连接，所述第三输出信号端被配置为与奇数行像素电连接；所述第一扫描输出单元被配置为，在所述第十四节点的电压的控制下，将来自所述第八时钟信号端的第八时钟信号传输至所述第三输出信号端，以打开对应的奇数行像素；
    第二移位寄存器子电路，包括第二补偿输入单元和第二扫描输出单元；其中，
    所述第二补偿输入单元与所述第十一节点、所述第七时钟信号端和第十五节点电连接，被配置为在所述第七时钟信号的控制下，将所述第十一节点的电压传输至所述第十五节点；
    所述第二扫描输出单元与所述第十五节点、第九时钟信号端和第四输出信号端电连接，所述第四输出信号端被配置为与偶数行像素电连接；所述第二扫描输出单元被配置为，在所述第十五节点的电压的控制下，将来自所述 第九时钟信号端的第九时钟信号传输至所述第四输出信号端，以打开对应的偶数行像素；
    其中，所述检测控制端与所述第十四节点或所述第十五节点电连接。
  12. 根据权利要求11所述的栅极驱动电路，其中，
    所述第一补偿输入单元包括第二十三晶体管，所述第二十三晶体管的控制极与所述第七时钟信号端电连接，第一极与所述第十一节点电连接，第二极与所述第十四节点电连接；
    所述第一扫描输出单元包括第二十四晶体管，所述第二十四晶体管的控制极与所述第十四节点电连接，第一端与所述第八时钟信号端电连接，第二极与所述第三输出信号端电连接；
    所述第二补偿输入单元包括第二十五晶体管，所述第二十五晶体管的控制极与所述第七时钟信号端电连接，第一极与所述第十一节点电连接，第二极与所述第十五节点电连接；
    所述第二扫描输出单元包括第二十六晶体管，所述第二十六晶体管的控制极与所述第十五节点电连接，第一极与所述第九时钟信号端电连接，第二极与所述第四输出信号端电连接。
  13. 根据权利要求11或12所述的栅极驱动电路，其中，
    所述第一移位寄存器子电路还包括第一扫描输入单元、第一反相器和第一复位单元；其中，
    所述第一扫描输入单元与所述第三输入信号端、所述第四电压信号端和所述第十四节点电连接，被配置为在所述第三输入信号的控制下，将所述第三电压信号传输至所述第十四节点；
    所述第一反相器的一端与所述第十四节点电连接，另一端与第十六节点电连接；
    所述第一复位单元与第一复位信号端、所述第十六节点、所述第五电压信号端、第十四节点和第三输出信号端电连接，被配置为在来自所述第一复位信号端的第一复位信号和所述第十六节点的电压的控制下，将所述第五电压信号端的第五电压信号传输至所述第十四节点和所述第三输出信号端；
    所述第二移位寄存器子电路还包括第二扫描输入单元、第二反相器和第二复位单元；
    所述第二扫描输入单元与所述第三输入信号端、所述第四电压信号端和所述第十五节点电连接，被配置为在所述第三输入信号的控制下，将所述第三电压信号传输至所述第十五节点；
    所述第二反相器的一端与所述第十五节点电连接，另一端与第十七节点电连接；
    所述第二复位单元与第二复位信号端、所述第五电压信号端、第十五节点、第十七节点和第四输出信号端电连接，被配置为在来自所述第二复位信号端的第二复位信号和所述第十七节点的电压的控制下，将所述第五电压信号传输至所述第十五节点和所述第四输出信号端。
  14. 根据权利要求13所述的栅极驱动电路，其中，
    所述第一扫描输入单元包括第二十七晶体管，所述第二十七晶体管的控制极与所述第三输入信号端电连接、第一极与所述第四电压信号端电连接，第二极与所述第十四节点电连接；
    所述第一复位单元包括第二十八晶体管、第二十九晶体管和第三十晶体管，所述第二十八晶体管的控制极与所述第一复位信号端电连接，第一极与所述第五电压信号端电连接，第二极与所述第十四节点电连接；所述第二十九晶体管的控制极与所述第十六节点电连接，第一极与所述第五电压信号端电连接，第二极与所述第三输出信号端电连接；第三十晶体管的控制极与所述第十六节点电连接，第一极与所述第五电压信号端电连接，第二极与所述第十四节点电连接；
    所述第二扫描输入单元包括第三十一晶体管，所述第三十一晶体管的控制极与所述第三输入信号端电连接，第一极与所述第四电压信号端电连接，第二极与所述第十四节点电连接；
    所述第二复位单元包括第三十二晶体管、第三十三晶体管和第三十四晶体管，所述第三十二晶体管的控制极与所述第二复位信号端电连接，第一极与所述第五电压信号端电连接，第二极与所述第十五节点电连接；所述第三十三晶体管的控制极与所述第十七节点电连接，第一极与所述第五电压信号端电连接，第二极与所述第四输出信号端电连接；所述第三十四晶体管的控制极与所述第十七节点电连接，第一极与所述第五电压信号端电连接，第二极与所述第十五节点电连接。
  15. 一种发光控制电路的控制方法，用于驱动如权利要求1～6中任一项所述的发光控制电路，所述发光控制电路的第一输出信号端与奇数行像素电连接，所述发光控制电路的第二输出信号端与偶数行像素电连接；
    一个帧周期包括显示阶段和空白阶段；
    在一组相邻的奇数行像素或偶数行像素被选中进行发光器件的补偿的情况下，在所述空白阶段，所述发光控制电路的第一发光控制子电路的第一检 测控制单元将第一电压信号传输至第一节点，所述第一发光控制子电路的第一输出单元在所述第一节点的电压的控制下，将所述第一电压信号传输至第一输出信号端，以使工作电流流经奇数行像素或偶数行像素的发光器件；或者，
    所述发光控制电路的第二发光控制子电路的第二检测控制单元将所述第一电压信号传输至第二节点，所述第二发光控制子电路的第二输出单元在所述第二节点的电压的控制下，将第一电压信号传输至第二输出信号端，以使工作电流流经所述奇数行像素或所述偶数行像素的发光器件。
  16. 根据权利要求15所述的控制方法，其中，所述第一发光控制子电路包括第一脉宽调制单元，第二发光控制子电路包括第二脉宽调制单元；
    在所述显示阶段，所述第一脉宽调制单元在第三时钟信号的控制下，将第一输入信号传输至所述第一节点；第一发光输出单元在所述第一节点的电压的控制下，将所述第一电压信号传输至所述第一输出信号端，以对所述奇数行像素和所述偶数行像素的发光时间进行调制；
    在一组相邻的奇数行像素或偶数行像素被选中进行发光器件的补偿的情况下，在所述空白阶段，所述第二检测控制单元将所述第一电压信号传输至第二节点，所述第二发光输出单元在所述第二节点的电压的控制下，将所述第一电压信号传输至第二输出信号端，以使工作电流流经奇数行像素或偶数行像素的发光器件；
    或者，
    在所述显示阶段，所述第二脉宽调制单元在第四时钟信号的控制下，将第二输入信号传输至所述第二节点；第二发光输出单元在所述第二节点的电压的控制下，将所述第一电压信号传输至所述第二输出信号端，以对所述奇数行像素和所述偶数行像素的发光时间进行调制；
    在一组相邻的奇数行像素或偶数行像素被选中进行发光器件的补偿的情况下，在所述空白阶段，所述第一检测控制单元将所述第一电压信号传输至第一节点，所述第一发光输出单元在所述第一节点的电压的控制下，将所述第一电压信号传输至所述第二输出信号端，以使工作电流流经奇数行像素或偶数行像素的发光器件。
  17. 根据权利要求16所述的控制方法，其中，
    在同一个帧周期，第一时钟信号端、第二输入信号端和第四时钟信号端输出脉冲信号，且第二时钟信号端、第一输入信号端和第三时钟信号端不输出电压信号；或者，
    在同一个帧周期，所述第二时钟信号端、所述第一输入信号端和所述第三时钟信号端输出脉冲信号，且所述第一时钟信号端、所述第二输入信号端和所述第四时钟信号端不输出电压信号。
  18. 一种栅极驱动电路的控制方法，被配置为驱动如权利要求7～14中任一项所述的栅极驱动电路；所述栅极驱动电路的发光控制电路的第一输出信号端与奇数行像素电连接，所述发光控制电路的第二输出信号端与偶数行像素电连接；
    一个帧周期包括显示阶段和空白阶段；
    在一组相邻的奇数行像素或偶数行像素被选中进行发光器件的补偿的情况下，
    在显示阶段，所述栅极驱动电路的随机检测电路在随机检测信号的控制下，将第三输入信号传输至随机检测电路中的电路节点，且维持对应电路节点电压至所述空白阶段；
    在所述空白阶段，所述随机检测电路在对应电路节点的电压的控制下，将第七时钟信号传输至所述栅极驱动电路的移位寄存器电路；所述移位寄存器电路向对应行像素输出扫描信号，以打开对应行像素；所述栅极驱动电路的发光控制电路在所述随机检测电路中的电路节点的电压或者所述移位寄存器电路中的电路节点的电压的控制下，将第一电压信号传输至第一输出信号端或第二输出信号端，以使工作电流流经所述奇数行像素或所述偶数行像素的发光器件。
  19. 根据权利要求18所述的控制方法，其中，所述移位寄存器电路包括第一移位寄存器子电路和第二移位寄存器子电路，所述第一移位寄存器子电路包括第一扫描输入单元和第一扫描输出单元，所述第二移位寄存器子电路包括第二扫描输入单元和第二扫描输出单元；所述发光控制电路的第一发光控制子电路包括第一脉宽调制单元，第二发光控制子电路包括第二脉宽调制单元；
    在所述显示阶段，
    所述第一扫描输入单元在第三输入信号的控制下，向第十四节点输入第四电压信号；所述第一扫描输出单元在所述第十四节点的电压的控制下，将第八时钟信号传输至所述第三输出信号端，以打开对应的奇数行像素；
    所述第二扫描输入单元在第三输入信号的控制下，向第十五节点输入所述第四电压信号；所述第二扫描输出单元在所述第十五节点的电压的控制下，将第九时钟信号传输至所述第四输出信号端，以打开对应的偶数行像素；
    所述第一脉宽调制单元在第三时钟信号的控制下，将来第一输入信号传输至所述第一节点，或者，所述第二脉宽调制单元在第四时钟信号的控制下，将第二输入信号传输至所述第二节点，以对所述奇数行像素和所述偶数行像素的发光时间进行调制。
  20. 一种显示面板的控制方法，其中，所述显示面板包括如权利要7～14中任一项所述的栅极驱动电路、数据驱动电路、奇数行像素和偶数行像素；所述栅极驱动电路的第一发光控制子电路与所述奇数行像素电连接，第二发光控制子电路与所述偶数行像素电连接；
    一个帧周期包括显示阶段和空白阶段，所述空白阶段包括第一数据写入阶段、第二数据写入阶段和感测阶段；
    在一组相邻的奇数行像素或偶数行像素被选中进行发光器件的补偿的情况下，
    在所述第一数据写入阶段，所述数据驱动电路向所述奇数行像素和所述偶数行像素中未被选中进行外部补偿的一者，写入零灰阶数据；
    在所述第二数据写入阶段，所述数据驱动电路向所述奇数行像素和所述偶数行像素中被选中进行发光器件的补偿的一者，写入感测灰阶数据；
    在所述感测阶段，所述第一发光控制子电路或所述第二发光控制子电路输出第一电压信号，以使工作电流流经所述奇数行像素和所述偶数行像素的发光器件；所述奇数行像素或所述偶数行像素的像素电路对所述发光器件的电压进行检测。
  21. 根据权利要求20所述的控制方法，其中，所述空白阶段还包括第一数据写回阶段和第二数据写回阶段；
    在所述第一数据写回阶段，所述奇数行像素和所述偶数行像素中未被选中进行发光器件的补偿的一者，写入第一初始灰阶数据；所述第一初始灰阶数据为在所述第一数据写入阶段之前，写入对应行像素的灰阶数据；
    在所述第二数据写回阶段，所述奇数行像素和所述偶数行像素中被选中进行发光器件的补偿的一者，写入第二初始灰阶数据；所述第二初始灰阶数据为在所述第二数据写入阶段之前，写入对应行像素的灰阶数据。
  22. 一种显示装置，包括如权利要求7～14中任一项所述的栅极驱动电路。
PCT/CN2022/088009 2022-04-20 2022-04-20 发光控制电路及其控制方法、栅极驱动电路及其控制方法 WO2023201589A1 (zh)

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