WO2023201581A1 - 显示面板及制作方法、显示装置 - Google Patents

显示面板及制作方法、显示装置 Download PDF

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Publication number
WO2023201581A1
WO2023201581A1 PCT/CN2022/087979 CN2022087979W WO2023201581A1 WO 2023201581 A1 WO2023201581 A1 WO 2023201581A1 CN 2022087979 W CN2022087979 W CN 2022087979W WO 2023201581 A1 WO2023201581 A1 WO 2023201581A1
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Prior art keywords
layer
hole
flexible layer
flexible
away
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PCT/CN2022/087979
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English (en)
French (fr)
Inventor
詹裕程
羊振中
张云鹏
景阳钟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000809.7A priority Critical patent/CN117280893A/zh
Priority to PCT/CN2022/087979 priority patent/WO2023201581A1/zh
Publication of WO2023201581A1 publication Critical patent/WO2023201581A1/zh

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  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method, and a display device.
  • the lower border of the display screen is affected by fanout wiring, etc., and the width of the lower border is usually wider than the width of the left and right borders.
  • the lower frame of the display screen can be reduced by redesigning the wiring, etc., but this method still needs to be perfected.
  • the purpose of this disclosure is to provide a display panel, a manufacturing method, and a display device that, while reducing the frame of the display panel, can help block the entry of external water vapor and avoid corrosion of components within the display panel, thereby ensuring the reliability of the display panel. sex.
  • a display panel which includes:
  • a signal line is provided between the first flexible layer and the second flexible layer.
  • a first through hole is provided in the second flexible layer. The first through hole exposes the signal line away from the third flexible layer. a surface of a flexible layer;
  • the orthographic projection on the first flexible layer is located within the orthographic projection of the first through hole on the first flexible layer, and the second through hole exposes the signal line away from the first flexible layer.
  • the first conductive layer includes a transfer line that covers at least the sidewall of the second through hole and the surface of the signal line exposed by the second through hole.
  • the display panel further includes:
  • An insulating layer is provided on a side of the inorganic layer away from the first flexible layer, a third through hole is provided in the insulating layer, and the third through hole and the second through hole penetrate;
  • the orthographic projection of the second through hole on the first flexible layer is located within the orthographic projection of the third through hole on the first flexible layer;
  • the second through hole has a second hole wall
  • the third through hole has a third hole wall
  • the second hole wall and the third hole wall are connected to each other to form a through hole wall
  • the through hole wall at least Has a step portion.
  • the display panel further includes:
  • An insulating layer is provided on a side of the inorganic layer away from the first flexible layer, a third through hole is provided in the insulating layer, and the third through hole and the second through hole penetrate;
  • the orthographic projection of the second through hole on the first flexible layer is located within the orthographic projection of the third through hole on the first flexible layer;
  • the second through hole has a second hole wall
  • the third through hole has a third hole wall, an end of the second hole wall away from the first flexible layer and the third hole wall is close to the first flexible layer.
  • a first spacing parallel to the direction of the first flexible layer is provided between one end of a flexible layer, and the first spacing is greater than or equal to 0;
  • the transfer line covers at least part of the surface of the insulating layer away from the first flexible layer, and at least covers the second hole wall and the third hole wall.
  • the insulating layer includes a first gate insulating layer, and the first gate insulating layer is provided with the third through hole;
  • the first conductive layer also includes a gate of the transistor and a first plate of the capacitor
  • the transfer line covers at least part of the surface of the first gate insulating layer away from the first flexible layer.
  • the insulating layer includes a first gate insulating layer and a second gate insulating layer sequentially arranged in a direction away from the first flexible layer, and the first gate insulating layer and the The third through hole is provided in the second gate insulating layer;
  • the first conductive layer includes a second plate of the capacitor
  • the transfer line covers at least part of the surface of the second gate insulation layer away from the first flexible layer.
  • the third through hole includes a first sub-through hole and a second sub-through hole
  • the first gate insulating layer is provided with the first sub-via hole, and the second gate insulating layer is provided with the second sub-via hole;
  • the orthographic projection of the first sub-via hole on the first flexible layer is located within the orthographic projection of the second sub-via hole on the first flexible layer;
  • the first sub-hole has a first sub-hole wall
  • the second sub-hole has a second sub-hole wall
  • an end of the first sub-hole wall away from the first flexible layer is connected to the second sub-hole wall.
  • a second spacing parallel to the direction of the first flexible layer is provided between one end of the hole wall close to the first flexible layer, and the second spacing is greater than or equal to 0.
  • the display panel further includes:
  • An active layer is provided between the inorganic layer and the insulating layer;
  • An interlayer dielectric layer is provided on the side of the first conductive layer away from the first flexible layer;
  • a third conductive layer is provided on the side of the interlayer dielectric layer away from the first flexible layer.
  • the third conductive layer includes the source and drain of the transistor, and the source and drain are connected to the active layer; and the third conductive layer is connected to the transfer line;
  • the signal line is used to provide power supply voltage to the pixel circuit.
  • the display panel further includes:
  • the signal line is provided on a side of the buffer layer close to the first flexible layer, or
  • the signal line is provided on a side of the buffer layer away from the first flexible layer.
  • the first spacing is not less than 3 ⁇ m, and/or the second spacing is not less than 3 ⁇ m.
  • a method for manufacturing a display panel including:
  • An inorganic layer is formed on a side of the second flexible layer away from the first flexible layer, and the inorganic layer covers a surface of the second flexible layer away from the first flexible layer and a side of the first through hole. wall;
  • first conductive layer including a transfer line
  • a second through hole is formed in the inorganic layer, and the orthographic projection of the second through hole on the first flexible layer is located between the orthographic projection of the first through hole on the first flexible layer. inside, and the second through hole exposes the signal line away from the surface of the first flexible layer;
  • the transfer line at least covers the side wall of the second through hole and the surface of the signal line exposed by the second through hole.
  • the method before forming the first conductive layer, the method further includes:
  • a third through hole is formed in the insulating layer, the insulating layer covers at least part of the surface of the inorganic layer, and the third through hole and the second through hole penetrate;
  • the orthographic projection of the second through hole on the first flexible layer is located within the orthographic projection of the third through hole on the first flexible layer;
  • the second through hole has a second hole wall
  • the third through hole has a third hole wall, an end of the second hole wall away from the first flexible layer and the third hole wall is close to the first flexible layer.
  • a first spacing parallel to the direction of the first flexible layer is provided between one end of a flexible layer, and the first spacing is greater than or equal to 0;
  • the transfer line covers at least part of the surface of the insulating layer away from the first flexible layer, and at least covers the second hole wall and the third hole wall.
  • forming an insulating layer on a side of the inorganic layer away from the first flexible layer includes:
  • first gate insulating layer Forming a first gate insulating layer on a side of the inorganic layer away from the first flexible layer, the first gate insulating layer covering at least part of the surface of the inorganic layer away from the first flexible layer;
  • a second gate insulating layer is formed on a side of the first gate insulating layer away from the first flexible layer, and the second gate insulating layer covers at least a portion of the first gate insulating layer away from the first flexible layer. surface;
  • a first sub-via hole is formed in the first gate insulating layer
  • a second sub-via hole is formed in the second gate insulating layer
  • the first sub-via hole and the second sub-via hole form the third through hole
  • the orthographic projection of the second through hole on the first flexible layer is located within the orthographic projection of the first sub through hole on the first flexible layer, and the first sub through hole is on the first flexible layer.
  • the orthographic projection on a flexible layer is located within the orthographic projection of the second sub-via on the first flexible layer;
  • the first sub-hole has a first sub-hole wall
  • the second sub-hole has a second sub-hole wall
  • an end of the first sub-hole wall away from the first flexible layer is connected to the second sub-hole wall.
  • a second spacing parallel to the direction of the first flexible layer is provided between one end of the hole wall close to the first flexible layer, and the second spacing is greater than or equal to 0.
  • a display device including the display panel as described in the first aspect.
  • the signal line is arranged between the first flexible layer and the second flexible layer, which helps to reduce the width of the lower frame of the display panel.
  • the inorganic layer covers the surface of the second flexible layer away from the first flexible layer and the sidewall of the first through hole, that is, the second flexible layer is wrapped. This structural design helps to reduce the frame of the display panel while also helping to block the The entry of external water vapor prevents corrosion of the components within the display panel to ensure the reliability of the display panel.
  • Figure 1 is a schematic structural diagram of a display panel in an exemplary embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • Figure 3 is a schematic structural diagram of a display panel in yet another exemplary embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of a display panel in yet another exemplary embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of a display panel in yet another exemplary embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of a display panel in yet another exemplary embodiment of the present disclosure.
  • Figure 7 is a schematic diagram of a first through hole structure formed in an exemplary embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of forming second through holes and third through holes in an exemplary embodiment of the present disclosure
  • Figure 9 is a schematic structural diagram of forming second through holes and third through holes in another exemplary embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of forming second through holes and third through holes in yet another exemplary embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of forming second through holes and third through holes in yet another exemplary embodiment of the present disclosure.
  • Figure 12 is a schematic structural diagram of forming a second through hole, a first sub-through hole, and a second sub-through hole in an exemplary embodiment of the present disclosure
  • Figure 13 is a schematic structural diagram of forming a second through hole, a first sub-through hole, and a second sub-through hole in another exemplary embodiment of the present disclosure
  • FIG. 14 is a schematic flowchart of a display panel manufacturing method in an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the present disclosure.
  • a structure When a structure is "on" another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” placed on the other structure, or that the structure is “indirectly” placed on the other structure through another structure. on other structures.
  • the lower border of the display screen is affected by fanout wiring, etc.
  • the width of the lower border is usually wider than the width of the left and right borders.
  • the signal line is provided with two flexible layers of polyimide (Polyimide, PI) layers, such as between the first flexible layer and the second flexible layer, and is provided in the drive circuit layer located above the two flexible layers.
  • the transfer hole exposes the signal line, and a transfer metal layer is formed in the transfer hole to transmit the power supply voltage.
  • the transfer metal layer formed in the transfer hole is usually in direct contact with the second flexible layer, and external water vapor will enter along the second flexible layer, affecting the reliability of the display screen.
  • an embodiment of the present disclosure provides a display panel, including a first flexible layer 120, a signal line 10, a second flexible layer 140, an inorganic layer 150 and a first conductive layer 230.
  • the second flexible layer 140 is provided on one side of the first flexible layer 120; the signal line 10 is provided between the first flexible layer 120 and the second flexible layer 140, and a first through hole 141 is provided in the second flexible layer 140.
  • the first through hole 141 exposes the surface of the signal line 10 away from the first flexible layer 120; the inorganic layer 150 covers the surface of the second flexible layer 140 away from the first flexible layer 120 and the sidewall of the first through hole 141, in the inorganic layer 150
  • a second through hole 151 is provided, the orthographic projection of the second through hole 151 on the first flexible layer 120 is within the orthographic projection of the first through hole 141 on the first flexible layer 120, and the second through hole 151 exposes signals.
  • the wire 10 is away from the surface of the first flexible layer 120; the first conductive layer 230 includes a transfer wire 231, which at least covers the sidewalls of the second through hole 151 and the surface of the signal line 10 exposed by the second through hole 151.
  • the signal line 10 is arranged between the first flexible layer 120 and the second flexible layer 140, which helps to reduce the width of the lower frame of the display panel.
  • the inorganic layer 150 covers the surface of the second flexible layer 140 away from the first flexible layer 120 and the sidewall of the first through hole 141, that is, the second flexible layer 140 is wrapped. This structural design reduces the display panel frame while , helps to block the entry of external water vapor and avoid corrosion of the components within the display panel, thereby ensuring the reliability of the display panel.
  • the present disclosure provides a display panel, which may be an organic light-emitting diode (OLED) display panel, such as an AMOLED (Active-matrix organic light-emitting diode, active matrix organic light-emitting diode) display panel. It can also be a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display panel, a micro light emitting diode (Micro Light Emitting Diodes, Micro LED) display panel, etc. This disclosure does not specifically limit this.
  • OLED organic light-emitting diode
  • AMOLED Active-matrix organic light-emitting diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED Micro Light Emitting Diodes
  • the display panel includes a first flexible layer 120 , a signal line 10 , a second flexible layer 140 , an inorganic layer 150 and a first conductive layer 230 .
  • the first flexible layer 120 , the second flexible layer 140 and the inorganic layer 150 may form the base substrate of the display panel, and the second flexible layer 140 is provided on one side of the first flexible layer 120 .
  • the material of the first flexible layer 120 and the second flexible layer 140 may include polyimide (PI).
  • the display panel further includes a buffer layer 130 disposed between the first flexible layer 120 and the second flexible layer 140.
  • the material of the buffer layer 130 may include inorganic materials, and the buffer layer 130 may be formed between the first flexible layer 120 and the second flexible layer 140.
  • the flexible layer 120 and the second flexible layer 140 have good adhesion.
  • the signal line 10 is provided between the first flexible layer 120 and the second flexible layer 140 .
  • the signal line 10 can be disposed on the side of the buffer layer 130 close to the first flexible layer 120 , or can be disposed on the side of the buffer layer 130 away from the first flexible layer 120 , which is not limited in this disclosure.
  • the signal line 10 is provided on a side of the buffer layer 130 away from the first flexible layer 120 .
  • a first through hole 141 is provided in the second flexible layer 140 , and the first through hole 141 exposes the surface of the signal line 10 away from the first flexible layer 120 .
  • the inorganic layer 150 covers the surface of the second flexible layer 140 away from the first flexible layer 120 and the sidewall of the first through hole 141, specifically in contact with the sidewall of the second flexible layer 140 at the position of the first through hole 141, thereby connecting the second flexible layer 140 to the sidewall of the first through hole 141.
  • the two flexible layers 140 are wrapped to prevent external water vapor from entering the first through hole 141 along the second flexible layer 140 .
  • a second through hole 151 is provided in the inorganic layer 150.
  • the orthographic projection of the second through hole 151 on the first flexible layer 120 is within the orthographic projection of the first through hole 141 on the first flexible layer 120, and the second through hole 151 is disposed in the inorganic layer 150.
  • the hole 151 exposes the surface of the signal line 10 away from the first flexible layer 120 . That is, the second through hole 151 penetrates the first through hole 141 to expose the surface of the signal line 10 away from the first flexible layer 120 .
  • the first conductive layer 230 includes an adapter wire 231 connected to the signal line 10 .
  • the adapter wire 231 at least covers the side wall of the second through hole 151 and the surface of the signal line 10 exposed by the second through hole 151 .
  • the first conductive layer 230 may include metal materials or alloy materials to ensure good conductive properties.
  • the first conductive layer 230 can also be made of transparent conductive materials, such as ITO (indium tin oxide), IZO (indium zinc oxide), etc.
  • the inorganic layer 150 is blocked between the adapter wire 231 and the second flexible layer 140. This structure helps to prevent external water vapor from penetrating into the adapter wire 231 along the second flexible layer 140 and prevents damage to the adapter wire 231 and other devices. corrosion.
  • the display panel further includes an insulating layer 220 , which is provided on a side of the inorganic layer 150 away from the first flexible layer 120 .
  • the insulating layer 220 may be a single film layer such as silicon nitride, silicon oxide, or aluminum oxide, or a multi-film layer formed by a combination thereof.
  • a third through hole 2200 is provided in the insulating layer 220, and the third through hole 2200 and the second through hole 151 pass through; and the orthographic projection of the second through hole 151 on the first flexible layer 120 is located at the position of the third through hole 2200 on the first flexible layer 120. within the orthographic projection on the flexible layer 120.
  • the surface of the signal line 10 away from the first flexible layer 120 is exposed by the second through hole 151 and the third through hole 2200 .
  • the diameter of the second through hole 151 is smaller than or equal to the diameter of the third through hole 2200 .
  • the total penetration depth of the third through hole 2200 and the second through hole 151 may be 5-8 ⁇ m.
  • the second through hole 151 has a second hole wall 51H
  • the third through hole 2200 has a third hole wall 00H.
  • the second hole wall 51H and the third hole wall 00H are connected to each other to form a through-hole wall.
  • the through-hole wall has at least a step portion, which can buffer the adapter wire 231 to avoid it. Breakage occurs.
  • a first hole parallel to the direction of the first flexible layer 120 is provided between an end of the second hole wall 51H away from the first flexible layer 120 and an end of the third hole wall 00H close to the first flexible layer 120 .
  • the distance L1, the first distance L1 is greater than or equal to 0.
  • the adapter wire 231 covers at least part of the surface of the insulating layer 220 away from the first flexible layer 120 , and at least covers the second hole wall 51H and the third hole wall 00H.
  • the end of the second hole wall 51H away from the first flexible layer 120 is the intersection line between the surface of the inorganic layer 150 away from the first flexible layer 120 and the edge of the second through hole 151 .
  • the third hole wall The end of OOH close to the first flexible layer 120 is the boundary line between the surface of the insulating layer 220 close to the first flexible layer 120 and the edge of the third through hole 2200 .
  • the surface of the insulating layer 220 close to the first flexible layer 120 is in contact with the surface of the inorganic layer 150 away from the first flexible layer 120 .
  • the adapter wire 231 located in the third through hole 2200 and the second through hole 151 covers the third hole wall 00H, the second hole wall 51H and the surface of the signal line 10 exposed by the second through hole 151 .
  • the first distance L1 is approximately equal to 0, and the end of the second hole wall 51H away from the first flexible layer 120 and the third hole wall 00H are close to the first flexible layer 120.
  • One end of the flexible layer 120 overlaps, and the second hole wall 51H and the third hole wall 00H are generally connected to form a smooth side wall.
  • the first distance L1 is greater than 0, and the end of the second hole wall 51H away from the first flexible layer 120 and the third hole wall 00H are close to the first flexible layer 120.
  • One end of the flexible layer 120 does not overlap, and the third hole wall 00H, the surface of the inorganic layer 150 away from the first flexible layer 120 and the second hole wall 51H can be connected to form at least one step portion.
  • the adapter wire 231 located in the third through hole 2200 and the second through hole 151 covers the third hole wall 00H and the part of the inorganic layer 150 away from the first flexible layer 120
  • the surface that is, the surface of the inorganic layer 150 corresponding to the first spacing L1, as well as the surface of the second hole wall 51H and the signal line 10 exposed by the second through hole 151.
  • the adapter wire 231 located in the third through hole 2200 and the second through hole 151 is less likely to break during production due to the buffering of the step portion.
  • the first distance L1 is not less than 3 ⁇ m. Specifically, it can be 3 ⁇ m, 3.1 ⁇ m, 3.2 ⁇ m, 3.3 ⁇ m, 3.4 ⁇ m, 3.5 ⁇ m, 3.6 ⁇ m, 3.7 ⁇ m, 3.8 ⁇ m, 3.9 ⁇ m or 4 ⁇ m, but is not limited thereto. In actual applications, it can be set according to needs.
  • the display panel further includes an active layer 210 , and the active layer 210 is provided between the inorganic layer 150 and the insulating layer 220 .
  • the material of the active layer 210 may be polysilicon or IGZO (Indium Gallium Zinc Oxide), which can change the conductive properties at different locations through processes such as doping.
  • the insulating layer 220 may include one layer, two layers, or a multi-layer structure, and the details may be set according to actual conditions. Different arrangements of the insulating layer 220 of the present disclosure will be described in detail below with reference to specific embodiments.
  • the insulating layer 220 includes a first gate insulating layer 221 , and the first gate insulating layer 221 is provided with a third through hole 2200 .
  • the first gate insulation layer 221 is located between the active layer 210 and the first conductive layer 230 .
  • the first conductive layer 230 also includes a gate electrode of the transistor and a first plate of the capacitor.
  • the transfer line 231 covers at least part of the surface of the first gate insulation layer 221 away from the first flexible layer 120 . In this type of embodiment, the transfer line 231 covers the third hole wall 00H, and the third hole wall 00H is the sidewall of the first gate insulating layer 221 at the position of the third through hole 2200 .
  • the display panel further includes a second gate insulating layer 222, a second conductive layer (not shown in the figure), an interlayer dielectric layer ILD and a third conductive layer 250.
  • the second gate insulating layer 222 is provided on the side of the first conductive layer 230 away from the first flexible layer 120 , and the second gate insulating layer 222 covers the surfaces of the first conductive layer 230 and the first gate insulating layer 221 .
  • the second conductive layer is disposed on the surface of the second gate insulating layer 222 away from the first flexible layer 120 , and the second conductive layer includes the second plate of the capacitor.
  • the interlayer dielectric layer ILD is disposed on the side of the second conductive layer away from the first flexible layer 120 , and the interlayer dielectric layer ILD covers the second conductive layer and the second gate insulating layer 222 .
  • the third conductive layer 250 is provided on the side of the interlayer dielectric layer ILD away from the first flexible layer 120.
  • the third conductive layer 250 includes the source and drain of the transistor, and the source and drain are connected to the active layer 210; and
  • the three conductive layers 250 are connected to the transfer wire 231 and further to the signal line 10.
  • the signal line 10 can be used to provide a power supply voltage signal to the pixel circuit, thereby applying the power supply voltage signal to the source or drain of the transistor.
  • the insulating layer 220 includes a first gate insulating layer 221 and a first gate insulating layer 221 that are sequentially arranged in a direction away from the first flexible layer 120 .
  • a third through hole 2200 is provided in the second gate insulating layer 222, the first gate insulating layer 221 and the second gate insulating layer 222.
  • the first gate insulation layer 221 covers the active layer 210 .
  • the first conductive layer 230 includes the second plate of the capacitor.
  • the first conductive layer 230 is provided on the side of the second gate insulating layer 222 away from the first flexible layer 120 , and the adapter wire 231 covers at least part of the surface of the second gate insulating layer 222 away from the first flexible layer 120 .
  • the transfer line 231 covers the third hole wall 00H, which is the sidewall of the first gate insulating layer 221 and the second gate insulating layer 222 at the position of the third through hole 2200 .
  • the display panel also includes a second conductive layer 240, an interlayer dielectric layer ILD, and a third conductive layer 250.
  • the second conductive layer 240 is disposed between the first gate insulating layer 221 and the second gate insulating layer 222 , and the second gate insulating layer 222 covers the second conductive layer 240 and the first gate insulating layer 221 .
  • the second conductive layer 240 includes the gate of the transistor and the first plate of the capacitor.
  • the interlayer dielectric layer ILD is provided on the side of the first conductive layer 230 away from the first flexible layer 120 , and the interlayer dielectric layer ILD covers the first conductive layer 230 and the second gate insulating layer 222 .
  • the third conductive layer 250 is provided on the side of the interlayer dielectric layer ILD away from the first flexible layer 120.
  • the third conductive layer 250 includes the source and drain of the transistor, and the source and drain are connected to the active layer 210; and
  • the three conductive layers 250 are connected to the transfer wire 231 and further to the signal line 10.
  • the signal line 10 can be used to provide a power supply voltage signal to the pixel circuit, thereby applying the power supply voltage signal to the source or drain of the transistor.
  • the third via hole 2200 includes a first sub-via hole 2211 and a second sub-via hole 2221; the first gate insulation layer 221 is provided with The first sub-via hole 2211 and the second sub-via hole 2221 are provided in the second gate insulation layer 222; the orthographic projection of the first sub-via hole 2211 on the first flexible layer 120 is located on the second sub-via hole 2221 on the first flexible layer 120.
  • the first sub-hole 2211 has a first sub-hole wall 11H
  • the second sub-hole 2221 has a second sub-hole wall 21H
  • the first sub-hole wall 11H is away from the first flexible layer 120
  • a second spacing L2 parallel to the direction of the first flexible layer 120 is provided between one end and the end of the second sub-hole wall 21H close to the first flexible layer 120 , and the second spacing L2 is greater than or equal to 0.
  • the end of the first sub-hole wall 11H away from the first flexible layer 120 is the intersection line between the surface of the first gate insulating layer 221 away from the first flexible layer 120 and the edge of the first sub-via 2211, and the second end of the first sub-hole wall 11H away from the first flexible layer 120.
  • One end of the sub-hole wall 21H close to the first flexible layer 120 is the boundary line between the surface of the second gate insulating layer 222 close to the first flexible layer 120 and the edge of the second sub-via 2221, where the first gate insulating layer 221 is away from the first
  • the surface of the flexible layer 120 is in contact with the surface of the second gate insulating layer 222 close to the first flexible layer 120 .
  • the adapter line 231 located in the third through hole 2200 and the second through hole 151 covers the second sub-hole wall 21H, the first sub-hole wall 11H, the second hole wall 51H and the signal line 10 is covered by the second through hole 151 Exposed surfaces.
  • the second distance L2 is approximately equal to 0, and the end of the first sub-hole wall 11H away from the first flexible layer 120 and the second sub-hole wall 21H are close to the first flexible layer 120 .
  • One end of the layer 120 overlaps, and the first sub-hole wall 11H and the second sub-hole wall 21H are generally connected to form a smooth side wall.
  • the second distance L2 is greater than 0, and the end of the first sub-hole wall 11H away from the first flexible layer 120 and the second sub-hole wall 21H are close to the first flexible layer 120 .
  • One end of the layer 120 does not overlap, and the first sub-hole wall 11H, the surface of the first gate insulation layer 221 away from the first flexible layer 120 and the second sub-hole wall 21H can be connected to form at least one step portion.
  • the transfer line 231 located in the first sub-via hole 2211 and the second sub-via hole 2221 covers the second sub-hole wall 21H, and the first gate insulation layer 221 is away from the first flexible layer.
  • the first sub-hole wall 11H and the second sub-hole wall 21H form a step portion, which can further buffer the formation of the transfer line 231 and help further reduce the risk of the transfer line 231 passing through. Possibility of breakage in the hole due to excessive depth of the hole.
  • the second distance L2 is not less than 3 ⁇ m. Specifically, it can be 3 ⁇ m, 3.1 ⁇ m, 3.2 ⁇ m, 3.3 ⁇ m, 3.4 ⁇ m, 3.5 ⁇ m, 3.6 ⁇ m, 3.7 ⁇ m, 3.8 ⁇ m, 3.9 ⁇ m or 4 ⁇ m, but is not limited thereto. In actual applications, it can be set according to needs.
  • the display panel further includes a passivation layer PVX, a first planarization layer PLN1 , a fourth conductive layer 260 and a second planarization layer PLN2 .
  • the passivation layer PVX is disposed on the side of the third conductive layer 250 away from the first flexible layer 120 , and the passivation layer PVX covers the third conductive layer 250 and the interlayer dielectric layer ILD.
  • the first planarization layer PLN1 is provided on the side of the passivation layer PVX away from the first flexible layer 120 , and the first passivation layer PVX covers the passivation layer PVX.
  • the fourth conductive layer 260 is provided on the side of the first planarization layer PLN1 away from the first flexible layer 120 , and the fourth conductive layer 260 is connected to the third conductive layer 250 through via holes.
  • the display panel also includes a second planarization layer PLN2, a light-emitting layer and a spacer 400.
  • the second planarization layer PLN2 is provided on the side of the fourth conductive layer 260 away from the first flexible layer 120.
  • the second planarization layer PLN2 covers the fourth conductive layer 260.
  • the light-emitting layer is provided on the side of the second planarization layer PLN2 away from the first flexible layer 120 .
  • the light-emitting layer includes a pixel definition layer 310 and a plurality of light-emitting devices.
  • the spacer 400 is provided on a side of the pixel definition layer 310 away from the first flexible layer 120 .
  • the pixel definition layer 310 is provided on the side of the second planarization layer PLN2 away from the first flexible layer 120 .
  • the pixel definition layer 310 may be provided with a plurality of openings, and the range defined by each opening is the range of a light-emitting device.
  • the shape of the opening that is, the shape of the outline of the orthographic projection of the opening on the first flexible layer 120, may be a polygon, a smooth closed curve, or other shapes, and is not specifically limited here.
  • the light-emitting device can be connected to the fourth conductive layer 260 and can emit light under the driving of the driving circuit.
  • the light-emitting device may include a first electrode 320 , a light-emitting functional layer 330 and a second electrode sequentially stacked in a direction away from the first flexible layer 120 .
  • the first electrode 320 may be an anode
  • the second electrode may be a cathode.
  • the structure of the light-emitting device is a conventional structure in the art and will not be described in detail here.
  • the present disclosure also provides a method for manufacturing a display panel, including:
  • Step S100 forming the first flexible layer 120
  • Step S200 forming the signal line 10 on one side of the first flexible layer 120;
  • Step S300 forming a second flexible layer 140 on the side of the signal line 10 away from the first flexible layer 120;
  • Step S400 forming a first through hole 141 in the second flexible layer 140.
  • the first through hole 141 exposes the surface of the signal line 10 away from the first flexible layer 120;
  • Step S500 forming an inorganic layer 150 on the side of the second flexible layer 140 away from the first flexible layer 120.
  • the inorganic layer 150 covers the surface of the second flexible layer 140 away from the first flexible layer 120 and the sidewall of the first through hole 141;
  • Step S600 forming a first conductive layer 230.
  • the first conductive layer 230 includes a transfer line 231;
  • the second through hole 151 is formed in the inorganic layer 150
  • the orthographic projection of the second through hole 151 on the first flexible layer 120 is located within the orthographic projection of the first through hole 141 on the first flexible layer 120
  • the third through hole 151 is formed in the inorganic layer 150.
  • the two through holes 151 expose the surface of the signal line 10 away from the first flexible layer 120; the adapter wire 231 at least covers the side walls of the second through hole 151 and the surface of the signal line 10 exposed by the second through hole 151.
  • the first through hole 141 is formed in the second flexible layer 140 and then the inorganic layer 150 is formed, so that the formed inorganic layer 150 can respond to the second through hole 141 at the position of the first through hole 141 .
  • the flexible layer 140 wraps it, so that the inorganic layer 150 is used to block the entry of external water vapor and avoid corrosion of the devices in the display panel.
  • step S100 it may also include providing a hard base substrate 110, and the material of the hard base substrate 110 may be glass or the like.
  • the first flexible layer 120 may be formed on one side of the hard base substrate 110.
  • step S600 also includes:
  • Step S501 forming an insulating layer 220 on the side of the inorganic layer 150 away from the first flexible layer 120.
  • a third through hole 2200 is formed in the insulating layer 220 , the insulating layer 220 covers at least part of the surface of the inorganic layer 150 , and the third through hole 2200 and the second through hole 151 pass through.
  • the orthographic projection of the second through hole 151 on the first flexible layer 120 is located within the orthographic projection of the third through hole 2200 on the first flexible layer 120 .
  • the second through hole 151 has a second hole wall 51H
  • the third through hole 2200 has a third hole wall 00H, an end of the second hole wall 51H away from the first flexible layer 120 and an end of the third hole wall 00H close to the first flexible layer 120
  • a first spacing L1 parallel to the direction of the first flexible layer 120 is provided between one end, and the first spacing L1 is greater than or equal to 0.
  • the adapter wire 231 covers at least part of the surface of the insulating layer 220 away from the first flexible layer 120, and at least covers the second hole wall 51H and the third hole wall 00H.
  • the insulating layer 220 formed may include a single layer or a multi-layer structure. Detailed description will be given below with reference to different embodiments.
  • step S501 includes:
  • a first gate insulating layer 221 is formed on a side of the inorganic layer 150 away from the first flexible layer 120 .
  • the first gate insulating layer 221 covers at least part of the surface of the inorganic layer 150 away from the first flexible layer 120 .
  • a third through hole 2200 is formed in the first gate insulation layer 221 ; the transfer line 231 covers at least part of the surface of the first gate insulation layer 221 away from the first flexible layer 120 .
  • the third through hole 2200 in the first gate insulating layer 221 and the second through hole 151 in the inorganic layer 150 may be formed using a single etching process or a divided etching process.
  • the third through hole 2200 and the second through hole 151 may be formed using one etching process.
  • an etching process is used to simultaneously etch the first gate insulating layer 221 and the inorganic layer 150 to form a third gate insulating layer 221 in the first gate insulating layer 221 .
  • the three through holes 2200 form the second through holes 151 in the inorganic layer 150 .
  • step S600 is performed to form the first conductive layer 230
  • the display panel as shown in FIG. 1 can be formed.
  • the structure of the display panel may refer to the description in the above embodiments and will not be described in detail here.
  • the third through hole 2200 and the second through hole 151 are formed using different etching processes.
  • a first etching process may be used to form the third through hole 2200 in the first gate insulating layer 221 , and then a second etching process may be used.
  • the etching process forms a second through hole 151 in the inorganic layer 150 , and the diameter of the second through hole 151 may be smaller than the diameter of the third through hole 2200 .
  • step S600 is performed to form the first conductive layer 230
  • the display panel as shown in FIG. 3 can be formed.
  • the structure of the display panel may refer to the description in the above embodiments and will not be described in detail here.
  • step S501 includes:
  • Step S5011 forming a first gate insulating layer 221 on the side of the inorganic layer 150 away from the first flexible layer 120.
  • the first gate insulating layer 221 covers at least part of the surface of the inorganic layer 150 away from the first flexible layer 120;
  • Step S5012 forming a second gate insulating layer 222 on the side of the first gate insulating layer 221 away from the first flexible layer 120.
  • the second gate insulating layer 222 covers at least part of the surface of the first gate insulating layer 221 away from the first flexible layer 120. .
  • the third through hole 2200 is provided in the first gate insulation layer 221 and the second gate insulation layer 222 ; the transfer line 231 covers at least part of the surface of the second gate insulation layer 222 away from the first flexible layer 120 .
  • the third through hole 2200 in the first gate insulating layer 221 and the second gate insulating layer 222 and the second through hole 151 in the inorganic layer 150 may be formed using a one-time etching process, or may be formed using separate etching processes. Formed by secondary etching process.
  • the third through hole 2200 and the second through hole 151 may be formed using one etching process.
  • an etching process is used to simultaneously etch the second gate insulating layer 222 , the first gate insulating layer 221 and the inorganic layer 150 to form the second gate insulating layer 222 .
  • the third through hole 2200 is formed in the gate insulating layer 222 and the first gate insulating layer 221
  • the second through hole 151 is formed in the inorganic layer 150 .
  • step S600 is performed to form the first conductive layer 230
  • the display panel as shown in FIG. 2 can be formed.
  • the structure of the display panel may refer to the description in the above embodiments and will not be described in detail here.
  • the third through hole 2200 and the second through hole 151 are formed using different etching processes.
  • an etching process can be used to form the third through hole 2200 in the second gate insulating layer 222 and the first gate insulating layer 221 , and then using Another etching process forms a second through hole 151 in the inorganic layer 150.
  • the diameter of the second through hole 151 may be smaller than the diameter of the third through hole 2200.
  • step S600 is performed to form the first conductive layer 230
  • the display panel as shown in FIG. 4 can be formed.
  • the structure of the display panel may refer to the description in the above embodiments and will not be described in detail here.
  • a first sub-via hole 2211 is formed in the first gate insulation layer 221
  • a second sub-via hole 2221 is formed in the second gate insulation layer 222
  • the first sub-via hole 2211 and the second sub-via hole are formed in the second gate insulation layer 222.
  • the orthographic projection of the second through hole 151 on the first flexible layer 120 is located within the orthographic projection of the first sub through hole 2211 on the first flexible layer 120, and the first sub through hole 2211 is within The orthographic projection on the first flexible layer 120 is located within the orthographic projection of the second sub-via hole 2221 on the first flexible layer 120; the first sub-via hole 2211 has a first sub-hole wall 11H, and the second sub-via hole 2221 has Between the second sub-hole wall 21H, the end of the first sub-hole wall 11H away from the first flexible layer 120 and the end of the second sub-hole wall 21H close to the first flexible layer 120, there is a third hole parallel to the direction of the first flexible layer 120.
  • the second distance L2 is greater than or equal to 0.
  • the first sub-via hole 2211 in the first gate insulating layer 221 and the second sub-via hole 2221 in the second gate insulating layer 222 may be formed using a one-time etching process, or may be formed using multiple etching processes. Formed by etching process.
  • the first sub-via hole 2211 and the second sub-via hole 2221 can be formed using one etching process.
  • a structure as shown in Figure 10 or Figure 11 can be formed. It should be noted here that when the first spacing L1 is also equal to 0, the second sub-via hole 2221, the first sub-via hole 2211 and the second via hole 151 can be formed using one etching process. The specific formation is as shown in Figure 10 the structure shown.
  • the first sub-via hole 2211 and the second sub-via hole 2221 can be formed using two etching processes. Specifically, a structure as shown in Figure 12 or Figure 13 can be formed. For example, as shown in FIG. 13 , when the first spacing L1 is also greater than 0, after the second gate insulating layer 222 is formed, an etching process can be used to form a second sub-via hole in the second gate insulating layer 222 . 2221, another etching process is used to form the first sub-via hole 2211 in the first gate insulating layer 221. The aperture of the first sub-via hole 2211 is smaller than the aperture of the second sub-via hole 2221, and then another etching process is used.
  • a second through hole 151 is formed in the inorganic layer 150 , and the diameter of the second through hole 151 is smaller than the diameter of the first sub-through hole 2211 .
  • the display panel as shown in FIG. 6 can be formed.
  • the structure of the display panel may refer to the description in the above embodiments and will not be described in detail here.
  • the first sub-via hole 2211 and the second through-hole 151 can be formed using one etching process. Specifically, after the second gate insulating layer 222 is formed, one etching process can be used to form the second sub-via 2221 in the second gate insulating layer 222 , and another etching process can be used to simultaneously etch the first gate insulating layer 221 and the inorganic layer 150. A first sub-via hole 2211 is formed in the first gate insulating layer 221, and a second via hole 151 is formed in the inorganic layer 150. Specifically, a structure as shown in FIG. 12 can be formed. In this embodiment, after step S600 is performed to form the first conductive layer 230, the display panel as shown in FIG. 5 can be formed. The structure of the display panel may refer to the description in the above embodiments and will not be described in detail here.
  • neither the first distance L1 nor the second distance L2 is less than 3 ⁇ m. Specifically, it can be 3 ⁇ m, 3.1 ⁇ m, 3.2 ⁇ m, 3.3 ⁇ m, 3.4 ⁇ m, 3.5 ⁇ m, 3.6 ⁇ m, 3.7 ⁇ m, 3.8 ⁇ m, 3.9 ⁇ m or 4 ⁇ m, but is not limited thereto. In actual applications, it can be set according to needs.
  • the manufacturing method of the display panel further includes:
  • Step S700 on the side of the first conductive layer 230 away from the first flexible layer 120, an interlayer dielectric layer ILD, a third conductive layer 250, a passivation layer PVX, a first planarization layer PLN1, a fourth conductive layer 260, The second planarization layer PLN2 and the light-emitting layer are used.
  • This step can specifically adopt conventional methods in the art and will not be described in detail here.
  • An embodiment of the present disclosure also provides a display device, including a display panel.
  • the display panel can be the display panel of any of the above embodiments.
  • the display device of the present disclosure may be an electronic device such as a mobile phone, a tablet computer, or a television, which will not be listed here.

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Abstract

一种显示面板及制作方法、显示装置，属于显示技术领域。该显示面板包括第一柔性层(120)；第二柔性层(140)，设于第一柔性层(120)的一侧；信号线(10)设于两者之间。第二柔性层(140)中设有第一通孔(141)，第一通孔(141)暴露信号线(10)的表面；无机层(150)覆盖第二柔性层(140)的表面和第一通孔(141)的侧壁，无机层(150)中设有第二通孔(151)，第二通孔(151)暴露信号线(10)的表面；第一导电层(230)包括转接线(231)，转接线(231)至少覆盖第二通孔(151)的侧壁和信号线(10)暴露的表面。在减小显示面板边框的同时，有助于阻挡外界水汽的进入，避免对显示面板内器件造成腐蚀，以保证显示面板的信赖性。

Description

显示面板及制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及制作方法、显示装置。
背景技术
近几年全面屏的发展十分迅速，这对屏幕的形态提出了新的需求。对于全面屏显示，减小屏幕边框十分重要。
目前，显示屏幕的下边框受扇形区(Fanout)走线等的影响，下边框的宽度通常比左右边框的宽度较宽。现有技术中通过对走线等进行重新设计，可减小显示屏幕的下边框，但该种方式还有待完善。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种显示面板及制作方法、显示装置，在减小显示面板边框的同时，有助于阻挡外界水汽的进入，避免对显示面板内器件造成腐蚀，以保证显示面板的信赖性。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种显示面板，其中，包括：
第一柔性层；
第二柔性层，设于所述第一柔性层的一侧；
信号线，设于所述第一柔性层和所述第二柔性层之间，所述第二柔性层中设有第一通孔，所述第一通孔暴露所述信号线远离所述第一柔性层的表面；
无机层，覆盖所述第二柔性层远离所述第一柔性层的表面和所述第一通孔的侧壁，所述无机层中设有第二通孔，所述第二通孔在所述第一柔性层上的正投影位于所述第一通孔在所述第一柔性层上的正投影之内， 且所述第二通孔暴露所述信号线远离所述第一柔性层的表面；
第一导电层，包括转接线，所述转接线至少覆盖所述第二通孔的侧壁和所述信号线被所述第二通孔暴露的表面。
在本公开的一种示例性实施例中，所述显示面板还包括：
绝缘层，设于所述无机层远离所述第一柔性层的一侧，所述绝缘层中设有第三通孔，所述第三通孔和所述第二通孔贯通；
所述第二通孔在所述第一柔性层上的正投影位于所述第三通孔在所述第一柔性层上的正投影之内；
所述第二通孔具有第二孔壁，所述第三通孔具有第三孔壁，所述第二孔壁和所述第三孔壁相互连接形成一通孔壁，所述通孔壁至少具有一台阶部。
在本公开的一种示例性实施例中，所述显示面板还包括：
绝缘层，设于所述无机层远离所述第一柔性层的一侧，所述绝缘层中设有第三通孔，所述第三通孔和所述第二通孔贯通；
所述第二通孔在所述第一柔性层上的正投影位于所述第三通孔在所述第一柔性层上的正投影之内；
所述第二通孔具有第二孔壁，所述第三通孔具有第三孔壁，所述第二孔壁远离所述第一柔性层的一端与所述第三孔壁靠近所述第一柔性层的一端之间设有平行于所述第一柔性层方向的第一间距，所述第一间距大于等于0；
所述转接线覆盖所述绝缘层远离所述第一柔性层的至少部分表面，且至少覆盖所述第二孔壁和所述第三孔壁。
在本公开的一种示例性实施例中，所述绝缘层包括第一栅绝缘层，所述第一栅绝缘层设有所述第三通孔；
所述第一导电层还包括晶体管的栅极和电容的第一极板；
所述转接线覆盖所述第一栅绝缘层远离所述第一柔性层的至少部分表面。
在本公开的一种示例性实施例中，所述绝缘层包括沿远离所述第一柔性层方向依次设置的第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层和所述第二栅绝缘层中设有所述第三通孔；
所述第一导电层包括电容的第二极板；
所述转接线覆盖所述第二栅绝缘层远离所述第一柔性层的至少部分表面。
在本公开的一种示例性实施例中，所述第三通孔包括第一子通孔和第二子通孔；
所述第一栅绝缘层中设有所述第一子通孔，所述第二栅绝缘层中设有所述第二子通孔；
所述第一子通孔在所述第一柔性层上的正投影位于所述第二子通孔在所述第一柔性层上的正投影之内；
所述第一子通孔具有第一子孔壁，所述第二子通孔具有第二子孔壁，所述第一子孔壁远离所述第一柔性层的一端与所述第二子孔壁靠近所述第一柔性层的一端之间设有平行于所述第一柔性层方向的第二间距，所述第二间距大于等于0。
在本公开的一种示例性实施例中，所述显示面板还包括：
有源层，设于所述无机层和所述绝缘层之间；
层间介质层，设于所述第一导电层远离所述第一柔性层的一侧；
第三导电层，设于层间介质层远离所述第一柔性层的一侧，所述第三导电层包括晶体管的源极和漏极，所述源极和漏极连接于所述有源层；且所述第三导电层与所述转接线连接；
所述信号线用于向像素电路提供电源电压。
在本公开的一种示例性实施例中，所述显示面板还包括：
缓冲层，设于所述第一柔性层和所述第二柔性层之间；
所述信号线设于所述缓冲层靠近所述第一柔性层的一侧，或
所述信号线设于所述缓冲层远离所述第一柔性层的一侧。
在本公开的一种示例性实施例中，所述第一间距不小于3μm，和/或所述第二间距不小于3μm。
根据本公开第二个方面，提供一种显示面板的制作方法，包括：
形成第一柔性层；
于所述第一柔性层的一侧形成信号线；
于所述信号线远离所述第一柔性层的一侧形成第二柔性层；
于所述第二柔性层中形成第一通孔，所述第一通孔暴露所述信号线远离所述第一柔性层的表面；
于所述第二柔性层远离所述第一柔性层的一侧形成无机层，所述无机层覆盖所述第二柔性层远离所述第一柔性层的表面和所述第一通孔的侧壁；
形成第一导电层，所述第一导电层包括转接线；
其中，所述无机层中形成有第二通孔，所述第二通孔在所述第一柔性层上的正投影位于所述第一通孔在所述第一柔性层上的正投影之内，且所述第二通孔暴露所述信号线远离所述第一柔性层的表面；
所述转接线至少覆盖所述第二通孔的侧壁和所述信号线被所述第二通孔暴露的表面。
在本公开的一种示例性实施例中，所述形成第一导电层之前还包括：
于所述无机层远离所述第一柔性层的一侧形成绝缘层；
其中，所述绝缘层中形成有第三通孔，所述绝缘层覆盖所述无机层的至少部分表面，所述第三通孔和所述第二通孔贯通；
所述第二通孔在所述第一柔性层上的正投影位于所述第三通孔在所述第一柔性层上的正投影之内；
所述第二通孔具有第二孔壁，所述第三通孔具有第三孔壁，所述第二孔壁远离所述第一柔性层的一端与所述第三孔壁靠近所述第一柔性层的一端之间设有平行于所述第一柔性层方向的第一间距，所述第一间距大于等于0；
所述转接线覆盖所述绝缘层远离所述第一柔性层的至少部分表面，且至少覆盖所述第二孔壁和所述第三孔壁。
在本公开的一种示例性实施例中，于所述无机层远离所述第一柔性层的一侧形成绝缘层包括：
于所述无机层远离所述第一柔性层的一侧形成第一栅绝缘层，所述第一栅绝缘层覆盖所述无机层远离所述第一柔性层的至少部分表面；
于所述第一栅绝缘层远离所述第一柔性层的一侧形成第二栅绝缘层，所述第二栅绝缘层覆盖所述第一栅绝缘层远离所述第一柔性层的至少部分表面；
其中，所述第一栅绝缘层中形成第一子通孔，所述第二栅绝缘层中形成第二子通孔，所述第一子通孔和所述第二子通孔形成所述第三通孔；
所述第二通孔在所述第一柔性层上的正投影位于所述第一子通孔在所述第一柔性层上的正投影之内，所述第一子通孔在所述第一柔性层上的正投影位于所述第二子通孔在所述第一柔性层上的正投影之内；
所述第一子通孔具有第一子孔壁，所述第二子通孔具有第二子孔壁，所述第一子孔壁远离所述第一柔性层的一端与所述第二子孔壁靠近所述第一柔性层的一端之间设有平行于所述第一柔性层方向的第二间距，所述第二间距大于等于0。
根据本公开第三个方面，提供一种显示装置，包括如第一方面所述的显示面板。
本公开提供的显示面板，将信号线设置于第一柔性层和第二柔性层之间，有助于减小显示面板下边框的宽度。另外，无机层覆盖第二柔性层远离第一柔性层的表面和第一通孔的侧壁，也即将第二柔性层予以包裹，该结构设计在减小显示面板边框的同时，有助于阻挡外界水汽的进入，避免对显示面板内器件造成腐蚀，以保证显示面板的信赖性。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是本公开示例性实施例中显示面板结构示意图；
图2是本公开另一示例性实施例中显示面板结构示意图；
图3是本公开又一示例性实施例中显示面板结构示意图；
图4是本公开又一示例性实施例中显示面板结构示意图；
图5是本公开又一示例性实施例中显示面板结构示意图；
图6是本公开又一示例性实施例中显示面板结构示意图；
图7是本公开示例性实施例中形成第一通孔结构示意图；
图8是本公开示例性实施例中形成第二通孔、第三通孔结构示意图；
图9是本公开另一示例性实施例中形成第二通孔、第三通孔结构示意图；
图10是本公开又一示例性实施例中形成第二通孔、第三通孔结构示意图；
图11是本公开又一示例性实施例中形成第二通孔、第三通孔结构示意图；
图12是本公开示例性实施例中形成第二通孔、第一子通孔、第二子通孔结构示意图；
图13是本公开另一示例性实施例中形成第二通孔、第一子通孔、第二子通孔结构示意图；
图14是本公开示例性实施例中显示面板制作方法流程示意图。
图中主要元件附图标记说明如下：
110-硬底基板；120-第一柔性层；130-缓冲层；140-第二柔性层；141-第一通孔；150-无机层；151-第二通孔；51H-第二孔壁；10-信号线；210-有源层；220-绝缘层；221-第一栅绝缘层；2211-第一子通孔；11H-第一子孔壁；222-第二栅绝缘层；2221-第二子通孔；21H-第二子孔壁；2200-第三通孔；00H-第三孔壁；230-第一导电层；231-转接线；240-第二导电层；ILD-层间介质层；250-第三导电层；PVX-钝化层；PLN1-第一平坦化层；260-第四导电层；PLN2-第二平坦化层；310-像素定义层；320-第一电极；330-发光功能层；400-隔垫物。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的 实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
显示屏幕的下边框受扇形区(Fanout)走线等的影响，下边框的宽度通常比左右边框的宽度较宽。相关技术中，将信号线设置两层柔性层聚酰亚胺(Polyimide，PI)层，如第一柔性层和第二柔性层之间，通过在位于两层柔性层上方的驱动电路层中设置转接孔，该转接孔暴露信号线，利用在该转接孔中形成转接金属层来进行电源电压的传输。然而，在该方案中，于转接孔中形成的转接金属层通常与第二柔性层直接接触，外界水汽会沿着第二柔性层进入，影响显示屏幕的信赖性。
如图1、图7和图8所示，本公开实施方式中提供一种显示面板，包括第一柔性层120、信号线10、第二柔性层140、无机层150和第一导电层230，其中，第二柔性层140设于第一柔性层120的一侧；信号线10设于第一柔性层120和第二柔性层140之间，第二柔性层140中设有第一通孔141，第一通孔141暴露信号线10远离第一柔性层120的表面；无机层150覆盖第二柔性层140远离第一柔性层120的表面和第一通孔141的侧壁，无机层150中设有第二通孔151，第二通孔151在第一柔性层120上的正投影位于第一通孔141在第一柔性层120上的正投影之内，且第二通孔151暴露信号线10远离第一柔性层120的表面；第一导电层230包括转接线231，转接线231至少覆盖第二通孔151的侧壁和信号线10被第二通孔151暴露的表面。
本公开提供的显示面板，将信号线10设置于第一柔性层120和第二 柔性层140之间，有助于减小显示面板下边框的宽度。另外，无机层150覆盖第二柔性层140远离第一柔性层120的表面和第一通孔141的侧壁，也即将第二柔性层140予以包裹，该结构设计在减小显示面板边框的同时，有助于阻挡外界水汽的进入，避免对显示面板内器件造成腐蚀，以保证显示面板的信赖性。
下面结合附图对本公开实施方式提供的显示面板的各部件进行详细说明：
本公开提供一种显示面板，该显示面板可以是有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，如AMOLED(Active-matrix organic light-emitting diode，有源矩阵有机发光二极管)显示面板，也可以是量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板、微发光二极管(Micro Light Emitting Diodes，Micro LED)显示面板等，本公开对此不做具体限定。
如图1至图6、图7和图8所示，显示面板包括第一柔性层120、信号线10、第二柔性层140、无机层150和第一导电层230。
第一柔性层120、第二柔性层140和无机层150可形成显示面板的衬底基板，第二柔性层140设于第一柔性层120的一侧。第一柔性层120和第二柔性层140的材料可包含聚酰亚胺(Polyimide，PI)。
在本公开一些实施例中，显示面板还包括缓冲层130，设于第一柔性层120和第二柔性层140之间，缓冲层130的材料可包含无机材料，且缓冲层130可在第一柔性层120和第二柔性层140间起到很好的粘接性。
信号线10设于第一柔性层120和第二柔性层140之间。该信号线10可设于缓冲层130靠近第一柔性层120的一侧，也可设于缓冲层130远离第一柔性层120的一侧，具体本公开不做限定。在一优选实施例中，信号线10设于缓冲层130远离第一柔性层120的一侧。第二柔性层140中设有第一通孔141，第一通孔141暴露信号线10远离第一柔性层120的表面。
无机层150覆盖第二柔性层140远离第一柔性层120的表面和第一通孔141的侧壁，具体与第一通孔141位置处的第二柔性层140的侧壁 接触，从而将第二柔性层140予以包裹，防止外界水汽沿第二柔性层140进入第一通孔141位置处。
无机层150中设有第二通孔151，第二通孔151在第一柔性层120上的正投影位于第一通孔141在第一柔性层120上的正投影之内，且第二通孔151暴露信号线10远离第一柔性层120的表面。也即第二通孔151与第一通孔141贯通，以暴露信号线10远离第一柔性层120的表面。
第一导电层230包括转接线231，转接线231与信号线10连接，转接线231至少覆盖第二通孔151的侧壁和信号线10被第二通孔151暴露的表面。第一导电层230可以包括金属材料或者合金材料，以保证其良好的导电性能。当然，该第一导电层230也可以采用透明导电材料，如ITO(氧化铟锡)、IZO(氧化铟锌)等。在本公开中，转接线231与第二柔性层140之间通过无机层150予以阻隔，该结构有助于阻挡外界水汽沿第二柔性层140渗入转接线231，防止对转接线231等器件造成腐蚀。
如图8至图13所示，在本公开一些实施例中，显示面板还包括绝缘层220，该绝缘层220设于无机层150远离第一柔性层120的一侧。绝缘层220可采用氮化硅、氧化硅、氧化铝等单膜层或由其组合形成的多膜层。绝缘层220中设有第三通孔2200，第三通孔2200和第二通孔151贯通；且第二通孔151在第一柔性层120上的正投影位于第三通孔2200在第一柔性层120上的正投影之内。在该类实施例中，信号线10远离第一柔性层120的表面被第二通孔151和第三通孔2200暴露。第二通孔151的孔径小于等于第三通孔2200的孔径。第三通孔2200与第二通孔151的总贯穿深度可以为5-8μm。
第二通孔151具有第二孔壁51H，第三通孔2200具有第三孔壁00H。在本公开一些实施例中，第二孔壁51H和第三孔壁00H相互连接形成一通孔壁，通孔壁至少具有一台阶部，该台阶部能够对转接线231起到缓冲作用，避免其发生断裂。
在本公开一些实施例中，第二孔壁51H远离第一柔性层120的一端与第三孔壁00H靠近第一柔性层120的一端之间设有平行于第一柔性层120方向的第一间距L1，第一间距L1大于等于0。如图1至图6所示， 转接线231覆盖绝缘层220远离第一柔性层120的至少部分表面，且至少覆盖第二孔壁51H和第三孔壁00H。
继续如图8至图13所示，第二孔壁51H远离第一柔性层120的一端为无机层150远离第一柔性层120的表面与第二通孔151边缘的交界线，第三孔壁00H靠近第一柔性层120的一端为绝缘层220靠近第一柔性层120的表面与第三通孔2200边缘的交界线。其中，绝缘层220靠近第一柔性层120的表面与无机层150远离第一柔性层120的表面相接触。此时，位于第三通孔2200和第二通孔151内的转接线231覆盖第三孔壁00H、第二孔壁51H和信号线10被第二通孔151暴露的表面。
如图8、图10和图12所示，在本公开一些实施例中，第一间距L1大致等于0，第二孔壁51H远离第一柔性层120的一端与第三孔壁00H靠近第一柔性层120的一端重合，第二孔壁51H和第三孔壁00H大致连接为一顺滑的侧壁。
如图9、图11和图13所示，在本公开另一些实施例中，第一间距L1大于0，第二孔壁51H远离第一柔性层120的一端与第三孔壁00H靠近第一柔性层120的一端不重合，且第三孔壁00H、无机层150远离第一柔性层120的表面和第二孔壁51H可连接形成至少一台阶部。如图3、图4和图6所示，此时，位于第三通孔2200和第二通孔151内的转接线231覆盖第三孔壁00H、无机层150远离第一柔性层120的部分表面，即第一间距L1对应的无机层150的表面，以及第二孔壁51H和信号线10被第二通孔151暴露的表面。在该类实施例中，位于第三通孔2200和第二通孔151内转接线231由于台阶部的缓冲，在制作形成时不易发生断裂。
在该类实施例中，第一间距L1不小于3μm。具体可以是3μm、3.1μm、3.2μm、3.3μm、3.4μm、3.5μm、3.6μm、3.7μm、3.8μm、3.9μm或4μm等，但不限于此。在实际应用中，可根据需求进行设定。
如图1至图6所示，在本公开一些实施例中，显示面板还包括有源层210，有源层210设于无机层150和绝缘层220之间。有源层210的材料可以为多晶硅或IGZO(铟镓锌氧化物)，其可以通过掺杂等工艺改变不同位置处的导电性能。绝缘层220可包含一层、两层或多层结构， 具体可根据实际情况进行设定。下面将结合具体实施例，详细说明本公开绝缘层220的不同设置方式。
如图1、图3、图8和图9所示在本公开一些实施例中，绝缘层220包括第一栅绝缘层221，第一栅绝缘层221设置有第三通孔2200。第一栅绝缘层221位于有源层210和第一导电层230之间。第一导电层230还包括晶体管的栅极和电容的第一极板。转接线231覆盖第一栅绝缘层221远离第一柔性层120的至少部分表面。在该类实施例中，转接线231覆盖第三孔壁00H，第三孔壁00H为第一栅绝缘层221在第三通孔2200位置处的侧壁。
在该类实施例中，显示面板还包括第二栅绝缘层222、第二导电层(图中未示出)、层间介质层ILD和第三导电层250。其中，第二栅绝缘层222设于第一导电层230远离第一柔性层120的一侧，第二栅绝缘层222覆盖第一导电层230和第一栅绝缘层221的表面。第二导电层设于第二栅绝缘层222远离第一柔性层120的表面，第二导电层包括电容的第二极板。层间介质层ILD设于第二导电层远离第一柔性层120的一侧，层间介质层ILD覆盖第二导电层和第二栅绝缘层222。第三导电层250设于层间介质层ILD远离第一柔性层120的一侧，第三导电层250包括晶体管的源极和漏极，源极和漏极连接于有源层210；且第三导电层250与转接线231连接，进而与信号线10连接，信号线10可用于向像素电路提供电源电压信号，从而将电源电压信号施加至晶体管的源极或漏极。
如图2、图4至图6、图10至图13所示，在本公开另一些实施例中，绝缘层220包括沿远离第一柔性层120方向依次设置的第一栅绝缘层221和第二栅绝缘层222，第一栅绝缘层221和第二栅绝缘层222中设置有第三通孔2200。第一栅绝缘层221覆盖有源层210。第一导电层230包括电容的第二极板。第一导电层230设于第二栅绝缘层222远离第一柔性层120的一侧，转接线231覆盖第二栅绝缘层222远离第一柔性层120的至少部分表面。在该类实施例中，转接线231覆盖第三孔壁00H，第三孔壁00H为第一栅绝缘层221和第二栅绝缘层222在第三通孔2200位置处的侧壁。
显示面板还包括第二导电层240、层间介质层ILD和第三导电层250。 其中，第二导电层240设于第一栅绝缘层221和第二栅绝缘层222之间，第二栅绝缘层222覆盖第二导电层240和第一栅绝缘层221。第二导电层240包括晶体管的栅极和电容的第一极板。层间介质层ILD设于第一导电层230远离第一柔性层120的一侧，层间介质层ILD覆盖第一导电层230和第二栅绝缘层222。第三导电层250设于层间介质层ILD远离第一柔性层120的一侧，第三导电层250包括晶体管的源极和漏极，源极和漏极连接于有源层210；且第三导电层250与转接线231连接，进而与信号线10连接，信号线10可用于向像素电路提供电源电压信号，从而将电源电压信号施加至晶体管的源极或漏极。
如图10、图11、图12和图13所示，在一些实施例中，第三通孔2200包括第一子通孔2211和第二子通孔2221；第一栅绝缘层221中设有第一子通孔2211，第二栅绝缘层222中设有第二子通孔2221；第一子通孔2211在第一柔性层120上的正投影位于第二子通孔2221在第一柔性层120上的正投影之内；第一子通孔2211具有第一子孔壁11H，第二子通孔2221具有第二子孔壁21H，第一子孔壁11H远离第一柔性层120的一端与第二子孔壁21H靠近第一柔性层120的一端之间设有平行于第一柔性层120方向的第二间距L2，第二间距L2大于等于0。
在该类实施例中，第一子孔壁11H远离第一柔性层120的一端为第一栅绝缘层221远离第一柔性层120的表面与第一子通孔2211边缘的交界线，第二子孔壁21H靠近第一柔性层120的一端为第二栅绝缘层222靠近第一柔性层120的表面与第二子通孔2221边缘的交界线，其中，第一栅绝缘层221远离第一柔性层120的表面与第二栅绝缘层222靠近第一柔性层120的表面相接触。此时，位于第三通孔2200和第二通孔151内的转接线231覆盖第二子孔壁21H、第一子孔壁11H、第二孔壁51H和信号线10被第二通孔151暴露的表面。
如图10和图11所示，在本公开一些实施例中，第二间距L2大致等于0，第一子孔壁11H远离第一柔性层120的一端与第二子孔壁21H靠近第一柔性层120的一端重合，第一子孔壁11H和第二子孔壁21H大致连接为一顺滑的侧壁。
如图12和图13所示，在本公开另一些实施例中，第二间距L2大于 0，第一子孔壁11H远离第一柔性层120的一端与第二子孔壁21H靠近第一柔性层120的一端不重合，且第一子孔壁11H、第一栅绝缘层221远离第一柔性层120的表面和第二子孔壁21H可连接形成至少一台阶部。此时，如图5和图6所示，位于第一子通孔2211和第二子通孔2221内的转接线231覆盖第二子孔壁21H、第一栅绝缘层221远离第一柔性层120的部分表面和第一子孔壁11H。在该类实施例中，第一子孔壁11H和第二子孔壁21H形成台阶部，该台阶部可进一步对转接线231的形成起到缓冲作用，有助于进一步降低转接线231在通孔内由于通孔深度过深而发生断裂的可能性。
在该类实施例中，第二间距L2不小于3μm。具体可以是3μm、3.1μm、3.2μm、3.3μm、3.4μm、3.5μm、3.6μm、3.7μm、3.8μm、3.9μm或4μm等，但不限于此。在实际应用中，可根据需求进行设定。
如图1至图6所示，在本公开一些实施例中，显示面板还包括钝化层PVX、第一平坦化层PLN1、第四导电层260和第二平坦化层PLN2。其中，钝化层PVX设于第三导电层250远离第一柔性层120的一侧，钝化层PVX覆盖第三导电层250和层间介质层ILD。第一平坦化层PLN1设于钝化层PVX远离第一柔性层120的一侧，第一钝化层PVX覆盖钝化层PVX。第四导电层260设于第一平坦化层PLN1远离第一柔性层120的一侧，第四导电层260通过过孔连接至第三导电层250。
显示面板还包括第二平坦化层PLN2、发光层和隔垫物400，第二平坦化层PLN2设于第四导电层260远离第一柔性层120的一侧，第二平坦化层PLN2覆盖第四导电层260和第一平坦化层PLN1。发光层设于第二平坦化层PLN2远离第一柔性层120的一侧。发光层包括像素定义层310多个发光器件。隔垫物400设于像素定义层310远离第一柔性层120的一侧。
像素定义层310设于第二平坦化层PLN2远离第一柔性层120的一侧。像素定义层310可设有多个开口，每个开口限定出的范围即为一发光器件的范围。开口的形状，即开口在第一柔性层120的正投影的轮廓的形状可为多边形、光滑的封闭曲线或其它形，在此不做特殊限定。
发光器件可与第四导电层260连接，可在驱动电路的驱动下发光。 以发光器件为OLED发光器件为例，发光器件可包括沿远离第一柔性层120的方向依次层叠的第一电极320、发光功能层330和第二电极。第一电极320可以为阳极，第二电极可以为阴极。发光器件结构为本领域常规结构，在此不详细描述。
如图1至图6、图14所示，本公开还提供一种显示面板的制作方法，包括：
步骤S100，形成第一柔性层120；
步骤S200，于第一柔性层120的一侧形成信号线10；
步骤S300，于信号线10远离第一柔性层120的一侧形成第二柔性层140；
步骤S400，于第二柔性层140中形成第一通孔141，第一通孔141暴露信号线10远离第一柔性层120的表面；
步骤S500，于第二柔性层140远离第一柔性层120的一侧形成无机层150，无机层150覆盖第二柔性层140远离第一柔性层120的表面和第一通孔141的侧壁；
步骤S600，形成第一导电层230，第一导电层230包括转接线231；
其中，无机层150中形成有第二通孔151，第二通孔151在第一柔性层120上的正投影位于第一通孔141在第一柔性层120上的正投影之内，且第二通孔151暴露信号线10远离第一柔性层120的表面；转接线231至少覆盖第二通孔151的侧壁和信号线10被第二通孔151暴露的表面。
本公开提供的显示面板的制作方法，在第二柔性层140中形成第一通孔141，之后再形成无机层150，以使形成的无机层150可以对第一通孔141位置处的第二柔性层140予以包裹，从而利用无机层150阻挡外界水汽的进入，避免对显示面板内器件造成腐蚀。
在本公开一些实施例中，在步骤S100之前还可以包括提供硬底基板110，硬底基板110的材料可以是玻璃等。在步骤S100中，可以在硬底基板110的一侧形成第一柔性层120。
如图8至图13所示，在本公开一些实施例中，步骤S600之前还包括：
步骤S501，于无机层150远离第一柔性层120的一侧形成绝缘层220。
绝缘层220中形成有第三通孔2200，绝缘层220覆盖无机层150的至少部分表面，第三通孔2200和第二通孔151贯通。第二通孔151在第一柔性层120上的正投影位于第三通孔2200在第一柔性层120上的正投影之内。第二通孔151具有第二孔壁51H，第三通孔2200具有第三孔壁00H，第二孔壁51H远离第一柔性层120的一端与第三孔壁00H靠近第一柔性层120的一端之间设有平行于第一柔性层120方向的第一间距L1，第一间距L1大于等于0。转接线231覆盖绝缘层220远离第一柔性层120的至少部分表面，且至少覆盖第二孔壁51H和第三孔壁00H。
在步骤S501中，形成的绝缘层220可包含单层或多层结构。下面将结合不同的实施例予以详细说明。
如图8和图9所示，在本公开一实施例中，步骤S501包括：
于无机层150远离第一柔性层120的一侧形成第一栅绝缘层221，第一栅绝缘层221覆盖无机层150远离第一柔性层120的至少部分表面。
在该类实施例中，第一栅绝缘层221中形成有第三通孔2200；转接线231覆盖第一栅绝缘层221远离第一柔性层120的至少部分表面。
在该类实施例中，第一栅绝缘层221中的第三通孔2200和无机层150中的第二通孔151可采用一次刻蚀工艺形成，也可采用分次刻蚀工艺形成。
具体地，当第一间距L1大致等于0时，第三通孔2200和第二通孔151可采用一次刻蚀工艺形成。举例而言，如图8所示，在形成第一栅绝缘层221后，采用刻蚀工艺，同时刻蚀第一栅绝缘层221和无机层150，以在第一栅绝缘层221中形成第三通孔2200，在无机层150中形成第二通孔151。在该实施例中，当进行步骤S600形成第一导电层230后，可形成如图1所示的显示面板。此显示面板的结构可参照上述实施例中的描述，在此不详细赘述。
当第一间距L1大于0时，第三通孔2200和第二通孔151采用不同次刻蚀工艺形成。举例而言，如图9所示，在形成第一栅绝缘层221后，可以先采用第一次刻蚀工艺于第一栅绝缘层221中形成第三通孔2200，之后再采用第二次刻蚀工艺于无机层150中形成第二通孔151，第二通 孔151的孔径可小于第三通孔2200的孔径。在该实施例中，当进行步骤S600形成第一导电层230后，可形成如图3所示的显示面板。此显示面板的结构可参照上述实施例中的描述，在此不详细赘述。
如图10至图13所示，在本公开另一实施例中，步骤S501包括：
步骤S5011，于无机层150远离第一柔性层120的一侧形成第一栅绝缘层221，第一栅绝缘层221覆盖无机层150远离第一柔性层120的至少部分表面；
步骤S5012，于第一栅绝缘层221远离第一柔性层120的一侧形成第二栅绝缘层222，第二栅绝缘层222覆盖第一栅绝缘层221远离第一柔性层120的至少部分表面。
在该类实施例中，第一栅绝缘层221和第二栅绝缘层222中设有第三通孔2200；转接线231覆盖第二栅绝缘层222远离第一柔性层120的至少部分表面。
在该类实施例中，第一栅绝缘层221和第二栅绝缘层222中的第三通孔2200和无机层150中的第二通孔151可采用一次刻蚀工艺形成，也可采用分次刻蚀工艺形成。
具体地，当第一间距L1大致等于0时，第三通孔2200和第二通孔151可采用一次刻蚀工艺形成。举例而言，如图10所示，在形成第二栅绝缘层222后，采用刻蚀工艺，同时刻蚀第二栅绝缘层222、第一栅绝缘层221和无机层150，以在第二栅绝缘层222、第一栅绝缘层221中形成第三通孔2200，在无机层150中形成第二通孔151。在该实施例中，当进行步骤S600形成第一导电层230后，可形成如图2所示的显示面板。此显示面板的结构可参照上述实施例中的描述，在此不详细赘述。
当第一间距L1大于0时，第三通孔2200和第二通孔151采用不同次刻蚀工艺形成。举例而言，如图11所示，在形成第二栅绝缘层222后，可以采用一次刻蚀工艺于第二栅绝缘层222、第一栅绝缘层221中形成第三通孔2200，再采用另一次次刻蚀工艺于无机层150中形成第二通孔151，第二通孔151的孔径可小于第三通孔2200的孔径。在该实施例中，当进行步骤S600形成第一导电层230后，可形成如图4所示的显示面板。此显示面板的结构可参照上述实施例中的描述，在此不详细赘述。
在本公开一些实施例中，第一栅绝缘层221中形成第一子通孔2211，第二栅绝缘层222中形成第二子通孔2221，第一子通孔2211和第二子通孔2221形成第三通孔2200；第二通孔151在第一柔性层120上的正投影位于第一子通孔2211在第一柔性层120上的正投影之内，第一子通孔2211在第一柔性层120上的正投影位于第二子通孔2221在第一柔性层120上的正投影之内；第一子通孔2211具有第一子孔壁11H，第二子通孔2221具有第二子孔壁21H，第一子孔壁11H远离第一柔性层120的一端与第二子孔壁21H靠近第一柔性层120的一端之间设有平行于第一柔性层120方向的第二间距L2，第二间距L2大于等于0。
在该类实施例中，第一栅绝缘层221中的第一子通孔2211和第二栅绝缘层222中的第二子通孔2221和可采用一次刻蚀工艺形成，也可采用分次刻蚀工艺形成。
具体地，当第二间距L2等于0时，第一子通孔2211和第二子通孔2221可采用一次刻蚀工艺形成，具体可形成如图10或图11所示的结构。在此需说明的是，当第一间距L1也等于0时，第二子通孔2221、第一子通孔2211和第二通孔151可采用一次刻蚀工艺形成，具体形成如图10所示的结构。
当第二间距L2大于0时，第一子通孔2211和第二子通孔2221可采用两次刻蚀工艺形成，具体可形成如图12或图13所示的结构。举例而言，如图13所示，当第一间距L1也大于0时，在形成第二栅绝缘层222后，可采用一次刻蚀工艺于第二栅绝缘层222中形成第二子通孔2221，采用另一次刻蚀工艺于第一栅绝缘层221中形成第一子通孔2211，第一子通孔2211的孔径小于第二子通孔2221的孔径，之后在采用另一次刻蚀工艺于无机层150中形成第二通孔151，第二通孔151的孔径小于第一子通孔2211的孔径。在该实施例中，当进行步骤S600形成第一导电层230后，可形成如图6所示的显示面板。此显示面板的结构可参照上述实施例中的描述，在此不详细赘述。
如图12所示，当第一间距L1等于0时，第一子通孔2211和第二通孔151可采用一次刻蚀工艺形成。具体地，当形成第二栅绝缘层222后，可采用一次刻蚀工艺于第二栅绝缘层222中形成第二子通孔2221，采用 另一次刻蚀工艺同时刻蚀第一栅绝缘层221和无机层150，于第一栅绝缘层221中形成第一子通孔2211，于无机层150中形成第二通孔151，具体可形成如图12所示的结构。在该实施例中，当进行步骤S600形成第一导电层230后，可形成如图5所示的显示面板。此显示面板的结构可参照上述实施例中的描述，在此不详细赘述。
在本公开一些实施例中，第一间距L1和第二间距L2均不小于3μm。具体可以是3μm、3.1μm、3.2μm、3.3μm、3.4μm、3.5μm、3.6μm、3.7μm、3.8μm、3.9μm或4μm等，但不限于此。在实际应用中，可根据需求进行设定。
如图1至图6所示，在本公开一些实施例中，显示面板的制作方法还包括：
步骤S700，于第一导电层230背离第一柔性层120的一侧依次形成层间介质层ILD、第三导电层250、钝化层PVX、第一平坦化层PLN1、第四导电层260、第二平坦化层PLN2和发光层等。该步骤具体可采用本领域常规方法，在此不详细描述。
本公开实施方式还提供一种显示装置，包括显示面板，该显示面板可为上述任意实施方式的显示面板，其具体结构和有益效果可参考上文中显示面板的实施方式，在此不再赘述。本公开的显示装置可以是手机、平板电脑、电视等电子设备，在此不再一一列举。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本公开的一部分。
可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (13)

  1. 一种显示面板，包括：
    第一柔性层；
    第二柔性层，设于所述第一柔性层的一侧；
    信号线，设于所述第一柔性层和所述第二柔性层之间，所述第二柔性层中设有第一通孔，所述第一通孔暴露所述信号线远离所述第一柔性层的表面；
    无机层，覆盖所述第二柔性层远离所述第一柔性层的表面和所述第一通孔的侧壁，所述无机层中设有第二通孔，所述第二通孔在所述第一柔性层上的正投影位于所述第一通孔在所述第一柔性层上的正投影之内，且所述第二通孔暴露所述信号线远离所述第一柔性层的表面；
    第一导电层，包括转接线，所述转接线至少覆盖所述第二通孔的侧壁和所述信号线被所述第二通孔暴露的表面。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    绝缘层，设于所述无机层远离所述第一柔性层的一侧，所述绝缘层中设有第三通孔，所述第三通孔和所述第二通孔贯通；
    所述第二通孔在所述第一柔性层上的正投影位于所述第三通孔在所述第一柔性层上的正投影之内；
    所述第二通孔具有第二孔壁，所述第三通孔具有第三孔壁，所述第二孔壁和所述第三孔壁相互连接形成一通孔壁，所述通孔壁至少具有一台阶部。
  3. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    绝缘层，设于所述无机层远离所述第一柔性层的一侧，所述绝缘层中设有第三通孔，所述第三通孔和所述第二通孔贯通；
    所述第二通孔在所述第一柔性层上的正投影位于所述第三通孔在所述第一柔性层上的正投影之内；
    所述第二通孔具有第二孔壁，所述第三通孔具有第三孔壁，所述第二孔壁远离所述第一柔性层的一端与所述第三孔壁靠近所述第一柔性层的一端之间设有平行于所述第一柔性层方向的第一间距，所述第一间距大于等于0；
    所述转接线覆盖所述绝缘层远离所述第一柔性层的至少部分表面，且至少覆盖所述第二孔壁和所述第三孔壁。
  4. 根据权利要求3所述的显示面板，其中，所述绝缘层包括第一栅绝缘层，所述第一栅绝缘层设有所述第三通孔；
    所述第一导电层还包括晶体管的栅极和电容的第一极板；
    所述转接线覆盖所述第一栅绝缘层远离所述第一柔性层的至少部分表面。
  5. 根据权利要求3所述的显示面板，其中，所述绝缘层包括沿远离所述第一柔性层方向依次设置的第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层和所述第二栅绝缘层中设有所述第三通孔；
    所述第一导电层包括电容的第二极板；
    所述转接线覆盖所述第二栅绝缘层远离所述第一柔性层的至少部分表面。
  6. 根据权利要求5所述的显示面板，其中，所述第三通孔包括第一子通孔和第二子通孔；
    所述第一栅绝缘层中设有所述第一子通孔，所述第二栅绝缘层中设有所述第二子通孔；
    所述第一子通孔在所述第一柔性层上的正投影位于所述第二子通孔在所述第一柔性层上的正投影之内；
    所述第一子通孔具有第一子孔壁，所述第二子通孔具有第二子孔壁，所述第一子孔壁远离所述第一柔性层的一端与所述第二子孔壁靠近所述第一柔性层的一端之间设有平行于所述第一柔性层方向的第二间距，所述第二间距大于等于0。
  7. 根据权利要求3所述的显示面板，其中，所述显示面板还包括：
    有源层，设于所述无机层和所述绝缘层之间；
    层间介质层，设于所述第一导电层远离所述第一柔性层的一侧；
    第三导电层，设于层间介质层远离所述第一柔性层的一侧，所述第三导电层包括晶体管的源极和漏极，所述源极和漏极连接于所述有源层；且所述第三导电层与所述转接线连接；
    所述信号线用于向像素电路提供电源电压。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    缓冲层，设于所述第一柔性层和所述第二柔性层之间；
    所述信号线设于所述缓冲层靠近所述第一柔性层的一侧，或
    所述信号线设于所述缓冲层远离所述第一柔性层的一侧。
  9. 根据权利要求6所述的显示面板，其中，所述第一间距不小于3μm，和/或所述第二间距不小于3μm。
  10. 一种显示面板的制作方法，包括：
    形成第一柔性层；
    于所述第一柔性层的一侧形成信号线；
    于所述信号线远离所述第一柔性层的一侧形成第二柔性层；
    于所述第二柔性层中形成第一通孔，所述第一通孔暴露所述信号线远离所述第一柔性层的表面；
    于所述第二柔性层远离所述第一柔性层的一侧形成无机层，所述无机层覆盖所述第二柔性层远离所述第一柔性层的表面和所述第一通孔的侧壁；
    形成第一导电层，所述第一导电层包括转接线；
    其中，所述无机层中形成有第二通孔，所述第二通孔在所述第一柔性层上的正投影位于所述第一通孔在所述第一柔性层上的正投影之内，且所述第二通孔暴露所述信号线远离所述第一柔性层的表面；
    所述转接线至少覆盖所述第二通孔的侧壁和所述信号线被所述第二通孔暴露的表面。
  11. 根据权利要求10所述的显示面板的制作方法，其中，所述形成第一导电层之前还包括：
    于所述无机层远离所述第一柔性层的一侧形成绝缘层；
    其中，所述绝缘层中形成有第三通孔，所述绝缘层覆盖所述无机层的至少部分表面，所述第三通孔和所述第二通孔贯通；
    所述第二通孔在所述第一柔性层上的正投影位于所述第三通孔在所述第一柔性层上的正投影之内；
    所述第二通孔具有第二孔壁，所述第三通孔具有第三孔壁，所述第二孔壁远离所述第一柔性层的一端与所述第三孔壁靠近所述第一柔性层 的一端之间设有平行于所述第一柔性层方向的第一间距，所述第一间距大于等于0；
    所述转接线覆盖所述绝缘层远离所述第一柔性层的至少部分表面，且至少覆盖所述第二孔壁和所述第三孔壁。
  12. 根据权利要求11所述的显示面板的制作方法，其中，于所述无机层远离所述第一柔性层的一侧形成绝缘层包括：
    于所述无机层远离所述第一柔性层的一侧形成第一栅绝缘层，所述第一栅绝缘层覆盖所述无机层远离所述第一柔性层的至少部分表面；
    于所述第一栅绝缘层远离所述第一柔性层的一侧形成第二栅绝缘层，所述第二栅绝缘层覆盖所述第一栅绝缘层远离所述第一柔性层的至少部分表面；
    其中，所述第一栅绝缘层中形成第一子通孔，所述第二栅绝缘层中形成第二子通孔，所述第一子通孔和所述第二子通孔形成所述第三通孔；
    所述第二通孔在所述第一柔性层上的正投影位于所述第一子通孔在所述第一柔性层上的正投影之内，所述第一子通孔在所述第一柔性层上的正投影位于所述第二子通孔在所述第一柔性层上的正投影之内；
    所述第一子通孔具有第一子孔壁，所述第二子通孔具有第二子孔壁，所述第一子孔壁远离所述第一柔性层的一端与所述第二子孔壁靠近所述第一柔性层的一端之间设有平行于所述第一柔性层方向的第二间距，所述第二间距大于等于0。
  13. 一种显示装置，包括如权利要求1-9任一项所述的显示面板。
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