WO2023197340A1 - Procédé de fabrication de structure semi-conductrice, et structure semi-conductrice - Google Patents

Procédé de fabrication de structure semi-conductrice, et structure semi-conductrice Download PDF

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Publication number
WO2023197340A1
WO2023197340A1 PCT/CN2022/087494 CN2022087494W WO2023197340A1 WO 2023197340 A1 WO2023197340 A1 WO 2023197340A1 CN 2022087494 W CN2022087494 W CN 2022087494W WO 2023197340 A1 WO2023197340 A1 WO 2023197340A1
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Prior art keywords
groove
etching
conductive layer
layer
mask layer
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PCT/CN2022/087494
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English (en)
Chinese (zh)
Inventor
徐陈明
林红波
武贺
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长鑫存储技术有限公司
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Priority to US17/842,788 priority Critical patent/US20230326760A1/en
Publication of WO2023197340A1 publication Critical patent/WO2023197340A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor manufacturing technology, and in particular, to a method of manufacturing a semiconductor structure and a semiconductor structure.
  • the packaging structure includes a rewiring layer.
  • the rewiring layer is disposed on the side of the chip with contact pads.
  • the rewiring layer has a plurality of metal lines. One end of each metal line is connected to the contact pad, and the other end of the metal line is provided with a welding Structure, reasonable setting of the shape of metal wires can change the arrangement of the welding structure.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including:
  • Dry etching removes part of the conductive layer to form a first groove, the depth of the first groove is less than the thickness of the conductive layer, and there is polymer residue on the groove wall of the first groove;
  • a passivation layer is formed filling the second groove.
  • dry etching removes part of the conductive layer to form the first groove, including:
  • the conductive layer is etched to form the first groove.
  • the conductive layer corresponding to the groove wall and groove bottom of the first groove is removed to form a conductive line and a second groove formed between adjacent conductive lines;
  • a second mask layer is formed on the conductive layer, the second mask layer has a second etching opening, the second etching opening is disposed facing the first groove, and the second etching opening
  • the orthographic projected area on the substrate is greater than the orthographic projected area of the first etching opening on the substrate;
  • the conductive layer is etched using the second mask layer as a mask to form the conductive line and the second groove.
  • forming the second mask layer on the conductive layer includes:
  • the first mask layer is shrunk to increase the orthographic projection area of the first etching opening on the substrate to form the second mask layer and
  • the second etching opening is located on the second mask layer.
  • shrinking the first mask layer includes:
  • the first mask layer is etched to remove sidewalls of the first etching opening.
  • etching the first mask layer includes dry etching, and the etching gas of the dry etching includes at least one of oxygen, hydrogen, and nitrogen.
  • the conductive layer is etched using the first mask layer as a mask to form a first groove, and the depth of the first groove is the thickness of the conductive layer. 1/3-1/2.
  • the distance between the second etching opening and the groove wall of the first groove includes 50 nm-100 nm.
  • etching the conductive layer using the second mask layer as a mask to form the second groove includes:
  • the conductive layer and part of the substrate are etched to form the second groove.
  • the conductive layer is etched by dry etching using the first mask layer as a mask; and dry etching is performed by using the second mask layer as a mask.
  • the conductive layer is etched.
  • removing the conductive layer corresponding to the groove wall and groove bottom of the first groove to form the conductive line and the second groove includes: intermediate etching;
  • the intermediate etching includes:
  • An intermediate mask layer is formed on the conductive layer.
  • the intermediate mask layer has an intermediate etching opening.
  • the intermediate etching opening is disposed facing the first groove.
  • the intermediate etching opening is located on the substrate.
  • the orthographic projection area of the first etching opening on the substrate is larger than the orthographic projection area of the middle etching opening on the substrate, and the orthographic projection area of the middle etching opening on the substrate is smaller than the orthographic projection of the second etching opening on the substrate. area;
  • the conductive layer is etched to form a middle groove.
  • the depth of the middle groove is greater than the depth of the first groove and less than the depth of the second groove. depth.
  • the conductive layer corresponding to the groove wall and groove bottom of the first groove is removed to form the conductive line and the second groove, and include:
  • the conductive layer corresponding to the groove wall and groove bottom of the middle groove is removed to form the conductive line and the second groove.
  • forming an intermediate mask layer on the conductive layer includes:
  • the first mask layer is shrunk to increase the orthographic projection area of the first etching opening on the substrate, and the intermediate mask layer is formed and located The second etching opening on the intermediate mask layer.
  • shrinking the intermediate mask layer includes:
  • the first mask layer is etched to remove sidewalls of the first etching opening.
  • etching the intermediate mask layer includes dry etching, and the etching gas of the dry etching includes at least one of oxygen, hydrogen, and nitrogen.
  • the intermediate etching is performed multiple times, and in each intermediate etching, the orthogonal projected area of the intermediate etching opening on the substrate is larger than that in the previous intermediate etching.
  • the orthogonal projected area of the middle etching opening on the substrate is larger than that in the previous intermediate etching.
  • forming a passivation layer, before filling the second groove further includes:
  • forming a passivation layer before filling the second groove further includes: after removing the second mask layer,
  • An insulating layer is formed covering the conductive line and the groove wall and groove bottom of the second groove.
  • the conductive layer includes a plurality of sub-conductive layers arranged sequentially on the substrate.
  • embodiments of the present disclosure provide a semiconductor structure, including a semiconductor structure formed by the above-mentioned manufacturing method of a semiconductor structure.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure.
  • the method for manufacturing a semiconductor structure includes: providing a substrate covered with a conductive layer; dry etching to remove part of the conductive layer to form a first groove, and a first groove.
  • the depth of the groove is less than the thickness of the conductive layer, and there is polymer residue on the groove wall of the first groove; remove the corresponding part of the conductive layer on the groove wall and bottom of the first groove to form conductive lines and adjacent conductive lines the second groove between; forming a passivation layer, which is filled in the second groove.
  • the polymer deposited on the groove wall of the first groove can be removed at the same time, thereby avoiding premature sealing when the passivation layer is subsequently filled in the second groove, further preventing The presence of gaps inside the passivation layer is beneficial to improving the performance of the semiconductor structure.
  • Figure 1 is a schematic structural diagram of a conductive line formed by dry etching
  • Figure 2 is a schematic structural diagram of a passivation layer formed on a conductive line
  • Figure 3 is a step flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram of forming a first mask layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of forming a first groove in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of forming a second mask layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 7 is a structural schematic diagram 1 of forming a second groove in the manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 8 is a schematic structural diagram of forming a passivation layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of forming an intermediate mask layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of forming an intermediate groove in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram 2 of the structure of forming a second mask layer in the manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 12 is a schematic diagram 2 of the structure of forming a second groove in the manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 13 is a second structural schematic diagram of forming a passivation layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • a passivation layer covering the metal lines and filling the grooves between adjacent metal lines needs to be formed to perform the formed metal lines. protection while ensuring that adjacent metal wires are insulated from each other.
  • the passivation layer formed through the above process flow is of relatively low quality and has relatively poor performance.
  • Figure 1 is a schematic structural diagram of a conductive line formed by dry etching
  • Figure 2 is a schematic structural diagram of a passivation layer formed on a conductive line.
  • the inventor of the present disclosure found that, as shown in FIG. 1 , after performing a dry etching on the metal layer in the redistribution layer to obtain the metal lines 20 , the side walls of the grooves between adjacent metal lines 20 are easily Polymer residue 40 is formed; as shown in Figure 2, due to the existence of polymer residue 40, when the passivation layer 60 is subsequently formed, the passivation layer 60 in the groove is easily sealed in advance, resulting in gaps in the passivation layer 60. , making the performance of the passivation layer 60 relatively poor.
  • inventions of the present disclosure provide a method of manufacturing a semiconductor structure and a semiconductor structure.
  • the method of manufacturing a semiconductor structure includes: providing a substrate covered with a conductive layer; dry etching to remove part of the conductive layer to form a first recess. groove, the depth of the first groove is less than the thickness of the conductive layer, and there is polymer residue on the groove wall of the first groove; remove the corresponding part of the conductive layer on the groove wall of the first groove and the bottom of the groove to form a conductive line and a
  • the second groove between adjacent conductive lines forms a passivation layer, which is filled in the second groove.
  • the polymer deposited on the groove wall of the first groove can be removed at the same time, thereby avoiding premature sealing when the passivation layer is subsequently filled in the second groove, further preventing The presence of gaps inside the passivation layer is beneficial to improving the performance of the semiconductor structure.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps S101 to S104.
  • Step S101 Provide a substrate covered with a conductive layer.
  • the substrate 10 can be a semiconductor substrate, such as single crystal silicon, polycrystalline silicon, amorphous silicon or silicon germanium (SiGe), or a mixed semiconductor structure, such as silicon carbide, antimony Indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof. This embodiment does not limit it here.
  • the conductive layer 30 may be formed by electroplating or deposition.
  • the conductive layer 30 may be connected to contact pads provided inside the substrate 10 , so that the semiconductor structure can subsequently be electrically connected to the outside through the conductive layer 30 .
  • the material of the conductive layer 30 may include, for example, conductive metals and/or compounds such as aluminum, titanium, tungsten, and titanium nitride.
  • the conductive layer 30 may include a plurality of sub-conductive layers sequentially disposed on the substrate 10 .
  • the conductive layer 30 may include three sub-conductive layers arranged sequentially on the substrate 10 , namely a first sub-conductive layer 301 , a second sub-conductive layer 302 , and a third sub-conductive layer 303 .
  • the material of the first sub-conductive layer 301 may include titanium
  • the material of the second sub-conductive layer 302 may include aluminum
  • the material of the third sub-conductive layer 303 may include titanium nitride. It should be noted that this embodiment includes but is not limited to this.
  • Step S102 Dry etching removes part of the conductive layer to form a first groove, the depth of the first groove is less than the thickness of the conductive layer, and a polymer is formed on the groove wall of the first groove.
  • dry etching removes part of the conductive layer 30 , including forming a first mask layer 50 on the conductive layer 30 , and having a first etching opening 51 on the first mask layer 50 .
  • the material of the first mask layer 50 may include photoresist, and part of the photoresist is removed through an exposure and development process to form the first etching opening 51 .
  • dry etching removes part of the conductive layer 30 , which also includes: after forming the first mask layer 50 on the conductive layer 30 , using the first mask layer 50 as a mask, etching the conductive layer 30 Etching is performed to form the first groove 31 .
  • the conductive layer 30 is dry etched using the first mask layer 50 as a mask. Dry etching is a technology that uses plasma to etch thin films. During the etching process, the plasma is bombarded and etched. The surface of the object, thereby removing the etched object and achieving the purpose of etching. In this embodiment, the conductive layer 30 is removed by dry etching. During the process of plasma bombardment of the conductive layer 30, a bond will be generated, and the bond will remain on the groove wall of the first groove 31. The remaining bond is 40 is the polymer residue.
  • the depth of the formed first groove 31 can be controlled by controlling the time of dry etching, so that the depth of the first groove 31 is smaller than the thickness of the conductive layer 30 for subsequent use.
  • the polymer residue 40 on the wall of the first groove 31 is removed.
  • Step S103 Remove part of the conductive layer corresponding to the groove wall and groove bottom of the first groove to form conductive lines and a second groove between adjacent conductive lines.
  • the conductive lines 20 can be formed.
  • the formed conductive lines 20 are redistribution lines, and the grooves between adjacent conductive lines 20 are the third conductive lines 20. Two grooves 33.
  • the polymer residue 40 deposited on the groove wall of the first groove 31 can be removed, thereby avoiding subsequent filling of the passivation layer 80 in the second groove 33 sealing in advance (even if there is still polymer residue on the side wall of the second groove 33, the volume of the polymer residue is much smaller than the volume of the polymer residue in one dry etching shown in Figure 1), thereby avoiding A gap appears inside the passivation layer 80, which is beneficial to improving the performance of the semiconductor structure.
  • the conductive layer 30 corresponding to the groove wall and groove bottom of the first groove 31 is removed to form the conductive line 20 and the second groove 33 located between the adjacent conductive lines 20 , including: forming a second mask layer 60 on the conductive layer 30 , the second mask layer 60 having a second etching opening 61 , the second etching opening 61 facing the first groove 31 , and the second etching opening 61
  • the orthographic projection area on the substrate 10 is larger than the orthographic projection area of the first etching opening 51 on the substrate 10 .
  • the second mask layer 60 may cover the first mask layer 50 , and the second etching opening 61 faces the first groove 31 , and since the first etching opening 51 faces the first groove 31 , the second etching opening 61 faces the first etching opening 51, and the orthographic projection area of the second etching opening 61 on the substrate 10 is larger than the orthographic projection area of the first etching opening 51 on the substrate 10, so as to facilitate the subsequent removal of the first recess.
  • the portion of the conductive layer 30 corresponding to the groove wall of the groove 31 is removed together with the polymer residue 40 deposited on the groove wall of the first groove 31 .
  • forming the second mask layer 60 on the conductive layer 30 includes: after forming the first groove 31, shrinking the first mask layer 50 to increase the area of the first etching opening 51 on the substrate. 10, a second mask layer 60 and a second etching opening 61 located on the second mask layer 60 are formed.
  • the second mask layer 60 is also the first mask layer 50 after shrinkage processing. Since the orthographic projection area of the first etching opening 51 on the substrate 10 increases, that is, the second etching opening 51 is formed.
  • the orthographic projection area of the opening 61 on the substrate 10 is larger than the orthographic projection area of the first etching opening 51 on the substrate 10 , so that when subsequent etching is performed using the second mask layer 60 as a mask, not only the first groove 31 can be etched
  • the part of the conductive layer 30 corresponding to the groove bottom can also be etched to the part of the conductive layer 30 corresponding to the groove wall of the first groove 31, so as to facilitate the subsequent removal of the part of the conductive layer 30 corresponding to the groove wall of the first groove 31, so that the part of the conductive layer 30 corresponding to the groove wall of the first groove 31 can be deposited on the first groove 31.
  • the polymer residue 40 on the wall of a groove 31 is also removed.
  • shrinking the first mask layer 50 includes etching the first mask layer 50 to remove the sidewalls of the first etching opening 51 .
  • the orthographic projection area of the first etching opening 51 on the substrate 10 can be increased, thereby forming the second etching opening 61 , and the formed second etching opening 61 faces the first groove. 31.
  • the first mask layer 50 may be dry etched to remove the sidewalls of the first etching opening 51 .
  • the first mask layer 50 is overall thinned from the upper surface and sidewalls of the first mask layer 50 through dry etching to expand the first etching opening 51 to obtain the first etching opening 51 .
  • the second mask layer 60 ie, the thinned first mask layer
  • the second etching opening 61 ie, the expanded first etching opening located in the second mask layer 60.
  • the etching gas for dry etching may include at least one of oxygen, hydrogen, and nitrogen.
  • the conductive layer 30 corresponding to the groove wall and groove bottom of the first groove 31 is removed to form the conductive line 20 and the second groove 33 between the adjacent conductive lines 20 , and also includes : After the second mask layer 60 is formed, the conductive layer 30 is etched using the second mask layer 60 as a mask to form the conductive lines 20 and the second grooves 33 .
  • the portion of the conductive layer 30 corresponding to the groove bottom of the first groove 31 will continue to be etched until the etching penetrates the conductive layer 30 to form the conductive line 20 .
  • the conductive layer 30 corresponding to the groove wall of the first groove 31 will continue to be etched to remove the polymer residue 40 deposited on the groove wall of the first groove 31 to avoid subsequent filling in the second groove 33
  • the passivation layer 80 is sealed in advance to further avoid gaps inside the passivation layer 80 and is beneficial to improving the performance of the semiconductor structure.
  • the distance D between the second etching opening 61 and the groove wall of the first groove 31 may include 50 nm-100 nm.
  • the volume of the removed polymer residue 40 may be adjusted. , in order to further remove the polymer residue 40 deposited on the groove wall of the first groove 31 to avoid premature sealing when the passivation layer 80 is subsequently filled in the second groove 33, thereby further improving the semiconductor structure performance.
  • the conductive layer 30 is etched using the second mask layer 60 as a mask to form the second groove 33 , which further includes: etching the conductive layer 30 using the second mask layer 60 as a mask; Part of the base 10 forms a second groove 33 .
  • the bottom of the formed second groove 33 is the base 10
  • the groove wall of the formed second groove 33 includes the base 10 and the conductive layer 30 .
  • etching the conductive layer 30 using the second mask layer 60 as a mask further includes etching the conductive layer 30 by dry etching using the second mask layer 60 as a mask.
  • plasma is used to bombard the conductive layer 30.
  • the plasma can also bombard the polymer residue 40 on the groove wall of the first groove 31, so that the polymer residue 40 is broken into debris, thereby Further removal of polymer residue 40.
  • the polymer residue 40 is removed, and at the same time, new polymer residue 40 may be formed on the groove wall of the second groove 33.
  • the volume of the residue 40 is smaller than the volume of the polymer residue 40 on the first groove 31 , which can avoid premature sealing when the passivation layer 80 is subsequently filled in the second groove 33 , thereby improving the performance of the semiconductor structure.
  • Step S104 Form a passivation layer and fill it in the second groove.
  • forming the passivation layer 80 which before filling the second groove 33 , further includes: removing the second mask layer 60 .
  • the second mask layer 60 can be removed by cleaning with a cleaning solution.
  • a cleaning solution When etching the portion of the conductive layer 30 corresponding to the groove wall of the first groove 31 , debris of the polymer residue 40 deposited on the groove wall of the first groove 31 may fall to the bottom of the second groove 33 .
  • debris dropped on the bottom of the second groove 33 can be further removed, which is beneficial to further improving the performance of the semiconductor structure.
  • the passivation layer 80 and filling it in the second groove 33 also includes: after removing the second mask layer 60, forming an insulating layer 70 covering the conductive line 20 and the groove of the second groove 33. wall and tank bottom. By forming the insulating layer 70, adjacent conductive lines 20 can be isolated.
  • the material of the insulating layer 70 may include, for example, nitride, oxide, oxynitride, and the like.
  • a passivation layer 80 covering the insulating layer 70 may be formed.
  • the passivation layer 80 is filled in the second groove 33 , and the passivation layer 80 also covers the conductive line 20 .
  • the passivation layer 80 may be made of, for example, polyimide, thereby buffering stress and protecting the conductive line 20 .
  • the passivation layer 80 can also play a planarizing role.
  • the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which includes: providing a substrate 10 covered with a conductive layer 30; dry etching to remove part of the conductive layer 30 to form a first groove 31.
  • the first groove 31 The depth is less than the thickness of the conductive layer 30, and polymer residue 40 is formed on the groove wall of the first groove 31; the corresponding portion of the conductive layer 30 on the groove wall and groove bottom of the first groove 31 is removed to form the conductive line 20 and the conductive layer 30 located on the groove wall.
  • the second groove 33 between adjacent conductive lines 20 forms a passivation layer 80 , which is filled in the second groove 33 .
  • the polymer residue 40 deposited on the groove wall of the first groove 31 can be removed at the same time, thereby avoiding subsequent filling of the passivation layer in the second groove 33. Sealing in advance at 80 o'clock can further avoid the occurrence of gaps inside the passivation layer 80 , which is beneficial to improving the performance of the semiconductor structure.
  • the first mask layer 50 is used as a mask to etch the conductive layer 30 to form the first groove 31 , and further includes: the depth H1 of the first groove 31 is the conductive layer 30 Thickness 1/3-1/2 of H2.
  • the polymer residue 40 formed on the wall of the first groove 31 facilitates subsequent etching of the wall of the first groove 31 , and peeling off the first groove 31 is beneficial to further removing the polymer residue 40, thereby further improving the performance of the semiconductor structure.
  • the depth of the formed first groove 31 can also be adjusted by controlling the etching time.
  • the conductive layer 30 is etched to form the first groove 31.
  • the etching time may be a first period, and the corresponding groove walls and groove bottoms of the first groove 31 are removed.
  • the etching time of part of the conductive layer 30 to form the conductive line 20 and the second groove 33 can be a second period.
  • the sum of the first period and the second period is the total etching time.
  • the performance of the semiconductor structure can make the first period 1/3-1/2 of the total etching time.
  • the second groove 33 is formed through one shrinking process and one etching process, thereby removing the polymer residue 40 on the first groove 31 .
  • the corresponding portion of the conductive layer 30 on the groove wall and groove bottom of the first groove 31 is removed.
  • Forming the conductive line 20 and the second groove 33 may also include intermediate etching. By providing an intermediate etching step, it is advantageous to further remove the polymer residue 40 on the groove wall of the first groove 31 .
  • the intermediate etching step may include: forming an intermediate mask layer 90 on the conductive layer 30 .
  • the intermediate mask layer 90 has an intermediate etching opening 91 .
  • the intermediate etching opening 91 is disposed facing the first groove 31 .
  • the orthogonal projected area of the etching opening 91 on the substrate 10 is larger than the orthographic projected area of the first etching opening 51 on the substrate 10
  • the orthogonal projected area of the middle etching opening 91 on the substrate 10 is smaller than that of the second etching opening 61 on the substrate 10 Orthographic projection area.
  • forming the intermediate mask layer 90 on the conductive layer 30 includes: after forming the first groove 31 , shrinking the first mask layer 50 to increase the opening of the first etching opening 51 on the substrate 10 An intermediate mask layer 90 and an intermediate etching opening 91 located on the intermediate mask layer 90 are formed on the orthographic projection area.
  • the intermediate mask layer 90 is also the first mask layer 50 after the shrinkage process. Since the orthographic projection area of the first etching opening 51 on the substrate 10 increases, that is, the formed intermediate etching opening 91 has a larger area on the substrate 10 . The orthographic projection area is larger than the orthographic projection area of the first etching opening 51 on the substrate 10 , so that when subsequent etching is performed using the intermediate mask layer 90 as a mask, not only the portion of the conductive layer 30 corresponding to the groove bottom of the first groove 31 can be etched , it can also etch the part of the conductive layer 30 corresponding to the groove wall of the first groove 31, so as to facilitate the subsequent removal of the part of the conductive layer 30 corresponding to the groove wall of the first groove 31, thereby making the deposited on the groove wall of the first groove 31 Polymer residue 40 is also removed.
  • Shrinking the intermediate mask layer 90 includes etching the first mask layer 50 to remove the sidewalls of the first etching opening 51 .
  • the orthogonal projected area of the first etching opening 51 on the substrate 10 can be increased, thereby forming a middle etching opening 91 , and the formed middle etching opening 91 faces the first groove 31 .
  • the first mask layer 50 may be dry etched to remove the sidewalls of the first etching opening 51 .
  • the first mask layer 50 is overall thinned from the upper surface and sidewalls of the first mask layer 50 through dry etching to expand the first etching opening 51 to obtain the middle
  • the mask layer 90 ie, the thinned first mask layer
  • the middle etching opening 91 ie, the enlarged first etching opening located in the middle mask layer 90 .
  • the etching gas for dry etching may include at least one of oxygen, hydrogen, and nitrogen.
  • the intermediate etching step further includes: after forming the intermediate mask layer 90 , etching the conductive layer 30 using the intermediate mask layer 90 as a mask to form the intermediate groove 32 . It is worth noting that by removing part of the conductive layer 30 corresponding to the groove wall of the first groove 31, part of the polymer residue 301 deposited on the groove wall of the first groove 31 is also removed. At the same time, during the process During the etching process, polymer residue 301 will continue to be formed on the groove wall of the middle groove 32. At this time, the volume of the polymer residue 301 is smaller than before.
  • the depth of the middle groove 32 is greater than the depth of the first groove 31 and less than the depth of the second groove 33 .
  • a portion of the conductive layer 30 corresponding to the bottom of the first groove 31 is removed, so that the depth of the middle groove 32 is greater than the depth of the first groove 31 .
  • the bottom of the middle groove 32 is continued to be etched.
  • the depth of the middle groove 32 is smaller than the depth of the second groove 33 .
  • the depth of the formed intermediate groove 32 can be controlled by controlling the etching time.
  • removing the conductive layer 30 corresponding to the groove wall and the groove bottom of the first groove 31 to form the conductive line 20 and the second groove 33 also includes: removing The conductive layer 30 corresponds to the groove wall of the middle groove 32 and the groove bottom to form the conductive line 20 and the second groove 33 .
  • a second mask layer 60 is formed on the conductive layer 30.
  • the second mask layer 60 has a second etching opening 61, and the second etching opening 61 is disposed facing the middle groove 32.
  • the orthogonal projected area of the second etching opening 61 on the substrate 10 is larger than the orthogonal projected area of the middle etching opening 91 on the substrate 10 .
  • the conductive layer 30 is etched using the second mask layer 60 as a mask to form the conductive lines 20 and the second grooves 33 to completely remove the polymer residue 40 . Referring to FIG. 13 , after the polymer residue 40 is completely removed, a passivation layer 80 filled in the second groove 33 is formed.
  • the intermediate etching in the above embodiment can be performed multiple times.
  • the orthogonal projected area of the intermediate etching opening 91 on the substrate 10 is larger than the area of the intermediate etching opening 91 on the substrate 10 in the previous intermediate etching.
  • Orthographic projection area According to the volume of the polymer residue 40 formed on the first groove 31 , the polymer residue 40 can be further removed by adjusting the number of intermediate etching steps.
  • By enlarging the projected area of the conductive layer 30 of the intermediate etching opening 91 in each intermediate etching compared to the previous time it is possible to remove the portion of the conductive layer corresponding to the groove wall of the intermediate groove 32 in each intermediate etching. 30, thereby allowing the polymer residue 40 deposited on the groove wall of the middle groove 32 to be removed together.
  • each intermediate etching step can be implemented using the steps in the above embodiments, and will not be described again here.
  • Embodiments of the present disclosure also provide a semiconductor structure, which is formed by the above-mentioned manufacturing method of the semiconductor structure.
  • the manufacturing method of the semiconductor structure includes: providing a substrate 10 covered with a conductive layer 30; dry etching to remove part of the conductive layer 30 to form a first groove 31, the depth of the first groove 31 is less than the thickness of the conductive layer 30 , polymer residue 40 is formed on the groove wall of the first groove 31; the corresponding portion of the conductive layer 30 on the groove wall and groove bottom of the first groove 31 is removed to form the conductive line 20 and the third conductive line 20 between adjacent conductive lines 20.
  • the polymer residue 40 deposited on the groove wall of the first groove 31 can be removed at the same time, thereby avoiding subsequent filling of the passivation layer in the second groove 33. Sealing in advance at 80 o'clock can further avoid the occurrence of gaps inside the passivation layer 80 , which is beneficial to improving the performance of the semiconductor structure.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Les modes de réalisation de la présente divulgation se rapportent au domaine technique de la fabrication de semi-conducteurs et concernent en particulier un procédé de fabrication de structure semi-conductrice, et une structure semi-conductrice. Le procédé de fabrication de la structure semi-conductrice consiste à : utiliser un substrat qui est recouvert d'une couche conductrice ; graver et retirer une partie de la couche conductrice au moyen d'un procédé par voie sèche, de sorte à former une première rainure, la profondeur de la première rainure étant inférieure à l'épaisseur de la couche conductrice, et un résidu polymère se trouvant sur une paroi de rainure de la première rainure ; retirer une partie de la couche conductrice qui correspond à la paroi de rainure et au fond de rainure de la première rainure, de sorte à former des fils conducteurs et une seconde rainure située entre les fils conducteurs adjacents ; et former une couche de passivation venant remplir la seconde rainure. Au moyen du retrait d'une partie de la couche conductrice qui correspond à la paroi de rainure de la première rainure, le résidu polymère déposé sur la paroi de rainure de la première rainure peut également être retiré, de sorte que le scellage des orifices à l'avance soit évité lorsque la seconde rainure est ensuite remplie avec la couche de passivation, et des espaces se produisant dans la couche de passivation soient évités.
PCT/CN2022/087494 2022-04-11 2022-04-18 Procédé de fabrication de structure semi-conductrice, et structure semi-conductrice WO2023197340A1 (fr)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855017A (en) * 1985-05-03 1989-08-08 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
US6277752B1 (en) * 1999-06-28 2001-08-21 Taiwan Semiconductor Manufacturing Company Multiple etch method for forming residue free patterned hard mask layer
US20020166838A1 (en) * 2001-05-10 2002-11-14 Institute Of Microelectronics Sloped trench etching process
CN101106066A (zh) * 2006-07-10 2008-01-16 中芯国际集成电路制造(上海)有限公司 可去除刻蚀后残留聚合物的半导体器件制造方法
CN102249179A (zh) * 2010-05-20 2011-11-23 上海华虹Nec电子有限公司 改善微机电系统传感薄膜空腔侧壁坡度的干法刻蚀方法
CN105789134A (zh) * 2014-12-25 2016-07-20 中芯国际集成电路制造(上海)有限公司 一种半导体存储器件及其制备方法、电子装置
CN110875240A (zh) * 2018-09-04 2020-03-10 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构
CN111900128A (zh) * 2020-09-30 2020-11-06 晶芯成(北京)科技有限公司 一种金属互连结构的形成方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855017A (en) * 1985-05-03 1989-08-08 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
US6277752B1 (en) * 1999-06-28 2001-08-21 Taiwan Semiconductor Manufacturing Company Multiple etch method for forming residue free patterned hard mask layer
US20020166838A1 (en) * 2001-05-10 2002-11-14 Institute Of Microelectronics Sloped trench etching process
CN101106066A (zh) * 2006-07-10 2008-01-16 中芯国际集成电路制造(上海)有限公司 可去除刻蚀后残留聚合物的半导体器件制造方法
CN102249179A (zh) * 2010-05-20 2011-11-23 上海华虹Nec电子有限公司 改善微机电系统传感薄膜空腔侧壁坡度的干法刻蚀方法
CN105789134A (zh) * 2014-12-25 2016-07-20 中芯国际集成电路制造(上海)有限公司 一种半导体存储器件及其制备方法、电子装置
CN110875240A (zh) * 2018-09-04 2020-03-10 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构
CN111900128A (zh) * 2020-09-30 2020-11-06 晶芯成(北京)科技有限公司 一种金属互连结构的形成方法

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