WO2023189744A1 - プリント配線板用基板及びプリント配線板 - Google Patents

プリント配線板用基板及びプリント配線板 Download PDF

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Publication number
WO2023189744A1
WO2023189744A1 PCT/JP2023/010643 JP2023010643W WO2023189744A1 WO 2023189744 A1 WO2023189744 A1 WO 2023189744A1 JP 2023010643 W JP2023010643 W JP 2023010643W WO 2023189744 A1 WO2023189744 A1 WO 2023189744A1
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WO
WIPO (PCT)
Prior art keywords
copper plating
plating layer
main surface
conductive layer
base film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/010643
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English (en)
French (fr)
Japanese (ja)
Inventor
拓斗 部谷
勝成 御影
健太 今北
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to US18/695,592 priority Critical patent/US12604399B2/en
Priority to JP2024511830A priority patent/JP7666736B2/ja
Priority to CN202380013832.4A priority patent/CN118056476A/zh
Publication of WO2023189744A1 publication Critical patent/WO2023189744A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/422—Plated through-holes or plated via connections characterised by electroless plating method; pretreatment therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present disclosure relates to a printed wiring board substrate and a printed wiring board.
  • This application claims priority based on Japanese Patent Application No. 2022-053407, which is a Japanese patent application filed on March 29, 2022. All contents described in the Japanese patent application are incorporated herein by reference.
  • Patent Document 1 International Publication No. 2019/208077 (Patent Document 1) describes a printed wiring board substrate.
  • the printed wiring board substrate described in Patent Document 1 includes a base film, a first sintered body layer, a second sintered body layer, a first electroless copper plating layer, and a second electroless copper plating layer. have.
  • the base film has a first main surface and a second main surface.
  • the first sintered body layer and the second sintered body layer are arranged on the first main surface and the second main surface, respectively.
  • the first sintered body layer and the second sintered body layer are formed by sintering a plurality of copper particles.
  • the first electroless copper plating layer and the second electroless copper plating layer are arranged on the first sintered body layer and the second sintered body layer, respectively.
  • the printed wiring board substrate of the present disclosure includes a base film having a first main surface and a second main surface, a first conductive layer disposed on the first main surface, and a first conductive layer disposed on the second main surface. a second conductive layer disposed on the first conductive layer, a second electroless copper plating layer disposed on the second conductive layer, and a third electroless copper plating layer disposed on the first conductive layer. It is equipped with a plating layer.
  • a through hole is formed in the base film, passing through the base film in the thickness direction.
  • the third electroless copper plating layer is arranged on the inner wall surface of the through hole. The amount of palladium in the base film on the first main surface and the second main surface is smaller than the amount of palladium in the base film on the inner wall surface.
  • FIG. 1 is a cross-sectional view of a printed wiring board substrate 100.
  • FIG. 2 is a manufacturing process diagram of the printed wiring board substrate 100.
  • FIG. 3 is a sectional view illustrating the preparation step S1.
  • FIG. 4 is a cross-sectional view illustrating the conductive layer forming step S2.
  • FIG. 5 is a cross-sectional view illustrating the through hole forming step S3.
  • FIG. 6 is a cross-sectional view illustrating the catalyst application step S4.
  • FIG. 7 is a cross-sectional view illustrating the film peeling step S5.
  • FIG. 8 is a schematic configuration diagram of a plating apparatus 300 used in the electroless plating step S6.
  • FIG. 9 is a cross-sectional view illustrating the first step S61.
  • FIG. 10 is a cross-sectional view illustrating the second step S62.
  • FIG. 11 is a cross-sectional view of printed wiring board 200.
  • FIG. 12 is a manufacturing process diagram of the printed wiring board 200.
  • FIG. 13 is a cross-sectional view illustrating the resist pattern forming step S7.
  • FIG. 14 is a cross-sectional view illustrating the electrolytic plating step S8.
  • FIG. 15 is a cross-sectional view illustrating the resist pattern removal step S9.
  • FIG. 16 is a plan view of the first evaluation TEG.
  • FIG. 17 is a plan view of the second evaluation TEG.
  • FIG. 18 is a sectional view taken along line XVIII-XVIII in FIG. 17.
  • the present disclosure has been made in view of the problems of the prior art as described above. More specifically, the present disclosure provides a print that allows fine pitch wiring while ensuring continuity reliability between wiring formed on one main surface and wiring formed on the other main surface.
  • the present invention provides a substrate for a wiring board.
  • the printed wiring board substrate includes a base film having a first main surface and a second main surface, a first conductive layer disposed on the first main surface, and a first conductive layer disposed on the second main surface. a second conductive layer disposed on the first conductive layer; a first electroless copper plating layer disposed on the first conductive layer; a second electroless copper plating layer disposed on the second conductive layer; 3 electroless copper plating layers.
  • a through hole is formed in the base film, passing through the base film in the thickness direction.
  • the third electroless copper plating layer is arranged on the inner wall surface of the through hole.
  • the amount of palladium in the base film on the first main surface and the second main surface is smaller than the amount of palladium in the base film on the inner wall surface. According to the printed wiring board substrate of (1) above, while ensuring continuity reliability between the wiring formed on the first main surface and the wiring formed on the second main surface, fine pitch of the wiring is achieved. It is possible to
  • the amount of palladium in the base film on the first main surface and the second main surface may be 0.02 atomic percent or less.
  • the amount of palladium in the base film on the inner wall surface may be 0.06 atomic percent or more.
  • the amount of palladium in the base film on the first main surface and the second main surface may be 0.008 atomic percent or less.
  • the amount of palladium in the base film on the inner wall surface may be 0.07 atomic percent or more.
  • the first conductive layer and the second conductive layer may be layers containing a plurality of sintered copper particles.
  • the amount of palladium in the first conductive layer and the second conductive layer may be 0.08 atomic percent or less.
  • the amount of palladium in the first electroless copper plating layer and the second electroless copper plating layer is 0.07 atomic percent or less. Good too.
  • the amount of nickel in the base film on the first main surface and the second main surface is smaller than the amount of nickel in the base film on the inner wall surface. Good too.
  • the printed wiring board according to the embodiment includes a base film having a first main surface and a second main surface, a first conductive layer disposed on the first main surface, and a first conductive layer disposed on the first conductive layer.
  • a first wiring having a first electroless copper plating layer disposed on the first electroless copper plating layer; and a first electrolytic copper plating layer disposed on the first electroless copper plating layer;
  • a second wiring having a second conductive layer, a second electroless copper plating layer disposed on the second conductive layer, and a second electrolytic copper plating layer disposed on the second electroless copper plating layer; , a third electroless copper plating layer, and a third electrolytic copper plating layer.
  • a through hole is formed in the base film, passing through the base film in the thickness direction.
  • the third electroless copper plating layer is arranged on the inner wall surface of the through hole.
  • the third electrolytic copper plating layer is disposed on the third electroless copper plating layer.
  • the first wiring is electrically connected to the second wiring through a third electroless copper plating layer and a third electrolytic copper plating layer.
  • the amount of palladium in the base film on the first main surface and the second main surface is smaller than the amount of palladium in the base film on the inner wall surface. According to the printed wiring board of (8) above, it is possible to make the first wiring and the second wiring fine pitch while ensuring continuity reliability between the first wiring and the second wiring.
  • the distance between the two parts of the first wiring that are adjacent to each other with a gap between them and the distance between the parts of the second wiring that are adjacent to each other with a gap between them are as follows: It may be 20 ⁇ m or less.
  • the printed wiring board substrate and the printed wiring board according to the embodiment are referred to as a printed wiring board substrate 100 and a printed wiring board 200, respectively.
  • FIG. 1 is a cross-sectional view of a printed wiring board substrate 100.
  • the printed wiring board substrate 100 includes a base film 10, a first conductive layer 21, a second conductive layer 22, a first electroless copper plating layer 31, and a second electroless copper plating layer. 32 and a third electroless copper plating layer 33.
  • the base film 10 has a first main surface 10a and a second main surface 10b.
  • the first main surface 10a and the second main surface 10b are end faces of the base film 10 in the thickness direction.
  • the second main surface 10b is the opposite surface to the first main surface 10a.
  • a through hole 10c is formed in the base film 10.
  • the through hole 10c penetrates the base film 10 along the thickness direction.
  • the base film 10 is made of a flexible insulating material.
  • the base film 10 is made of, for example, polyimide, liquid crystal polymer, fluororesin, or the like. However, the constituent materials of the base film 10 are not limited to these.
  • the amount of palladium in the base film 10 on the first main surface 10a and the second main surface 10b is smaller than the amount of palladium in the base film 10 on the inner wall surface of the through hole 10c.
  • the amount of nickel in the base film 10 on the first main surface 10a and the second main surface 10b may be smaller than the amount of nickel in the base film 10 on the inner wall surface of the through hole 10c.
  • the amount of palladium in the base film 10 on the first main surface 10a and the second main surface 10b may be 0.02 atomic percent or less.
  • the amount of palladium in the base film 10 on the first main surface 10a and the second main surface 10b may be 0.008 atomic percent or less.
  • the amount of palladium in the base film 10 on the inner wall surface of the through hole 10c may be 0.06 atomic percent or more.
  • the amount of palladium in the base film 10 on the inner wall surface of the through hole 10c may be 0.07 atomic percent or more.
  • the amount of palladium in the base film 10 is measured by an energy dispersive X-ray analyzer (for example, SU8020 manufactured by Hitachi High-Technologies, Ltd.).
  • the accelerating voltage during measurement is 6 kV.
  • the measurement position of the amount of palladium in the base film 10 on the first main surface 10a is an arbitrary area up to a position where the distance from the interface with the first conductive layer 21 is 100 nm.
  • the measurement position of the amount of palladium in the base film 10 on the second main surface 10b is an arbitrary area up to a position where the distance from the interface with the second conductive layer 22 is 100 nm.
  • the measurement position of the amount of palladium in the base film 10 on the inner wall surface of the through hole 10c is an arbitrary area up to a position at a distance of 100 nm from the interface with the third electroless copper plating layer 33.
  • the amount of nickel in the base film 10 is measured by the same method as the amount of palladium in the base film 10.
  • the first conductive layer 21 is arranged on the first main surface 10a.
  • the first conductive layer 21 is formed of a plurality of sintered copper particles. Therefore, the first conductive layer 21 is porous.
  • the average particle size of the copper particles included in the first conductive layer 21 may be 1 nm or more or 30 nm or more.
  • the average particle size of the copper particles included in the first conductive layer 21 may be 100 nm or less or 500 nm or less. That is, the copper particles contained in the first conductive layer 21 may be nano-copper particles. Note that the average particle size of the copper particles contained in the first conductive layer 21 is measured by a particle size distribution measuring device (for example, Microtrac particle size distribution meter UPA-150EX manufactured by Nikkiso Co., Ltd.).
  • the second conductive layer 22 is arranged on the second main surface 10b.
  • the second conductive layer 22 is formed of a plurality of sintered copper particles. Therefore, the second conductive layer 22 is porous.
  • the average particle size of the copper particles contained in the second conductive layer 22 may be 1 nm or more or 30 nm or more.
  • the average particle size of the copper particles contained in the second conductive layer 22 may be 100 nm or less or 500 nm or less. That is, the copper particles contained in the second conductive layer 22 may be nano-copper particles. Note that the average particle size of the copper particles contained in the second conductive layer 22 is measured by the same method as the average particle size of the copper particles contained in the first conductive layer 21.
  • the amount of palladium in the first conductive layer 21 and the second conductive layer 22 may be 0.08 atomic percent or less.
  • the amount of palladium in the first conductive layer 21 and the second conductive layer 22 may be 0 atomic percent. Expressing this from another perspective, palladium may not be contained in the first conductive layer 21 and the second conductive layer 22.
  • the amount of palladium in the first conductive layer 21 includes the entire thickness direction from the interface between the base film 10 and the first conductive layer 21 to the interface between the first conductive layer 21 and the first electroless copper plating layer 31. This is the palladium content in any given region.
  • the amount of palladium in the second conductive layer 22 is determined by an arbitrary amount including the entire thickness direction from the interface between the base film 10 and the second conductive layer 22 to the interface between the second conductive layer 22 and the second electroless copper plating layer 32. Palladium content in the area.
  • the amount of palladium in the first conductive layer 21 and the amount of palladium in the second conductive layer 22 are measured by the same method as the amount of palladium in the base film 10 except for the measurement area.
  • a through hole 21a is formed in the first conductive layer 21, passing through the first conductive layer 21 along the thickness direction.
  • a through hole 22a is formed in the second conductive layer 22, passing through the second conductive layer 22 in the thickness direction.
  • the through hole 21a and the through hole 22a overlap the through hole 10c in plan view.
  • the inner wall surface of the through hole 21a and the inner wall surface of the through hole 22a are continuous with the inner wall surface of the through hole 10c.
  • the constituent material of the first conductive layer 21 and the second conductive layer 22 is a sintered body of copper particles, but the first conductive layer 21 and the second conductive layer 22 are It is not limited to layers composed of solid bodies.
  • the first electroless copper plating layer 31 is arranged on the first conductive layer 21.
  • the first electroless copper plating layer 31 is a copper layer formed by electroless plating.
  • the amount of palladium in the first electroless copper plating layer 31 may be 0.07 atomic percent or less.
  • the second electroless copper plating layer 32 is disposed on the second conductive layer 22.
  • the second electroless copper plating layer 32 is a copper layer formed by electroless plating.
  • the amount of palladium in the second electroless copper plating layer 32 may be 0.07 atomic percent or less.
  • the amount of palladium in the first electroless copper plating layer 31 is determined from the interface between the first conductive layer 21 and the first electroless copper plating layer 31 to the side of the first electroless copper plating layer 31 opposite to the interface.
  • the amount of palladium in the second electroless copper plating layer 32 is determined from the interface between the second conductive layer 22 and the second electroless copper plating layer 32 to the surface of the second electroless copper plating layer 32 opposite to the interface. This is the palladium content in any region including the entire thickness direction.
  • the amount of palladium in the first electroless copper plating layer 31 and the amount of palladium in the second electroless copper plating layer 32 are measured by the same method as the amount of palladium in the base film 10, except for the measurement area.
  • the third electroless copper plating layer 33 is arranged on the inner wall surface of the through hole 10c.
  • the third electroless copper plating layer 33 is also arranged on the inner wall surface of the through hole 21a and on the inner wall surface of the through hole 22a.
  • the third electroless copper plating layer 33 is a copper layer formed by electroless plating. Note that the first electroless copper plating layer 31, the second electroless copper plating layer 32, and the third electroless copper plating layer 33 may contain nickel.
  • Method for manufacturing printed wiring board substrate 100 A method for manufacturing printed wiring board substrate 100 will be described below.
  • FIG. 2 is a manufacturing process diagram of the printed wiring board substrate 100.
  • the method for manufacturing the printed wiring board substrate 100 includes a preparation step S1, a conductive layer forming step S2, a through hole forming step S3, a catalyst applying step S4, a film peeling step S5, It has an electroless plating step S6.
  • the conductive layer forming step S2 is performed after the preparation step S1.
  • the through hole forming step S3 is performed after the conductive layer forming step S2.
  • the catalyst application step S4 is performed after the through hole forming step S3.
  • the film peeling step S5 is performed after the catalyst application step S4.
  • Electroless plating step S6 is performed after film peeling step S5.
  • FIG. 3 is a cross-sectional view illustrating the preparation step S1.
  • the base film 10 is prepared.
  • the first conductive layer 21 and the first electroless copper plating layer 31 are not arranged on the first main surface 10a, and the second conductive layer 31 is not arranged on the second main surface 10b.
  • Layer 22 and second electroless copper plating layer 32 are not disposed.
  • the through hole 10c is not formed in the base film 10 prepared in the preparation step S1.
  • FIG. 4 is a cross-sectional view illustrating the conductive layer forming step S2.
  • the first conductive layer 21 and the second conductive layer 22 are formed on the first main surface 10a and the second main surface 10b, respectively.
  • a paste containing copper particles is applied onto the first main surface 10a and the second main surface 10b.
  • the solvent contained in the applied paste is dried.
  • the dried paste is fired. Thereby, the copper particles contained in the dried paste are sintered with each other, and the first conductive layer 21 and the second conductive layer 22 are formed.
  • the surface of the first conductive layer 21 (the surface of the first conductive layer 21 opposite to the first main surface 10a) and the second conductive layer 22 are A degreasing process and a pickling process are performed on the surface (the surface of the second conductive layer 22 opposite to the second main surface 10b).
  • FIG. 5 is a cross-sectional view illustrating the through-hole forming step S3.
  • through holes 10c are formed in the base film 10.
  • a masking film 41 and a masking film 42 are placed on the first conductive layer 21 and the second conductive layer 22, respectively.
  • the base film 10, the first conductive layer 21, the second conductive layer 22, the masking film 41, and the masking film 42 are irradiated with the laser L.
  • a through hole 10c is formed in the base film 10.
  • a through hole 21a is formed in the first conductive layer 21, and a through hole 22a is formed in the second conductive layer 22.
  • a through hole 41a and a through hole 42a are also formed in the masking film 41 and the masking film 42, respectively.
  • FIG. 6 is a cross-sectional view illustrating the catalyst application step S4.
  • the catalyst application step S4 on the inner wall surface of the through hole 10c, on the inner wall surface of the through hole 21a, on the inner wall surface of the through hole 22a, on the inner wall surface of the through hole 41a, and on the inner wall surface of the through hole 42a.
  • a palladium catalyst 43 is applied on the inner wall surface. Note that the palladium catalyst 43 is also provided on the masking film 41 and the masking film 42.
  • FIG. 7 is a cross-sectional view illustrating the film peeling step S5. As shown in FIG. 7, in the film peeling step S5, the masking film 41 is peeled off from the first conductive layer 21, and the masking film 42 is peeled from the second conductive layer 22.
  • the electroless plating step S6 is performed using the plating apparatus 300.
  • FIG. 8 is a schematic configuration diagram of a plating apparatus 300 used in the electroless plating step S6. As shown in FIG. 8, the plating apparatus 300 includes a plating tank 310, a plurality of rollers 320, an electrode roller 331 and an electrode roller 332, and a power source 340.
  • a plating solution is stored in the plating treatment tank 310.
  • the plating solution contains copper. Further, the plating solution may contain nickel.
  • An electrode 311 is arranged inside the plating tank 310.
  • the electrode 311 is made of a conductive material.
  • the electrode 311 is made of titanium, for example. Electrode 311 is immersed in a plating solution.
  • the plurality of rollers 320 are lined up along the conveyance direction of the base film 10 (see arrow in FIG. 8). By rotating the plurality of rollers 320, the base film 10 is transported along the transport direction. During the transportation process, the base film 10 passes through a plating solution stored in a plating tank 310.
  • the electrode roller 331 and the electrode roller 332 are arranged at positions where they contact the base film 10 before passing through the plating solution. Electrode roller 331 and electrode roller 332 are in contact with first conductive layer 21 and second conductive layer 22, respectively.
  • the electrode roller 331 and the electrode roller 332 are made of stainless steel, for example.
  • the power source 340 is electrically connected to the electrode 311 and the electrode rollers 331 and 332. More specifically, the positive electrode of the power source 340 is electrically connected to the electrode 311, and the negative electrode of the power source 340 is electrically connected to the electrode roller 331 and the electrode roller 332.
  • the electroless plating step S6 includes a first step S61 and a second step S62 performed after the first step S61.
  • the power supply 340 energizes between the electrode 311 and the electrode rollers 331 and 332.
  • FIG. 9 is a cross-sectional view illustrating the first step S61. As shown in FIG. 9, driven by the electrical energy accompanying this energization, the first electroless copper plating layer 31 and the second electroless copper plating layer 32 are formed on the surface of the first conductive layer 21 and the second electroless copper plating layer 32, respectively. It is rapidly formed on the surface of the second conductive layer 22.
  • FIG. 10 is a cross-sectional view illustrating the second step S62.
  • the electricity supply between the electrode 311 and the electrode rollers 331 and 332 is stopped.
  • the first electroless copper plating layer 31 and the second electroless copper plating layer 32 are formed in the first step S61, as shown in FIG. Even if it is not used, the growth of the first electroless copper plating layer 31 and the second electroless copper plating layer 32 continues.
  • the palladium catalyst 43 is provided on the inner wall surface of the through hole 10c, the inner wall surface of the through hole 21a, and the inner wall surface of the through hole 22a. Therefore, as shown in FIG. 9 and FIG. 10, in the first step S61 and the second step S62, the palladium catalyst 43 is driven to perform the process on the inner wall surface of the through hole 10c, on the inner wall surface of the through hole 21a, and on the inner wall surface of the through hole 21a.
  • a third electroless copper plating layer 33 is grown on the inner wall surface of 22a.
  • printed wiring board substrate 100 having the structure shown in FIG. 1 is manufactured.
  • annealing may be performed after the electroless plating step S6 is performed.
  • FIG. 11 is a cross-sectional view of the printed wiring board 200.
  • the printed wiring board 200 has a base film 10, a first wiring 51, and a second wiring 52, as shown in FIG.
  • the normal direction of the first main surface 10a (second main surface 10b) is defined as a first direction DR1.
  • a direction perpendicular to the first direction DR1 is defined as a second direction DR2.
  • a direction perpendicular to the first direction DR1 and the second direction DR2 is defined as a third direction DR3.
  • the first wiring 51 is arranged on the first main surface 10a.
  • the first wiring 51 includes a first conductive layer 21 disposed on the first main surface 10a, a first electroless copper plating layer 31 disposed on the first conductive layer 21, and a first electroless copper plating layer 31 disposed on the first conductive layer 21.
  • a first electrolytic copper plating layer 61 is disposed on the plating layer 31.
  • the first electrolytic copper plating layer 61 is a copper layer formed by electrolytic plating.
  • the second wiring 52 is arranged on the second main surface 10b.
  • the second wiring 52 includes a second conductive layer 22 disposed on the second main surface 10b, a second electroless copper plating layer 32 disposed on the second conductive layer 22, and a second electroless copper plating layer 32 disposed on the second conductive layer 22.
  • a second electrolytic copper plating layer 62 is disposed on the plating layer 32.
  • the second electrolytic copper plating layer 62 is a copper layer formed by electrolytic plating.
  • the printed wiring board 200 further includes a third electrolytic copper plating layer 63.
  • the third electrolytic copper plating layer 63 is arranged on the third electroless copper plating layer 33.
  • the first wiring 51 and the second wiring 52 are electrically connected to each other by the third electroless copper plating layer 33 and the third electrolytic copper plating layer 63.
  • the first wiring 51 has a plurality of wiring parts 51a.
  • the wiring portion 51a extends along the second direction DR2.
  • the plurality of wiring parts 51a are lined up along the third direction DR3.
  • the distance in the third direction DR3 between two adjacent wiring parts 51a is defined as a distance DIS1.
  • the distance DIS1 may be 20 ⁇ m or less.
  • the distance DIS1 may be 10 ⁇ m or less.
  • the second wiring 52 has a plurality of wiring parts 52a.
  • the wiring portion 52a extends along the second direction DR2.
  • the plurality of wiring parts 52a are lined up along the third direction DR3.
  • the distance in the third direction DR3 between two adjacent wiring sections 52a is defined as a distance DIS2.
  • the distance DIS2 may be 20 ⁇ m or less.
  • the distance DIS2 may be 10 ⁇ m or less.
  • FIG. 12 is a manufacturing process diagram of the printed wiring board 200. As shown in FIG. 12, the method for manufacturing printed wiring board 200 includes a resist pattern forming step S7, an electrolytic plating step S8, a resist pattern removing step S9, and an etching step S10.
  • the electrolytic plating step S8 is performed after the resist pattern forming step S7.
  • the resist pattern removal step S9 is performed after the electrolytic plating step S8.
  • Etching step S10 is performed after resist pattern removal step S9.
  • Printed wiring board 200 is formed using printed wiring board substrate 100.
  • FIG. 13 is a cross-sectional view illustrating the resist pattern forming step S7.
  • a resist pattern 71 and a resist pattern 72 are formed on the first electroless copper plating layer 31 and the second electroless copper plating layer 32, respectively.
  • the resist pattern 71 has an opening 71a.
  • the opening 71a penetrates the resist pattern 71 along the thickness direction.
  • the first electroless copper plating layer 31 is exposed through the opening 71a.
  • the resist pattern 72 has an opening 72a.
  • the opening 72a penetrates the resist pattern 72 along the thickness direction.
  • the second electroless copper plating layer 32 is exposed from the opening 72a.
  • first electroless copper plating layer 31 around the through hole 10c is exposed from the opening 71a
  • second electroless copper plating layer 32 around the through hole 10c is exposed from the opening 72a. are doing.
  • a resist is pasted on the first electroless copper plating layer 31 and the second electroless copper plating layer 32.
  • the pasted resist is exposed and developed.
  • the remaining portions of the resist that were not removed become a resist pattern 71 and a resist pattern 72, and the portions of the resist that were removed become an opening 71a and an opening 72a.
  • FIG. 14 is a cross-sectional view illustrating the electrolytic plating step S8.
  • the first electrolytic copper plating layer 61 is formed on the first electroless copper plating layer 31 exposed from the opening 71a, and the first electrolytic copper plating layer 61 is formed on the first electroless copper plating layer 31 exposed from the opening 72a.
  • a second electrolytic copper plating layer 62 is formed on the second electroless copper plating layer 32.
  • a third electrolytic copper plating layer 63 is formed on the third electroless copper plating layer 33.
  • the first electrolytic copper plating layer 61, the second electrolytic copper plating layer 62, and the third electrolytic copper plating layer 63 are formed in a plating solution containing copper. It is formed by applying electricity to the third electroless copper plating layer 33 to perform electrolytic plating.
  • FIG. 15 is a cross-sectional view illustrating the resist pattern removal step S9.
  • the resist pattern 71 is removed from above the first electroless copper plating layer 31, and the resist pattern 72 is removed from above the second electroless copper plating layer 32. Ru.
  • the first electroless copper plating layer 31 and the first conductive layer 21 are exposed between the two adjacent first electrolytic copper plating layers 61, and the first electrolytic copper plating layer 21 is exposed between the two adjacent second electrolytic copper plating layers 61.
  • the second electroless copper plating layer 32 and the second conductive layer 22 are exposed between the holes 62 .
  • etching process S10 the portions of the first electroless copper plating layer 31 and the first conductive layer 21 exposed between the two adjacent first electrolytic copper plating layers 61 and the portions of the two adjacent second electrolytic copper plating layers 61 are removed. Portions of the second electroless copper plating layer 32 and the second conductive layer 22 exposed between the electrolytic copper plating layers 62 are removed by etching. Through the above steps, a printed wiring board 200 having the structure shown in FIG. 11 is formed.
  • the amount of palladium in the base film 10 on the inner wall surface of the through hole 10c is large. That is, in the printed wiring board substrate 100, the third electroless copper plating layer 33 is formed using a palladium catalyst 43. Therefore, in the printed wiring board 200 formed using the printed wiring board substrate 100, reliability of conduction between the first wiring 51 and the second wiring 52 is ensured.
  • the masking film 41 is placed on the first conductive layer 21, and the masking film 42 is placed on the second conductive layer 22.
  • the palladium catalyst 43 is not applied to the surface of the first conductive layer 21 and the surface of the second conductive layer 22.
  • the amount of palladium in the base film 10 on the first main surface 10a and the second main surface 10b is smaller than the amount of palladium in the base film 10 on the inner wall surface of the through hole 10c. There is.
  • the first electroless copper plating layer 31 and the second electroless copper plating layer 32 are grown on the first conductive layer 21 and the second conductive layer 22, respectively. Further, in the first step S61, the first electroless copper plating layer 31 and the second electroless copper plating layer 32 are rapidly grown on the surface of the first conductive layer 21 and the second conductive layer 22, respectively. Therefore, nickel in the plating solution does not easily reach the first conductive layer 21 and the first main surface 10a thereunder, and the second conductive layer 22 and the second main surface 10b thereunder.
  • the inner wall surface of the through hole 10c comes into contact with the plating solution.
  • the third electroless copper plating layer 33 on the inner wall surface of the through hole 10c is not an electroless copper plating layer that rapidly grows by being driven by electrical energy due to energization, but is driven by a palladium catalyst 43. This is a growing electroless copper plating layer. Therefore, the amount of nickel in the base film 10 on the first main surface 10a and the second main surface 10b is smaller than the amount of nickel in the base film 10 on the inner wall surface of the through hole 10c.
  • the etching step S10 is not performed. Undercutting of the first wiring 51 and the second wiring 52 is less likely to occur when the first wiring 51 and the second wiring 52 are placed at a fine pitch.
  • the undercut of the first wiring 51 refers to a notch that occurs between the first electroless copper plating layer 31 and the first electrolytic copper plating layer 61 on the side surface of the first wiring 51.
  • the undercut of the second wiring 52 refers to a notch that occurs between the second electroless copper plating layer 32 and the second electrolytic copper plating layer 62 on the side surface of the second wiring 52.
  • the first wiring 51 and the second wiring 52 can be connected to each other while ensuring continuity reliability between the first wiring 51 and the second wiring 52. It is possible to make the wiring 52 fine pitch.
  • FIG. 16 is a plan view of the first evaluation TEG.
  • the first evaluation TEG includes a base film 10 and a first wiring 51.
  • the first main surface 10a has 20 wiring formation regions R1, 20 wiring formation regions R2, and 20 wiring formation regions R3.
  • the 20 wiring formation regions R1, the 20 wiring formation regions R2, and the 20 wiring formation regions R3 are arranged in a row along the left-right direction.
  • a first wiring 51 having a plurality of wiring parts 51a is formed on the wiring formation region R1, the wiring formation region R2, and the wiring formation region R3.
  • the wiring portion 51a formed on the wiring formation region R1 extends in the vertical direction.
  • the wiring portion 51a formed on the wiring formation region R2 and the wiring portion 51a formed on the wiring formation region R3 are arranged along directions inclined at 45° and ⁇ 45° with respect to the vertical direction, respectively. Extending.
  • the L/S of the wiring portion 51a formed on the wiring formation region R1 located at the nth position from the right is n ⁇ m/n ⁇ m.
  • L is the width of the wiring portion 51a
  • S is the distance DIS1.
  • the L/S of the wiring portion 51a formed on the wiring formation region R2 and the wiring portion 51a formed on the wiring formation region R3 is changed.
  • the aspect ratio of the wiring portion 51a (the value obtained by dividing the height of the wiring portion 51a by the width of the wiring portion 51a) was set to be 1 or more and 2 or less.
  • the evaluation was given as A when the minimum value of the width and distance DIS1 of the wiring portion 51a that can be formed appropriately was 10 ⁇ m or less.
  • the evaluation was given as B.
  • the evaluation was given as C.
  • the evaluation was given as D when the minimum value of the width and distance DIS1 of the wiring portion 51a that can be appropriately formed was more than 30 ⁇ m.
  • FIG. 17 is a plan view of the second evaluation TEG.
  • FIG. 18 is a sectional view taken along line XVIII-XVIII in FIG. 17.
  • the second evaluation TEG includes a base film 10, a first wiring 51, a second wiring 52, a third electroless copper plating layer 33, and a third electrolytic copper plating layer. 63.
  • the amount of palladium in the base film 10 on the first main surface 10a and the second main surface 10b is 0.02 atomic percent or less, and the amount of palladium in the base film 10 on the inner wall surface of the through hole 10c is 0.06 atomic percent. If it is at least atomic percent, the first wiring 51 and the second wiring 52 can be formed at a fine pitch while ensuring continuity reliability between the first wiring 51 and the second wiring 52.
  • the first electroless copper plating layer 31, the second electroless copper plating layer 32, and the third electroless copper plating layer 33 When forming the first electroless copper plating layer 31, the second electroless copper plating layer 32, and the third electroless copper plating layer 33 by an electroless plating method using a palladium catalyst 43, the first main surface 10a and the second electroless copper plating layer The amount of palladium in the base film 10 on the main surface 10b is approximately the same as the amount of palladium in the base film 10 on the inner wall surface of the through hole 10c. Therefore, when the first electroless copper plating layer 31, the second electroless copper plating layer 32, and the third electroless copper plating layer 33 are formed by such a method, the connection between the first wiring 51 and the second wiring 52 is It is not possible to achieve a fine pitch between the first wiring 51 and the second wiring 52 while ensuring continuity reliability between them.
  • the third electroless copper plating layer 33 is formed by an electroless plating method using a palladium catalyst 43
  • the first electroless copper plating layer 31 and the second electroless copper plating layer The plating layer 32 is formed by an electroless plating method using electricity without using a palladium catalyst 43. Therefore, in the printed wiring board substrate 100, the amount of palladium in the base film 10 on the first main surface 10a and the second main surface 10b can be made smaller than the amount of palladium in the base film 10 on the inner wall surface of the through hole 10c. This is possible, and the first wiring 51 and the second wiring 52 can be formed at a fine pitch while ensuring continuity reliability between the first wiring 51 and the second wiring 52.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
PCT/JP2023/010643 2022-03-29 2023-03-17 プリント配線板用基板及びプリント配線板 Ceased WO2023189744A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US18/695,592 US12604399B2 (en) 2022-03-29 2023-03-17 Substrate for printed wiring board and printed wiring board
JP2024511830A JP7666736B2 (ja) 2022-03-29 2023-03-17 プリント配線板用基板及びプリント配線板
CN202380013832.4A CN118056476A (zh) 2022-03-29 2023-03-17 印刷布线板用基板以及印刷布线板

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JP2022053407 2022-03-29

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03201592A (ja) * 1989-12-28 1991-09-03 Hitachi Chem Co Ltd プリント配線板の製造法
JP2003158364A (ja) * 2001-11-22 2003-05-30 Hitachi Chem Co Ltd プリント配線板の製造方法
JP2016058545A (ja) * 2014-09-09 2016-04-21 住友電気工業株式会社 プリント配線板用基板、プリント配線板及びプリント配線板用基板の製造方法
JP2017098422A (ja) * 2015-11-25 2017-06-01 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP2019197851A (ja) * 2018-05-11 2019-11-14 住友電気工業株式会社 プリント配線板及びプリント配線板の製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57177966A (en) 1981-04-24 1982-11-01 Fujitsu Ltd Plating method for printed wiring board
JP4137279B2 (ja) 1999-04-23 2008-08-20 イビデン株式会社 プリント配線板及びその製造方法
JP2004095972A (ja) * 2002-09-03 2004-03-25 Sumitomo Metal Electronics Devices Inc プラスチックパッケージの製造方法
US8119920B2 (en) * 2004-02-04 2012-02-21 Ibiden Co., Ltd. Multilayer printed wiring board
US7834273B2 (en) * 2005-07-07 2010-11-16 Ibiden Co., Ltd. Multilayer printed wiring board
KR101119308B1 (ko) * 2009-02-03 2012-03-19 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US8756804B2 (en) * 2010-09-29 2014-06-24 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing printed circuit board
JP6406598B2 (ja) * 2014-07-24 2018-10-17 学校法人福岡大学 プリント配線板及びその製造方法
JP6816486B2 (ja) * 2016-12-07 2021-01-20 凸版印刷株式会社 コア基板、多層配線基板、半導体パッケージ、半導体モジュール、銅張基板、及びコア基板の製造方法
WO2019208077A1 (ja) 2018-04-26 2019-10-31 住友電気工業株式会社 プリント配線板用基材及びプリント配線板用基材の製造方法
WO2022075239A1 (ja) 2020-10-09 2022-04-14 住友電気工業株式会社 プリント回路用基材、プリント回路、及びプリント回路用基材の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03201592A (ja) * 1989-12-28 1991-09-03 Hitachi Chem Co Ltd プリント配線板の製造法
JP2003158364A (ja) * 2001-11-22 2003-05-30 Hitachi Chem Co Ltd プリント配線板の製造方法
JP2016058545A (ja) * 2014-09-09 2016-04-21 住友電気工業株式会社 プリント配線板用基板、プリント配線板及びプリント配線板用基板の製造方法
JP2017098422A (ja) * 2015-11-25 2017-06-01 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP2019197851A (ja) * 2018-05-11 2019-11-14 住友電気工業株式会社 プリント配線板及びプリント配線板の製造方法

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US12604399B2 (en) 2026-04-14
JPWO2023189744A1 (https=) 2023-10-05

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