Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
  • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
  • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
  • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
  • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
  • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

• the present disclosure relates to a display device and a method for driving the same.
• Display devices using self-luminous elements such as organic EL (Electro-luminescence) elements are known. Light emission brightness is adjusted by controlling the current flowing through the self-luminous element using a drive transistor.
• organic EL Electro-luminescence
• the threshold voltage of the drive transistor may vary due to manufacturing reasons. When the threshold voltage fluctuates, variations in screen brightness occur and image quality deteriorates. For this reason, in pixel circuits using self-luminous elements, it is common to correct the threshold voltage of the drive transistor before causing the self-luminous elements to emit light (see Patent Document 1).
• a driving method in which the threshold voltage of the driving transistor of each pixel is corrected, and then a pixel signal voltage is written to the gate of the driving transistor. If the threshold voltages of the drive transistors of all pixels are corrected at the same timing, and then the pixel signal voltage is written for each pixel row, the timing to start writing the pixel signal voltage for each pixel row will be Since the threshold voltages are different, the threshold voltage correction periods for each pixel row will also be different, causing a difference in luminance between the upper end and the lower end of the display device, which may cause shading to be visually recognized. Therefore, the present disclosure provides a display device that can improve display quality and a method for driving the same.
• a pixel array in which a plurality of pixel groups including two or more pixels arranged in a first direction are arranged in a second direction intersecting the first direction.
• Department and a light emitting element provided in each pixel in the pixel array section; a first transistor provided in each pixel in the pixel array section and controlling light emission brightness of the light emitting element; a first capacitor provided in each pixel in the pixel array section and connected between the gate and source of the first transistor; After performing a first correction process that simultaneously corrects the threshold voltages of the first transistors in the plurality of pixel groups, restoring the source-gate voltage of the first transistor to the voltage before starting the first correction process.
• a display device including a display control unit that supplies voltage.
• the correction of the threshold voltage of the first transistor of each pixel may be completed by the second correction process.
• the length of the period of the first correction process is different for each of the plurality of pixel groups arranged in the second direction,
• the length of the period of the second correction process may be substantially the same for the plurality of pixel groups.
• the display control section includes: Immediately before the first correction processing period, an offset voltage is temporarily supplied to the gates of the first transistors in the plurality of pixel groups to temporarily connect the sources to the first reference voltage node; During the period of the first correction process, the supply of the offset voltage to the gate of the first transistor may be cut off, and the connection between the source of the first transistor and the first reference voltage node may be cut off. good.
• the display control unit sequentially drives each of the plurality of pixel groups to temporarily connect the source of the first transistor in the pixel group to be driven to a first reference voltage node, and then During the second correction process, the threshold voltage of the first transistor may be corrected by disconnecting the source of the first transistor from the first reference voltage node.
• the display control unit may match the source-gate voltage of the first transistor in the pixel group to be driven with the threshold voltage of the first transistor during the period of the second correction process.
• the display control section simultaneously raises the source voltage of the first transistors in the plurality of pixel groups, and
• the light emitting elements in the pixel group may simultaneously emit light at a brightness that corresponds to the pixel signal voltage.
• the display control unit may start the first correction process within the vertical blanking period.
• the display control unit sequentially raises the source voltages of the first transistors in the pixel group to be driven for which the second correction process has been completed, and controls the light emitting elements in the pixel group to be driven by the pixel signal.
• the light may be emitted with a brightness depending on the voltage.
• the display control unit may perform the first correction process within a predetermined period.
• the display control unit simultaneously performs the first correction process on the first transistors in all the pixel groups in the pixel array unit, and then sequentially performs the first correction process on the first transistors in all the pixel groups.
• the second correction process may be performed.
• the plurality of pixel groups arranged in the second direction in the pixel array section are divided into two or more pixel blocks,
• the display control unit performs the first correction process on the first transistor in the pixel block for each of the two or more pixel blocks, and then sequentially performs the first correction process on each of the pixel groups in the pixel block.
• the second correction process for the first transistor may be performed.
• the display control section includes: During the first correction process, the second transistors in the plurality of pixel groups are temporarily turned on to temporarily supply an offset voltage to the gates of the first transistors, and the second transistors in the plurality of pixel groups are temporarily turned on. temporarily turn on the third transistor in the plurality of pixel groups arranged in the second direction and temporarily connect the source of the first transistor to the first reference voltage node.
• each of the plurality of pixel groups is sequentially driven, and the third transistor in the pixel group to be driven is temporarily turned on to temporarily change the source of the first transistor to the first reference voltage. connect to the node, During the second correction process, the connection between the source of the first transistor and the first reference voltage node is cut off, and the threshold voltage of the first transistor is corrected; Thereafter, the second transistor connected to the gate of the first transistor whose threshold voltage has been corrected may be temporarily turned on to supply the pixel signal voltage to the gate of the first transistor whose threshold voltage has been corrected.
• the display control unit repeats an operation of temporarily turning on the third transistor in the pixel group to be driven a plurality of times, and then turns on the second transistor and the third transistor.
• the threshold voltage of the first transistor may be corrected by turning off the third transistor.
• a fourth transistor that switches whether or not to connect the drain of the first transistor to a second reference voltage node; a second capacitor connected between the source of the first transistor and the source of the third transistor, The light emitting element may be connected between the drain of the first transistor and the second reference voltage node.
• the fourth transistor Before the second transistor transitions from off to on with the pixel signal voltage being supplied to the source of the second transistor, the fourth transistor remains on, and the drain of the first transistor remains on. connected to the second reference voltage node; When the second transistor transitions from off to on with the pixel signal voltage being supplied to the source of the second transistor, the fourth transistor turns off, and then the third transistor turns on, causing the The light emitting element may start emitting light.
• the first transistor, the second transistor, the third transistor, and the fourth transistor may be P-type MOS (Metal Oxide Semiconductor) transistors.
• the display control section is configured to apply the pixel signal voltage to the gate of the first transistor in the other while correcting the threshold voltage of the first transistor in one of the two pixel groups in the second direction. May be supplied.
• the light emitting element may be an organic EL (Electro-luminescence) element.
• a pixel array section in which a plurality of pixel groups including two or more pixels arranged in a first direction are arranged in a second direction intersecting the first direction; a light emitting element provided in each pixel in the pixel array section; a first transistor provided in each pixel in the pixel array section and controlling light emission brightness of the light emitting element;
• a method for driving a display device comprising: a first capacitor provided in each pixel in the pixel array section and connected between the gate and source of the first transistor, After performing a first correction process that simultaneously corrects the threshold voltages of the first transistors in the plurality of pixel groups, restoring the source-gate voltage of the first transistor to the voltage before starting the first correction process.
• a second correction process is performed to sequentially correct the threshold voltage of the first transistor for each of the plurality of pixel groups, and a pixel signal voltage is applied to the gate of the first transistor after the second correction process.
• FIG. 1 is a block diagram showing a schematic configuration of a display device.
• FIG. 2 is a block diagram showing a detailed configuration of a display unit.
• FIG. 3 is a diagram showing a circuit configuration of each pixel in a pixel array section.
• FIG. 3 is a diagram illustrating a line sequential driving method.
• FIG. 3 is a diagram illustrating a surface batch driving method.
• FIG. 4B is a drive timing diagram according to a comparative example when the surface batch drive method of FIG. 4B is adopted.
• 6 is a diagram showing source voltage waveforms and gate voltage waveforms of the drive transistor in FIG. 5.
• FIG. FIG. 7 is a diagram showing source voltage waveforms and gate voltage waveforms of the drive transistor when the Vth correction period is too short.
• FIG. 7 is a diagram showing the source voltage waveform and gate voltage waveform of the drive transistor when the Vth correction period is too long.
• FIG. 6 is a diagram illustrating the amount of variation in the gate voltage and the amount of variation in the source voltage of the drive transistor during Vth correction.
• FIG. 7 is a diagram showing a current flowing through a pixel during Vth correction.
• FIG. 2 is a circuit diagram of a pixel according to an embodiment. 11 is a diagram showing source voltage waveforms and gate voltage waveforms of the drive transistor in the circuit of FIG. 10.
• FIG. FIG. 12 is a diagram showing the current flowing through the pixels of FIGS. 8 and 11.
• FIG. FIG. 2 is a diagram schematically showing the scanning order of the display device 1 according to the present embodiment.
• FIG. 2 is a timing diagram of the display device 1 according to one embodiment.
• FIG. 4 is a timing diagram of a display device 1 according to a comparative example.
• FIG. 14B is a timing diagram according to a modified example of FIG. 14A.
• FIG. 3 is a diagram showing the inside of the vehicle from the rear to the front of the vehicle. A diagram showing the interior of the vehicle from diagonally rearward to diagonally forward.
• FIG. 7 is a front view of a digital camera that is a second application example of the electronic device. Rear view of the digital camera.
• FIG. 3 is an external view of an HMD, which is a third application example of electronic equipment. External view of smart glasses.
• FIG. 4 is an external view of a TV, which is a fourth application example of electronic equipment.
• FIG. 7 is an external view of a smartphone, which is a fifth application example of an electronic device.
• the display device may include components and functions that are not shown or explained. The following description does not exclude components or features not shown or described.
• FIG. 1 is a block diagram showing a schematic configuration of a display device 1.
• the display device 1 in FIG. 1 is a display device 1 using a self-luminous element such as an OLED (Organic Light Emitting Device), and one implementation is a microdisplay.
• OLED Organic Light Emitting Device
• the display device 1 in FIG. 1 is not limited to a microdisplay, and can be incorporated into various electronic devices and used as a display unit of any size and display resolution.
• the display device 1 in FIG. 1 includes a display section 2, a display control section 3, a timing control section 4, and a data input/output I/F section 5.
• the display section 2 includes a pixel array section 6, a write scanning section 7, a light emission driving section 8, an auto zero scanning section 9, and a signal output section 10.
• the internal configuration and operation of the display section 2 will be described later.
• the display control section 3 includes a scanning control section 11 and a writing control section 12.
• the scan control section 11 determines the scan timing of each pixel row in the pixel array section 6 and controls the write scanning section 7 .
• the write control section 12 determines the light emission brightness of each pixel 14 in the pixel array section 6 and controls the signal output section 10 .
• the timing control section 4 includes a clock generation section 21, a timing generation section 22, and an image processing section 23.
• the clock generation section 21 generates a clock signal according to the driving timing of each pixel row in the pixel array section 6 and a clock signal according to the timing to write a pixel signal voltage to each pixel 14 of each pixel row in the pixel array section 6. etc.
• the timing generation section 22 generates a signal (for example, a horizontal synchronization signal, a vertical synchronization signal, etc.) that controls the timing of the display control section 3.
• the image processing section 23 generates a pixel signal according to the luminance of the self-luminous element in each pixel 14 of the display section 2 .
• the data input/output I/F section 5 includes a high-speed I/F section 24, an S/P conversion section 25, a clock control section 26, and an H/V synchronization generation section 27.
• the high-speed I/F unit 24 receives image data, clock signals, etc. from a host device (not shown) at high speed.
• the S/P conversion unit 25 converts the parallel image data received by the high-speed I/F unit 24 into serial image data, and supplies the serial image data to the image processing unit 23.
• the clock control section 26 extracts a clock signal from the data received by the high-speed I/F section 24 and supplies it to the clock generation section 21 .
• the H/V synchronization generation section 27 extracts a horizontal synchronization signal and a vertical synchronization signal from the data received by the high-speed I/F section 24 and supplies them to the timing generation section 22 .
• FIG. 2 is a block diagram showing the detailed configuration of the display section 2.
• a plurality of pixels 14 are arranged in the horizontal direction (first direction) and the vertical direction (second direction).
• the horizontal direction is called a row
• the vertical direction is called a column
• the plurality of pixels 14 arranged in the horizontal direction are called a pixel row 13 or a pixel group.
• a plurality of pixel rows 13 extending in the horizontal direction are arranged in a plurality of columns in the vertical direction.
• the number of pixels 14 in the horizontal and vertical directions within the pixel array section 6 is arbitrary. The detailed configuration of the pixel 14 will be described later.
• the write scanning section 7 drives a plurality of write scanning lines.
• a plurality of write scanning lines are provided for each pixel row 13.
• Each write scan line extends horizontally and provides a write scan signal to each pixel 14 in the corresponding pixel row 13.
• the light emission driving section 8 drives a plurality of light emission control lines.
• a plurality of light emission control lines are provided for each pixel row 13.
• Each light emission control line extends in the horizontal direction and supplies a light emission control signal to each pixel 14 in the corresponding pixel row 13.
• the auto-zero scanning unit 9 drives a plurality of auto-zero signal lines (hereinafter referred to as AZ signal lines).
• the plurality of AZ signal lines extend in the horizontal direction and supply AZ signals to each pixel 14 in the corresponding pixel row 13.
• the AZ signal is used to stop the light emitting element from emitting light until the threshold voltage correction of the drive transistor in each pixel 14 is completed.
• the signal output section 10 drives a plurality of data lines sig.
• the plurality of data lines sig extend in the vertical direction and supply offset voltages or pixel signal voltages to the corresponding pixels 14. In this way, the data line sig is used to supply offset voltages or pixel signal voltages at different timings.
• FIG. 3 is a diagram showing the circuit configuration of each pixel 14 in the pixel array section 6.
• Each pixel 14 has four PMOS transistors Q1 to Q4 and two capacitors Cs and Csub, and is sometimes called a Pch 4Tr2C.
• the four transistors in each pixel 14 are referred to as a drive transistor (first transistor) Q1, a WS transistor (second transistor) Q2, a DS transistor (third transistor) Q3, and an AZ transistor (fourth transistor) Q4. call.
• the two capacitors Cs and Csub in each pixel 14 will be referred to as a first capacitor Cs and a second capacitor Csub.
• a self-luminous element including an OLED 20 is arranged in each pixel 14.
• An AZ transistor Q4 is connected between the drain of the drive transistor Q1 and the second reference voltage node Vss. More specifically, the drain of the drive transistor Q1 is connected to the source of the AZ transistor Q4, and the drain of the AZ transistor Q4 is connected to the second reference voltage node Vss.
• An OLED 20 is connected between the drain of the drive transistor Q1 and the third reference voltage node Vcath. More specifically, the drain of the drive transistor Q1 is connected to the anode of the OLED 20, and the cathode of the OLED 20 is connected to the third reference voltage node Vcath.
• the voltage level of the third reference voltage node Vcath may be the same as or different from the voltage level of the second reference voltage node Vss.
• a WS transistor Q2 is connected between the gate of the drive transistor Q1 and the data line sig. More specifically, the gate of the drive transistor Q1 is connected to the drain of the WS transistor Q2, and the source of the WS transistor Q2 is connected to the data line sig. A WS signal is input to the gate of the WS transistor Q2.
• a DS transistor Q3 is connected between the source of the drive transistor Q1 and a power supply potential node (first reference voltage node) Vdd. More specifically, the source of the drive transistor Q1 is connected to the drain of the DS transistor Q3. The source of the DS transistor Q3 is connected to the power supply potential node Vdd.
• a first capacitor Cs is connected between the gate and source of the drive transistor Q1.
• a second capacitor Csub is connected between the source and drain of the DS transistor Q3. That is, the first capacitor Cs and the second capacitor Csub are connected in series between the power supply potential node Vdd and the gate of the driving transistor Q1.
• the display device 1 As methods for driving pixels of the display device 1, there are a line-sequential driving method in which each pixel row 13 is driven line-sequentially, and a surface batch driving method in which all pixels 14 in all pixel rows 13 are driven at once.
• the line sequential drive method is also called a progressive drive method.
• the display device 1 according to one embodiment is applicable to both a line sequential driving method and a surface batch driving method.
• the pixel array section 6 may be divided into a plurality of pixel blocks in the vertical direction, and each pixel 14 may be driven for each pixel block using a line sequential driving method or a surface batch driving method.
• FIG. 4A is a diagram for explaining the line-sequential driving method
• FIG. 4B is a diagram for explaining the surface-at-a-time driving method.
• the OLED 20 starts emitting light immediately after the pixel signal voltage of each pixel row 13 is written. That is, the light emission timing is shifted for each pixel row 13.
• the surface batch driving method of FIG. 4B after the writing of pixel signal voltages for all pixel rows 13 is completed, all pixel rows 13 are caused to emit light at once.
• FIG. 5 is a drive timing chart according to a comparative example when the surface batch drive method of FIG. 4B is adopted.
• the operation of the circuit of the pixel 14 in FIG. 3 will be described below with reference to the timing diagram in FIG. However, in the following description, depending on the pixel signal voltage to be written, the direction of some voltage fluctuations may be reversed from the following description.
• the threshold voltage of the drive transistor Q1 is corrected before the pixel signal voltage is supplied to the data line sig.
• the DS transistor Q3 in the first pixel row 13 is turned on (time t1).
• the accumulated charge in the second capacitor Csub is discharged and reset.
• the AZ transistor Q4 is continuously set to the on state until the OLED 20 starts emitting light.
• the offset voltage Vofs is supplied to the data line sig to turn on the WS transistor Q2 (time t2).
• the offset voltage Vofs is supplied to the gate of the drive transistor Q1 via the WS transistor Q2.
• the source of the drive transistor Q1 becomes the power supply potential Vdd.
• the WS transistor Q2 is turned off (time t3), and then the DS transistor Q3 is turned off (time t4).
• the source voltage of drive transistor Q1 begins to decrease. Since the first capacitor Cs is connected between the gate and source of the drive transistor Q1, when the source voltage of the drive transistor Q1 decreases, the gate voltage of the drive transistor Q1 also decreases. Eventually, when the gate-source voltage of the drive transistor Q1 matches the threshold voltage of the drive transistor Q1, the gate voltage and source voltage of the drive transistor Q1 become stable, and the threshold voltage correction process ends.
• the pixel signal voltage Vsig is supplied to the data line sig, and the WS transistor Q2 of each pixel 14 in the pixel row 13 whose threshold voltage has been corrected is temporarily turned on (times t5 to t6).
• a voltage corresponding to the pixel signal voltage Vsig and the threshold voltage is supplied to the gate of the driving transistor Q1 to be driven, and writing of the pixel signal voltage Vsig is performed.
• FIG. 6 is a diagram showing the source voltage waveform w1 and gate voltage waveform w2 of the drive transistor Q1 from time t1 to t8 in FIG.
• the source voltage of the drive transistor Q1 begins to rise.
• the WS transistor Q2 is turned on, and the gate voltage of the drive transistor Q1 begins to rise due to the offset voltage Vofs on the data line sig. Note that depending on the voltage level of the offset voltage Vofs, the gate voltage of the drive transistor Q1 may start to decrease.
• the voltage levels of the source voltage and gate voltage of the drive transistor Q1 become stable.
• the potential difference between the source voltage and the gate voltage is (Vdd-Vofs).
• the source voltage of the drive transistor Q1 starts to fall, and accordingly, the gate voltage of the drive transistor Q1 also starts to fall.
• the potential difference between the source voltage and the gate voltage of the drive transistor Q1 is stabilized to match the threshold voltage of the drive transistor Q1.
• the gate voltage of the drive transistor Q1 begins to decrease due to the pixel signal voltage Vsig on the data line sig. Along with this, the source voltage of the drive transistor Q1 also begins to decrease. Note that depending on the voltage level of the pixel signal voltage Vsig, the gate voltage of the drive transistor Q1 may start to rise and the source voltage of the drive transistor Q1 may start to fall.
• the source voltage of the drive transistor Q1 increases, and accordingly, the gate voltage of the drive transistor Q1 also increases, and the potential difference between the source voltage and the gate voltage of the drive transistor Q1 becomes The value corresponds to the signal voltage Vsig.
• a current flows from the DS transistor Q3 to the OLED 20 via the drive transistor Q1, and the OLED 20 emits light with a luminance according to the pixel signal voltage Vsig.
• the source voltage and gate voltage of the drive transistor Q1 may decrease at time t8.
• Time t4 to t5 in FIG. 6 is a correction period for the threshold voltage of the drive transistor Q1, and is also called a Vth correction period.
• the period from time t4 to time t5 needs to be set to such a length that the source-gate voltages of all drive transistors Q1 to be corrected reach the threshold voltage.
• FIG. 7A is a diagram showing the source voltage waveform w1 and gate voltage waveform w2 of the drive transistor Q1 when the Vth correction period is relatively short.
• FIG. 7B is a diagram showing the source voltage waveform w1 and gate voltage waveform w2 of the drive transistor Q1 when the Vth correction period is relatively long.
• the source-gate voltage of the drive transistor Q1 becomes larger than the threshold voltage.
• the Vth correction period is relatively long as shown in FIG. 7B, the accumulated charge in the first capacitor Cs is gradually discharged, and the source-gate voltage of the drive transistor Q1 becomes smaller than the threshold voltage, and the final Specifically, the source voltage and gate voltage are approximately equal.
• the source-gate voltage of the drive transistor Q1 changes depending on whether the Vth correction period is relatively short or long. As the voltage between the source and gate of the drive transistor Q1 is larger, as shown in FIG. 7A, the current flowing through the OLED 20 during light emission becomes larger, and the luminance becomes higher.
• FIG. 8 is a diagram illustrating the amount of variation ⁇ Vg in the gate voltage of the drive transistor Q1 and the amount of variation Vs in the source voltage during Vth correction.
• Cgg in equation (2) is the total gate capacitance of drive transistor Q1
• Cgs in equation (2) is the coupling capacitance between the source and gate of drive transistor Q1.
• FIG. 9 is a diagram showing the current flowing through the pixel 14 during Vth correction.
• both the WS transistor Q2 and the DS transistor Q3 are off, and the AZ transistor Q4 is on.
• the accumulated charge in the first capacitor Cs is discharged through the source-drain of the drive transistor Q1.
• the current flowing between the source and drain of the drive transistor Q1 flows to the AZ transistor Q4. Therefore, the source voltage and gate voltage of drive transistor Q1 gradually decrease.
• Equation (1) The degree of change in the source voltage and the degree of change in the gate voltage have a linear relationship as shown in Equation (1), and the proportionality constant ⁇ , which is the slope of the degree of change in the source voltage with respect to the degree of change in the gate voltage, is expressed by Equation (2). As shown in , it depends on the source-gate coupling capacitance with respect to the total capacitance of the drive transistor Q1, and 0 ⁇ 1.
• both the source voltage and the gate voltage of the drive transistor Q1 gradually decrease, but since the proportionality constant ⁇ in equation (2) is less than 1, the source voltage decreases more than the gate voltage. As the voltage increases, the voltage between the source and gate of the drive transistor Q1 gradually decreases.
• the voltage between the source and gate of the drive transistor Q1 changes depending on the length of the Vth correction period, and even when the pixel signal voltage Vsig is subsequently applied to the gate voltage of the drive transistor Q1, the voltage between the source and gate of the drive transistor Q1 changes. A difference occurs in the voltage between source and gate. If the voltage between the source and gate of the drive transistor Q1 changes, it will affect the luminance of the OLED 20, so control is required so that the voltage between the source and gate of the drive transistor Q1 does not change depending on the length of the Vth correction period.
• the display device 1 according to the embodiment described below is characterized in that the voltage between the source and gate of the drive transistor Q1 is kept constant regardless of the length of the Vth correction period.
• FIG. 10 is a circuit diagram of the pixel 14 according to one embodiment
• FIG. 11 is a diagram showing the source voltage waveform w1 and gate voltage waveform w2 of the drive transistor Q1 in the circuit of FIG.
• the circuit in FIG. 10 has the same circuit configuration as the circuit in FIG. 3, but differs from that in FIG. 9 in the current flowing through the circuit during Vth correction.
• the Vth correction period is divided into two, as shown in FIG. This period is called the 2-correction processing period.
• the second correction process is performed after the first correction process. Through the second correction process, correction of the threshold voltage of the drive transistor Q1 of each pixel 14 is completed.
• FIG. 10 shows the current flowing within the pixel 14 immediately before the start of the second correction process.
• the length of the first correction processing period is different for each of the plurality of pixel rows 13 arranged in the second direction.
• the length of the second correction processing period is approximately the same for the plurality of pixel rows 13.
• the display control unit 3 temporarily supplies the offset voltage Vofs to the gates of the drive transistors Q1 in the plurality of pixel rows 13 to temporarily set the sources to the first reference voltage node Vdd. , and during the first correction processing period, the supply of the offset voltage Vofs to the gate of the drive transistor Q1 is cut off, and the connection between the source of the drive transistor Q1 and the first reference voltage node Vdd is cut off.
• the display control unit 3 sequentially drives each of the plurality of pixel rows 13 to temporarily set the source of the drive transistor Q1 in the pixel row 13 to be driven to the first reference voltage node. After that, during the second correction processing period, the connection between the source of the drive transistor Q1 and the first reference voltage node Vdd is cut off to correct the threshold voltage of the drive transistor Q1.
• the display control unit 3 matches the source-gate voltage of the drive transistor Q1 in the pixel row 13 to be driven with the threshold voltage of the drive transistor Q1 during the second correction processing period. After the second correction process for the drive transistors Q1 in the plurality of pixel rows 13 is completed, the display control unit 3 simultaneously raises the source voltages of the drive transistors Q1 in the plurality of pixel rows 13 to The light-emitting elements are caused to emit light at the same time with a brightness corresponding to the pixel signal voltage Vsig.
• the display control unit 3 sequentially raises the source voltage of the drive transistor Q1 in the pixel row 13 to be driven, for which the second correction process has been completed, and controls the light emitting elements in the pixel row 13 to be driven according to the pixel signal voltage Vsig. emit light at a brightness level.
• the display control unit 3 may perform the first correction process within a predetermined period.
• the display control unit 3 simultaneously performs the first correction process on the drive transistors Q1 in all the pixel rows 13 in the pixel array unit 6, and then sequentially performs the second correction process on the drive transistors Q1 in each of all the pixel rows 13. Correction processing may also be performed.
• the plurality of pixel rows 13 arranged in the second direction within the pixel array unit 6 may be divided into two or more pixel blocks.
• the display control unit 3 performs the first correction process on the drive transistor Q1 in the pixel block for each of two or more pixel blocks, and then sequentially performs the drive transistor Q1 on each pixel row 13 in the pixel block.
• a second correction process may be performed.
• the threshold voltages of the drive transistors Q1 in all the pixels 14 are corrected at the same time.
• the DS transistor Q3 is turned on at time t1 in FIG.
• the source voltage of the drive transistor Q1 gradually increases and eventually reaches the power supply voltage Vdd.
• the source voltage of the drive transistor Q1 may gradually decrease.
• WS transistor Q2 is temporarily turned on.
• an offset voltage Vofs is supplied on the data line sig.
• the gate voltage of the drive transistor Q1 gradually increases.
• the gate voltage of the drive transistor Q1 may gradually decrease.
• the DS transistor Q3 is turned on at time t5a.
• the operation from time t1 to t5a is the same as that from time t1 to t5 in FIG.
• Turning on the DS transistor Q3 at time t5a is an operation not envisioned in FIGS. 8 and 9.
• the source voltage of the drive transistor Q1 increases rapidly, and accordingly, the gate voltage of the drive transistor Q1 also increases rapidly, causing The voltage is the same as the voltage between the source and gate of the drive transistor Q1 at the time when the first correction process is started (time t4a).
• FIG. 10 shows the state at time t5a.
• the DS transistor Q3 and the AZ transistor Q4 are turned on, and the WS transistor Q2 is turned off.
• the current flowing between the source and drain of the DS transistor Q3 flows to the second reference voltage node Vss through the source and drain of the AZ transistor Q4, but does not flow to the OLED 20. Therefore, the OLED 20 does not emit light.
• part of the current flowing between the source and drain of the DS transistor Q3 also flows into the first capacitor Cs, and the voltage across the first capacitor Cs, that is, the voltage between the source and gate of the drive transistor Q1 is reduced by the first correction process.
• the potential difference is approximately equal to the potential difference at time t4a at which .
• the voltage between the source and gate of the drive transistor Q1 at the end of the first correction processing period changes depending on the length of the first correction processing period, but the voltage between the source and gate of the drive transistor Q1 changes after the end of the first correction processing period.
• the voltage between the source and gate of the drive transistor Q1 can be restored to the voltage immediately before starting the first correction process.
• the DS transistor Q3 is turned off and the second correction process is started.
• the second correction processing period as in the first correction processing period, since the WS transistor Q2 and the DS transistor Q3 are off, both the source voltage and gate voltage of the drive transistor Q1 gradually decrease, and the voltage of the drive transistor Q1 gradually decreases. The source-gate voltage also gradually decreases.
• the period of the second correction process (times t4b to t5b) is controlled to have an appropriate length of time. Specifically, the period of the second correction process is set in advance to a time length such that the voltage between the source and gate of the drive transistor Q1 substantially matches the threshold voltage of the drive transistor Q1.
• the second correction process ends by turning on the WS transistor Q2 at time t5b.
• pixel signal voltage Vsig is supplied onto data line sig. Therefore, the gate voltage of the drive transistor Q1 decreases according to the voltage level of the pixel signal voltage Vsig, and as the gate voltage changes, the source voltage of the drive transistor Q1 also changes.
• the source voltage of the drive transistor Q1 increases, and the gate voltage also increases accordingly.
• the voltage between the source and gate of the drive transistor Q1 has a value that depends on the pixel signal voltage Vsig, and the OLED 20 starts emitting light with a luminance that corresponds to the pixel signal voltage Vsig.
• FIG. 12 is a diagram showing the current flowing through the pixel 14 at time t2 in FIGS. 8 and 11.
• the WS transistor Q2, the DS transistor Q3, and the AZ transistor Q4 are all turned on, and the offset voltage Vofs is supplied to the data line sig.
• both the DS transistor Q3 and the AZ transistor Q4 are turned on, but the WS transistor Q2 is turned off. Therefore, no matter what voltage the data line sig has, it does not affect the source voltage and gate voltage of the drive transistor Q1.
• the individual data lines sig extend in the vertical direction within the pixel array section 6 and are connected to pixels 14 in the same column of different pixel rows 13. Therefore, at time t5a, when the voltage between the source and gate of the drive transistor Q1 of the corresponding pixel 14 in a certain pixel row 13 is restored to the potential difference immediately before the start of the first correction process, the same data line sig is connected. A pixel signal can be written to the corresponding pixel 14 in another pixel row 13 by turning on the WS transistor Q2.
• the pixel signal voltage Vsig is applied to the drive transistor Q1 in the other pixel row 13. Since it is possible to perform parallel processing, it is possible to draw one frame at high speed.
• FIG. 13 is a diagram schematically showing the scanning order of the display device 1 according to this embodiment.
• FIG. 13 shows an example in which a surface batch driving method is adopted.
• the offset voltage Vofs is written to all pixels 14 in all pixel rows 13 at once during the vertical blanking period, and the first correction process is performed.
• the second correction process is performed for each pixel row 13 sequentially from the upper end side pixel row 13 to correct the threshold voltage of each pixel 14 in the pixel row 13 to be driven, and then the pixel signal voltage Vsig Write.
• the second correction process is completed up to the bottom pixel row 13, all the pixels 14 in all the pixel rows 13 start emitting light.
• the timing at which the offset voltage Vofs is written to all pixels 14 of all pixel rows 13 at once does not necessarily have to be during the vertical blanking period.
• FIG. 14A is a timing diagram of the display device 1 according to one embodiment. Further, FIG. 14B is a timing diagram of the display device 1 according to a comparative example. The timing diagram of FIG. 14B is substantially the same as FIG. 5.
• both the WS transistor Q2 and the DS transistor Q3 of all the pixels 14 in the pixel array section 6 are turned on (times t12 to t13), and the first Correction processing is performed (times t11 to t15).
• the DS transistor Q3 is turned on for each pixel 14 in the pixel row 13 to be driven (times t15 to t16), and the second correction process is performed.
• the WS transistor Q2 is turned on and the pixel signal voltage Vsig on the data line sig is written to the gate of the drive transistor Q1 (times t18 to t19).
• the DS transistor Q3 is turned on (times t17 to t20). In the pixel 14 where the DS transistor Q3 is turned on, the WS transistor Q2 is turned off, so the source of the drive transistor Q1 is The gate-to-gate voltage can be restored to the voltage immediately before the first correction processing period.
• both the WS transistor Q2 and the DS transistor Q3 are turned on for each pixel 14 in the corresponding pixel row 13 within one horizontal line period.
• the WS transistor Q2 is turned on again and the pixel signal voltage Vsig is written to the gate of the drive transistor Q1 (times t1 to t6).
• the display device 1 according to the present embodiment can shorten the length of one horizontal line period and draw one frame at a higher speed than the display device 1 according to a comparative example.
• the DS transistor Q3 when the first correction processing period ends, the DS transistor Q3 is turned on within a predetermined period (time t15 to t16), and the voltage between the source and gate of the drive transistor Q1 is set to the voltage immediately before the first correction processing period. However, by turning on the DS transistor Q3 multiple times, the source-to-gate voltage of the drive transistor Q1 can be restored more stably.
• FIG. 15 is a timing diagram according to a modified example of FIG. 14A.
• the DS transistor Q3 is turned on twice (times t15 to t16, t17 to t18, and t19 to t22). Thereby, the source-gate voltage of the drive transistor Q1 can be more accurately restored to the voltage immediately before the first correction process.
• the first correction process is performed by writing the offset voltage Vofs to the gates of the drive transistors Q1 of all the pixels 14 in all the pixel rows 13 during the vertical blanking period or the like. Thereafter, for each pixel row 13, the DS transistor Q3 is temporarily turned on to restore the source-gate voltage of the drive transistor Q1 to the voltage immediately before the first correction process, and then the second correction process is performed. A pixel signal voltage Vsig is written to the gate of the drive transistor Q1. Thereby, even if the first correction processing period differs for each pixel row 13, the threshold voltage of the drive transistor Q1 of each pixel 14 can be appropriately corrected.
• the one horizontal line period can be shortened.
• a pixel signal is sent to the gate of the drive transistor Q1 in the other pixel row 13.
• the voltage Vsig can be written, and drawing for one frame can be performed at high speed.
• 16A and 16B are diagrams showing the internal configuration of a vehicle 100 that is a first application example of an electronic device 50 equipped with an image display device 1 according to the present disclosure.
• 16A is a diagram showing the interior of the vehicle 100 from the rear to the front of the vehicle 100
• FIG. 16B is a diagram showing the interior of the vehicle 100 from the diagonally rear to the diagonally front.
• the vehicle 100 of FIGS. 16A and 16B includes a center display 101, a console display 102, a head-up display 103, a digital rear mirror 104, a steering wheel display 105, and a rear entertainment display 106.
• the center display 101 is placed on the dashboard 107 at a location facing the driver's seat 108 and passenger seat 109.
• FIG. 16 shows an example of a horizontally long center display 101 extending from the driver's seat 108 side to the passenger seat 109 side
• the screen size and placement location of the center display 101 are arbitrary.
• Center display 101 can display information detected by various sensors. As a specific example, the center display 101 displays images taken by an image sensor, distance images to obstacles in front and on the side of the vehicle measured by a ToF sensor, and passenger body temperature detected by an infrared sensor. Can be displayed.
• the center display 101 can be used to display at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information, for example.
• Safety-related information includes information such as detection of falling asleep, detection of looking away, detection of mischief by children in the same vehicle, presence or absence of seatbelts, and detection of leaving passengers behind. This information is detected by The operation-related information uses sensors to detect gestures related to operations by the occupant.
• the detected gestures may include manipulation of various equipment within the vehicle 100. For example, the operation of air conditioning equipment, navigation equipment, AV equipment, lighting equipment, etc. is detected.
• the life log includes life logs of all crew members. For example, a life log includes a record of the actions of each occupant during the ride. By acquiring and saving life logs, it is possible to check the condition of the occupants at the time of the accident.
• a temperature sensor is used to detect the occupant's body temperature, and the occupant's health condition is estimated based on the detected body temperature.
• an image sensor may be used to capture an image of the occupant's face, and the occupant's health condition may be estimated from the captured facial expression.
• Authentication/identification related information includes a keyless entry function that performs facial recognition using a sensor, and a function that automatically adjusts seat height and position using facial recognition.
• the entertainment-related information includes a function that uses a sensor to detect operation information of an AV device by a passenger, a function that recognizes the passenger's face using a sensor, and provides the AV device with content suitable for the passenger.
• the console display 102 can be used, for example, to display life log information.
• the console display 102 is arranged near a shift lever 111 on a center console 110 between a driver's seat 108 and a passenger seat 109.
• the console display 102 can also display information detected by various sensors. Further, the console display 102 may display an image around the vehicle captured by an image sensor, or may display a distance image to an obstacle around the vehicle.
• the head-up display 103 is virtually displayed behind the windshield 112 in front of the driver's seat 108.
• the head-up display 103 can be used, for example, to display at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information. Since the head-up display 103 is often placed virtually in front of the driver's seat 108, it is difficult to display information directly related to the operation of the vehicle 100, such as the speed of the vehicle 100 and the remaining amount of fuel (battery). Are suitable.
• the digital rear mirror 104 can display not only the rear of the vehicle 100 but also the state of the occupants in the rear seats. Therefore, by arranging a sensor on the back side of the digital rear mirror 104, it can be used for displaying life log information, for example. be able to.
• the steering wheel display 105 is placed near the center of the steering wheel 113 of the vehicle 100.
• Steering wheel display 105 can be used, for example, to display at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information.
• life log information such as the driver's body temperature, information regarding the operation of AV equipment, air conditioning equipment, etc. There is.
• the rear entertainment display 106 is attached to the back side of the driver's seat 108 and the passenger seat 109, and is for viewing by passengers in the rear seats.
• the rear entertainment display 106 can be used, for example, to display at least one of safety-related information, operation-related information, lifelog, health-related information, authentication/identification-related information, and entertainment-related information.
• information relevant to the rear seat occupant is displayed. For example, information regarding the operation of the AV device or air conditioning equipment may be displayed, or the results of measuring the body temperature of the passenger in the rear seat using a temperature sensor may be displayed.
• a passive type sensor measures distance by receiving light from an object without emitting light from the sensor to the object.
• Passive methods include the lens focusing method, stereo method, and monocular viewing method.
• the active type measures distance by projecting light onto an object and receiving the reflected light from the object with a sensor.
• Active types include an optical radar method, an active stereo method, a photometric stereo method, a moiré topography method, and an interferometry method.
• the image display device 1 according to the present disclosure is applicable to any of these methods of distance measurement.
• the image display device 1 according to the present disclosure is applicable not only to various displays used in vehicles, but also to displays mounted on various electronic devices 50.
• FIG. 17A is a front view of a digital camera 120, which is a second application example of the electronic device 50, and FIG. 17B is a rear view of the digital camera 120.
• the digital camera 120 in FIGS. 17A and 17B is an example of a single-lens reflex camera in which the lens 121 can be replaced, but the present invention is also applicable to a camera in which the lens 121 cannot be replaced.
• a monitor screen 126 for displaying shooting data, live images, etc., and an electronic viewfinder 124 are provided on the top surface of the camera.
• the image display device 1 By arranging a sensor overlapping the back side of the monitor screen 126, electronic viewfinder 124, sub-screen, etc. used in the camera, it can be used as the image display device 1 according to the present disclosure.
• the image display device 1 according to the present disclosure is also applicable to a head mounted display (hereinafter referred to as HMD).
• HMDs can be used for VR (Virtual Reality), AR (Augmented Reality), MR (Mixed Reality), SR (Substitutional Reality), and the like.
• FIG. 18A is an external view of an HMD 130 that is a third application example of the electronic device 50.
• the HMD 130 in FIG. 18A has a mounting member 131 that is worn to cover a human's eyes. This mounting member 131 is fixed by being hooked onto a human ear, for example.
• a display device 132 is provided inside the HMD 130, and the wearer of the HMD 130 can view stereoscopic images and the like on this display device 132.
• the HMD 130 includes, for example, a wireless communication function and an acceleration sensor, and can switch the stereoscopic image displayed on the display device 132 according to the wearer's posture, gestures, and the like.
• a camera may be provided in the HMD 130 to take images of the surroundings of the wearer, and an image obtained by combining the image taken by the camera and an image generated by a computer may be displayed on the display device 132.
• a camera is placed on the back side of the display device 132 that is visible to the wearer of the HMD 130, and the camera takes pictures of the area around the eyes of the wearer, and the captured image is sent to another camera provided on the outer surface of the HMD 130.
• the image display device 1 can also be applied to smart glasses 130a that display various information on glasses 134.
• Smart glasses 130a in FIG. 18B include a main body portion 135, an arm portion 136, and a lens barrel portion 137.
• the main body portion 135 is connected to an arm portion 136.
• the main body portion 135 is removably attached to the glasses 134.
• the main body section 135 incorporates a control board and a display section for controlling the operation of the smart glasses 130a.
• the main body part 135 and the lens barrel part 137 are connected to each other via an arm part 136.
• the lens barrel section 137 emits the image light emitted from the main body section 135 via the arm section 136 to the lens 138 side of the glasses 134 .
• This image light enters the human eye through lens 138.
• the wearer of the smart glasses 130a in FIG. 18B can visually recognize not only the surrounding situation but also various information emitted from the lens barrel section 137, like normal glasses.
• the image display device 1 according to the present disclosure is also applicable to a television device (hereinafter referred to as TV).
• TV television device
• Recent TVs tend to have frame sizes as small as possible from the viewpoint of miniaturization and aesthetic design. For this reason, when a TV is provided with a camera for photographing the viewer, it is desirable to arrange it so as to overlap the back side of the display section 2 of the TV.
• FIG. 19 is an external view of a TV 140 that is a fourth application example of the electronic device 50.
• the TV 140 in FIG. 19 has a minimized frame, and almost the entire front side is the display area.
• the TV 140 may have a built-in sensor such as a camera for photographing the viewer.
• FIG. 20 is an external view of a smartphone 150 that is a fifth application example of the electronic device 50.
• the display surface 1z extends to nearly the external size of the electronic device 50, and the width of the bezel 1y around the display surface 1z is set to several mm or less.
• a front camera is often mounted on the bezel 1y, but in FIG. 20, as shown by the broken line, an image sensor module functioning as a front camera is arranged on the back side of the display surface 1z, for example, approximately in the center. are doing.
• the present technology can have the following configuration. (1) a pixel array section in which a plurality of pixel groups including two or more pixels arranged in a first direction are arranged in a second direction intersecting the first direction; a light emitting element provided in each pixel in the pixel array section; a first transistor provided in each pixel in the pixel array section and controlling light emission brightness of the light emitting element; a first capacitor provided in each pixel in the pixel array section and connected between the gate and source of the first transistor; After performing a first correction process that simultaneously corrects the threshold voltages of the first transistors in the plurality of pixel groups, restoring the source-gate voltage of the first transistor to the voltage before starting the first correction process.
• a display device comprising: a display control section that supplies voltage.
• the length of the period of the first correction process is different for each of the plurality of pixel groups arranged in the second direction, The display device according to (1) or (2), wherein the length of the second correction processing period is substantially the same for the plurality of pixel groups.
• the display control section Immediately before the first correction processing period, an offset voltage is temporarily supplied to the gates of the first transistors in the plurality of pixel groups to temporarily connect the sources to the first reference voltage node; During the period of the first correction process, the supply of the offset voltage to the gate of the first transistor is cut off, and the connection between the source of the first transistor and the first reference voltage node is cut off.
• the display device according to any one of 1) to (3).
• the display control unit sequentially drives each of the plurality of pixel groups to temporarily connect the source of the first transistor in the pixel group to be driven to a first reference voltage node; Thereafter, during the period of the second correction process, the connection between the source of the first transistor and the first reference voltage node is cut off to correct the threshold voltage of the first transistor (1) to (4).
• the display device according to any one of the above.
• the display control unit matches the source-gate voltage of the first transistor in the pixel group to be driven with the threshold voltage of the first transistor during the period of the second correction process; The display device according to (5).
• the display control unit After the second correction process of the first transistors in the plurality of pixel groups is completed, the display control unit simultaneously raises the source voltages of the first transistors in the plurality of pixel groups;
• the display device any one of (1) to (6), wherein the light emitting elements in the plurality of pixel groups simultaneously emit light at a brightness according to the pixel signal voltage.
• the display device (8) The display device according to (7), wherein the display control unit starts the first correction process within a vertical blanking period.
• the display control unit sequentially raises the source voltage of the first transistor in the pixel group to be driven for which the second correction process has been completed, and increases the voltage of the light emitting element in the pixel group to be driven.
• the display device according to any one of (1) to (6), which emits light with a brightness that corresponds to the pixel signal voltage. (10) The display device according to (9), wherein the display control unit performs the first correction process within a predetermined period. (11) The display control unit simultaneously performs the first correction process on the first transistors in all the pixel groups in the pixel array unit, and then sequentially performs the first correction process on each of all the pixel groups. The display device according to any one of (1) to (10), wherein the second correction process for one transistor is performed.
• the plurality of pixel groups arranged in the second direction in the pixel array section are divided into two or more pixel blocks,
• the display control unit performs the first correction process on the first transistor in the pixel block for each of the two or more pixel blocks, and then sequentially performs the first correction process on each of the pixel groups in the pixel block.
• the display device according to any one of (1) to (10), wherein the second correction process of the first transistor is performed.
• the display control section includes: During the first correction process, the second transistors in the plurality of pixel groups are temporarily turned on to temporarily supply an offset voltage to the gates of the first transistors, and the second transistors in the plurality of pixel groups are temporarily turned on. temporarily turn on the third transistor in the plurality of pixel groups arranged in the second direction and temporarily connect the source of the first transistor to the first reference voltage node.
• each of the plurality of pixel groups is sequentially driven, and the third transistor in the pixel group to be driven is temporarily turned on to temporarily change the source of the first transistor to the first reference voltage. connect to the node, During the second correction process, the connection between the source of the first transistor and the first reference voltage node is cut off, and the threshold voltage of the first transistor is corrected; Thereafter, temporarily turning on the second transistor connected to the gate of the first transistor whose threshold voltage has been corrected, and supplying the pixel signal voltage to the gate of the first transistor whose threshold voltage has been corrected; (1) The display device according to any one of (12) to (12).
• the display control unit repeats an operation of temporarily turning on the third transistor in the pixel group to be driven a plurality of times, and then the second The display device according to (13), wherein the threshold voltage of the first transistor is corrected by turning off the transistor and the third transistor.
• a fourth transistor that switches whether or not to connect the drain of the first transistor to a second reference voltage node; a second capacitor connected between the source of the first transistor and the source of the third transistor, The display device according to (13) or (14), wherein the light emitting element is connected between the drain of the first transistor and the second reference voltage node.
• the fourth transistor Before the second transistor transitions from off to on with the pixel signal voltage being supplied to the source of the second transistor, the fourth transistor maintains the on state and the first transistor a drain of is connected to the second reference voltage node, When the second transistor transitions from off to on with the pixel signal voltage being supplied to the source of the second transistor, the fourth transistor turns off, and then the third transistor turns on, causing the The display device according to (15), wherein the light emitting element starts emitting light.
• the first transistor, the second transistor, the third transistor, and the fourth transistor are P-type MOS (Metal Oxide Semiconductor) transistors.
• the display control unit may cause the pixel to be connected to the gate of the first transistor in the other.
• the light emitting element is an organic EL (Electro-luminescence) element.
• a pixel array section in which a plurality of pixel groups including two or more pixels arranged in a first direction are arranged in a second direction intersecting the first direction; a light emitting element provided in each pixel in the pixel array section; a first transistor provided in each pixel in the pixel array section and controlling light emission brightness of the light emitting element;
• a method for driving a display device comprising: a first capacitor provided in each pixel in the pixel array section and connected between the gate and source of the first transistor, After performing a first correction process that simultaneously corrects the threshold voltages of the first transistors in the plurality of pixel groups, restoring the source-gate voltage of the first transistor to the voltage before starting the first correction process.
• a second correction process is performed to sequentially correct the threshold voltage of the first transistor for each of the plurality of pixel groups, and a pixel signal voltage is applied to the gate of the first transistor after the second correction process.
• 1 display device 1y bezel, 1z display surface, 2 display section, 3 display control section, 4 timing control section, 5 data input/output I/F section, 6 pixel array section, 7 write scanning section, 8 light emission drive section, 9 Auto zero scanning section, 10 Signal output section, 11 Scan control section, 12 Write control section, 13 Pixel row, 13 All pixel rows, 14 Pixel, 21 Clock generation section, 22 Timing generation section, 23 Image processing section, 24 High speed I/F section, 25 S/P conversion section, 26 clock control section, 27 H/V synchronization generation section, 50 electronic equipment, 100 vehicle, 101 center display, 102 console display, 103 head-up display, 104 digital rear mirror, 105 Steering wheel display, 106 Rear entertainment display, 107 Dashboard, 108 Driver's seat, 109 Passenger seat, 110 Center console, 111 Shift lever, 112 Windshield, 113 Steering wheel, 120 Digital camera, 121 Lens, 122 Camera body, 123 Grip, 124 Electronic viewfinder, 125 Shutter,

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• 2023
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