WO2023178516A1 - 纹路识别模组、其制作方法及显示装置 - Google Patents

纹路识别模组、其制作方法及显示装置 Download PDF

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Publication number
WO2023178516A1
WO2023178516A1 PCT/CN2022/082287 CN2022082287W WO2023178516A1 WO 2023178516 A1 WO2023178516 A1 WO 2023178516A1 CN 2022082287 W CN2022082287 W CN 2022082287W WO 2023178516 A1 WO2023178516 A1 WO 2023178516A1
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Prior art keywords
electrode
texture recognition
layer
substrate
recognition module
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PCT/CN2022/082287
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English (en)
French (fr)
Inventor
海晓泉
王迎姿
董学
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/082287 priority Critical patent/WO2023178516A1/zh
Priority to CN202280000498.4A priority patent/CN117256018A/zh
Publication of WO2023178516A1 publication Critical patent/WO2023178516A1/zh

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  • the present disclosure relates to the field of display technology, and in particular, to a texture recognition module, its manufacturing method and a display device.
  • biometric recognition technology has been increasingly widely used.
  • fingerprint recognition technology has been widely used in mobile terminals and smart homes. and other fields to provide security for user information.
  • Embodiments of the present disclosure provide a texture recognition module, its manufacturing method and a display device.
  • the specific solutions are as follows:
  • a texture recognition module including:
  • a texture recognition substrate which includes a base substrate and a plurality of photosensitive devices arranged in an array on one side of the base substrate;
  • An aperture layer is located on the side of the texture recognition substrate having the plurality of photosensitive devices.
  • the number of the aperture layers is one layer.
  • the aperture layer includes light-transmitting holes arranged in an array.
  • the orthographic projection of the light hole on the base substrate is located within the orthographic projection of the photosensitive device on the base substrate, and the ratio of the depth of the light-transmitting hole to the maximum aperture of the light-transmitting hole is greater than or equal to 1 /6 and less than or equal to 2;
  • a plurality of microlenses are located on the side of the diaphragm layer away from the texture identification substrate.
  • the orthographic projection of the microlenses on the substrate covers the orthographic projection of the light-transmitting hole on the substrate. projection.
  • the apertures of the light-transmitting holes are substantially the same.
  • the aperture of the light-transmitting hole gradually increases.
  • the maximum aperture d 1 of the light-transmitting hole and the minimum aperture d 2 of the light-transmitting hole satisfy the following relationship:
  • d 1 D*h/H+d 2 ;
  • D is the diameter of the microlens
  • h is the depth of the light-transmitting hole
  • H is the surface of the pattern recognition substrate facing the diaphragm layer and the surface of the microlens facing the diaphragm layer. The distance between side surfaces.
  • the above-mentioned texture recognition module provided by the embodiment of the present disclosure also includes a transparent filling layer located between the aperture layer and the layer where the plurality of microlenses are located;
  • H [D 2 /(8h x )+h x /2]/(n x -1)-n*h x /n x ;
  • h x is the sagittal height of the microlens
  • n is the refractive index of the material used in the microlens
  • n x is the refractive index of the transparent filling layer.
  • the microlenses are arranged in one-to-one correspondence with the light-transmitting holes, and the orthographic projection center of the microlenses on the substrate is It roughly coincides with the center of the orthographic projection of the corresponding light-transmitting hole on the base substrate.
  • the microlens includes a convex surface and a flat surface, and the convex surface is located on a side of the flat surface away from the light-transmitting hole.
  • the above-mentioned texture recognition module provided by the embodiment of the present disclosure further includes: an infrared cutoff film located between the aperture layer and the texture recognition substrate.
  • the substrate includes a texture recognition area and a frame area located on at least one side of the texture recognition area;
  • the texture identification substrate also includes a shielding electrode located on a side of the layer where the plurality of photosensitive devices are located away from the base substrate.
  • the shielding electrode is located in the display area and the frame area, and is in the frame area.
  • the shielding electrode includes a plurality of hollow structures.
  • the orthogonal projected area of the outermost hollow structure on the substrate is larger than that of the rest.
  • the orthogonal projected area of the hollow structure on the base substrate is larger than that of the rest.
  • the plurality of photosensitive devices are arranged in an array in the texture recognition area, and the plurality of hollow structures are arranged with each of the photosensitive devices. Or set in the same column.
  • each of the hollow structures in the same row or in the same row as the photosensitive device is arranged independently or electrically conductively with each other.
  • the above-mentioned texture recognition module provided by the embodiment of the present disclosure also includes a plurality of gate lines and a plurality of data lines arranged crosswise, and the plurality of gate lines and/or the plurality of data lines are Extends from the texture identification area to a side of the shielding electrode away from the texture identification area.
  • the texture recognition substrate further includes a bias electrode located between the layer where the multiple photosensitive devices are located and the layer where the shielding electrode is located. , the bias electrode is electrically connected to the shield electrode.
  • the orthographic projection of the bias electrode on the substrate is the same as the orthographic projection of the shield electrode on the substrate. The projections roughly coincide.
  • the texture recognition substrate further includes a resistance-reducing electrode located between the layer where the bias electrode is located and the base substrate, so The resistance reducing electrode is electrically connected to the shielding electrode through the bias electrode.
  • the resistance-reducing electrode is located in the frame area, and in the frame area, the resistance-reducing electrode is on the substrate.
  • the orthographic projection substantially coincides with the orthographic projection of the shield electrode on the base substrate.
  • the resistance-reducing electrode is located in the frame area, and in the frame area, the resistance-reducing electrode is located entirely in the area where the shield electrode is located. Face settings.
  • the photosensitive device includes a first electrode, a photoelectric conversion layer and a second electrode arranged in a stack, and the first electrode is adjacent to the substrate The substrate is arranged; the resistance-reducing electrode and the first electrode are arranged on the same layer.
  • the above-mentioned texture recognition module provided by the embodiment of the present disclosure further includes a plurality of transistors located between the photoelectric conversion layer and the base substrate, and the first electrode and the transistor The first pole is reused.
  • the above-mentioned texture recognition module provided by the embodiment of the present disclosure further includes a plurality of transistors located between the photoelectric conversion layer and the base substrate, and the layer where the first electrode is located is located on the The first electrode of the transistor is on a side away from the base substrate, and the first electrode is electrically connected to the first electrode of the transistor.
  • the texture recognition substrate further includes a plurality of binding electrodes, and the plurality of binding electrodes are located on the shielding electrode away from the texture recognition module. On one side of the area, the plurality of binding electrodes and the first electrode are arranged in the same layer.
  • the frame area surrounds the texture recognition area, and the frame area includes a first frame area for binding a bias voltage chip;
  • the binding electrode includes a first binding electrode located in the first frame area
  • the texture identification substrate also includes a first connection electrode arranged in the same layer as the bias electrode at the first binding electrode, and the first binding electrode is connected to the bias electrode through the first connection electrode.
  • the piezo electrodes are electrically connected.
  • the first frame area is also used to bind a data driver chip
  • the binding electrode further includes a second binding electrode located in the first frame area;
  • the texture recognition substrate further includes a second connection electrode disposed on the same layer as the first pole of the transistor at the second binding electrode, and the second binding electrode is connected to the second binding electrode through the second connection electrode.
  • the second pole of the transistor is electrically connected.
  • the frame area further includes a second frame area for binding a gate driver chip, and the second frame area is connected to the third frame area.
  • a border area is connected;
  • the binding electrode further includes a third binding electrode located in the second frame area;
  • the texture recognition substrate further includes a third connection electrode having corresponding electrical connections in the layer where the first electrode of the transistor is located and the layer where the gate electrode of the transistor is located at the third binding electrode, the A third binding electrode is electrically connected to the gate of the transistor through the third connection electrode.
  • embodiments of the present disclosure provide a method for manufacturing the above-mentioned texture recognition module, including:
  • an aperture layer having a plurality of light-transmitting holes arranged in an array on the substrate
  • a texture recognition substrate is provided, and the side where the diaphragm layer is located is fixed on the light incident side of the texture recognition substrate.
  • forming an aperture layer and a plurality of microlenses specifically includes: using an imprinting or patterning process to form the aperture layer and a plurality of microlenses.
  • an embodiment of the present disclosure provides a display device, including: a display module, a texture recognition module and an adhesive layer; wherein the texture recognition module is the above-mentioned texture recognition module provided by the embodiment of the present disclosure. , the texture recognition module is located on the opposite side of the display side of the display module, the adhesive layer is located between the display module and the texture recognition module, and the adhesive layer is on the display The orthographic projection on the module surrounds the display area of the display module.
  • Figure 1 is a schematic structural diagram of a texture recognition module provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of a film structure located on the light incident side of the texture recognition substrate in the texture recognition module provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of the microlens and light-transmitting hole in Figure 2;
  • Figure 4 is another structural schematic diagram of the microlens and light-transmitting hole in Figure 2;
  • Figure 5 is a schematic diagram of another film structure located on the light incident side of the texture recognition substrate in the texture recognition module provided by the embodiment of the present disclosure
  • Figure 6 is a schematic structural diagram of the microlens and light-transmitting hole in Figure 5;
  • Figure 7 is another structural schematic diagram of the microlens and light-transmitting hole in Figure 5;
  • Figure 8 is the light collection angle curve of the texture recognition module shown in Figure 2;
  • Figure 9 is the light collection angle curve of the texture recognition module shown in Figure 5;
  • Figure 10 is a schematic structural diagram of a shield electrode provided by an embodiment of the present disclosure.
  • Figure 11 is an enlarged schematic diagram of the M area in Figure 10;
  • Figure 12 is an enlarged schematic diagram of the N area in Figure 10;
  • Figure 13 is a schematic structural diagram of a texture recognition substrate provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic diagram of a shielding structure provided by an embodiment of the present disclosure.
  • Figure 15 is another structural schematic diagram of a texture recognition substrate provided by an embodiment of the present disclosure.
  • Figure 16 is an enlarged schematic diagram of the N area in Figure 13;
  • Figure 17 is an enlarged schematic diagram of the M area in Figure 13;
  • Figure 18 is another enlarged schematic diagram of the M area in Figure 13;
  • Figure 19 is a cross-sectional view along line II' in Figure 18;
  • Figure 20 is another enlarged schematic diagram of the N area in Figure 13;
  • Figure 21 is a cross-sectional view along line II-II' in Figure 20;
  • Figure 22 is another structural schematic diagram of a texture recognition module provided by an embodiment of the present disclosure.
  • Figure 23 is another structural schematic diagram of a texture recognition module provided by an embodiment of the present disclosure.
  • Figure 24 is another structural schematic diagram of a texture recognition module provided by an embodiment of the present disclosure.
  • Figure 25 is another structural schematic diagram of a texture recognition module provided by an embodiment of the present disclosure.
  • Figure 26 is another structural schematic diagram of a texture recognition module provided by an embodiment of the present disclosure.
  • Figure 27 is another structural schematic diagram of a texture recognition module provided by an embodiment of the present disclosure.
  • Figure 28 is another structural schematic diagram of a texture recognition module provided by an embodiment of the present disclosure.
  • Figure 29 is a schematic structural diagram of a pixel in the noise reduction area provided by an embodiment of the present disclosure.
  • Figure 30 is another structural schematic diagram of a pixel in the noise reduction area provided by an embodiment of the present disclosure.
  • Figure 31 is a flow chart of a method for making a texture recognition module according to an embodiment of the present disclosure
  • Figure 32 is a schematic structural diagram of the texture recognition module during the production process according to the embodiment of the present disclosure.
  • Figure 33 is another structural schematic diagram of the texture recognition module during the production process according to the embodiment of the present disclosure.
  • Figure 34 is another structural schematic diagram of the texture recognition module during the production process provided by the embodiment of the present disclosure.
  • Figure 35 is another structural schematic diagram of the texture recognition module during the production process provided by the embodiment of the present disclosure.
  • Figure 36 is another structural schematic diagram of the texture recognition module during the production process provided by the embodiment of the present disclosure.
  • Figure 37 is another structural schematic diagram of the texture recognition module during the production process provided by the embodiment of the present disclosure.
  • Figure 38 is another structural schematic diagram of the texture recognition module during the production process provided by the embodiment of the present disclosure.
  • Figure 39 is another structural schematic diagram of the texture recognition module during the production process provided by the embodiment of the present disclosure.
  • Figure 40 is a schematic structural diagram of a texture recognition module provided by an embodiment of the present disclosure.
  • FIG. 41 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • under-screen fingerprint recognition is achieved by setting up a texture recognition module under a full-screen display.
  • the existing texture recognition module uses at least two diaphragm layers on the texture recognition substrate to collimate the fingerprint reflected light collected by the microlens, and then collects the collimated light through the texture recognition substrate to achieve fingerprint recognition.
  • adjacent aperture layers need to be separated by a thicker transparent filling layer. Therefore, this solution cannot meet the development trend of thinner and lighter products.
  • a texture recognition module as shown in Figures 1 and 2, including:
  • the texture recognition substrate 101 includes a base substrate 1011 and a plurality of photosensitive devices 1012 arranged in an array on one side of the base substrate 1011; optionally, the base substrate 1011 can be a flexible base substrate, For example, a polyimide (PI) substrate; alternatively, the substrate substrate 1011 can also be a rigid substrate substrate, such as a glass (Glass) substrate; the photosensitive device 1012 can include a stacked first electrode 121, a photoelectric conversion layer 122 and a third Two electrodes 123, wherein the photoelectric conversion layer 122 may be a PIN structure, specifically may include a P-type semiconductor layer, an I-type semiconductor layer (also called an intrinsic semiconductor layer) and an N-type semiconductor layer; wherein the P-type semiconductor layer is located on the first Between the electrode 121 and the I-type semiconductor layer, the N-type semiconductor layer is located between the I-type semiconductor layer and the second electrode 123; or, the N-type semiconductor layer is located between the first electrode 121 and the I-type semiconductor layer, and the
  • the diaphragm layer 102 is located on the side of the texture identification substrate 101 that has a plurality of photosensitive devices 1012 (equivalent to the light incident side of the texture identification substrate 101).
  • the number of the diaphragm layer 102 is one layer.
  • the diaphragm layer 102 includes an array of The light-transmitting hole V of the cloth, the orthographic projection of the light-transmitting hole V on the substrate 1011 is located within the orthographic projection of the photosensitive device 1012 on the substrate 1011.
  • one photosensitive device 1012 can be connected to at least one light-transmitting hole.
  • the material of the diaphragm layer 102 can be It is black resin, molybdenum oxide, aluminum oxide or chromium metal and other light-shielding materials;
  • a plurality of microlenses 103 are located on the side of the diaphragm layer 102 away from the texture recognition substrate 101.
  • the orthographic projection of the microlenses 103 on the substrate 1011 covers the orthographic projection of the light-transmitting hole V on the substrate 1011; optionally , the material of the microlens 103 may be transparent resin.
  • the diaphragm layer 102 can be made to reflect the fingerprints condensed by the microlens 103 The light has a good collimation effect, so it can achieve a good fingerprint recognition effect while achieving thinness and lightness.
  • the light-transmitting hole V in the above-mentioned texture recognition module provided by the embodiment of the present disclosure, in the direction Z from the texture recognition substrate 101 to the aperture layer 102 , the light-transmitting hole V
  • the aperture d is approximately the same, for example, exactly the same, or within the error range caused by factors such as manufacturing and measurement.
  • the aperture of the light transmission hole V may gradually increase. That is to say, the light transmission hole V may have a diameter close to the texture recognition substrate 101 .
  • the minimum aperture d 2 of the substrate 101 , and the maximum aperture d 1 away from the texture recognition substrate 101 in the above-mentioned texture recognition module provided by the embodiment of the present disclosure, as shown in FIGS. 2 to 4 , the light-transmitting hole V The aperture d is approximately the same, for example, exactly the same, or within the error range caused by factors such as manufacturing and measurement.
  • the aperture of the light transmission hole V may gradually increase. That is to say, the light transmission hole V may have a diameter close to the texture
  • the aperture d of the light-transmitting hole V with a uniform aperture size may be equal to the maximum aperture d 1 .
  • the maximum aperture d 1 of the light-transmitting hole V and the minimum aperture d 2 of the light-transmitting hole V satisfy the following relationship:
  • d 1 D*h/H+d 2 ;
  • D is the diameter of the microlens 103
  • h is the depth of the light transmission hole V
  • H is the surface of the texture recognition substrate 101 facing the diaphragm layer 102 and the microlens 103 The distance between the surfaces facing the side of the aperture layer 102.
  • 1 ⁇ m ⁇ D ⁇ 50 ⁇ m
  • 2 ⁇ m ⁇ h ⁇ 8 ⁇ m 4 ⁇ m ⁇ d 1 ⁇ 12 ⁇ m
  • 1 ⁇ m ⁇ d 2 ⁇ 6 ⁇ m 40 ⁇ m ⁇ H ⁇ 160 ⁇ m.
  • the texture recognition module in order to improve the central transmittance of the light-transmitting hole V and effectively prevent crosstalk caused by stray light, as shown in Figure 1, Figure 2 and Figure 5 As shown, it may also include a transparent filling layer 104 located between the diaphragm layer 102 and the layer where the plurality of microlenses 103 are located; the surface of the texture recognition substrate 101 facing the diaphragm layer 102 and the side of the microlens 103 facing the diaphragm layer 102 The distance H between surfaces satisfies the following relationship:
  • H [D 2 /(8h x )+h x /2]/(n x -1)-n*h x /n x ;
  • h Alternatively , 2 ⁇ m ⁇ hx ⁇ 16 ⁇ m , 1.4 ⁇ m ⁇ nx ⁇ 1.8 ⁇ m, 1.5 ⁇ m ⁇ n ⁇ 2.2 ⁇ m.
  • Figure 8 shows the light collection angle curve when the above parameter relationship is satisfied and the light transmission hole V is in the shape shown in Figure 2.
  • Figure 9 shows the light collection angle curve when the above parameter relationship is satisfied and the light transmission hole V is in the shape shown in Figure 5.
  • FWHM full width at half maximum
  • the central transmittance that is, the peak of the light-density angle curve
  • FWHM is the core indicator that characterizes the fingerprint recognition effect.
  • FWHM is required to be within 8°
  • the area enclosed by the light collection angle curve and the abscissa is the fingerprint signal amount received by the photosensitive device 1012.
  • the fingerprint signal amount The higher the recognition accuracy, the greater the recognition accuracy. Therefore, when the FWHM is fixed, the center transmittance of the light-transmitting hole V is usually required to be as high as possible.
  • a texture recognition module using more than two aperture layers 102 has a corresponding center transmittance of about 42% under the condition that the FWHM is within 8°. Comparatively, it can be seen that compared to the related art, the center transmittance of the present disclosure is The transmittance increases by about 18%, which helps improve fingerprint recognition accuracy.
  • the microlenses 103 are arranged in one-to-one correspondence with the light-transmitting holes V, and the microlenses 103 are on the base substrate 1011
  • the orthographic projection center O 1 on the substrate 1011 roughly coincides with the orthographic projection center O 2 of the corresponding light-transmitting hole V on the base substrate 1011 , for example, they coincide exactly, or are within the deviation range caused by factors such as manufacturing and measurement.
  • the microlens 103 can also be provided corresponding to at least two light-transmitting holes V, which is not specifically limited here.
  • the microlens 103 may include a convex surface S 1 and a plane S 2 , and the convex surface S 1 is located on the side of the plane S 2 away from the light-transmitting hole V.
  • the microlens 103 may include a convex surface S 1 and a plane S 2 , wherein the convex surface S 1 is located on the side of the plane S 2 away from the light-transmitting hole V, so that the microlens 103 can effectively converge the reflected light of the fingerprint to the corresponding light-transmitting hole V.
  • the orthographic projection shape of the microlens 103 on the base substrate 1011 may be a circle as shown in FIGS. 3 and 6 , or a hexagon as shown in FIGS. 4 and 7 , etc., which will not be discussed here. limited.
  • the above-mentioned texture recognition module may also include: an infrared cutoff film (IR cut) 105, the infrared cut-off film 105 can accurately control the central wavelength in the visible light range below 600nm (380nm ⁇ 600nm), that is, the infrared cut-off film 105 only allows light from 380nm to 600nm to pass through, while light above 600nm will be absorbed. Since the light in the ambient light above 600 nm can shine on the microlens 103 through the finger, and then be collected by the photosensitive device 1012 through the light-transmitting hole V, thereby interfering with the fingerprint recognition effect. Therefore, the infrared cutoff film 105 is provided between the aperture layer 102 and the texture recognition substrate 101, which can effectively avoid interference from ambient light and improve the fingerprint recognition effect.
  • IR cut infrared cutoff film
  • the infrared cut-off film 105 and the texture recognition substrate 101 can be bonded and fixed through the first glue layer 106, and the infrared cut-off film 105 can be bonded and fixed through the second glue layer 107. and aperture layer 102.
  • a second transparent filling layer 108 can also be provided between the aperture layer 102 and the second glue layer 107.
  • the material of the first glue layer 106 and the second glue layer 107 may be optical adhesive tape (OCA), optical water glue (OCR), etc.
  • the base substrate 1011 includes a texture recognition area AA, and at least one area located in the texture recognition area AA.
  • the texture recognition substrate 101 also includes a shielding electrode 1013 located on the side of the layer where the plurality of photosensitive devices 102 are located away from the base substrate 101.
  • the shielding electrode 1013 is located in the display area AA and the frame area BB, and is in the frame area BB.
  • the shield electrode 1013 includes a plurality of first hollow structures K 1 to reduce the voltage drop (RC loading) of the shield electrode 1013 and improve the uniformity of the potential on the shield electrode 1013 .
  • the outermost first hollow structure K 1 in the extension direction X/Y of the frame area BB, the outermost first hollow structure K 1
  • the orthographic projection area on the base substrate 1011 is larger than the orthographic projection area of the remaining hollow structures K 1 on the base substrate 1011. That is, in the same frame area BB, the first hollow structure K 1 at both ends is larger, while the third hollow structure K 1 in the middle is larger.
  • a hollow structure K 1 is smaller, so that the area of the un-hollowed shield electrode 1013 at both ends of the frame area BB can be similar or the same as the area of the un-hollowed shield electrode 1013 in the middle of the frame area BB, further increasing the potential of the shield electrode 1013 of uniformity.
  • a plurality of photosensitive devices 1012 are arranged in an array in the texture recognition area AA, and a plurality of first hollow structures K 1 and Each photosensitive device 1012 is arranged in the same row or column, so that the average area of the shielding electrode 1013 in each row and column is similar or the same, ensuring the uniformity of the potential on the shielding electrode 1013.
  • the first hollow structures K 1 in the same row or column as the photosensitive device 1012 are independent of each other, or, as shown in FIG. 15 , the first hollow structures K 1 in the same row or column as the photosensitive device 1012 Structures K 1 are configured to be connected to each other.
  • the shielding electrode 1013 may have a shielding structure 1013 ′ covering the photosensitive device 1012 in the pattern identification area AA to shield external electromagnetic interference through the shielding electrode 1013 .
  • each shielding structure 1013' can be provided integrally.
  • a second hollow structure K 2 can also be provided around the shielding structure 1013'. The arrangement of the second hollow structure K2 can not only improve the potential uniformity on the shielding electrode 1013', but also effectively reduce the distance between the shielding electrode 1013' and the lower gate.
  • the coupling capacitance between the signal lines such as the line GL and the data line DL prevents the shield electrode 1013' from interfering with the signal lines such as the gate line GL and the data line DL.
  • multiple gate lines GL and/or multiple data lines DL extend from the texture recognition area AA to the shield.
  • the electrode 1013 is on one side away from the pattern identification area AA, so as to facilitate the detection of the gate line GL or the data line DL where the signal is abnormal (short circuit or open circuit).
  • the gate line GL and/or the data line DL extend at least a distance of one pixel relative to the shield electrode 1013. That is to say, the ends of the gate line GL and/or the data line DL in the frame area BB are separated from the shield electrode 1013.
  • the distance s between 1013 is greater than or equal to the size of one pixel (pitch).
  • the texture recognition substrate 101 may also include a layer where a plurality of photosensitive devices 1012 are located and a layer where the shielding electrode 1013 is located.
  • the bias electrode 1014 is electrically connected to the shield electrode 1013, so that the shield electrode 1013 is loaded with a bias voltage signal with a fixed potential through the bias electrode 1014.
  • the orthographic projection of the bias electrode 1014 on the substrate 1011 can be aligned with the shield electrode 1013 on the substrate.
  • the orthographic projections on the base substrate 1011 roughly coincide, that is, they coincide exactly or are within the error range caused by factors such as production and measurement. In this way, the same mask can be used to complete the production of the shield electrode 1013 and the bias electrode 1014. , saving mask costs.
  • both the shielding electrode 1013 and the bias electrode 1014 can be made of transparent conductive materials with good transmittance and low resistance, such as indium tin oxide, indium zinc oxide, etc.
  • the texture recognition substrate 101 also includes a layer where the bias electrode 1014 is located and a base substrate.
  • the resistance-reducing electrode 1015 between 1011 is electrically connected to the shield electrode 1013 through the bias electrode 1014 to further reduce the voltage drop of the shield electrode 1013 and improve the uniformity of the potential on the shield electrode 1013.
  • the resistance-reducing electrode 1015 is located in the frame area BB, and the resistance-reducing electrode 1015 is located on the base substrate
  • the orthographic projection on 1011 roughly coincides with the orthographic projection of the shielding electrode 1013 on the base substrate 1011 (that is, exactly coincident or within the error range caused by factors such as manufacturing and measurement).
  • the resistance-reducing electrode 1015 is on the base substrate 1011
  • the orthographic projection on the substrate 1011 does not overlap with the orthographic projection of all the first hollow structures K 1 on the base substrate 1011 .
  • the resistance-reducing electrode 1015 can also be provided on the entire area where the shielding electrode 1013 is located in the frame area BB.
  • the resistance reduction electrode 1015 can be provided in the same layer as the first electrode 121 of the photosensitive device 1012, so as to use the same film layer and complete the reduction based on one patterning process.
  • the production of the resistive electrode 1015 and the first electrode 121 saves patterning times and improves production efficiency.
  • the above-mentioned texture recognition module provided by the embodiment of the present disclosure also includes a plurality of transistors TFT located between the photoelectric conversion layer 122 and the base substrate 1011, and the first electrode 121 It is reused with the first electrode (such as the source electrode or the drain electrode) of the transistor TFT, that is, the first electrode and the first electrode 121 can be integrally formed.
  • the layer where the first electrode 121 is located may also be located on the side of the first pole of the transistor TFT away from the base substrate 1011 , and the first electrode 121 is electrically connected to the first pole of the transistor TFT. .
  • the texture recognition substrate 101 may also include a plurality of binding electrodes 1016.
  • the plurality of binding electrodes 1016 are located at On the side of the shielding electrode 1013 away from the pattern identification area AA, a plurality of binding electrodes 1016 and the first electrode 121 are arranged in the same layer to complete the production of the binding electrode 1016 and the first electrode 121 based on the same film layer and based on one patterning process. Save composition times and improve production efficiency.
  • the frame area BB surrounds the texture identification area AA, and the frame area BB includes a Set the first frame area BB 1 of the voltage chip (not shown in the figure); the bonding electrode 1016 includes a first bonding electrode 161 located in the first frame area BB 1 ; the texture recognition substrate 101 also includes a first bonding electrode 161 located in the first frame area BB 1.
  • the first connection electrode 1017 at the electrode 161 is arranged in the same layer as the bias electrode 1013.
  • the first binding electrode 161 is electrically connected to the bias electrode 1013 through the first connection electrode 1017, so that the bias provided by the bias chip can be
  • the set voltage signal is provided to the bias electrode 1013 through the first binding electrode 161 and the first connection electrode 1017 in sequence.
  • the first connection electrode 1017 may be integrally provided with the bias electrode 1013 .
  • the first frame area BB 1 is also used to bind the data driver chip (Source IC) IC 1
  • the binding electrode 1016 may also include a second binding electrode 162 located in the first frame area BB 1
  • the texture recognition substrate 101 may also include a third binding electrode 162 located in the same layer as the first pole of the transistor TFT.
  • the second connection electrode 1018 and the second binding electrode 162 are electrically connected to the first pole of the transistor TFT through the second connection electrode 1018.
  • the second connection electrode 1018 can be electrically connected to the first pole of the transistor TFT through the data line DL. .
  • the frame area BB can also include a gate driver chip (Gate IC) for binding
  • the second frame area BB 2 of IC 2 is connected to the first frame area BB 1 ;
  • the bonding electrode 1016 also includes a third bonding electrode 163 located in the second frame area BB 2 ;
  • the texture recognition substrate 101 It also includes a third connecting electrode 1019 with corresponding electrical connections in the layer where the first electrode of the transistor TFT is located and the layer where the gate electrode of the transistor TFT is located at the third binding electrode 163.
  • the third binding electrode 163 passes through the third
  • the connection electrode 1019 is electrically connected to the gate electrode of the transistor TFT.
  • the third connection electrode 1019 may be electrically connected to the gate electrode of the transistor TFT through the gate line GL.
  • the above-mentioned texture recognition module may also include a noise reduction area ODNC located between the texture recognition area AA and the frame area BB.
  • the noise reduction area ODNC has a plurality of dummy devices 1020 arranged in an array.
  • the dummy devices 1020 include opposite third electrodes 201 and fourth electrodes 202, and there is an insulating layer 1021 between the third electrode 201 and the fourth electrode 202.
  • the third electrode 201 can be placed in the same layer as the first electrode 121
  • the fourth electrode 202 can be placed in the same layer as the bias electrode 1013
  • the insulating layer 1021 can include a first inorganic insulating layer 211, a protective layer 212, and an organic insulating layer. layer 213 and the second inorganic insulating layer 214.
  • the texture recognition substrate 101 provided by the embodiment of the present disclosure may also include a gate insulating layer 1022 , a third inorganic insulation layer 1023 , etc., and other essential features of the texture recognition substrate 101 .
  • the components are all understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • embodiments of the present disclosure provide a method for manufacturing the above-mentioned texture recognition module. Since the principle of solving the problem of this manufacturing method is similar to the principle of solving the problem of the above-mentioned texture recognition module, therefore, the embodiment of the present disclosure provides For the implementation of this production method, please refer to the implementation of the above-mentioned texture recognition module provided by the embodiment of the present disclosure, and the repeated details will not be repeated.
  • an embodiment of the present disclosure provides a method for manufacturing the above-mentioned texture recognition module, as shown in Figure 31, including the following steps:
  • S3105 Provide a texture recognition substrate, and fix the side of the diaphragm layer on the light incident side of the texture recognition substrate.
  • the above-mentioned production method provided by the embodiments of the present disclosure can be implemented in the following ways:
  • a substrate 100 is provided, as shown in Figure 32.
  • a second transparent filling layer 108 with a thickness of 10 ⁇ m to 40 ⁇ m and a refractive index of 1.4 to 1.8 is formed on the substrate 100, as shown in FIG. 33 .
  • a light-shielding material layer 102' for making the diaphragm layer 102 is formed on the second transparent filling layer 108, as shown in Figure 34; the thickness of the light-shielding material layer 102' is between 2 ⁇ m and 8 ⁇ m.
  • the light-shielding material layer 102' is embossed to form an aperture layer 102 with a plurality of light-transmitting holes arranged in an array, as shown in Figure 35;
  • the thickness of the aperture layer 102 is 0.5 ⁇ m ⁇ 1 ⁇ m, and a patterning process is usually used to etch to form the light-transmitting hole in the aperture layer 102; the thickness of the aperture layer 102 in this disclosure is 2 ⁇ m ⁇ 8 ⁇ m.
  • the aperture layer 102 in this disclosure is thicker, so , the light-transmitting hole in the aperture layer 102 can be formed using an imprinting process with lower cost and simple procedures.
  • the present disclosure may also use a patterning process to etch and form light-transmitting holes in the aperture layer 102 .
  • a first transparent filling layer 104 with a thickness of 10 ⁇ m to 40 ⁇ m and a refractive index of 1.4 to 1.8 is formed on the diaphragm layer 102, as shown in FIG. 36 .
  • the sixth step is to form a transparent material layer 103' for making the microlens 103 on the first transparent filling layer 104, as shown in Figure 37; the thickness of the transparent material layer 103' is 2 ⁇ m to 16 ⁇ m, and the thickness of the transparent material layer 103' is 2 ⁇ m to 16 ⁇ m.
  • the refractive index is 1.5 ⁇ 2.2.
  • the transparent material layer 103' is imprinted or patterned to form multiple microlenses 103 covering multiple light-transmitting holes, as shown in Figure 38; the diameter of the microlenses 103 is 1 ⁇ m to 30 ⁇ m.
  • the substrate 100 is peeled off to obtain the stacked second transparent filling layer 108, the aperture layer 102, the first transparent filling layer 104 and a plurality of microlenses 103, as shown in FIG. 39 .
  • a texture recognition substrate 101 and an infrared cutoff film 105 are provided, and a first adhesive layer 106 is used to fix the infrared cutoff film 105 on the light incident side of the texture recognition substrate 101, and then a second adhesive layer 107 is used to fix the second transparent film 105 on the light incident side of the texture recognition substrate 101.
  • the filling layer 108 is fixedly bonded to the side of the infrared cutoff film 105 away from the texture recognition substrate 101, as shown in Figure 40.
  • the thickness of the first glue layer 106 and the second glue layer 107 is less than or equal to 15 ⁇ m, and the thickness of the infrared cutoff film 105 is 10 ⁇ m to 40 ⁇ m.
  • an embodiment of the present disclosure provides a display device, as shown in Figure 41, including: a texture recognition module 001, a display module 002 and an adhesive layer 003; wherein, the texture recognition module 001 is a display device of the present disclosure.
  • the texture recognition module 001 is located on the opposite side of the display side of the display module 002; the adhesive layer 003 is located between the display module 002 and the texture recognition module 001, and the adhesive layer 003 is on
  • the orthographic projection on the display module 002 surrounds the display area of the display module 002, causing the space surrounded by the texture recognition module 001, the display module 002 and the adhesive layer 003 to form an air gap, which is conducive to maintaining the light reflected by the fingers.
  • the propagation direction of the optical path remains unchanged.
  • the microlens 103 combined with the aperture layer 102 can filter out the small-angle light reflected by the finger in a nearly collimated manner, so that it reaches the photosensitive device 1012 below. on the photoelectric conversion layer 122.
  • the photoelectric conversion layer 122 can detect the intensity of light. Due to the difference in energy of light diffusely reflected downward by the valleys and ridges, the photosensitive device 1012 array detects different light intensities, thereby obtaining fingerprint image information.
  • the above-mentioned display device provided by the embodiments of the present disclosure may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other device with A product or component that displays functionality.
  • the display device includes but is not limited to: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, memory, processor, power supply and other components.
  • the above structure does not constitute a limitation on the above display device provided by the embodiment of the present disclosure.
  • the above display device provided by the embodiment of the present disclosure may include more or less of the above. components, or combinations of certain components, or different arrangements of components.

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Abstract

纹路识别模组（001）、其制作方法及显示装置，包括纹路识别基板（101），纹路识别基板（101）包括衬底基板（1011），以及在衬底基板（1011）一侧呈阵列排布的多个光敏器件（1012）；光阑层（102），位于纹路识别基板（101）具有多个光敏器件（1012）的一侧，光阑层（102）的数量为一层，光阑层（102）包括呈阵列排布的透光孔（V），透光孔（V）在衬底基板（1011）上的正投影位于光敏器件（1012）在衬底基板（1011）上的正投影内，透光孔（V）的深度（h）与透光孔（V）的最大孔径（d1）之比大于等于1/6且小于等于2；多个微透镜（103），位于光阑层（102）远离纹路识别基板（101）的一侧，微透镜（103）在衬底基板（1011）上的正投影覆盖透光孔（V）在衬底基板（1011）上的正投影。

Description

纹路识别模组、其制作方法及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种纹路识别模组、其制作方法及显示装置。
背景技术
随着信息行业的高速发展，生物识别技术受到了越来越广泛的应用，特别地，由于不同用户的指纹不同，便于进行用户身份确认，因此，指纹识别技术已经广泛应用在移动终端、智能家居等多个领域，为用户信息提供安全保障。
发明内容
本公开实施例提供的一种纹路识别模组、其制作方法及显示装置，具体方案如下：
一方面，本公开实施例提供了一种纹路识别模组，包括：
纹路识别基板，所述纹路识别基板包括衬底基板，以及在所述衬底基板一侧呈阵列排布的多个光敏器件；
光阑层，位于所述纹路识别基板具有所述多个光敏器件的一侧，所述光阑层的数量为一层，所述光阑层包括呈阵列排布的透光孔，所述透光孔在所述衬底基板上的正投影位于所述光敏器件在所述衬底基板上的正投影内，所述透光孔的深度与所述透光孔的最大孔径之比大于等于1/6且小于等于2；
多个微透镜，位于所述光阑层远离所述纹路识别基板的一侧，所述微透镜在所述衬底基板上的正投影覆盖所述透光孔在所述衬底基板上的正投影。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，在由所述纹路识别基板指向所述光阑层的方向上，所述透光孔的孔径大致相同。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，在由所 述纹路识别基板指向所述光阑层的方向上，所述透光孔的孔径逐渐增大。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述透光孔的最大孔径d 1与所述透光孔的最小孔径d 2满足以下关系：
d 1＝D*h/H+d 2；
其中，D为所述微透镜的口径，h为所述透光孔的深度，H为所述纹路识别基板朝向所述光阑层一侧的表面与所述微透镜朝向所述光阑层一侧的表面之间的距离。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，1μm≤D≤50μm，2μm≤h≤8μm，4μm≤d 1≤12μm，1μm≤d 2≤6μm，40μm≤H≤160μm。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，还包括位于所述光阑层与所述多个微透镜所在层之间的透明填充层；
所述纹路识别基板朝向所述光阑层一侧的表面与所述微透镜朝向所述光阑层一侧的表面之间的距离H满足以下关系：
H＝[D 2/(8h x)+h x/2]/(n x-1)-n*h x/n x；
其中，h x为所述微透镜的矢高，n为所述微透镜所用材料的折射率，n x为所述透明填充层的折射率。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，2μm≤h x≤16μm，1.4μm≤n x≤1.8μm，1.5μm≤n≤2.2μm。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述微透镜与所述透光孔一一对应设置，所述微透镜在所述衬底基板上的正投影中心与对应所述透光孔在所述衬底基板上的正投影中心大致重合。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述微透镜包括凸面和平面，所述凸面位于所述平面远离所述透光孔的一侧。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，还包括：位于所述光阑层与所述纹路识别基板之间的红外截止膜。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述衬 底基板包括纹路识别区、以及位于所述纹路识别区至少一侧的边框区；
所述纹路识别基板还包括位于所述多个光敏器件所在层远离所述衬底基板一侧的屏蔽电极，所述屏蔽电极位于所述显示区和所述边框区，且在所述边框区内，所述屏蔽电极包括多个镂空结构。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，在所述边框区的延伸方向上，最外侧的所述镂空结构在所述衬底基板上的正投影面积大于其余所述镂空结构在所述衬底基板上的正投影面积。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述多个光敏器件在所述纹路识别区呈阵列排布，所述多个镂空结构与各所述光敏器件同行或同列设置。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，与所述光敏器件同行或同列的各所述镂空结构相互独立或导通设置。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，还包括交叉设置的多条栅线和多条数据线，所述多条栅线和/或所述多条数据线自所述纹路识别区延伸至所述屏蔽电极远离所述纹路识别区的一侧。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述纹路识别基板还包括位于所述多个光敏器件所在层与所述屏蔽电极所在层之间的偏压电极，所述偏压电极与所述屏蔽电极电连接。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述偏压电极在所述衬底基板上的正投影与所述屏蔽电极在所述衬底基板上的正投影大致重合。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述纹路识别基板还包括位于所述偏压电极所在层与所述衬底基板之间的降阻电极，所述降阻电极通过所述偏压电极与所述屏蔽电极电连接。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述降阻电极位于所述边框区，且在所述边框区所述降阻电极在所述衬底基板上的正投影与所述屏蔽电极在所述衬底基板上的正投影大致重合。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述降阻电极位于所述边框区，且在所述边框区所述降阻电极在所述屏蔽电极所在区域整面设置。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述光敏器件包括层叠设置的第一电极、光电转换层和第二电极，所述第一电极邻近所述衬底基板设置；所述降阻电极与所述第一电极同层设置。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，还包括位于所述光电转换层与所述衬底基板之间的多个晶体管，所述第一电极与所述晶体管的第一极复用。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，还包括位于所述光电转换层与所述衬底基板之间的多个晶体管，所述第一电极所在层位于所述晶体管的第一极远离所述衬底基板的一侧，且所述第一电极与所述晶体管的第一极电连接。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述纹路识别基板还包括多个绑定电极，所述多个绑定电极位于所述屏蔽电极远离所述纹路识别区的一侧，所述多个绑定电极与所述第一电极同层设置。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述边框区包围所述纹路识别区，所述边框区包括用于绑定偏置电压芯片的第一边框区；
所述绑定电极包括位于所述第一边框区内的第一绑定电极；
所述纹路识别基板还包括在所述第一绑定电极处与所述偏压电极同层设置的第一连接电极，所述第一绑定电极通过所述第一连接电极与所述偏压电极电连接。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述第一边框区还用于绑定数据驱动芯片；
所述绑定电极还包括位于所述第一边框区的第二绑定电极；
所述纹路识别基板还包括在所述第二绑定电极处与所述晶体管的第一极 同层设置的第二连接电极，所述第二绑定电极通过所述第二连接电极与所述晶体管的第二极电连接。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，所述边框区还包括用于绑定栅极驱动芯片的第二边框区，所述第二边框区与所述第一边框区相连；
所述绑定电极还包括位于所述第二边框区的第三绑定电极；
所述纹路识别基板还包括在所述第三绑定电极处，在所述晶体管的第一极所在层、以及所述晶体管的栅极所在层中具有对应电连接的第三连接电极，所述第三绑定电极通过所述第三连接电极与所述晶体管的栅极电连接。
另一方面，本公开实施例提供了一种上述纹路识别模组的制作方法，包括：
提供一基底；
在所述基底上形成具有阵列排布的多个透光孔的一个光阑层；
在所述光阑层上形成覆盖所述多个透光孔的多个微透镜；
剥离掉所述基底；
提供一纹路识别基板，并将所述光阑层所在侧固定在所述纹路识别基板的入光侧。
在一些实施例中，在本公开实施例提供的上述制作方法中，形成光阑层和多个微透镜，具体包括：采用压印或构图工艺形成光阑层和多个微透镜。
另一方面，本公开实施例提供了一种显示装置，包括：显示模组、纹路识别模组和胶粘层；其中，所述纹路识别模组为本公开实施例提供的上述纹路识别模组，所述纹路识别模组位于所述显示模组显示侧的相对侧，所述胶粘层位于所述显示模组与所述纹路识别模组之间，且所述胶粘层在所述显示模组上的正投影包围所述显示模组的显示区。
附图说明
图1为本公开实施例提供的纹路识别模组的一种结构示意图；
图2为本公开实施例提供的纹路识别模组中位于纹路识别基板入光侧的一种膜层结构示意图；
图3为图2中微透镜与透光孔的一种结构示意图；
图4为图2中微透镜与透光孔的又一种结构示意图；
图5为本公开实施例提供的纹路识别模组中位于纹路识别基板入光侧的又一种膜层结构示意图；
图6为图5中微透镜与透光孔的一种结构示意图；
图7为图5中微透镜与透光孔的又一种结构示意图；
图8为图2所示纹路识别模组的收光角曲线；
图9为图5所示纹路识别模组的收光角曲线；
图10为本公开实施例提供的屏蔽电极的结构示意图；
图11为图10中M区域的放大示意图；
图12为图10中N区域的放大示意图；
图13为本公开实施例提供的纹路识别基板的一种结构示意图；
图14为本公开实施例提供的屏蔽结构的示意图；
图15为本公开实施例提供的纹路识别基板的又一种结构示意图；
图16为图13中N区域的一种放大示意图；
图17为图13中M区域的一种放大示意图；
图18为图13中M区域的又一种放大示意图；
图19为沿图18中I-I'线的截面图；
图20为图13中N区域的又一种放大示意图；
图21为沿图20中II-II'线的截面图；
图22为本公开实施例提供的纹路识别模组的又一种结构示意图；
图23为本公开实施例提供的纹路识别模组的又一种结构示意图；
图24为本公开实施例提供的纹路识别模组的又一种结构示意图；
图25为本公开实施例提供的纹路识别模组的又一种结构示意图；
图26为本公开实施例提供的纹路识别模组的又一种结构示意图；
图27为本公开实施例提供的纹路识别模组的又一种结构示意图；
图28为本公开实施例提供的纹路识别模组的又一种结构示意图；
图29为本公开实施例提供的降噪区内一个像素的一种结构示意图；
图30为本公开实施例提供的降噪区内一个像素的又一种结构示意图；
图31为本公开实施例提供纹路识别模组的制作方法的流程图；
图32为本公开实施例提供的纹路识别模组在制作过程中的一种结构示意图；
图33为本公开实施例提供的纹路识别模组在制作过程中的又一种结构示意图；
图34为本公开实施例提供的纹路识别模组在制作过程中的又一种结构示意图；
图35为本公开实施例提供的纹路识别模组在制作过程中的又一种结构示意图；
图36为本公开实施例提供的纹路识别模组在制作过程中的又一种结构示意图；
图37为本公开实施例提供的纹路识别模组在制作过程中的又一种结构示意图；
图38为本公开实施例提供的纹路识别模组在制作过程中的又一种结构示意图；
图39为本公开实施例提供的纹路识别模组在制作过程中的又一种结构示意图；
图40为本公开实施例提供的纹路识别模组的一种结构示意图；
图41为本公开实施例提供的显示装置的一种结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要 注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
全面屏的市占率逐渐提高，指纹识别的需求逐年增长，光学式大面积屏下指纹识别的需求逐渐显现。相关技术中通过在全面屏下设置纹路识别模组来实现屏下指纹识别。具体的，现有纹路识别模组在纹路识别基板上采用至少两个光阑层对由微透镜汇聚的指纹反射光线进行准直，再通过纹路识别基板采集准直后的光线实现指纹识别。然而，相邻光阑层需要通过较厚的透明填充层隔开，因此，这种方案不能满足产品轻薄化的发展趋势。
为了改善相关技术中存在的上述技术问题，本公开实施例提供了一种纹路识别模组，如图1和图2所示，包括：
纹路识别基板101，该纹路识别基板101包括衬底基板1011，以及在衬底基板1011一侧呈阵列排布的多个光敏器件1012；可选地，衬底基板1011可以为柔性衬底基板，例如聚酰亚胺(PI)基板；或者，衬底基板1011还可以为刚性衬底基板，例如玻璃(Glass)基板；光敏器件1012可以包括层叠设置的第一电极121、光电转换层122和第二电极123，其中，光电转换层122可以为PIN结构，具体可以包括P型半导体层、I型半导体层(也称本征半导体层)和N型半导体层；其中，P型半导体层位于第一电极121与I型半导体层之间，N型半导体层位于I型半导体层与第二电极123之间；或者，N型半 导体层位于第一电极121与I型半导体层之间，P型半导体层位于I型半导体层与第二电极123之间，在此不做限；
光阑层102，位于纹路识别基板101具有多个光敏器件1012的一侧(相当于纹路识别基板101的入光侧)，光阑层102的数量为一层，光阑层102包括呈阵列排布的透光孔V，透光孔V在衬底基板1011上的正投影位于光敏器件1012在衬底基板1011上的正投影内，可选地，一个光敏器件1012可以与至少一个透光孔V对应设置，透光孔V的深度h与透光孔V的最大孔径d 1之比(即深宽比)大于等于1/6且小于等于2；可选地，光阑层102的材料可以为黑色树脂、氧化钼、氧化铝或铬金属等遮光材料；
多个微透镜103，位于光阑层102远离纹路识别基板101的一侧，微透镜103在衬底基板1011上的正投影覆盖透光孔V在衬底基板1011上的正投影；可选地，微透镜103的材料可以为透明树脂。
在本公开实施例提供的上述纹路识别模组中，仅设置了单一的光阑层102，相较于相关技术中设置两层以上光阑层102的技术方案，不仅减少了光阑层102的数量，同时节约了光阑层102之间的透明填充层，由此可有效减小纹路识别模组的整体厚度，利于实现纹路识别模组的轻薄化设计。并且，由于本公开中光阑层102的深度h与透光孔V的最大孔径d 1之比大于等于1/6且小于等于2，可以使得光阑层102对由微透镜103汇聚的指纹反射光线起到良好的准直效果，因此，在实现轻薄化的同时可以兼顾良好的指纹识别效果。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图2至图4所示，在由纹路识别基板101指向光阑层102的方向Z上，透光孔V的孔径d大致相同，例如恰好相同，或在因制作、测量等因素造成的误差范围内。或者，如图5至图7所示，在由纹路识别基板101指向光阑层102的方向Z上，透光孔V的孔径可以逐渐增大，也就是说，透光孔V具有靠近纹路识别基板101的最小孔径d 2，以及远离纹路识别基板101的最大孔径d 1。在本公开中，孔径大小均一的透光孔V的孔径d可以等于最大孔径d 1。可选地，为保证指纹识别的质量，透光孔V的最大孔径d 1与透光孔V的最小孔径 d 2满足以下关系：
d 1＝D*h/H+d 2；
其中，如图1、图2和图5所示，D为微透镜103的口径，h为透光孔V的深度，H为纹路识别基板101朝向光阑层102一侧的表面与微透镜103朝向光阑层102一侧的表面之间的距离。在一些实施例中，1μm≤D≤50μm，2μm≤h≤8μm，4μm≤d 1≤12μm，1μm≤d 2≤6μm，40μm≤H≤160μm。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，为了提高透光孔V的中心透过率并有效防止杂散光造成的串扰，如图1、图2和图5所示，还可以包括位于光阑层102与多个微透镜103所在层之间的透明填充层104；纹路识别基板101朝向光阑层102一侧的表面与微透镜103朝向光阑层102一侧的表面之间的距离H满足以下关系：
H＝[D 2/(8h x)+h x/2]/(n x-1)-n*h x/n x；
其中，h x为微透镜103的矢高，n为微透镜103所用材料的折射率，n x为透明填充层104的折射率。可选地，2μm≤h x≤16μm，1.4μm≤n x≤1.8μm，1.5μm≤n≤2.2μm。
图8示出了满足上述参数关系且透光孔V为图2所示形状的情况下的收光角曲线，图9示出了满足上述参数关系且透光孔V为图5所示形状的情况下的收光角曲线。在图8和图9中收光角曲线的半峰全宽(full width at half maxima，FWHM)均可以达到7°～8°时，中心透过率(即收光角曲线的峰值)约60％。FWHM是表征指纹识别效果的核心指标，通常为满足指纹识别要求，FWHM要求在8°以内，而收光角曲线与横坐标围起来的面积是光敏器件1012接收到的指纹信号量，指纹信号量越高识别精度越大，因此通常要求在FWHM固定的情况下，透光孔V的中心透过率越高越好。相关技术中采用两层以上光阑层102的纹路识别模组，在满足8°以内的FWHM的条件下对应的中心透过率约为42％，对比可知，相对于相关技术，本公开的中心透过率增大约18％，利于提升指纹识别精度。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图2至图7所示，微透镜103与透光孔V一一对应设置，微透镜103在衬底基板1011上的正投影中心O 1与对应透光孔V在衬底基板1011上的正投影中心O 2大致重合，例如恰好重合，或在因制作、测量等因素造成的偏差范围内。这样可以使得被微透镜103汇聚后的指纹反射光经由透光孔V全部入射至光敏器件1012内，从而提高信号量，增大信噪比。当然，在具体实施时，一个微透镜103还可以与至少两个透光孔V对应设置，在此不做具体限定。在一些实施例中，微透镜103可以包括凸面S 1和平面S 2，凸面S 1位于平面S 2远离透光孔V的一侧微透镜103包括凸面S 1和平面S 2，其中，凸面S 1位于平面S 2远离透光孔V的一侧，以使得微透镜103可将指纹的反射光线有效汇聚至对应透光孔V处。可选地，微透镜103在衬底基板1011上的正投影形状可以为图3和图6所示的圆形，也可以为图4和图7所示的六边形等，在此不做限定。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图2和图5所示，还可以包括：位于光阑层102与纹路识别基板101之间的红外截止膜(IR cut)105，该红外截止膜105可将中心波长精确控制在低于600nm的可见光范围(380nm～600nm)，即红外截止膜105仅允许380nm～600nm的光线通过，而高于600nm的光线都会被吸收掉。由于环境光中600nm以上的光线可透过手指照射至微透镜103上，进而经过透光孔V被光敏器件1012采集而干扰指纹识别效果。因此光阑层102与纹路识别基板101之间设置红外截止膜105，可以有效避免环境光的干扰，提高指纹识别效果。
可选地，如图1、图2和图5所示，可通过第一胶层106粘结固定红外截止膜105与纹路识别基板101，并通过第二胶层107粘结固定红外截止膜105与光阑层102。为了给光阑层102提供一个平整的制作表面，还可以在光阑层102与第二胶层107之间设置第二透明填充层108。在一些实施例中，第一胶层106和第二胶层107的材料可以为光学胶带(OCA)、光学水胶(OCR)等。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图1、 图10至图12所示，衬底基板1011包括纹路识别区AA、以及位于纹路识别区AA至少一侧的边框区BB；纹路识别基板101还包括位于多个光敏器件102所在层远离衬底基板101一侧的屏蔽电极1013，屏蔽电极1013位于显示区AA和边框区BB，且在边框区BB内，屏蔽电极1013包括多个第一镂空结构K 1，以减小屏蔽电极1013的压降(RC loading)，提高屏蔽电极1013上电位的均一性。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图10至图12所示，在边框区BB的延伸方向X/Y上，最外侧的第一镂空结构K 1在衬底基板1011上的正投影面积大于其余镂空结构K 1在衬底基板1011上的正投影面积，即在同一边框区BB内，两端的第一镂空结构K 1较大，而中间的第一镂空结构K 1较小，这样就可以使得边框区BB两端处未镂空的屏蔽电极1013面积与边框区BB中间处未镂空的屏蔽电极1013的面积相近或相同，进一步提高屏蔽电极1013上电位的均一性。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图13所示，多个光敏器件1012在纹路识别区AA呈阵列排布，多个第一镂空结构K 1与各光敏器件1012同行或同列设置，以使得屏蔽电极1013在每行和每列上的均摊面积相近或相同，保证屏蔽电极1013上电位的均一性。可选地，如图13所示，与光敏器件1012同行或同列的各第一镂空结构K 1之间相互独立，或者，如图15所示，与光敏器件1012同行或同列的各第一镂空结构K 1之间相互导通设置。
继续参见图10、图13至图15，屏蔽电极1013在纹路识别区AA内可以具有覆盖光敏器件1012的屏蔽结构1013’，以通过屏蔽电极1013屏蔽外界电磁干扰。可选地，为便于为各屏蔽结构1013’加载电信号，可以将各屏蔽结构1013’一体设置。同时屏蔽结构1013’的周围还可以设置第二镂空结构K 2，第二镂空结构K 2的设置不但可以提高屏蔽电极1013’上的电位均一性，而且可以有效减小屏蔽电极1013’与下方栅线GL、数据线DL等信号线之间的耦合电容，避免屏蔽电极1013’与栅线GL、数据线DL等信号线相互干扰。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图16和图17所示，多条栅线GL和/或多条数据线DL自纹路识别区AA延伸至屏蔽电极1013远离纹路识别区AA的一侧，以便于检测信号发生异常(短路或断路)的栅线GL或数据线DL。可选地，栅线GL和/或数据线DL相对于屏蔽电极1013至少延伸出一个像素的距离，也就是说，栅线GL和/或数据线DL在边框区BB内的端部与屏蔽电极1013之间的距离s大于等于一个像素的尺寸(pitch)。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图18和图19所示，纹路识别基板101还可以包括位于多个光敏器件1012所在层与屏蔽电极1013所在层之间的偏压电极1014，该偏压电极1014与屏蔽电极1013电连接，以通过偏压电极1014为屏蔽电极1013加载电位固定的偏置电压信号。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图18和图19所示，偏压电极1014在衬底基板1011上的正投影可以与屏蔽电极1013在衬底基板1011上的正投影大致重合，即恰好重合或在因制作、测量等因素造成的误差范围内，这样就可以利用同一掩膜板(Mask)完成屏蔽电极1013与偏压电极1014的制作，节省了掩膜板成本。为了提高光线透过率，屏蔽电极1013和偏压电极1014均可以采用透过率较好且电阻较小的透明导电材料制作，例如氧化铟锡、氧化铟锌等。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图13、图20和图21所示，纹路识别基板101还包括位于偏压电极1014所在层与衬底基板1011之间的降阻电极1015，降阻电极1015通过偏压电极1014与屏蔽电极1013电连接，以进一步减小屏蔽电极1013的压降，提高屏蔽电极1013上电位的均一性。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图13、图20和图21所示，降阻电极1015位于边框区BB，且降阻电极1015在衬底基板1011上的正投影与屏蔽电极1013在衬底基板1011上的正投影大致重合 (即恰好重合或在因制作、测量等因素造成的误差范围内)，换言之，降阻电极1015在衬底基板1011上的正投影与全部第一镂空结构K 1在衬底基板1011上的正投影互不交叠。在一些实施例中，为便于制作降阻电极1015，降阻电极1015也可以在边框区BB内屏蔽电极1013所在区域整面设置。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，降阻电极1015可以与光敏器件1012的第一电极121同层设置，以采用同一膜层并基于一次构图工艺完成降阻电极1015与第一电极121的制作，节约构图次数，提高生产效率。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图1所示，还包括位于光电转换层122与衬底基板1011之间的多个晶体管TFT，第一电极121与晶体管TFT的第一极(例如源极或漏极)复用，即第一极和第一电极121可以一体成型。在一些实施例中，如图22所示，第一电极121所在层还可以位于晶体管TFT的第一极远离衬底基板1011的一侧，且第一电极121与晶体管TFT的第一极电连接。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图1和图22所示，纹路识别基板101还可以包括多个绑定电极1016，多个绑定电极1016位于屏蔽电极1013远离纹路识别区AA的一侧，多个绑定电极1016与第一电极121同层设置，以采用同一膜层并基于一次构图工艺完成绑定电极1016与第一电极121的制作，节约构图次数，提高生产效率。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图1、图22和图23所示，边框区BB包围纹路识别区AA，边框区BB包括用于绑定偏置电压芯片(图中未示出)的第一边框区BB 1；绑定电极1016包括位于第一边框区BB 1内的第一绑定电极161；纹路识别基板101还包括在第一绑定电极161处与偏压电极1013同层设置的第一连接电极1017，第一绑定电极161通过第一连接电极1017与偏压电极1013电连接，这样就可以使得偏置芯片提供的偏置电压信号依次通过第一绑定电极161和第一连接电极1017提供给偏压电极1013。在一些实施例中，第一连接电极1017可以与偏压电极1013 一体设置。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图23至图25所示，第一边框区BB 1内还用于绑定数据驱动芯片(Source IC)IC 1，绑定电极1016还可以包括位于第一边框区BB 1的第二绑定电极162；纹路识别基板101还可以包括在第二绑定电极162处与晶体管TFT的第一极同层设置的第二连接电极1018，第二绑定电极162通过第二连接电极1018与晶体管TFT的第一极电连接，可选地，第二连接电极1018可以通过数据线DL与晶体管TFT的第一极电连接。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图23、图26和图27所示，边框区BB还可以包括用于绑定栅极驱动芯片(Gate IC)IC 2的第二边框区BB 2，第二边框区BB 2与第一边框区BB 1相连；绑定电极1016还包括位于第二边框区BB 2的第三绑定电极163；纹路识别基板101还包括在第三绑定电极163处，在晶体管TFT的第一极所在层、以及晶体管TFT的栅极所在层中具有对应电连接的第三连接电极1019，第三绑定电极163通过第三连接电极1019与晶体管TFT的栅极电连接，可选地，第三连接电极1019可以通过栅线GL与晶体管TFT的栅极电连接。
在一些实施例中，在本公开实施例提供的上述纹路识别模组中，如图28至图30所示，还可以包括位于纹路识别区AA与边框区BB之间的降噪区ODNC，在降噪区ODNC具有多个阵列排布的虚拟器件1020，虚拟器件1020包括相对而置的第三电极201和第四电极202，且在第三电极201和第四电极202之间具有绝缘层1021，其中，第三电极201可以与第一电极121同层设置，第四电极202可以与偏压电极1013同层设置，绝缘层1021可以包括第一无机绝缘层211、保护层212、有机绝缘层213和第二无机绝缘层214。
可选地，如图29和图30所示，本公开实施例提供的纹路识别基板101还可以包括栅绝缘层1022、第三无机绝缘层1023等，对于纹路识别基板101的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
基于同一发明构思，本公开实施例提供了一种上述纹路识别模组的制作方法，由于该制作方法解决问题的原理与上述纹路识别模组解决问题的原理相似，因此，本公开实施例提供的该制作方法的实施可以参见本公开实施例提供的上述纹路识别模组的实施，重复之处不再赘述。
具体地，本公开实施例提供的一种上述纹路识别模组的制作方法，如图31所示，包括以下步骤：
S3101、提供一基底；
S3102、在基底上形成具有阵列排布的多个透光孔的一个光阑层；
S3103、在光阑层上形成覆盖多个透光孔的多个微透镜；
S3104、剥离掉基底；
S3105、提供一纹路识别基板，并将光阑层所在侧固定在纹路识别基板的入光侧。
在一些实施例中，本公开实施例提供的上述制作方法，具体可以通过以下方式进行实现：
第一步，提供一基底100，如图32所示。
第二步，在基底100上形成厚度为10μm～40μm、折射率为1.4～1.8的第二透明填充层108，如图33所示。
第三步，在第二透明填充层108上形成用于制作光阑层102的遮光材料层102'，如图34所示；遮光材料层102'的厚度在2μm～8μm。
第四步，对遮光材料层102'进行压印形成具有阵列排布的多个透光孔的一个光阑层102，如图35所示；相关技术中光阑层102的厚度为0.5μm～1μm，且通常采用构图工艺刻蚀形成光阑层102中的透光孔；本公开中的光阑层102的厚度为2μm～8μm，可以看出，本公开的光阑层102较厚，因此，可采用成本较低、工序简单的压印工艺形成光阑层102中的透光孔。当然，在一些实施例中，本公开也可以采用构图工艺刻蚀形成光阑层102中的透光孔。
第五步，在光阑层102上形成厚度为10μm～40μm、折射率为1.4～1.8的第一透明填充层104，如图36所示。
第六步，在第一透明填充层104上形成用于制作微透镜103的透明材料层103'，如图37所示；透明材料层103'的厚度为2μm～16μm，透明材料层103'的折射率为1.5～2.2。
第七步，对透明材料层103'进行压印或构图形成覆盖多个透光孔的多个微透镜103，如图38所示；微透镜103的口径为1μm～30μm。
第八步，剥离掉基底100，获得层叠设置的第二透明填充层108、光阑层102、第一透明填充层104和多个微透镜103，如图39所示。
第九步，提供一纹路识别基板101和红外截止膜105，并采用第一胶层106将红外截止膜105固定在纹路识别基板101的入光侧，之后采用第二胶层107将第二透明填充层108与红外截止膜105远离纹路识别基板101的一侧固定粘结，如图40所示。其中，第一胶层106和第二胶层107的厚度均小于等于15μm，红外截止膜105的厚度为10μm～40μm。至此完成了本公开实施例提供的纹路识别模组的制作。
基于同一发明构思，本公开实施例提供了一种显示装置，如图41所示，包括：纹路识别模组001、显示模组002和胶粘层003；其中，纹路识别模组001为本公开实施例提供的上述纹路识别模组001，纹路识别模组001位于显示模组002显示侧的相对侧；胶粘层003位于显示模组002与纹路识别模组001之间，胶粘层003在显示模组002上的正投影包围显示模组002的显示区，使得纹路识别模组001、显示模组002以及胶粘层003围成的空间形成空气层(air gap)，利于维持手指反射光的光路传播方向不变。
在进行指纹识别时，当手指触摸到显示模组001时，微透镜103结合光阑层102可将手指反射光线中小角度的光线近于准直化的筛选出，使其到达下方光敏器件1012的光电转换层122上。光电转换层122可以探测出光线的强度，由于谷与脊向下漫反射光的能量不同，光敏器件1012阵列探测得到的光强不同，由此获取指纹图像信息。
在一些实施例中，本公开实施例提供的上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健 身腕带、个人数字助理等任何具有显示功能的产品或部件。该显示装置包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (30)

  1. 一种纹路识别模组，其中，包括：
    纹路识别基板，所述纹路识别基板包括衬底基板，以及在所述衬底基板一侧呈阵列排布的多个光敏器件；
    光阑层，位于所述纹路识别基板具有所述多个光敏器件的一侧，所述光阑层的数量为一层，所述光阑层包括呈阵列排布的透光孔，所述透光孔在所述衬底基板上的正投影位于所述光敏器件在所述衬底基板上的正投影内，所述透光孔的深度与所述透光孔的最大孔径之比大于等于1/6且小于等于2；
    多个微透镜，位于所述光阑层远离所述纹路识别基板的一侧，所述微透镜在所述衬底基板上的正投影覆盖所述透光孔在所述衬底基板上的正投影。
  2. 如权利要求1所述的纹路识别模组，其中，在由所述纹路识别基板指向所述光阑层的方向上，所述透光孔的孔径大致相同。
  3. 如权利要求1所述的纹路识别模组，其中，在由所述纹路识别基板指向所述光阑层的方向上，所述透光孔的孔径逐渐增大。
  4. 如权利要求3所述的纹路识别模组，其中，所述透光孔的最大孔径d 1与所述透光孔的最小孔径d 2满足以下关系：
    d 1＝D*h/H+d 2；
    其中，D为所述微透镜的口径，h为所述透光孔的深度，H为所述纹路识别基板朝向所述光阑层一侧的表面与所述微透镜朝向所述光阑层一侧的表面之间的距离。
  5. 如权利要求4所述的纹路识别模组，其中，1μm≤D≤50μm，2μm≤h≤8μm，4μm≤d 1≤12μm，1μm≤d 2≤6μm，40μm≤H≤160μm。
  6. 如权利要求1～5任一项所述的纹路识别模组，其中，还包括位于所述光阑层与所述多个微透镜所在层之间的透明填充层；
    所述纹路识别基板朝向所述光阑层一侧的表面与所述微透镜朝向所述光阑层一侧的表面之间的距离H满足以下关系：
    H＝[D 2/(8h x)+h x/2]/(n x-1)-n*h x/n x；
    其中，h x为所述微透镜的矢高，n为所述微透镜所用材料的折射率，n x为所述透明填充层的折射率。
  7. 如权利要求6所述的纹路识别模组，其中，2μm≤h x≤16μm，1.4μm≤n x≤1.8μm，1.5μm≤n≤2.2μm。
  8. 如权利要求1～7任一项所述的纹路识别模组，其中，所述微透镜与所述透光孔一一对应设置，所述微透镜在所述衬底基板上的正投影中心与对应所述透光孔在所述衬底基板上的正投影中心大致重合。
  9. 如权利要求8所述的纹路识别模组，其中，所述微透镜包括凸面和平面，所述凸面位于所述平面远离所述透光孔的一侧。
  10. 如权利要求1～9任一项所述的纹路识别模组，其中，还包括：位于所述光阑层与所述纹路识别基板之间的红外截止膜。
  11. 如权利要求1～10任一项所述的纹路识别模组，其中，所述衬底基板包括纹路识别区、以及位于所述纹路识别区至少一侧的边框区；
    所述纹路识别基板还包括位于所述多个光敏器件所在层远离所述衬底基板一侧的屏蔽电极，所述屏蔽电极位于所述显示区和所述边框区，且在所述边框区内，所述屏蔽电极包括多个镂空结构。
  12. 如权利要求11所述的纹路识别模组，其中，在所述边框区的延伸方向上，最外侧的所述镂空结构在所述衬底基板上的正投影面积大于其余所述镂空结构在所述衬底基板上的正投影面积。
  13. 如权利要求11或12所述的纹路识别模组，其中，所述多个光敏器件在所述纹路识别区呈阵列排布，所述多个镂空结构与各所述光敏器件同行或同列设置。
  14. 如权利要求13所述的纹路识别模组，其中，与所述光敏器件同行或同列的各所述镂空结构相互独立或导通设置。
  15. 如权利要求11～24任一项所述的纹路识别模组，其中，还包括交叉设置的多条栅线和多条数据线，所述多条栅线和/或所述多条数据线自所述纹 路识别区延伸至所述屏蔽电极远离所述纹路识别区的一侧。
  16. 如权利要求11～15任一项所述的纹路识别模组，其中，所述纹路识别基板还包括位于所述多个光敏器件所在层与所述屏蔽电极所在层之间的偏压电极，所述偏压电极与所述屏蔽电极电连接。
  17. 如权利要求16所述的纹路识别模组，其中，所述偏压电极在所述衬底基板上的正投影与所述屏蔽电极在所述衬底基板上的正投影大致重合。
  18. 如权利要求16或17所述的纹路识别模组，其中，所述纹路识别基板还包括位于所述偏压电极所在层与所述衬底基板之间的降阻电极，所述降阻电极通过所述偏压电极与所述屏蔽电极电连接。
  19. 如权利要求18所述的纹路识别模组，其中，所述降阻电极位于所述边框区，且在所述边框区所述降阻电极在所述衬底基板上的正投影与所述屏蔽电极在所述衬底基板上的正投影大致重合。
  20. 如权利要求18所述的纹路识别模组，其中，所述降阻电极位于所述边框区，且在所述边框区所述降阻电极在所述屏蔽电极所在区域整面设置。
  21. 如权利要求18～20任一项所述的纹路识别模组，其中，所述光敏器件包括层叠设置的第一电极、光电转换层和第二电极，所述第一电极邻近所述衬底基板设置；所述降阻电极与所述第一电极同层设置。
  22. 如权利要求21所述的纹路识别模组，其中，还包括位于所述光电转换层与所述衬底基板之间的多个晶体管，所述第一电极与所述晶体管的第一极复用。
  23. 如权利要求21所述的纹路识别模组，其中，还包括位于所述光电转换层与所述衬底基板之间的多个晶体管，所述第一电极所在层位于所述晶体管的第一极远离所述衬底基板的一侧，且所述第一电极与所述晶体管的第一极电连接。
  24. 如权利要求21～23任一项所述的纹路识别模组，其中，所述纹路识别基板还包括多个绑定电极，所述多个绑定电极位于所述屏蔽电极远离所述纹路识别区的一侧，所述多个绑定电极与所述第一电极同层设置。
  25. 如权利要求24所述的纹路识别模组，其中，所述边框区包围所述纹路识别区，所述边框区包括用于绑定偏置电压芯片的第一边框区；
    所述绑定电极包括位于所述第一边框区内的第一绑定电极；
    所述纹路识别基板还包括在所述第一绑定电极处与所述偏压电极同层设置的第一连接电极，所述第一绑定电极通过所述第一连接电极与所述偏压电极电连接。
  26. 如权利要求25所述的纹路识别模组，其中，所述第一边框区还用于绑定数据驱动芯片；
    所述绑定电极还包括位于所述第一边框区的第二绑定电极；
    所述纹路识别基板还包括在所述第二绑定电极处与所述晶体管的第一极同层设置的第二连接电极，所述第二绑定电极通过所述第二连接电极与所述晶体管的第二极电连接。
  27. 如权利要求25或26所述的纹路识别模组，其中，所述边框区还包括用于绑定栅极驱动芯片的第二边框区，所述第二边框区与所述第二边框区相连；
    所述绑定电极还包括位于所述第二边框区的第三绑定电极；
    所述纹路识别基板还包括在所述第三绑定电极处，在所述晶体管的第一极所在层、以及所述晶体管的栅极所在层中具有对应电连接的第三连接电极，所述第三绑定电极通过所述第三连接电极与所述晶体管的栅极电连接。
  28. 一种如权利要求1～27任一项所述纹路识别模组的制作方法，其中，包括：
    提供一基底；
    在所述基底上形成具有阵列排布的多个透光孔的一个光阑层；
    在所述光阑层上形成覆盖所述多个透光孔的多个微透镜；
    剥离掉所述基底；
    提供一纹路识别基板，并将所述光阑层所在侧固定在所述纹路识别基板的入光侧。
  29. 如权利要求28所述的制作方法，其中，形成光阑层和多个微透镜，具体包括：采用压印或构图工艺形成光阑层和多个微透镜。
  30. 一种显示装置，其中，包括：显示模组、纹路识别模组和胶粘层；其中，所述纹路识别模组为如权利要求1～27任一项所述的纹路识别模组，所述纹路识别模组位于所述显示模组显示侧的相对侧，所述胶粘层位于所述显示模组与所述纹路识别模组之间，且所述胶粘层在所述显示模组上的正投影包围所述显示模组的显示区。
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