WO2023173628A1 - 半导体结构及存储器 - Google Patents

半导体结构及存储器 Download PDF

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Publication number
WO2023173628A1
WO2023173628A1 PCT/CN2022/103958 CN2022103958W WO2023173628A1 WO 2023173628 A1 WO2023173628 A1 WO 2023173628A1 CN 2022103958 W CN2022103958 W CN 2022103958W WO 2023173628 A1 WO2023173628 A1 WO 2023173628A1
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test pad
chip
semiconductor
test
stacked chip
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PCT/CN2022/103958
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English (en)
French (fr)
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杨正杰
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长鑫存储技术有限公司
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Publication of WO2023173628A1 publication Critical patent/WO2023173628A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a memory.
  • packaging technology continues to improve. Three-dimensional stacked chips formed using stacked packaging technology can effectively utilize the chip area and increase storage capacity.
  • the present disclosure provides a semiconductor structure and memory.
  • a semiconductor structure including a stacked chip assembly.
  • the stacked chip assembly includes a plurality of semiconductor chips arranged in a stack, and a first electrical connection structure is provided in each of the semiconductor chips. The adjacent semiconductor chips are connected through the first electrical connection structure;
  • a stacked chip test pad is provided on at least one of the semiconductor chips.
  • the stacked chip test pad is connected to the first electrical connection structure in the semiconductor chip where it is located and the circuit to be tested, so as to test the stacked chip test pad received. Signals are transmitted to each of the semiconductor chips.
  • the first electrical connection structure includes a through electrode, and the stacked chip test pad is connected to the through electrode through a first conductive layer.
  • each of the stacked chip test pads is provided with a plurality of through electrodes
  • the stacked chip test pad is in a square shape
  • the plurality of through electrodes are provided on one side of the stacked chip test pad and along this side. The edges are arranged at intervals.
  • multiple stacked chip test pads are provided on the same semiconductor chip, and different stacked chip test pads are used to receive different test signals.
  • the test signal includes a command signal, an address signal, a data signal and/or a power signal.
  • the stacked chip test pad is provided in an edge area of the semiconductor chip.
  • the semiconductor chip is provided with a plurality of spaced-apart channels, with a spacing area between the channels, and the stacked chip test pad is disposed in the spacing area.
  • the stacked chip test pad is disposed on top of an edge area of the semiconductor chip.
  • each of the semiconductor chips is provided with a wafer test pad, and the wafer test pad is connected to the circuit to be tested in the semiconductor chip where it is located.
  • the semiconductor chip provided with the stacked chip test pad includes a first test pad area and a second test pad area, the stacked chip test pad and the first electrical connection structure connected to the stacked chip test pad are both Located in the first test pad area, the wafer test pad is located in the second test pad area.
  • the stacked chip test pads in the first test pad area and the wafer test pads in the second test pad area are separated from each other.
  • the number of the stacked chip test pads in the first test pad area is different from the number, shape and/or size of the wafer test pads in the second test pad area.
  • the first test pad area and the second test pad area are arranged adjacently, and the stacked chip test pad in the first test pad area and the wafer in the second test pad area
  • the test pads are connected through a second conductive layer, and the stacked chip test pad and the wafer test pad connected through the second conductive layer are used to receive the same test signal.
  • the stacked chip test pad has an opposite first side and a second side, and the wafer test pad is connected to the first side of the stacked chip test pad through the second conductive layer, and the The first electrical connection structure is located on the second side of the stacked chip test pad.
  • the stacked chip test pad is provided in the semiconductor chip on the top layer or the bottom layer.
  • a second aspect of the present disclosure provides a memory, including the semiconductor structure as described above and a control chip disposed above or below the semiconductor structure.
  • a second electrical connection structure is provided in the control chip.
  • the second electrical connection structure is provided in the control chip.
  • the connection structure is connected to the first electrical connection structure in the adjacent semiconductor chip.
  • Figure 1 is a schematic structural diagram of a single semiconductor chip
  • Figure 2 is a cross-sectional view of a semiconductor memory system according to the present invention.
  • Figure 3 is a perspective view of a semiconductor structure according to an exemplary embodiment
  • Figure 4 is a cross-sectional view of a semiconductor structure according to an exemplary embodiment
  • Figure 5 is a cross-sectional view of a semiconductor structure according to an exemplary embodiment
  • FIG. 6 is a schematic layout diagram of stacked chip test pads and through-electrodes in a semiconductor structure according to an exemplary embodiment
  • FIG. 7 is a top view of a first semiconductor chip in a semiconductor structure according to an exemplary embodiment
  • FIG. 8 is a top view of a first semiconductor chip in a semiconductor structure according to an exemplary embodiment
  • Figure 9 is a cross-sectional view of a semiconductor structure according to an exemplary embodiment
  • FIG. 10 is a schematic layout diagram of stacked chip test pads and wafer test pads according to an exemplary embodiment
  • FIG. 11 is a schematic layout diagram of stacked chip test pads and wafer test pads according to an exemplary embodiment.
  • First semiconductor chip 1211. First surface; 1211a, first surface part; 1211b, second surface part; 1211c, connection surface part; 1212. Second surface; 122. Second semiconductor chip; 1221. Circuit to be tested ;
  • the first test pad area 162. The second test pad area;
  • Substrate 20. Semiconductor device layer; 30. Protective layer; 31. First through hole; 41. First conductive layer; 42. Second conductive layer.
  • the single semiconductor chip is divided into a MAT (memory arraytile) area and a Peripheral area.
  • the test pads used for testing are all set in the Peripheral area.
  • the test pads are, for example, wafer test Pad (CP test PAD), the wafer test pad is also used as a pad for wire bonding in the packaging process.
  • the semiconductor memory system in which the stacked chip is located includes a stacked chip 100 , a controller 200 , an interposer 300 and a substrate 400 .
  • the interposer 300 is formed on the substrate 400 .
  • the stacked chip 100 and the controller 200 are formed on the interposer.
  • the controller 300 illustratively, the stacked chip 100 and the controller 200 do not overlap each other in the vertical direction (ie, the direction perpendicular to the substrate).
  • the stacked chip 100 has a port physical layer (Physical, PHY) 111.
  • the port physical layer 111 can be connected to the port physical layer 111 of the controller 200 through the interposer 300, thereby realizing communication between the stacked chip 100 and the controller 200.
  • the stacked chip 100 also has a data access layer (Direct Access, DA) 112, which can be used to receive data such as test data.
  • DA Data access layer
  • the stacked chip 100 may be, for example, a High Bandwidth Memory (HBM).
  • the high bandwidth memory may include multi-layer semiconductor chips 120 arranged in a stack.
  • the semiconductor chips 120 are electrically connected through electrical connection structures such as through silicon vias 130.
  • a control chip 110 also called a buffer layer chip, is provided below the multi-layer semiconductor chip 120 .
  • the port physical layer 111 and the data access layer 112 are provided on the control chip 110 .
  • the number of semiconductor chips 120 is not limited, for example, it can be three as shown in FIG. 2 , and can be set according to requirements.
  • the above-mentioned stacked chip 100 needs to be tested through the MBIST (Memory Built In Self Test) of the control chip 110 or through the data access layer 112, but the independent multi-layer semiconductor chip 120 cannot be tested, so resulting in testing limitations.
  • MBIST Memory Built In Self Test
  • embodiments of the present disclosure provide a semiconductor structure in which adjacent semiconductor chips in a stacked chip assembly are connected through a first electrical connection structure, and a stacked chip test pad is provided on at least one semiconductor chip.
  • the stacked chip test The pad is connected to the circuit to be tested in the semiconductor chip where it is located, so that the test signal is transmitted to the circuit to be tested in the semiconductor chip where it is located through the stacked chip test pad, so as to test the semiconductor chip where it is located.
  • the stacked chip test pad also It is connected to the first electrical connection structure in the semiconductor chip where it is located.
  • the test signal received by the stacked chip test pad can also be transmitted to other semiconductor chips through the first electrical connection structure to implement testing of other semiconductor chips, so , the semiconductor structure provided by the embodiment of the present disclosure can realize the testing of the stacked chip components without being connected to the control chip by setting the stacked chip test pad, thereby improving the testing flexibility and applicability of the semiconductor structure.
  • FIG. 3 shows a schematic structural diagram of the semiconductor structure provided according to an exemplary embodiment of the present disclosure.
  • the semiconductor structure includes a stacked chip assembly.
  • the stacked chip assembly includes a plurality of semiconductor chips 120 arranged in a stack.
  • Each semiconductor chip 120 is provided with a first electrical connection structure, as shown in Figures 3 and 4.
  • Adjacent semiconductor chips 120 are connected through a first electrical connection structure.
  • the first electrical connection structure may be, for example, the through electrode 140.
  • the first electrical connection structure is a through silicon via (TSV).
  • Each semiconductor chip 120 may include one or more channels, and each channel may include a memory cell array.
  • the controller 200 can transmit data to and read data from each channel through the control chip 110 .
  • This channel can be configured with an independent memory interface.
  • the semiconductor structure includes three semiconductor chips 120, and each semiconductor chip 120 includes two channels. Therefore, the semiconductor structure includes first to sixth channels CH0 to CH5.
  • a plurality of first electrical connection structures passing through the plurality of semiconductor chips 120 may be configured to be applied to the first to sixth channels CH0 to CH5 respectively.
  • a stacked chip test pad 151 is provided on at least one semiconductor chip 120 .
  • the stacked chip test pad 151 is used to receive test signals to test the stacked chip assembly.
  • the stacked chip test pad 151 is connected to the first electrical connection structure in the semiconductor chip 120 where it is located, and is connected to the circuit to be tested in the semiconductor chip 120 where it is located, so as to transmit the test signals received by the stacked chip test pad 151 to each semiconductor chip. 120, thereby realizing testing of each semiconductor chip 120.
  • a stacked chip test pad 151 is provided on at least one semiconductor chip 120.
  • the stacked chip test pad 151 is connected to the circuit to be tested in the semiconductor chip 120 where it is located, so that through the stacked chip test pad 151 transmits the test signal to the circuit to be tested in the semiconductor chip 120 where it is located to implement testing of the semiconductor chip 120 where it is located.
  • the stacked chip test pad 151 is also connected to the first electrical connection structure in the semiconductor chip 120 where it is located. In this way, the test signals received by the stacked chip test pad 151 can also be transmitted to other semiconductor chips 120 through the first electrical connection structure to implement testing of other semiconductor chips 120. In this way, the semiconductor structure provided by the embodiment of the present disclosure is configured
  • the stacked chip test pad 151 can test the stacked chip components without being connected to the control chip 110, thereby improving the testing flexibility and applicability of the semiconductor structure.
  • the semiconductor chip 120 provided with the stacked chip test pad 151 is referred to as the first semiconductor chip 121 below, and the semiconductor chip 120 without the stacked chip test pad 151 is referred to as the second semiconductor chip 122 .
  • the first semiconductor chip 121 may be one or multiple, and the first semiconductor chip 121 may be disposed at any position in the stacked chip assembly.
  • the first semiconductor chip 121 It is located on the top or bottom layer of the stacked chip assembly, thereby exposing the stacked chip test pad 151 to facilitate the contact between the stacked chip test pad 151 and the test pin during testing.
  • the first semiconductor chip 121 is located on the top layer of the stacked chip assembly, and the stacked chip test pad 151 is located on top of the edge area of the first semiconductor chip 121 so that the surface of the stacked chip test pad 151 is exposed. Externally, it is convenient for the test pins to contact the exposed surface of the stacked chip test pad 151 for testing.
  • the stacked chip test pad 151 is connected to the through electrode 140 through the first conductive layer 41.
  • the first conductive layer 41 can be arranged in the same layer as a certain conductive layer in the channel, thereby facilitating wiring and production and improve production efficiency.
  • the first semiconductor chip 121 includes a substrate 10 , a semiconductor device layer 20 disposed on the substrate 10 , and a protective layer 30 covering the semiconductor device layer 20 .
  • the semiconductor device layer 20 may be one layer. It can also be multi-layered. One end of the through electrode 140 penetrates the substrate 10 , and the other end penetrates the protective layer 30 .
  • the first conductive layer 41 and one of the semiconductor device layers 20 are arranged in the same layer, so that the first conductive layer 41 is completed while the semiconductor device layer 20 is being produced, thereby improving production efficiency.
  • the first conductive layer 41 and the semiconductor device layer 20 closest to the protective layer 30 are arranged in the same layer to facilitate contact connection between the stacked chip test pad 151 and the first conductive layer 41 .
  • a first through hole 31 is provided in a partial area of the protective layer 30 corresponding to the first conductive layer 41 .
  • the first through hole 31 exposes a part of the surface of the first conductive layer 41 .
  • 31 is filled with conductive material, thereby forming a stacked chip test pad 151 .
  • the stacked chip test pad 151 can also be disposed at the bottom of the substrate 10 , and its surface can be exposed so as to be in contact with the test pins.
  • a stacked chip test pad 151 is provided with a through electrode 140 correspondingly, that is, a stacked chip test pad 151 is connected to a through electrode 140 in the first semiconductor chip 121, and the test signal is transmitted to the through electrode 140 through the through electrode 140. in the second semiconductor chip 122 .
  • a stacked chip test pad 151 is provided with a through electrode 140 correspondingly, that is, a stacked chip test pad 151 is connected to a through electrode 140 in the first semiconductor chip 121, and the test signal is transmitted to the through electrode 140 through the through electrode 140. in the second semiconductor chip 122 .
  • a first through electrode 141 is provided in the first semiconductor chip 121 , the stacked chip test pad 151 is connected to the first through electrode 141 through the first conductive layer 41 , and in each second semiconductor chip 122 are provided with a second through electrode 142, the second through electrode 142 is connected to the circuit to be tested 1221 in the second semiconductor chip 122, and the position of the second through electrode 142 on each second semiconductor chip 122 is consistent with the first through electrode.
  • the positions of the electrodes 141 are corresponding, and the first through electrode 141 and the adjacent second through electrode 142 and the two adjacent second through electrodes 142 are connected through a bonding structure.
  • test signals received by the stacked chip test pads 151 in the first semiconductor chip 121 can be transmitted to the test signals in each second semiconductor chip 122 through the signal transmission lines formed by the first through electrodes 141 and the respective second through electrodes 142 .
  • the test circuit 1221 is used to test each second semiconductor chip 122.
  • the structure and process are simple, the production efficiency is improved, and the test of each semiconductor chip 120 can be realized with fewer through electrodes 140, which improves the overall stability of the stacked chip assembly. Structural reliability.
  • one stacked chip test pad 151 is provided with multiple through electrodes 140 correspondingly, that is, one stacked chip test pad 151 is connected to multiple through electrodes 140 in the first semiconductor chip 121 , and different through electrodes 140 are used for The test signal is transmitted to a different second semiconductor chip 122 .
  • a third through electrode 143 and a fourth through electrode 144 are provided in the first semiconductor chip 121 , and both the third through electrode 143 and the fourth through electrode 144 are connected to the first conductive layer 41 , so that the stacked chip test pad 151 is connected to both the third through electrode 143 and the fourth through electrode 144 through the first conductive layer 41 .
  • the second semiconductor chip 122 adjacent to the first semiconductor chip 121 is provided with a fifth through electrode 145 corresponding to the position of the third through electrode 143 and a sixth through electrode 146 corresponding to the position of the fourth through electrode 144.
  • the fifth through electrode 145 is connected to the circuit to be tested 1221 in the second semiconductor chip 122 where it is located, and the sixth through electrode 146 is separated from the circuit to be tested 1221 .
  • Another second semiconductor chip 122 is provided with a seventh through electrode 147 corresponding to the position of the sixth through electrode 146.
  • the seventh through electrode 147 is connected to the circuit to be tested 1221 in the second semiconductor chip 122 where it is located.
  • the third through electrode 143 and the fifth through electrode 145, the fourth through electrode 144 and the sixth through electrode 146, and the sixth through electrode 146 and the seventh through electrode 147 are all connected through bonding structures. In this way, the third through electrode 143 and the fifth through electrode 145 form a first signal transmission line, and the fourth through electrode 144, the sixth through electrode 146 and the seventh through electrode 147 form a second signal transmission line.
  • the test signal received by the stacked chip test pad 151 can be transmitted through the first signal transmission line to the circuit to be tested 1221 in the second semiconductor chip 122 adjacent to the first semiconductor chip 121, and transmitted through the second signal transmission line. to the circuit to be tested 1221 in another second semiconductor chip 122, so that the test signals are isolated from each other and avoid crosstalk between the test signals.
  • the stacked chip test pad 151 is in a square shape.
  • the stacked chip test pad 151 is in a square shape of 50umx50um.
  • a plurality of through electrodes 140 are disposed on one side of the stacked chip test pad 151 and are arranged at intervals along the side. Such an arrangement can make the arrangement of the stacked chip test pad 151 and the through electrodes 140 more compact and facilitate stacking of chips.
  • the connection of pad 151 to each through-electrode 140 is tested. For example, as shown in FIG.
  • each stacked chip test pad 151 is provided with four through-electrodes 140 , the four through-electrodes 140 are provided on the right side of the stacked chip test pad 151 , and the four through-electrodes 140 are arranged along the stacked chip.
  • the right side of the test pad 151 is arranged at intervals.
  • the center connection line of the four through-electrodes 140 is parallel to the right side of the stacked chip test pad 151 .
  • One stacked chip test pad 151 may be provided in each first semiconductor chip 121 , or multiple stacked chip test pads 151 may be provided to receive different test signals, that is, each stacked chip test pad 151 is used to receive a Different test signals, for example, test signals include command signals, address signals, data signals, power signals, etc.
  • test signals include command signals, address signals, data signals, power signals, etc.
  • four through electrodes 140 are arranged at intervals on the right side of each stacked chip test pad 151.
  • the multiple stacked chip test pads The arrangement direction of 151 is consistent with the arrangement direction of the four through-electrodes 140. In this way, it can not only ensure the reception of multiple different test signals to meet different test requirements, but also make the structure more compact.
  • the stacked chip test pad 151 can be disposed at any position on the semiconductor chip 120.
  • the first semiconductor chip 121 is provided with a plurality of spaced-apart channels, with spacing areas between the channels.
  • the stacked chip test pad 151 is disposed in the spacing area.
  • the through electrode 140 is also disposed in the spacing area.
  • four channels are provided on the first semiconductor chip 121, namely channel CHO, channel CH1, channel CH2 and channel CH3. The four channels are respectively located in the four corner areas of the first semiconductor chip 121.
  • a cross-shaped spacing area is formed in the first semiconductor chip 121 , and the stacked chip test pads 151 are disposed in the cross-shaped spacing area.
  • some of the stacked chip test pads 151 are arranged at intervals along a strip of the cross-shaped area.
  • another part of the stacked chip test pads 151 is arranged at intervals along another strip-shaped area in the cross.
  • the stacked chip test pads 151 are disposed in the edge area of the semiconductor chip 120.
  • a plurality of stacked chip test pads 151 are arranged at intervals along one side of the first semiconductor chip 121.
  • the stacked chip test pads 151 may be arranged in one row on one side of the first semiconductor chip 121, or may be arranged in multiple rows. Disposing the stacked chip test pad 151 at the edge area of the semiconductor chip 120 can facilitate contact with the test pins to test the stacked chip assembly.
  • the edge of the semiconductor chip 120 is provided with a step structure, and the stacked chip test pad 151 is provided on the step surface of the step structure.
  • the first semiconductor chip 121 includes an opposite The first surface 1211 and the second surface 1212, the second surface 1212 is a plane, the first surface 1211 includes a first surface part 1211a and a second surface part 1211b, the second surface part 1211b is closer to the first surface part 1211a The second surface 1212 is provided.
  • the first surface part 1211a and the second surface part 1211b are connected through a connecting surface part 1211c perpendicular to the second surface 1212.
  • the area where the second surface part 1211b and the connecting surface part 1211c is located forms a step structure.
  • the second surface part 1211b constitutes a step surface, and the stacked chip test pad 151 is located on the second surface portion 1211b.
  • the first semiconductor chip 121 includes a substrate 10 , a semiconductor device layer 20 disposed on the substrate 10 , and a protective layer 30 covering the semiconductor device layer 20 .
  • the semiconductor device layer 20 may be one layer. It can also be multi-layered.
  • One end of the through electrode 140 penetrates the substrate 10 , and the other end penetrates the protective layer 30 .
  • the protective layer 30 covers the semiconductor device layer 20 and the exposed part of the surface of the substrate 10 . As shown in FIG. 9 , the upper surface of one side edge region of the substrate 10 is exposed.
  • the bottom surface of the substrate 10 constitutes the second surface 1212
  • the surface of the protective layer 30 constitutes the first surface part 1211a
  • the side surface of the protective layer 30 constitutes the connecting surface part 1211c
  • the exposed upper surface of the substrate 10 constitutes the second surface part 1211b.
  • the stacked chip test pad 151 is disposed on the exposed upper surface of the substrate 10 .
  • the stacked chip test pad 151 is, for example, disposed on the same layer as one of the semiconductor device layers 20 , so that the stacked chip test pad is completed while the semiconductor device layer 20 is being produced. 151 production to improve production efficiency.
  • the stacked chip test pad 151 is arranged on the same layer as the semiconductor device layer 20 closest to the substrate 10 .
  • the wafer testing process includes wafer aging test (Wafer level bum-in, referred to as WLBI), wafer low temperature test (Low Temp, referred to as LT), and wafer high temperature test (High Temp, referred to as HT).
  • WLBI wafer level bum-in
  • LT wafer low temperature test
  • High Temp wafer high temperature test
  • the stacked chip components must be subjected to burn-in testing (Bum-in Testing, referred to as BI), low-temperature test and high-temperature test respectively.
  • test processes such as wafer aging test, wafer low temperature test and wafer high temperature test have been omitted. It is only necessary to test the stacked chip components after the stacked chip components are formed, thereby simplifying the test process and improving the efficiency. Test efficiency.
  • each semiconductor chip 120 is provided with a wafer test pad 152 , and the wafer test pad 152 is connected to the circuit to be tested in its semiconductor chip 120 .
  • each semiconductor chip 120 can perform wafer testing at the wafer stage through the wafer test signal received by the wafer test pad 152 . That is, during wafer testing, the wafer test pad 152 is used to contact the test pins to test the wafer where the semiconductor chip 120 is located. After the stacking of the semiconductor chip 120 is completed, the stacked chip test pad 151 is used to test the stack. Chip components are tested. Under normal circumstances, during wafer testing, 3 to 4 tests are usually performed, which will form 3 to 4 needle marks on the test pad. Excessive needle marks or the number of needle insertions can easily cause damage to the test pad.
  • This implementation In this example, different test pads are used for wafer testing and stacked chip testing, thereby effectively avoiding damage to the test pads and ensuring smooth testing.
  • the semiconductor chip 120 provided with the stacked chip test pad 151 includes a first test pad area 161 and a second test pad area 162 , the stacked chip test pad 151 is connected to the stacked chip test pad 151
  • the first electrical connection structures such as the through electrodes 140 are located in the first test pad area 161
  • the wafer test pads 152 are located in the second test pad area 162 .
  • the stacked chip test pads 151 and the wafer test pads 152 are arranged in different areas to facilitate the layout design of the first semiconductor chip 121 .
  • the stacked chip test pads 151 in the first test pad area 161 and the wafer test pads 152 in the second test pad area 162 are separated from each other, that is, between the stacked chip test pads 151 and the wafer test pads 152 There is no mutual connection relationship. At this time, the wafer test pad 152 and the stacked chip test pad 151 can be used independently. Since there is no connection relationship between the two, there are no restrictions on the setting position, quantity, size, etc. of the two, which makes the position, quantity, and size design of the stacked chip test pads 151 and wafer test pads 152 more flexible to obtain A more optimized arrangement.
  • the number of stacked chip test pads 151 within the first test pad area 161 is different from the number, shape, and/or size of the wafer test pads 152 within the second test pad area 162 .
  • the semiconductor chip 120 is provided with four channels, namely channel CH0, channel CH1, channel CH2 and channel CH3.
  • the four channels are respectively located in the four corner areas of the semiconductor chip, thereby forming a cross-shaped spacing area in the semiconductor chip 120.
  • the stacked chip test pads 151 are arranged at intervals along one strip area in the cross shape, and the wafer test pads 152 are arranged at intervals along the other strip area in the cross shape.
  • the stacked chip test pad 151 and the wafer test pad 152 are connected together.
  • the stacked chip test pad 151 can be connected to the circuit to be tested in the semiconductor chip 120 through the wafer test pad 152, or the wafer test pad 152 can be connected to the circuit under test in the semiconductor chip 120.
  • the test pad 152 is connected to the circuit to be tested in the semiconductor chip 120 through the stacked chip test pad 151, thereby making layout design more convenient, simplifying the circuit structure, and effectively reducing costs.
  • the shapes and sizes of the stacked chip test pads 151 and the wafer test pads 152 can be set to be consistent, for example, both are set to be a square of 50umx50um. In this way, during layout design, each stacked chip test pad 151 and the wafer test pads 152 can be formed in an array manner.
  • the circular test pad 152 is used to improve layout design efficiency.
  • the first test pad area 161 and the second test pad area 162 are arranged adjacently, and the stacked chip test pads 151 in the first test pad area 161 are adjacent to the chip test pads 151 in the second test pad area 162 .
  • the circular test pad 152 is connected through the second conductive layer 42, and the stacked chip test pad 151 and the wafer test pad 152 connected through the second conductive layer 42 are used to receive the same test signal, that is, the connected stacked chip test pad 151 and the wafer test pad 152 are connected to each other through the second conductive layer 42.
  • the pins of the circular test pad 152 have the same definition, for example, they can all be command signals (CMD), address signals (ADDRESS), data signals (DQ), and power signals (POWER).
  • the stacked chip test pad 151 and the wafer test pad 152 can be arranged on the same layer, and the second conductive layer 42 and the first conductive layer 41 can be arranged on the same layer, thereby improving production efficiency.
  • spaced first through holes 31 and second through holes are formed by etching on the protective layer 30 at positions corresponding to the second conductive layer 42 , wherein the first through hole 31 fills the stacked chip test pad 151 , and the second through hole 31 fills the stacked chip test pad 151 .
  • the hole fills the wafer test pad 152 .
  • the stacked chip test pad 151 has an opposite first side and a second side, and the wafer test pad 152 is connected to the first side of the stacked chip test pad 151 through the second conductive layer 42 The edges are connected, and the first electrical connection structure such as the through electrode 140 is located on the second side of the stacked chip test pad 151 .
  • Such arrangement not only facilitates the second conductive layer 42 to connect the wafer test pad 152 and the stacked chip test pad 151, but also makes the structure more compact.
  • An exemplary embodiment of the present disclosure also provides a memory, including a semiconductor structure as described above and a control chip 110 disposed above or below the semiconductor structure.
  • the control chip 110 can be provided with structures such as a port physical layer and a data access layer, so that The controller 200 can transmit data to and read data from each semiconductor chip 120 in the stacked chip assembly through the control chip 110 .
  • the control chip 110 is provided with a second electrical connection structure, and the second electrical connection structure is connected to the first electrical connection structure in the adjacent semiconductor chip 120 .
  • the second electrical connection structure may be, for example, a through electrode.
  • the second electrical connection structure is a through silicon via (TSV).
  • the memory provided in this embodiment may be, for example, a three-dimensional stacked chip such as WoW (Wafer-on-Wafer), CoW (Chip-on-Wafer), and CoC (Chip-on-Chip).
  • WoW WoW
  • CoW Chip-on-Wafer
  • CoC Chip-on-Chip
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions
  • the device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.
  • adjacent semiconductor chips in the stacked chip assembly are connected through a first electrical connection structure, and a stacked chip test pad is provided on at least one semiconductor chip.
  • the stacked chip test pad It is connected to the circuit to be tested in the semiconductor chip where it is located, so that the test signal is transmitted to the circuit to be tested in the semiconductor chip where it is located through the stacked chip test pad, so as to test the semiconductor chip where it is located.
  • the stacked chip test pad is also connected to the circuit to be tested.
  • the first electrical connection structure in the semiconductor chip where it is located is connected. In this way, the test signal received by the stacked chip test pad can also be transmitted to other semiconductor chips through the first electrical connection structure to implement testing of other semiconductor chips. In this way,
  • the semiconductor structure provided by the embodiment of the present disclosure can realize testing of stacked chip components without being connected to a control chip by setting stacked chip test pads, thereby improving the testing flexibility and applicability of the semiconductor structure.

Abstract

本公开提供一种半导体结构及存储器，涉及半导体技术领域，半导体结构包括堆叠芯片组件，堆叠芯片组件包括堆叠设置的多个半导体芯片，各半导体芯片中均设置有第一电连接结构，相邻半导体芯片之间通过第一电连接结构连接；至少一个半导体芯片上设置有堆叠芯片测试垫，堆叠芯片测试垫与其所在的半导体芯片中的第一电连接结构以及待测试电路均相连，以将堆叠芯片测试垫接收的测试信号传输至各半导体芯片。

Description

半导体结构及存储器
本公开基于申请号为202210245948.8、申请日为2022年03月14日、申请名称为“半导体结构及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及存储器。
背景技术
为了满足集成电路的微型化和效率提升要求，封装技术不断提高，采用堆叠封装技术形成的三维堆叠芯片能够有效地利用芯片面积，提高存储容量。
在上述三维堆叠芯片的开发、生产等过程中，需要对其进行各项测试，以测试芯片的各项性能。然而，上述三维堆叠芯片在测试过程中存在着局限性，难以满足不同的测试要求。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构及存储器。
根据本公开实施例的第一方面，提供一种半导体结构，包括堆叠芯片组件，所述堆叠芯片组件包括堆叠设置的多个半导体芯片，各所述半导体芯片中均设置有第一电连接结构，相邻所述半导体芯片之间通过所述第一电连接结构连接；
至少一个所述半导体芯片上设置有堆叠芯片测试垫，所述堆叠芯片测试垫与其所在的半导体芯片中的第一电连接结构以及待测试电路均相连，以将所述堆叠芯片测试垫接收的测试信号传输至各所述半导体芯片。
其中，所述第一电连接结构包括穿通电极，所述堆叠芯片测试垫通过第一导电层与所述穿通电极连接。
其中，每个所述堆叠芯片测试垫对应设置多个所述穿通电极，所述堆叠芯片测试垫呈方形，多个所述穿通电极设置于所述堆叠芯片测试垫的一侧边并沿该侧边间隔排布。
其中，同一所述半导体芯片上设置有多个所述堆叠芯片测试垫，不同的堆叠芯片测试垫用于接收不同的测试信号。
其中，所述测试信号包括命令信号、地址信号、数据信号和/或电源信号。
其中，所述堆叠芯片测试垫设置于所述半导体芯片的边缘区域；或者，
所述半导体芯片上设置有多个间隔排布的通道，所述通道之间具有间隔区域，所述堆叠芯片测试垫设置于所述间隔区域。
其中，所述堆叠芯片测试垫设置于所述半导体芯片的边缘区域的顶部。
其中，各所述半导体芯片上均设置有晶圆测试垫，所述晶圆测试垫与其所在的半导体芯片中的待测试电路相连。
其中，设置有所述堆叠芯片测试垫的所述半导体芯片包括第一测试垫区域和第二测试垫区域，所述堆叠芯片测试垫以及与所述堆叠芯片测试垫相连的第一电连接结构均位于所述第一测试垫区域，所述晶圆测试垫位于所述第二测试垫区域。
其中，所述第一测试垫区域内的所述堆叠芯片测试垫与所述第二测试垫区域内的所述晶圆测试垫相互分离。
其中，所述第一测试垫区域内的所述堆叠芯片测试垫的数量与所述第二测试垫区域内的所述晶圆测试垫的数量、形状和/或尺寸不同。
其中，所述第一测试垫区域和所述第二测试垫区域相邻设置，所述第一测试垫区域内的所述堆叠芯片测试垫与所述第二测试垫区域内的所述晶圆测试垫通过第二导电层连接，通过所述第二导电层相连的所述堆叠芯片测试垫和所述晶圆测试垫用于接收相同的测试信号。
其中，所述堆叠芯片测试垫具有相对的第一侧边和第二侧边，所述晶圆测试垫通过所述第二导电层与所述堆叠芯片测试垫的第一侧边相连，所述第一电连接结构位于所述堆叠芯片测试垫的第二侧边。
其中，所述堆叠芯片测试垫设置在顶层或底层的所述半导体芯片中。
本公开的第二方面提供一种存储器，包括如上所述的半导体结构以及设置于所述半导体结构上方或下方的控制芯片，所述控制芯片中设置有第二电连接结构，所述第二电连接结构和相邻所述半导体芯片中的第一电连接结构连接。
阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是单片半导体芯片的结构示意图；
图2根据本发明的半导体存储系统的截面图；
图3是根据一示例性实施例示出的一种半导体结构的立体图；
图4是根据一示例性实施例示出的一种半导体结构的剖视图；
图5是根据一示例性实施例示出的一种半导体结构的剖视图；
图6是根据一示例性实施例示出的半导体结构中堆叠芯片测试垫与穿通电极的布局示意图；
图7是根据一示例性实施例示出的半导体结构中第一半导体芯片的俯视图；
图8是根据一示例性实施例示出的半导体结构中第一半导体芯片的俯视图；
图9是根据一示例性实施例示出的一种半导体结构的剖视图；
图10是根据一示例性实施例示出的堆叠芯片测试垫和晶圆测试垫的布局示意图；
图11是根据一示例性实施例示出的堆叠芯片测试垫和晶圆测试垫的布局示意图。
附图标记：
100、堆叠芯片；110、控制芯片；111、端口物理层；112、数据访问层；120、半导体芯片；130、硅通孔；200、控制器；300、插入器；400、基底；
121、第一半导体芯片；1211、第一表面；1211a、第一表面部；1211b、第二表面部；1211c、连接面部；1212、第二表面；122、第二半导体芯片；1221、待测试电路；
140、穿通电极；141、第一穿通电极；142、第二穿通电极；143、第三穿通电极；144、第四穿通电极；145、第五穿通电极；146、第六穿通电极；147、第七穿通电极；
151、堆叠芯片测试垫；152、晶圆测试垫；
161、第一测试垫区域；162、第二测试垫区域；
10、衬底；20、半导体器件层；30、保护层；31、第一通孔；41、第一导电层；42、第二导电层。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于 本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
半导体结构例如半导体芯片在开发和生产过程中需要进行测试，以测试芯片的各项性能。对于单片半导体芯片而言，如图1所示，将单片半导体芯片划分为MAT(memory arraytile)区和Peripheral区，用于测试的测试垫均设置在Peripheral区，测试垫例如为晶圆测试垫(CP test PAD)，该晶圆测试垫也作为封装工艺中引线键合(wire bond)的焊盘。
而对于堆叠芯片进行测试时，需要将由堆叠设置的多个半导体芯片形成的堆叠芯片组件与控制芯片堆叠在一起之后才能进行测试。例如，如图2所示，堆叠芯片所在的半导体存储系统包括堆叠芯片100、控制器200、插入器300和基底400，插入器300形成于基底400上，堆叠芯片100和控制器200形成于插入器300上方，示例性地，堆叠芯片100和控制器200在竖直方向(即垂直于衬底的方向)上彼此不重叠。
堆叠芯片100具有端口物理层(Physical，PHY)111，端口物理层111可通过插入器300与控制器200的端口物理层111连接，从而实现堆叠芯片100与控制器200之间的通信。堆叠芯片100还具有数据访问层(Direct Access，DA)112，数据访问层112可以用于接收数据例如测试数据。
堆叠芯片100例如可以为高带宽存储器(High Bandwidth Memory，HBM)，高带宽存储器可以包括层叠设置的多层半导体芯片120，半导体芯片120之间通过电连接结构例如硅通孔130实现电连接。继续参考图2，多层半导体芯片120的下方设置有控制芯片110，也称为缓冲层芯片，端口物理层111和数据访问层112设置于控制芯片110上。半导体芯片120的数量不作限制，例如可以为图2所示的三片，具体可根据需求进行设置。
上述堆叠芯片100中，需要通过控制芯片110的MBIST(Memory Built In Self Test，存储器内置自测)，或者通过数据访问层112来进行测试，而单独的多层半导体芯片120则无法进行测试，从而导致测试的局限性。
基于此，本公开实施例提供一种半导体结构，其堆叠芯片组件中的相邻半导体芯片之间通过第一电连接结构连接，且在至少一个半导体芯片上设置有堆叠芯片测试垫，堆叠芯片测试垫与其所在的半导体芯片中的待测试电路相连，从而通过堆叠芯片测试垫将测试信号传输至其所在半导体芯片中的待测试电路，以实现对其所在的半导体芯片的测试，堆叠芯片测试垫还与其所在的半导体芯片中的第一电连接结构连接，如此，堆叠芯片测试垫接收的测试信号还可通过第一电连接结构传输至其他的半导体芯片中，以实现对其他半导体芯片的测试，如此，本公开实施例提供的半导体结构通过设置堆叠芯片测试垫，无需与控制芯片连接即可实现对堆叠芯片组件的测试，提高该半导体结构的测试灵活性和适用性。
本公开示例性的实施例中提供一种半导体结构，图3示出了根据本公开一示例性的实施例提供的半导体结构的结构示意图。如图3所示，半导体结构包括堆叠芯片组件，该堆叠芯片组件包括堆叠设置的多个半导体芯片120，各半导体芯片120中均设置有第一电连接结构，如图3和图4所示，相邻的半导体芯片120之间通过第一电连接结构连接。第一电连接结构例如可以是穿通电极140，示例性地，第一电连接结构为硅通孔(Through Silicon Via，TSV)。
每个半导体芯片120可以包括一个或者多个通道，每个通道均可以包括存储器单元阵列，控制器200能够通过控制芯片110向各个通道传输数据以及从各个通道中读取数据。该通道可以配置独立的内存接口。示例性地，如图3所示，半导体结构包括三个半导体芯片120，每个半导体芯片120包括两个通道，因此，半导体结构包括第 一通道CH0至第六通道CH5。穿过多个半导体芯片120的多个第一电连接结构可以被设置为分别应用于第一通道CH0至第六通道CH5。
其中，如图4所示，在至少一个半导体芯片120上设置有堆叠芯片测试垫151，该堆叠芯片测试垫151用于接收测试信号以对堆叠芯片组件进行测试。堆叠芯片测试垫151与其所在的半导体芯片120中的第一电连接结构连接，并与其所在的半导体芯片120中的待测试电路连接，以将堆叠芯片测试垫151接收的测试信号传输至各半导体芯片120中，从而实现对各半导体芯片120的测试。
本公开实施例所提供的半导体结构中，在至少一个半导体芯片120上设置有堆叠芯片测试垫151，堆叠芯片测试垫151与其所在的半导体芯片120中的待测试电路相连，从而通过堆叠芯片测试垫151将测试信号传输至其所在半导体芯片120中的待测试电路，以实现对其所在的半导体芯片120的测试，堆叠芯片测试垫151还与其所在的半导体芯片120中的第一电连接结构连接，如此，堆叠芯片测试垫151接收的测试信号还可通过第一电连接结构传输至其他的半导体芯片120中，以实现对其他半导体芯片120的测试，如此，本公开实施例提供的半导体结构通过设置堆叠芯片测试垫151，无需与控制芯片110连接即可实现对堆叠芯片组件的测试，提高该半导体结构的测试灵活性和适用性。
为了方便描述，以下将设置有堆叠芯片测试垫151的半导体芯片120称为第一半导体芯片121，将未设置堆叠芯片测试垫151的半导体芯片120称为第二半导体芯片122。可以理解的，堆叠芯片组件中，第一半导体芯片121可以为一个，也可以为多个，且第一半导体芯片121可以设置在堆叠芯片组件中的任意位置，示例性地，第一半导体芯片121位于堆叠芯片组件的顶层或者底层，从而便于暴露出堆叠芯片测试垫151，以便于进行测试时堆叠芯片测试垫151与测试触脚的接触。
在一个实施例中，如图4所示，第一半导体芯片121位于堆叠芯片组件的顶层，堆叠芯片测试垫151位于第一半导体芯片121的边缘区域的顶部，使得堆叠芯片测试垫151的表面暴露于外部，从而方便测试触脚与堆叠芯片测试垫151的暴露表面接触以进行测试。
在第一半导体芯片121中，堆叠芯片测试垫151通过第一导电层41与穿通电极140连接，如此，第一导电层41可以与通道中的某一层导电层同层设置，从而方便布线和生产，提高生产效率。
示例性地，如图4所示，第一半导体芯片121包括衬底10、设置于衬底10上的半导体器件层20以及覆盖半导体器件层20的保护层30，半导体器件层20可以为一层也可以为多层。穿通电极140的一端贯穿衬底10，另一端贯穿保护层30。第一导电层41与其中的一层半导体器件层20为同层设置，从而在制作半导体器件层20的同时完成第一导电层41的制作，以提高生产效率。例如，第一导电层41与最靠近保护层30的一层半导体器件层20为同层设置，以便堆叠芯片测试垫151与第一导电层41的接触连接。继续参考图4所示，保护层30上与第一导电层41对应的部分区域设置有第一通孔31，第一通孔31暴露出第一导电层41的部分表面，向第一通孔31内填充导电材料，从而形成堆叠芯片测试垫151。在其他的实施例中，堆叠芯片测试垫151也可以设置在衬底10的底部，能够暴露出其表面以便与测试触脚接触即可。
在一些实施例中，一个堆叠芯片测试垫151对应设置一个穿通电极140，即一个堆叠芯片测试垫151与第一半导体芯片121中的一个穿通电极140连接，通过该穿通电极140将测试信号传输至第二半导体芯片122中。示例性地，如图4所示，在第一半导体芯片121中设置有第一穿通电极141，堆叠芯片测试垫151通过第一导电层41与第一穿通电极141连接，在各个第二半导体芯片122中均设置有第二穿通电极142，第二穿通电极142与第二半导体芯片122中的待测试电路1221连接，各个第二半导 体芯片122上的第二穿通电极142的位置均与第一穿通电极141位置相对应，第一穿通电极141与相邻的第二穿通电极142之间，以及相邻的两个第二穿通电极142之间均通过键合结构连接。如此，第一半导体芯片121中的堆叠芯片测试垫151接收到的测试信号即可通过第一穿通电极141以及各个第二穿通电极142形成的信号传输线路传输至各个第二半导体芯片122中的待测试电路1221，以实现对各个第二半导体芯片122的测试，结构和工艺简单，提高生产效率，且通过较少的穿通电极140即可实现各个半导体芯片120的测试，提高了堆叠芯片组件的整体结构可靠性。
在另一些实施例中，一个堆叠芯片测试垫151对应设置多个穿通电极140，即一个堆叠芯片测试垫151与第一半导体芯片121中的多个穿通电极140连接，不同的穿通电极140用于将测试信号传输至不同的第二半导体芯片122。示例性地，如图5所示，在第一半导体芯片121中设置有第三穿通电极143和第四穿通电极144，第三穿通电极143和第四穿通电极144均与第一导电层41连接，以使得堆叠芯片测试垫151通过第一导电层41与第三穿通电极143、第四穿通电极144均连接。与第一半导体芯片121相邻的第二半导体芯片122中设置有与第三穿通电极143的位置对应的第五穿通电极145、以及与第四穿通电极144位置对应的第六穿通电极146，第五穿通电极145与其所在的第二半导体芯片122内的待测试电路1221连接，第六穿通电极146则与待测试电路1221相分离。另一第二半导体芯片122中设置有与第六穿通电极146位置对应的第七穿通电极147，第七穿通电极147与其所在的第二半导体芯片122内的待测试电路1221连接。第三穿通电极143与第五穿通电极145之间、第四穿通电极144与第六穿通电极146之间、以及第六穿通电极146与第七穿通电极147之间均通过键合结构连接。如此，第三穿通电极143与第五穿通电极145形成第一信号传输线路，第四穿通电极144、第六穿通电极146以及第七穿通电极147形成第二信号传输线路，第一半导体芯片121中的堆叠芯片测试垫151接收到的测试信号即可通过第一信号传输线路传输至与第一半导体芯片121相邻的第二半导体芯片122中的待测试电路1221，并通过第二信号传输线路传输至另一第二半导体芯片122中的待测试电路1221，从而使得各测试信号相互隔离，避免测试信号之间的相互串扰。
本实施例中，参考图6所示，堆叠芯片测试垫151呈方形，示例性地，堆叠芯片测试垫151呈50umx50um的正方形。多个穿通电极140设置于堆叠芯片测试垫151的一侧边并沿该侧边间隔排布，如此排布，能够使得堆叠芯片测试垫151和穿通电极140的排布更加紧凑，且方便堆叠芯片测试垫151与各穿通电极140的连接。示例性地，如图6所示，每个堆叠芯片测试垫151对应设置四个穿通电极140，四个穿通电极140设置于堆叠芯片测试垫151的右侧，且四个穿通电极140沿堆叠芯片测试垫151的右侧边间隔排布，例如，四个穿通电极140的中心连线与堆叠芯片测试垫151的右侧边相平行。
每个第一半导体芯片121中可以设置一个堆叠芯片测试垫151，也可以设置多个堆叠芯片测试垫151，以用于接收不同的测试信号，即每一个堆叠芯片测试垫151均用于接收一个不同的测试信号，示例性地，测试信号包括命令信号、地址信号、数据信号、电源信号等。当一个第一半导体芯片121中设置有多个堆叠芯片测试垫151时，一实施例中，每个堆叠芯片测试垫151的右侧边间隔排布四个穿通电极140，多个堆叠芯片测试垫151的排布方向与四个穿通电极140的排布方向一致，如此，既能够保证多个不同的测试信号的接收以满足不同的测试需求，又能够使得结构更加紧凑。
堆叠芯片测试垫151可以设置在半导体芯片120的任意位置，在一实施例中，如图7所示，第一半导体芯片121上设置有多个间隔排布的通道，通道之间具有间隔区域，堆叠芯片测试垫151设置于该间隔区域内，同时，为了便于与穿通电极140连接，穿通电极140也设置于该间隔区域内。示例性地，如图7所示，第一半导体芯片121 上设置有四个通道，分别为通道CH0、通道CH1、通道CH2和通道CH3，四个通道分别位于第一半导体芯片121的四角区域，从而在第一半导体芯片121内形成十字形的间隔区域，堆叠芯片测试垫151设置于该十字形的间隔区域中，例如，其中一部分堆叠芯片测试垫151沿十字形中的一条形区域间隔排布，另一部分堆叠芯片测试垫151沿十字形中的另一条形区域间隔排布。
另一实施例中，堆叠芯片测试垫151设置于半导体芯片120的边缘区域，例如，如图8所示，多个堆叠芯片测试垫151沿第一半导体芯片121的一侧边间隔排布，多个堆叠芯片测试垫151可以在第一半导体芯片121的一侧边设置一排，也可以设置为多排。将堆叠芯片测试垫151设置在半导体芯片120的边缘区域能够便于与测试触脚接触，以便对堆叠芯片组件进行测试。
示例性地，如图9所示，半导体芯片120的边缘设置有台阶结构，堆叠芯片测试垫151设置于台阶结构的台阶面上，具体地，如图9所示，第一半导体芯片121包括相对的第一表面1211和第二表面1212，第二表面1212为平面，第一表面1211包括第一表面部1211a和第二表面部1211b，第二表面部1211b相较于第一表面部1211a更靠近第二表面1212设置，第一表面部1211a和第二表面部1211b通过垂直于第二表面1212的连接面部1211c连接，第二表面部1211b和连接面部1211c所在区域即构成台阶结构，第二表面部1211b即构成台阶面，堆叠芯片测试垫151位于第二表面部1211b。
示例性地，如图9所示，第一半导体芯片121包括衬底10、设置于衬底10上的半导体器件层20以及覆盖半导体器件层20的保护层30，半导体器件层20可以为一层也可以为多层。穿通电极140的一端贯穿衬底10，另一端贯穿保护层30。保护层30覆盖半导体器件层20以及衬底10暴露出的部分表面，如图9所示，衬底10的一侧边缘区域的上表面露出。如此，衬底10的底面构成第二表面1212，保护层30的表面构成第一表面部1211a，保护层30的侧面构成连接面部1211c，衬底10上露出的上表面构成第二表面部1211b，堆叠芯片测试垫151设置于衬底10的漏出的上表面上，堆叠芯片测试垫151例如与其中一层半导体器件层20为同层设置，从而在制作半导体器件层20的同时完成堆叠芯片测试垫151的制作，以提高生产效率。例如，堆叠芯片测试垫151与最靠近衬底10的一层半导体器件层20为同层设置。
本实施例中，在半导体芯片120上可以是仅设置堆叠芯片测试垫151，如此，可以省去晶圆测试的流程，而是在形成堆叠芯片组件之后，统一进行测试，从而能够减少测试次数，有效提升良率。示例性地，晶圆测试流程包括晶圆老化测试(Wafer level bum-in，简称WLBI)、晶圆低温测试(Low Temp，简称LT)以及晶圆高温测试(High Temp，简称HT)，在形成堆叠芯片组件之后，还要对堆叠芯片组件分别进行预烧测试(Bum-in Testing，简称BI)、低温测试和高温测试。本实施例中，而已省去晶圆老化测试、晶圆低温测试以及晶圆高温测试等测试流程，只需要在堆叠形成堆叠芯片组件后对堆叠芯片组件进行测试，从而简化了测试流程，提高了测试效率。
本公开一示例性实施例中，如图10所示，各半导体芯片120上均设置有晶圆测试垫152，晶圆测试垫152与其的半导体芯片120中的待测试电路相连。如此，各半导体芯片120在晶圆阶段能够通过晶圆测试垫152接收的晶圆测试信号进行晶圆测试。即，在进行晶圆测试时，使用晶圆测试垫152与测试触脚接触，以对半导体芯片120所在的晶圆进行测试，在完成半导体芯片120的堆叠之后，使用堆叠芯片测试垫151对堆叠芯片组件进行测试。通常情况下，在晶圆测试时，通常会进行3至4次测试，进而会在测试垫上形成3至4道针痕，过多的针痕或下针次数容易造成测试垫的损坏，本实施例中，晶圆测试和堆叠芯片测试分别采用不同的测试垫，从而有效避免测试垫的破坏，保证测试的顺利进行。
一实施例中，设置有堆叠芯片测试垫151的半导体芯片120即第一半导体芯片121包括第一测试垫区域161和第二测试垫区域162，堆叠芯片测试垫151以及与堆叠芯片测试垫151相连的第一电连接结构例如穿通电极140均位于第一测试垫区域161，晶圆测试垫152位于第二测试垫区域162。堆叠芯片测试垫151和晶圆测试垫152分区域设置，以便第一半导体芯片121的版图设计。
在一些实施例中，第一测试垫区域161内的堆叠芯片测试垫151与第二测试垫区域162内的晶圆测试垫152相互分离，即堆叠芯片测试垫151与晶圆测试垫152之间没有相互连接关系，此时，晶圆测试垫152和堆叠芯片测试垫151可以单独使用。由于两者没有连接关系，因此两者的设置位置、设置数量、设置尺寸等均不受限制，从而使得堆叠芯片测试垫151和晶圆测试垫152的位置、数量、尺寸设计更加灵活，以获得更加优化的排布方式。示例性地，第一测试垫区域161内的堆叠芯片测试垫151的数量与第二测试垫区域162内的晶圆测试垫152的数量、形状和/或尺寸不同。
作为示例，半导体芯片120上设置有四个通道，分别为通道CH0、通道CH1、通道CH2和通道CH3，四个通道分别位于半导体芯片的四角区域，从而在半导体芯片120内形成十字形的间隔区域，堆叠芯片测试垫151沿十字形中的一条形区域间隔排布，晶圆测试垫152沿十字形中的另一条形区域间隔排布。
在另一些实施例中，堆叠芯片测试垫151与晶圆测试垫152连接在一起，如此，堆叠芯片测试垫151可通过晶圆测试垫152与半导体芯片120内的待测试电路连接，或者晶圆测试垫152通过堆叠芯片测试垫151与半导体芯片120内的待测试电路连接，从而能够更加方便版图设计，且简化了电路结构，能够有效降低成本。堆叠芯片测试垫151与晶圆测试垫152的形状和大小可以设置为一致，例如均设置为呈50umx50um的正方形，如此，在进行版图设计时，可通过阵列方式形成各堆叠芯片测试垫151和晶圆测试垫152，从而提高版图的设计效率。
示例性地，如图11所示，第一测试垫区域161和第二测试垫区域162相邻设置，第一测试垫区域161内的堆叠芯片测试垫151与第二测试垫区域162内的晶圆测试垫152通过第二导电层42连接，通过第二导电层42相连的堆叠芯片测试垫151和晶圆测试垫152用于接收相同的测试信号，即，相连的堆叠芯片测试垫151和晶圆测试垫152的pin脚定义相同，例如可以均为命令信号(CMD)、地址信号(ADDRESS)、数据信号(DQ)、电源信号(POWER)。
本实施例中，堆叠芯片测试垫151与晶圆测试垫152可以设置为同层设置，第二导电层42与第一导电层41设置为同层设置，从而提高了生产效率。示例性地，在保护层30上与第二导电层42对应的位置刻蚀形成间隔的第一通孔31和第二通孔，其中第一通孔31填充堆叠芯片测试垫151，第二通孔填充晶圆测试垫152。
一实施例中，如图11所示，堆叠芯片测试垫151具有相对的第一侧边和第二侧边，晶圆测试垫152通过第二导电层42与堆叠芯片测试垫151的第一侧边相连，第一电连接结构例如穿通电极140位于堆叠芯片测试垫151的第二侧边。如此布置，既便于第二导电层42将晶圆测试垫152和堆叠芯片测试垫151连接，又使得结构布置的更加紧凑。
本公开一示例性实施例还提供一种存储器，包括如上所述的半导体结构以及设置于半导体结构上方或下方的控制芯片110，控制芯片110上可以设置端口物理层、数据访问层等结构，使得控制器200能够通过控制芯片110向堆叠芯片组件中的各个半导体芯片120传输数据以及从各个半导体芯片120中读取数据。
控制芯片110中设置有第二电连接结构，第二电连接结构和相邻半导体芯片120中的第一电连接结构连接。第二电连接结构例如可以是穿通电极，示例性地，第二电连接结构为硅通孔(Through Silicon Via，TSV)。
本实施例提供的存储器例如可以为WoW(Wafer-on-Wafer)，CoW(Chip-on-Wafer)以及CoC(Chip-on-Chip)等三维堆叠芯片。
本公开是参照根据本公开实施例的方法、装置(设备)和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及存储器中，堆叠芯片组件中的相邻半导体芯片之间通过第一电连接结构连接，且在至少一个半导体芯片上设置有堆叠芯片测试垫，堆叠芯片测试垫与其所在的半导体芯片中的待测试电路相连，从而通过堆叠芯片测试垫将测试信号传输至其所在半导体芯片中的待测试电路，以实现对其所在的半导体芯片的测试，堆叠芯片测试垫还与其所在的半导体芯片中的第一电连接结构连接，如此，堆叠芯片测试垫接收的测试信号还可通过第一电连接结构传输至其他的半导体芯片中，以实现对其他半导体芯片的测试，如此，本公开实施例提供的半导体结构通过设置堆叠芯片测试垫，无需与控制芯片连接即可实现对堆叠芯片组件的测试，提高该半导体结构的测试灵活性和适用性。

Claims (15)

  1. 一种半导体结构，包括堆叠芯片组件，所述堆叠芯片组件包括堆叠设置的多个半导体芯片，各所述半导体芯片中均设置有第一电连接结构，相邻所述半导体芯片之间通过所述第一电连接结构连接；
    至少一个所述半导体芯片上设置有堆叠芯片测试垫，所述堆叠芯片测试垫与其所在的半导体芯片中的第一电连接结构以及待测试电路均相连，以将所述堆叠芯片测试垫接收的测试信号传输至各所述半导体芯片。
  2. 根据权利要求1所述的半导体结构，其中，所述第一电连接结构包括穿通电极，所述堆叠芯片测试垫通过第一导电层与所述穿通电极连接。
  3. 根据权利要求2所述的半导体结构，其中，每个所述堆叠芯片测试垫对应设置多个所述穿通电极，所述堆叠芯片测试垫呈方形，多个所述穿通电极设置于所述堆叠芯片测试垫的一侧边并沿该侧边间隔排布。
  4. 根据权利要求1所述的半导体结构，其中，同一所述半导体芯片上设置有多个所述堆叠芯片测试垫，不同的堆叠芯片测试垫用于接收不同的测试信号。
  5. 根据权利要求4所述的半导体结构，其中，所述测试信号包括命令信号、地址信号、数据信号和/或电源信号。
  6. 根据权利要求1至5任一项所述的半导体结构，其中，所述堆叠芯片测试垫设置于所述半导体芯片的边缘区域；或者，
    所述半导体芯片上设置有多个间隔排布的通道，所述通道之间具有间隔区域，所述堆叠芯片测试垫设置于所述间隔区域。
  7. 根据权利要求6所述的半导体结构，其中，所述堆叠芯片测试垫设置于所述半导体芯片的边缘区域的顶部。
  8. 根据权利要求1至5任一项所述的半导体结构，其中，各所述半导体芯片上均设置有晶圆测试垫，所述晶圆测试垫与其所在的半导体芯片中的待测试电路相连。
  9. 根据权利要求8所述的半导体结构，其中，设置有所述堆叠芯片测试垫的所述半导体芯片包括第一测试垫区域和第二测试垫区域，所述堆叠芯片测试垫以及与所述堆叠芯片测试垫相连的第一电连接结构均位于所述第一测试垫区域，所述晶圆测试垫位于所述第二测试垫区域。
  10. 根据权利要求9所述的半导体结构，其中，所述第一测试垫区域内的所述堆叠芯片测试垫与所述第二测试垫区域内的所述晶圆测试垫相互分离。
  11. 根据权利要求10所述的半导体结构，其中，所述第一测试垫区域内的所述堆叠芯片测试垫的数量与所述第二测试垫区域内的所述晶圆测试垫的数量、形状和/或尺寸不同。
  12. 根据权利要求9所述的半导体结构，其中，所述第一测试垫区域和所述第二测试垫区域相邻设置，所述第一测试垫区域内的所述堆叠芯片测试垫与所述第二测试垫区域内的所述晶圆测试垫通过第二导电层连接，通过所述第二导电层相连的所述堆叠芯片测试垫和所述晶圆测试垫用于接收相同的测试信号。
  13. 根据权利要求12所述的半导体结构，其中，所述堆叠芯片测试垫具有相对的第 一侧边和第二侧边，所述晶圆测试垫通过所述第二导电层与所述堆叠芯片测试垫的第一侧边相连，所述第一电连接结构位于所述堆叠芯片测试垫的第二侧边。
  14. 根据权利要求1至5任一项所述的半导体结构，其中，所述堆叠芯片测试垫设置在顶层或底层的所述半导体芯片中。
  15. 一种存储器，包括如权利要求1至14任一项所述的半导体结构以及设置于所述半导体结构上方或下方的控制芯片，所述控制芯片中设置有第二电连接结构，所述第二电连接结构和相邻所述半导体芯片中的第一电连接结构连接。
PCT/CN2022/103958 2022-03-14 2022-07-05 半导体结构及存储器 WO2023173628A1 (zh)

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CN109801897A (zh) * 2017-11-16 2019-05-24 长鑫存储技术有限公司 芯片堆栈立体封装结构及其制造方法
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CN106449590A (zh) * 2016-11-08 2017-02-22 华进半导体封装先导技术研发中心有限公司 一种半导体存储模块及其制作方法
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